Organic light emitting display device

Abstract

An organic light-emitting display device may include a first thin-film transistor (TFT), the TFT including a first active layer formed of a first material and including a first source region, a first channel region, a first drain region, a first gate, a first source electrode, and a first drain electrode; a second TFT including a second active layer formed of a second material and including a second source region, a second channel region, a second drain region, a second gate, a second source electrode, and a second drain electrode; a light-blocking layer overlapping the lower portion of the second active layer and formed on the same layer as a second capacitor electrode; and a first protrusion pattern and a second protrusion pattern disposed on the same layer as the first gate and overlapping the light-blocking layer.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202111470489.5 (application date: December 3, 2021, invention title: organic light-emitting display device). Technical Field

[0002] This disclosure relates to organic light-emitting display devices comprising multiple types of thin-film transistors, and more specifically, to organic light-emitting display devices wherein different types of thin-film transistors are disposed on a single substrate. Background Technology

[0003] Recently, as our society has developed towards an information society, the field of display devices for visually expressing electrical information signals has developed rapidly. Correspondingly, various display devices with excellent performance in terms of thinness, lightweight, and low power consumption are being developed.

[0004] Specific examples of such display devices include liquid crystal displays (LCDs) and electroluminescent display devices, such as organic light-emitting displays (OLEDs) and quantum dot light-emitting displays (QLEDs). In particular, electroluminescent display devices are next-generation display devices with self-emissive properties and have superior characteristics compared to liquid crystal displays in terms of viewing angle, contrast ratio, response speed, and power consumption.

[0005] An electroluminescent display device includes a display area for displaying an image and a non-display area adjacent to the display area. Furthermore, the pixel area includes pixel circuitry and light-emitting elements. Multiple thin-film transistors are located in the pixel circuitry to drive the light-emitting elements disposed in multiple pixels.

[0006] Thin-film transistors (TFTs) can be classified according to the materials that make up the semiconductor layer. Among them, low-temperature polycrystalline silicon (LTPS) TFTs and oxide semiconductor TFTs are the most widely used transistors. Meanwhile, technologies for electroluminescent display devices in which LTPS TFTs and oxide semiconductor TFTs are formed on the same substrate are under active development. Summary of the Invention

[0007] The inventors of this disclosure have recognized that, in a method of manufacturing a display device, the operating characteristics of pixels can be improved by forming multiple thin-film transistors using different semiconductors.

[0008] Therefore, in order to form multiple thin-film transistors with different semiconductors, the inventors of this disclosure have invented a display device that can reduce damage to semiconductor elements while forming the individual semiconductors of multiple thin-film transistors on different layers.

[0009] Meanwhile, it has been discovered that thin-film transistors (TFTs) formed from oxide semiconductors exhibit defects that vary under the influence of external light. For example, TFTs formed from oxide semiconductors may have defects that increase the photocurrent due to external light, thereby increasing brightness. Therefore, the object of this disclosure is to provide a display device capable of reducing damage to TFTs formed from oxide semiconductors.

[0010] The purpose of this disclosure is not limited to the foregoing objectives, and other objectives not mentioned above will be clearly understood by those skilled in the art from the following description.

[0011] To achieve the objectives described above, an organic light-emitting display device according to an exemplary embodiment of the present disclosure may include a substrate comprising a first substrate, a second substrate, and an inorganic insulating layer disposed between the first substrate and the second substrate. A first buffer layer may be located on the substrate. The organic light-emitting display device may include a first thin-film transistor comprising a first active layer formed of a first material and including a first source region, a first channel region, and a first drain region, a first gate overlapping the first active layer, and a first source electrode and a first drain electrode electrically connected to the first active layer, wherein a first gate insulating layer is interposed between the first gate electrode and the first active layer. The organic light-emitting display device may include a second thin-film transistor comprising a second active layer formed of a second material and including a second source region, a second channel region, and a second drain region, a second gate overlapping the second active layer, and a second source electrode and a second drain electrode electrically connected to the second active layer, wherein a second gate insulating layer is interposed between the second gate electrode and the second active layer. An organic light-emitting display device may include a storage capacitor comprising a first capacitor electrode disposed on the same layer as a first gate, and a second capacitor electrode overlapping the first capacitor electrode, with a first interlayer insulating layer inserted between them. The organic light-emitting display device may include a light-blocking layer overlapping the lower portion of a second active layer and formed on the same layer as the second capacitor electrode. The organic light-emitting display device may include a first protrusion pattern and a second protrusion pattern disposed on the same layer as the first gate and overlapping the light-blocking layer, wherein the distance between the first protrusion pattern and the second protrusion pattern may be greater than the width of the second channel region of the second active layer.

[0012] In another embodiment, an organic light-emitting display device may include: a substrate; a first thin-film transistor on the substrate, the first thin-film transistor including a first active layer formed of a first material; a second thin-film transistor on the substrate, the second thin-film transistor including: an active layer formed of a second material and including a source region, a channel region and a drain region, a gate insulating layer on the active layer, and a gate located on the gate insulating layer and overlapping the active layer; a light blocking layer overlapping the active layer, the light blocking layer having a first portion located below the channel region and a second portion extending upward to horizontally overlap at least a portion of the active layer.

[0013] Further details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0014] In an organic light-emitting display device according to an exemplary embodiment of the present disclosure, a light-blocking layer may be disposed below an oxide semiconductor layer to block light introduced through the lower portion of the oxide semiconductor layer. Furthermore, by forming a protruding pattern under the light-blocking layer, sidewalls are formed on the light-blocking layer disposed on the protruding pattern, thereby also blocking light incident through the lower portion of the oxide semiconductor layer and lateral light incident through the side surfaces of the oxide semiconductor layer. Therefore, by preventing changes in the oxide semiconductor element caused by external light, a highly reliable display device can be provided.

[0015] The effects of this disclosure are not limited to the examples above, and many more effects are included in this specification. Attached Figure Description

[0016] Figure 1 This is a block diagram illustrating an organic light-emitting display device including multiple types of thin-film transistors according to an exemplary embodiment of the present disclosure.

[0017] Figure 2A and Figure 2B It is set in an embodiment according to this disclosure. Figure 1 The diagram shows a planar view of the sub-pixels in the active region AA.

[0018] Figure 3 This is a circuit diagram illustrating a pixel driving circuit in a display device according to an exemplary embodiment of the present disclosure.

[0019] Figure 4 It is based on the embodiments of this disclosure. Figure 3 Detailed circuit diagram of pixel light-emitting driving element T2.

[0020] Figure 5 This is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure.

[0021] Figure 6This is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Detailed Implementation

[0022] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0023] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms used herein, such as “comprising,” “having,” and “consisting of,” are generally intended to allow for the addition of other components unless used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0024] The component is interpreted to include the normal tolerance range, even if not explicitly stated otherwise.

[0025] When using terms such as “above,” “over,” “below,” and “next to” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless the term is used with the terms “exactly” or “directly.”

[0026] When an element or layer is placed "on" another element or layer, the other layer or element can be directly inserted on or between the other element.

[0027] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component referred to below may be the second component in the technical concept of this disclosure.

[0028] Throughout the specification, the same reference numerals generally denote the same elements.

[0029] The dimensions and thicknesses of each component shown in the accompanying drawings are for illustrative purposes only, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0030] Features of the various embodiments of this disclosure may be partially or wholly superimposed or combined with each other, and may be interlocked and operated in various technical ways, and the embodiments may be performed independently or in conjunction with each other.

[0031] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] In an organic light-emitting display device including multiple types of thin-film transistors according to an exemplary embodiment of the present disclosure, at least two types of thin-film transistors can be formed on the same substrate. Multiple types of thin-film transistors refer to thin-film transistors of different types formed on a single substrate. Here, as at least two types of thin-film transistors, low-temperature polycrystalline silicon (LTPS) thin-film transistors using polycrystalline silicon as the active layer and oxide semiconductor thin-film transistors using metal oxide as the active layer can be used.

[0033] In organic light-emitting display devices including various types of thin-film transistors according to exemplary embodiments of the present disclosure, LTPS thin-film transistors using LTPS are used as thin-film transistors using polycrystalline silicon material as the active layer. This is because polycrystalline silicon material has a high mobility (100 cm⁻¹). 2 With low power consumption and excellent reliability (Vs or higher), LTPS thin-film transistors can be used in multiplexers (MUX) and / or gating drivers for driving elements, which in turn drive thin-film transistors for display elements. That is, the transistor constituting the gating driver (GD) can be an LTPS thin-film transistor. It is preferably used as a driving thin-film transistor in pixels of organic light-emitting display devices.

[0034] In an organic light-emitting display device including various types of thin-film transistors according to an exemplary embodiment of the present disclosure, an oxide semiconductor thin-film transistor (OST) using an oxide semiconductor material as the active layer can be used. Since the band gap of an oxide semiconductor material is larger than that of silicon, electrons do not pass through the band gap in the off state, resulting in a low cutoff current. Therefore, OSTs are suitable for switching thin-film transistors with short on-time and long off-time. Furthermore, due to the low cutoff current, the size of the auxiliary capacitor can be reduced, making OSTs suitable for high-resolution display devices.

[0035] An organic light-emitting display device including multiple types of thin-film transistors according to an exemplary embodiment of the present disclosure can provide improved functionality by providing LPTS thin-film transistors and oxide semiconductor thin-film transistors with different properties on the same substrate.

[0036] Figure 1This is a block diagram illustrating an organic light-emitting display device including multiple types of thin-film transistors according to an exemplary embodiment of the present disclosure.

[0037] Reference Figure 1 The organic light-emitting display device 100 includes an organic light-emitting display panel 10, a gating driver 11, a data driver 12, a multiplexer (MUX) 14, and a timing controller 13.

[0038] The timing controller 13 controls the display panel driving circuit, which includes a gating driver 11 and a data driver 12, to write data of the input image to the pixels P of the organic light-emitting display panel 10. When the organic light-emitting display panel 10 further includes a touch sensing unit, the display panel driving circuit may further include a touch sensing driving unit.

[0039] In the organic light-emitting display panel 10, multiple data lines DL and multiple scan lines SL intersect each other, and multiple pixels P are arranged in a matrix. Furthermore, various lines such as initialization voltage lines, light-emitting control signal lines, high-potential voltage lines, and low-potential voltage lines can be further arranged in the organic light-emitting display panel 10.

[0040] Each of the plurality of pixels P is a pixel used to achieve a certain color, and the plurality of pixels P may include red pixels, green pixels, and blue pixels. Furthermore, to improve the brightness and lifespan of the organic light-emitting display panel 10, the plurality of pixels P may also include white pixels. The red, green, and blue pixels (as well as the white pixels) form a group, thereby enabling the achievement of the desired color.

[0041] Data driver 12 converts each frame of digital video data DATA from the input image received from timing controller 13 into an analog data voltage, and then provides this data voltage to data line DL. Data driver 12 can use a digital-to-analog converter (DAC) that converts digital data into a gamma-compensated voltage to output the data voltage.

[0042] Multiplexer 14 can be disposed between data driver 12 and data line DL of organic light-emitting display panel 10. Multiplexer 14 can reduce the number of output channels of data driver 12 to N (N is a positive integer greater than or equal to 2) by dividing the data voltage output from data driver 12 via one output channel. Multiplexer 14 can be omitted depending on the resolution and application of organic light-emitting display device 100. Multiplexer 14 can be configured as a switching circuit, and the switching circuit is turned on / off under the control of timing controller 13.

[0043] Under the control of the timing controller 13, the gating driver 11 outputs a scan signal and an emission control signal, selects the pixel P charged by the data voltage through the scan line SL, and adjusts the emission timing. The gating driver 11 can use a shift register to shift the scan signal and the emission control signal, and sequentially provide the corresponding signals to the scan line SL. The shift register of the gating driver 11 can be directly formed on the substrate of the organic light-emitting display panel 10 using the gating driver input panel (GIP) method.

[0044] The timing controller 13 receives digital video data DATA of the input image and timing signals synchronized with the digital video data DATA from the host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, a data enable signal DE, etc. The host system can be any of various electronic devices such as a television system, set-top box, navigation system, DVD player, Blu-ray player, personal computer (PC), home theater system, telephone system, etc.

[0045] The timing controller 13 can generate a data timing control signal DDC for controlling the operation timing of the data driver 12, MUX selection signals MUX_R, MUX_G, and MUX_B for controlling the operation timing of the multiplexer 14, and a gating timing control signal GDC for controlling the operation timing of the gating driver 11 based on timing signals Vsync, Hsync, DCLK, and DE received from the host system.

[0046] The data timing control signal DDC may include a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE). The source start pulse (SSP) controls the sampling start timing of the data driver 12. The source sampling clock (SSC) is the clock used for shift data sampling timing. The polarity control signal (POL) controls the polarity of the data signal output from the data driver 12. If the signal transmission interface between the timing controller 13 and the data driver 12 is a mini-LVDS (low-voltage differential signaling) interface, the source start pulse (SSP) and the source sampling clock (SSC) can be omitted.

[0047] The gating timing control signal GDC includes the gating start pulse GSP, the gating shift clock CLK, and the gating output enable signal GOE. In the case of a GIP circuit, the gating output enable signal GOE can be omitted. At the beginning of each frame period, a gating start pulse GSP is generated and input to the shift register. The gating start pulse GSP controls the initial timing of the first block of gating pulses output in each frame period. The clock CLK is input to the shift register to control the shift timing of the shift register. The gating output enable signal GOE limits the output timing of the gating pulses.

[0048] Figure 2A and Figure 2B It is set in an embodiment according to this disclosure. Figure 1 The diagram shows a planar view of the sub-pixels in the active region AA.

[0049] The active area AA displays the image through unit pixels arranged in a matrix. Each unit pixel consists of red (R), green (G), and blue (B) sub-pixels, or red (R), green (G), blue (B), and white (W) sub-pixels. For example, as... Figure 2A As shown, red (R), green (G), and blue (B) subpixels can be arranged in a row on the same imaginary horizontal line, or as... Figure 2B As shown, the red (R), green (G), and blue (B) subpixels can be arranged spaced apart from each other and arranged in a virtual triangular structure. The shape of the unit pixel is not limited to... Figure 2A and 2B It can take on various shapes and can be achieved in a variety of ways.

[0050] Figure 3 This is a circuit diagram illustrating a pixel driving circuit in a display device according to an exemplary embodiment of the present disclosure. The sub-pixel SPX includes a light-emitting element EL and a pixel driving circuit, the pixel driving circuit including six transistors and a capacitor to provide driving current to the light-emitting element EL. Figure 3 The equivalent circuit of the sub-pixel SPX shown is not limited to this and can be implemented in various ways.

[0051] Specifically, the pixel driving circuit includes a driving transistor T2, a first switching transistor T1, and third to sixth switching transistors T3 to T6, as well as a storage capacitor Cst.

[0052] The driving transistor T2 includes a gate node connected to a first node N1, a drain node connected to a second node N2, and a source node connected to a third node N3. The first node N1 is connected to a node of the storage capacitor Cst. The second node N2 is connected to the third switching transistor T3 and the fourth switching transistor T4. The third node N3 is connected to the first switching transistor T1 and the fifth switching transistor T5. The source node of the driving transistor T2 is electrically connected to the organic light-emitting element. The driving transistor T2 can be referred to as a pixel light-emitting driving element.

[0053] Specifically, the source node of the driving transistor T2 is connected to the drain node of the fifth switching transistor T5 and the third node N3. Furthermore, the driving transistor T2 is electrically connected to the anode of the organic light-emitting element.

[0054] The drain node of the driving transistor T2 is connected to the high-potential voltage line providing the high-potential voltage VDDEL via the fourth transistor T4. Therefore, during the light-emitting period, the driving transistor T2 is turned on by receiving the high-potential voltage VDDEL via the fourth transistor T4 and provides driving current to the light-emitting element EL.

[0055] The first switching transistor T1 includes a gate node connected to the second scan signal line providing the second scan signal Scan2, a drain node connected to the data line providing the data voltage Data, and a source node connected to the third node N3. The first switching transistor T1 is turned on or off by the second scan signal Scan2. When the first switching transistor T1 is turned on, it provides the data voltage Data to the third node N3.

[0056] The third switching transistor T3 includes a gate node connected to a first scan signal line providing the first scan signal Scan1, a drain node connected to a second node N2, and a source node connected to the first node. The third switching transistor T3 can be turned on, and a diode connects the gate node and the drain node of the driving transistor T2 to sense the threshold voltage of the driving transistor T2.

[0057] The fourth switching transistor T4 includes: a gate node connected to the nth light emission control signal line providing the nth light emission control signal EM[n]; a drain node connected to the high-potential voltage line; and a source node connected to the second node N2. The fourth switching transistor T4 is turned on by the nth light emission control signal EM[n] and provides the high-potential voltage VDDEL to the drain node of the driving transistor T2.

[0058] Therefore, the fourth switching transistor T4 provides a high potential voltage VDDEL to the drain node of the driving transistor T2, causing the drain-source current of the driving transistor T2 (hereinafter referred to as Ids) to flow to the light-emitting element EL. Thus, the driving transistor T2 can display grayscale by adjusting the amount of current supplied to the light-emitting element EL according to the data voltage Data.

[0059] The fifth switching transistor T5 includes: a gate node connected to the (n-1)th light-emitting control signal line providing the (n-1)th light-emitting control signal EM[n-1]; a drain node connected to the third node N3; and a source node connected to the fourth node N4. To sample the threshold voltage of the driving transistor T2 through the coupling effect of the storage capacitor Cst, the fifth switching transistor T5 is turned on, providing the data voltage Data of the third node N3 to the fourth node N4. Furthermore, when the light-emitting element EL emits light, the fifth switching transistor T5 is turned on and provides a driving current to the light-emitting element EL.

[0060] The sixth switching transistor T6 includes: a gate node connected to a second scan signal line that provides a first scan signal Scan1 thereto; a source node connected to an initialization voltage line that provides an initialization voltage Vini thereto; and a drain node connected to a fourth node N4.

[0061] The sixth switching transistor T6 is turned on by the first scan signal Scan1 and provides the initialization voltage Vini to the fourth node N4, thereby causing the anode of the light-emitting element EL to discharge.

[0062] The storage capacitor Cst is connected to the first node N1 and the fourth node N4, and stores the voltage applied to the gate node of the driving transistor T2.

[0063] The storage capacitor Cst is electrically connected to the first node N1 and the fourth node N4, and stores the difference between the voltage supplied to the gate node of the driving transistor T2 and the voltage supplied to the anode of the light-emitting element EL.

[0064] The structure of the driving transistor T2 will be described in detail below.

[0065] Figure 4 It is based on the embodiments of this disclosure. Figure 3 Detailed circuit diagram of pixel light-emitting driving element T2.

[0066] According to the exemplary implementation herein, because it is necessary to allow for both drive current supply performance and S-factor characteristics for low grayscale rendering, the drive transistor T2 can be configured as follows: Figure 4 The design uses two transistors connected in parallel. Therefore, the driving performance of the sub-pixel SPX can be greatly improved.

[0067] In this disclosure, such as Figure 3 The diagram illustrates that each sub-pixel SPX includes an organic light-emitting element, first to sixth transistors T1 to T6, and a storage capacitor Cst; however, this disclosure is not limited thereto. For example, in a display device according to an exemplary embodiment of this disclosure, each sub-pixel SPX may include a light-emitting element, first to seventh transistors T1 to T7, and a storage capacitor Cst.

[0068] Figure 5 This is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure.

[0069] refer to Figure 5The display device 100 according to an exemplary embodiment of the present disclosure may include a substrate 110, a first buffer layer 111, a first thin film transistor 120, a second thin film transistor 130, a storage capacitor 140, a first gate insulating layer 112, a first interlayer insulating layer 113, a second buffer layer 114, a second gate insulating layer 115, a second interlayer insulating layer 116, a first planarization layer 117, a second planarization layer 118, a first electrode 170, a connecting electrode 150, a dam portion 180, an auxiliary electrode 160, a spacer portion 190, a light-emitting structure 200, a second electrode 210, and packaging units 220a, 220b, and 220c.

[0070] The substrate 110 supports various components of the display device 100. The substrate 110 can be formed of a flexible glass or plastic material. When the substrate 110 is formed of a plastic material, it can be formed of, for example, polyimide (PI). When the substrate 110 is formed of polyimide (PI), the display device manufacturing process is performed with a glass-formed support substrate disposed below the substrate 110, and the support substrate can be peeled off after the display device manufacturing process is completed. Furthermore, after peeling off the support substrate, a backplate for supporting the substrate 110 can be disposed below the substrate 110.

[0071] When the substrate 110 is formed of polyimide (PI), moisture can permeate through the polyimide (PI) substrate 110 to the first thin-film transistor 120 or the light-emitting structure 200, potentially degrading the performance of the display device 100. The display device 100 according to an exemplary embodiment of this disclosure can be formed of double polyimide (PI) to prevent performance degradation due to moisture penetration. Furthermore, by forming an inorganic layer between the two polyimides (PI), moisture components can be prevented from penetrating the lower polyimide (PI), thereby improving product performance reliability.

[0072] Furthermore, when an inorganic layer is formed between two polyimide (PI) layers, the charge in the lower polyimide PI layer creates a reverse bias, which can affect the first thin-film transistor 120. Therefore, a separate metal layer needs to be formed to block the charge in the polyimide (PI). However, in the display device 100 according to an exemplary embodiment of this disclosure, the charge in the lower polyimide PI layer can be blocked by forming an inorganic layer between the two polyimide PI layers, thereby improving product reliability. Furthermore, since the process of forming a metal layer to block the charge in the polyimide (PI) can be omitted, process simplification and reduced production costs are possible.

[0073] In flexible display devices that use polyimide (PI) as substrate 110, ensuring environmental reliability and panel performance reliability is of paramount importance.

[0074] The display device 100 according to an exemplary embodiment of this disclosure can achieve a structure for ensuring the environmental reliability performance of the product by using polyimide (PI) as a substrate. For example, as Figure 5 As shown, the substrate 110 of the display device 100 may include a first polyimide layer 110a, a second polyimide layer 110c, and an inorganic insulating layer 110b formed between the first polyimide layer 110a and the second polyimide layer 110c. When a charge is present in the first polyimide layer 110a, the inorganic insulating layer 110b can be used to prevent the charge from affecting the first thin-film transistor 120 through the second polyimide layer 110c. Furthermore, the inorganic insulating layer 110b formed between the first polyimide layer 110a and the second polyimide layer 110c can be used to prevent moisture components from passing through and permeating the first polyimide layer 110a.

[0075] The inorganic insulating layer 110b can be formed from a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). In the display device 100 according to an exemplary embodiment of the present disclosure, the inorganic insulating layer 110b can be formed from silicon oxide (SiOx) material. For example, the inorganic insulating layer 110b can be formed from silicon dioxide material (silicon or silicon dioxide: SiO2). However, the present disclosure is not limited thereto, and the inorganic insulating layer 110b can be formed from a bilayer of silicon dioxide (SiO2) and silicon nitride (SiNx).

[0076] The first buffer layer 111 can be formed on the entire surface of the substrate 110. The first buffer layer 111 can be formed from a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The first buffer layer 111 can improve the adhesion between the layer formed on the first buffer layer 111 and the substrate 110, and prevent alkaline components from leaking from the substrate 110. Furthermore, the first buffer layer 111 is not a necessary component and can be omitted depending on the type and material of the substrate 110, the structure and type of the thin-film transistor, etc.

[0077] According to an exemplary embodiment of this disclosure, the first buffer layer 111 can be formed as a multilayer in which silicon dioxide (SiO2) and silicon nitride (SiNx) are alternately formed. Specifically, the first buffer layer 111 can be formed from (n+1) layers. Here, n represents an even number including 0, such as 0, 2, 4, 6, or 8. Therefore, when n=0, the first buffer layer 111 is formed as a single layer. Furthermore, the first buffer layer 111 can be silicon nitride (SiNx) or silicon dioxide (SiOx). When n=2, the first buffer layer 111 can be formed as a three-layer layer. When the first buffer layer 111 is formed as a three-layer layer, its upper and lower layers can be silicon dioxide (SiOx), and its intermediate layer disposed between the upper and lower layers can be silicon nitride (SiNx). And, when n=4, the first buffer layer 111 can be formed from five layers. When the first buffer layer 111 is formed from five layers, as... Figure 5 As shown, a 1-a buffer layer 111a can be formed on the substrate 110. Furthermore, the buffer layer 111a can be formed of silicon dioxide (SiO2) material. Furthermore, a 1-b buffer layer 111b can be formed of silicon nitride (SiNx) material and can be disposed on the 1-a buffer layer 111a. Furthermore, a 1-c buffer layer 111c can be formed of silicon dioxide (SiO2) material and can be disposed on the 1-b buffer layer 111b. Furthermore, a 1-d buffer layer 111d can be formed of silicon nitride (SiNx) material and can be disposed on the 1-c buffer layer 111c. Furthermore, a 1-e buffer layer 111e can be formed of silicon dioxide (SiO2) material and can be disposed on the 1-d buffer layer 111d. Thus, when n is an even number greater than or equal to 2, the first buffer layer 111 can be formed as a multilayer, wherein silicon dioxide (SiOx) and silicon nitride (SiNx) are alternately formed. Furthermore, the uppermost and lowermost layers of the first buffer layer 111, formed by multiple layers, can be formed of silicon oxide (SiOx) material. For example, the first buffer layer 111, formed by multiple layers, may include an upper layer in contact with the first active layer 121 of the first thin-film transistor 120, a lower layer in contact with the substrate 110, and an intermediate layer located between the upper and lower layers. Furthermore, the upper and lower layers can be formed of silicon oxide (SiOx) material. Furthermore, the upper layer of the first buffer layer 111, formed by multiple layers, can be formed to be thicker than the lower and intermediate layers. In the first buffer layer 111 formed by multiple layers, the thickness of the upper layer in contact with the first active layer 121 of the first thin-film transistor 120 can be greater than the thickness of the lower and intermediate layers of the first buffer layer 111. For example, when the first buffer layer 111 is as follows... Figure 5In the five-layer configuration shown, the 1-e buffer layer 111e, which contacts the first active layer 121, can be the upper layer. Furthermore, the buffer layer 111a, which contacts the substrate 110, can be the lower layer. Additionally, the 1-b buffer layer 111b, 1-c buffer layer 111c, and 1-d buffer layer 111d disposed between the 1-a buffer layer 111a and the 1-e buffer layer 111e can be intermediate layers. Here, the thickness of the upper 1-e buffer layer 111e can be greater than the thickness of the lower 1-a buffer layer 111a and the thickness of each of the intermediate layers 1-b buffer layer 111b, 1-c buffer layer 111c, and 1-d buffer layer 111d. More specifically, the 1-e buffer layer 111e can have a thickness of 3000 Å, and the 1-a buffer layer 111a can have a thickness of 1000 Å. In addition, the 1-b buffer layer 111b, the 1-c buffer layer 111c and the 1-d buffer layer 111d can each have a thickness of 1000 Å.

[0078] Furthermore, in the first buffer layer 111 formed by multiple layers, all the remaining layers except the upper layer that contacts the first active layer 121 of the first thin-film transistor 120 can have the same thickness. For example, except for the 1-e buffer layer 111e that contacts the first active layer 121, the 1-a buffer layer 111a, 1-b buffer layer 111b, 1-c buffer layer 111c, and 1-d buffer layer 111d can have the same thickness.

[0079] The first thin-film transistor 120 can be disposed on the first buffer layer 111. The first thin-film transistor 120 may include a first active layer 121, a first gate 124, a first source 122, and a first drain 123. Here, depending on the pixel circuit design, the first source 122 can be the drain, and the first drain 123 can be the source. The first active layer 121 of the first thin-film transistor 120 can be disposed on the first buffer layer 111.

[0080] The first active layer 121 may include low-temperature polycrystalline silicon (LTPS). Due to the high mobility (100 cm⁻¹) of polycrystalline silicon material... 2( / Vs or higher), which has low power consumption and excellent reliability, and therefore can be applied to multiplexers (MUX) and / or gate drivers for driving elements of thin-film transistors in display devices, and can be used as an active layer for driving thin-film transistors in a display device according to this embodiment. However, this disclosure is not limited thereto. For example, depending on the characteristics of the display device, it can be used as an active layer for switching thin-film transistors. Polycrystalline silicon is formed by depositing amorphous silicon (a-Si) material on the first buffer layer 111 and performing a dehydrogenation process and a crystallization process, and the first active layer 121 can be formed by patterning the polycrystalline silicon. The first active layer 121 may include a first channel region 121a in which a channel is formed when the first thin-film transistor 120 is driven, and a first source region 121b and a first drain region 121c on both sides of the first channel region 121a. The first source region 121b represents the portion of the first active layer 121 connected to the first source 122, and the first drain region 121c represents the portion of the first active layer 121 connected to the first drain 123. The first source region 121b and the first drain region 121c can be formed by ion doping (impurity doping) of the first active layer 121. The first source region 121b and the first drain region 121c can be formed by performing ion doping on polysilicon material, and the first channel region 121a can refer to the portion that is not ion doped and is retained as polysilicon material.

[0081] The first gate insulating layer 112 may be disposed on the first active layer 121 of the first thin-film transistor 120. The first gate insulating layer 112 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the first gate insulating layer 112 for connecting the first source 122 and the first drain 123 of the first thin-film transistor 120 to the first source region 121b and the first drain region 121c of the first active layer 121 of the first thin-film transistor 120, respectively.

[0082] The first gate 124 of the first thin-film transistor 120 and the first capacitor electrode 141 of the storage capacitor 140 can be disposed on the first gate insulating layer 112.

[0083] The first gate 124 and the first capacitor electrode 141 can be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof. The first gate 124 can be formed on the first gate insulating layer 112 to overlap with the first channel region 121a of the first active layer 121 of the first thin-film transistor 120. Based on the driving characteristics of the display device 100 and the structure and type of the thin-film transistor, the first capacitor electrode 141 can be omitted. The first gate 124 and the first capacitor electrode 141 can be formed by the same process. Furthermore, the first gate 124 and the first capacitor electrode 141 can be formed of the same material and can be formed on the same layer.

[0084] A first interlayer insulating layer 113 may be disposed on the first gate insulating layer 112, the first gate electrode 124, and the first capacitor electrode 141. The first interlayer insulating layer 113 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes for exposing the first source region 121b and the first drain region 121c of the first active layer 121 of the first thin-film transistor 120 may be formed in the first interlayer insulating layer 113.

[0085] The second capacitor electrode 142 of the storage capacitor 140 can be disposed on the first interlayer insulating layer 113. The second capacitor electrode 142 can be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof. The second capacitor electrode 142 can be formed on the first interlayer insulating layer 113 to overlap with the first capacitor electrode 141. Furthermore, the second capacitor electrode 142 can be formed of the same material as the first capacitor electrode 141. Based on the driving characteristics of the display device 100 and the structure and type of the thin-film transistor, the second capacitor electrode 142 can be omitted.

[0086] A second buffer layer 114 may be disposed on the first interlayer insulating layer 113 and the second capacitor electrode 142. The second buffer layer 114 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes for exposing the first source region 121b and the first drain region 121c of the first active layer 121 of the first thin-film transistor 120 may be formed in the second buffer layer 114. In addition, contact holes for exposing the second capacitor electrode 142 of the storage capacitor 140 may be formed.

[0087] The second active layer 131 of the second thin-film transistor 130 can be disposed on the second buffer layer 114. The second thin-film transistor 130 may include the second active layer 131, the second gate insulating layer 115, the second gate 134, the second source 132, and the second drain 133. Here, depending on the design of the pixel circuit, the second source 132 can be the drain, and the second drain 133 can be the source.

[0088] The second active layer 131 may include a second channel region 131a in which a channel is formed when the second thin-film transistor 130 is driven, and a second source region 131b and a second drain region 131c on both sides of the second channel region 131a. The second source region 131b may refer to the portion of the second active layer 131 connected to the second source 132, and the second drain region 131c may refer to the portion of the second active layer 131 connected to the second drain 133.

[0089] The second active layer 131 can be formed of an oxide semiconductor. Since oxide semiconductors have a larger band gap than silicon, electrons do not cross the band gap in the off-state, resulting in a lower cutoff current. Therefore, a thin-film transistor including an active layer formed of an oxide semiconductor can be used for switching thin-film transistors with short on-time and long off-time, but is not limited thereto. Depending on the characteristics of the display device, it can be used as a driving thin-film transistor. Furthermore, due to the low cutoff current, the size of the auxiliary capacitor can be reduced, which is suitable for high-resolution display devices. For example, the second active layer 131 can be formed of a metal oxide, such as various metal oxides such as indium gallium zinc oxide (IGZO). Assuming the second active layer 131 of the second thin-film transistor 130 is formed of IGZO among various metal oxides, the second active layer 131 of the second thin-film transistor 130 is described as being formed based on an IGZO layer, but this disclosure is not limited thereto. The second active layer 131 of the second thin-film transistor 130 can also be formed of another metal oxide such as IZO (indium zinc oxide), IGTO (indium gallium tin oxide), or IGO (indium gallium oxide).

[0090] The second active layer 131 can be formed by the following steps: depositing a metal oxide on the second buffer layer 114, performing a heat treatment process for stabilization, and then patterning the metal oxide.

[0091] Insulating material layers and metal material layers can be sequentially formed on the entire surface of the substrate, and photoresist patterns can be formed on the metal material layers.

[0092] Insulating material layers can be formed using PECVD, and metallic material layers can be formed using sputtering.

[0093] The second gate 134 can be formed by wet etching of the metal material layer using a photoresist pattern PR as a mask. As a wet etchant for etching the metal material layer, a material that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof constituting the metal material layer can be used without etching the insulating material layer.

[0094] The second gate insulating layer 115 can be formed by dry etching the insulating material layer using a photoresist pattern PR and the second gate 134 as a mask.

[0095] A dry etching process can be used to etch an insulating material layer to form a pattern of a second gate insulating layer 115 on the second active layer 131. Furthermore, the dry etching process allows a portion of the second active layer 131 exposed by the patterned second gate insulating layer 115 to be conductive.

[0096] A second active layer 131 may be formed, which includes a non-conductive second channel region 131a corresponding to the region in which the second gate 134 is formed, and a second source region 131b and a second drain region 131c that are conductive at both ends of the second active layer 131.

[0097] Since the resistance of the second source region 131b and the second drain region 131c of the conductive second active layer 131 is reduced, the device performance of the second thin film transistor 130 can be improved, and thus, the reliability of the display device 100 according to the exemplary embodiment of the present disclosure can be improved.

[0098] The second channel region 131a of the second active layer 131 may be configured to overlap with the second gate 134. Furthermore, the second source region 131b and the second drain region 131c of the second active layer 131 may be disposed on both sides of the second channel region 131a. Additionally, the second gate insulating layer 115 may be disposed between the second gate 134 and the second active layer 131. Furthermore, the second gate insulating layer 115 may be configured to overlap with the second gate 134 and the second channel region 131a of the second active layer 131.

[0099] When using a photoresist pattern PR as a mask to etch the insulating material layer and the metal material layer, the second gate insulating layer 115 and the second gate 134 can be formed with the same pattern. The second gate insulating layer 115 can be disposed on the second active layer 131. The second gate insulating layer 115 can be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The second gate insulating layer 115 can be patterned to overlap with the second channel region 131a of the second active layer 131. The second gate 134 can be disposed on the second gate insulating layer 115. The second gate 134 can be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or their alloys. The second gate 134 can be patterned to overlap with the second active layer 131 and the second gate insulating layer 115. The second gate 134 can be patterned to overlap with the second channel region 131a of the second active layer 131. Furthermore, the second gate insulating layer 115 can be patterned to overlap with the second channel region 131a of the second active layer 131. Therefore, the second gate 134 and the second gate insulating layer 115 can overlap with the second channel region 131a of the second active layer 131. A second interlayer insulating layer 116 can be disposed on the second buffer layer 114, the second active layer 131, and the second gate 134. Contact holes for exposing the first active layer 121 of the first thin-film transistor 120 and the second active layer 131 of the second thin-film transistor 130 can be formed in the second interlayer insulating layer 116. For example, contact holes for exposing the first source region 121b and the first drain region 121c of the first active layer 121 in the first thin-film transistor 120 can be formed in the second interlayer insulating layer 116. Furthermore, contact holes for exposing the second source region 131b and the second drain region 131c of the second active layer 131 in the second thin-film transistor 130 can be formed in the second interlayer insulating layer 116. The second interlayer insulating layer 116 can be composed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0100] On the second interlayer insulating layer 116, the connecting electrode 150, the first source 122 and the first drain 123 of the first thin film transistor 120, and the second source 132 and the second drain 133 of the second thin film transistor 130 can be disposed.

[0101] The first source 122 and the first drain 123 of the first thin-film transistor 120 can be connected to the first active layer 121 of the first thin-film transistor 120 through contact holes formed in the first gate insulating layer 112, the first interlayer insulating layer 113, the second buffer layer 114, and the second interlayer insulating layer 116. Therefore, the first source 122 of the first thin-film transistor 120 can be connected to the first source region 121b of the first active layer 121 through contact holes formed in the first gate insulating layer 112, the first interlayer insulating layer 113, the second buffer layer 114, and the second interlayer insulating layer 116. Furthermore, the first drain 123 of the first thin-film transistor 120 can be connected to the first drain region 121c of the first active layer 121 through contact holes formed in the first gate insulating layer 112, the first interlayer insulating layer 113, the second buffer layer 114, and the second interlayer insulating layer 116.

[0102] Furthermore, the connection electrode 150 can be electrically connected to the second drain 133 of the second thin-film transistor 130. Additionally, the connection electrode 150 can be electrically connected to the second capacitor electrode 142 of the storage capacitor 140 through contact holes formed in the second buffer layer 114 and the second interlayer insulating layer 116. Therefore, the connection electrode 150 can be used to electrically connect the second capacitor electrode 142 of the storage capacitor 140 and the second drain 133 of the second thin-film transistor 130.

[0103] Furthermore, the second source 132 and the second drain 133 of the second thin-film transistor 130 can be connected to the second active layer 131 through contact holes formed in the second interlayer insulating layer 116. Therefore, the second source 132 of the second thin-film transistor 130 can be connected to the second source region 131b of the second active layer 131 through contact holes formed in the second interlayer insulating layer 116, and the second drain 133 of the second thin-film transistor 130 can be connected to the second drain region 131c of the second active layer 131 through contact holes formed in the second interlayer insulating layer 116.

[0104] The connecting electrode 150, the first source 122 and the first drain 123 of the first thin-film transistor 120, and the second source 132 and the second drain 133 of the second thin-film transistor 130 can be formed using the same process. Furthermore, the connecting electrode 150, the first source 122 and the first drain 123 of the first thin-film transistor 120, and the second source 132 and the second drain 133 of the second thin-film transistor 130 can be formed from the same material. The connecting electrode 150, the first source 122 and the first drain 123 of the first thin-film transistor 120, and the second source 132 and the second drain 133 of the second thin-film transistor 130 can be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof. For example, the connecting electrode 150, the first source 122 and the first drain 123 of the first thin film transistor 120, and the second source 132 and the second drain 133 of the second thin film transistor 130 may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) formed of conductive metal material, but this disclosure is not limited thereto.

[0105] The connecting electrode 150 can be integrally formed with and connected to the second drain 133 of the second thin film transistor 130.

[0106] The first planarization layer 117 can be disposed on the connecting electrode 150, the first source 122 and the first drain 123 of the first thin-film transistor 120, the second source 132 and the second drain 133 of the second thin-film transistor 130, and the second interlayer insulating layer 116. For example... Figure 5 As shown, contact holes for exposing the second drain 133 can be formed in the first planarization layer 117, but are not limited thereto. For example, contact holes for exposing the second source 132 of the second thin-film transistor 130 can be formed in the first planarization layer 117. Alternatively, contact holes for exposing the connection electrode 150 electrically connected to the second drain 133 of the second thin-film transistor 130 can be formed in the first planarization layer 117. The first planarization layer 117 can be an organic material layer for planarizing and protecting the upper parts of the first thin-film transistor 120 and the second thin-film transistor 130. For example, the first planarization layer 117 can be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0107] An auxiliary electrode 160 may be disposed on the first planarization layer 117. Furthermore, the auxiliary electrode 160 may be connected to the second drain 133 of the second thin-film transistor 130 through contact holes in the first planarization layer 117. The auxiliary electrode 160 may be used to electrically connect the second thin-film transistor 130 and the first electrode 170. The auxiliary electrode 160 may be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof. The auxiliary electrode 160 may be formed of the same material as the second source 132 and the second drain 133 of the second thin-film transistor 130.

[0108] The second planarization layer 118 can be disposed on the auxiliary electrode 160 and the first planarization layer 117. Furthermore, as... Figure 5 As shown, contact holes for exposing the auxiliary electrode 160 can be formed in the second planarization layer 118. The second planarization layer 118 can be an organic material layer for planarizing the upper parts of the first thin-film transistor 120 and the second thin-film transistor 130. For example, the second planarization layer 118 can be formed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0109] The first electrode 170 can be disposed on the second planarization layer 118. The first electrode 170 can be electrically connected to the auxiliary electrode 160 through contact holes formed in the second planarization layer 118. Therefore, the first electrode 170 can be electrically connected to the second thin-film transistor 130 by connecting to the auxiliary electrode 160 through contact holes formed in the second planarization layer 118.

[0110] The first electrode 170 can be formed as a multilayer structure including a transparent conductive layer and an opaque conductive layer with high reflectivity. The transparent conductive layer can be formed of a material with a relatively large work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Furthermore, the opaque conductive layer can have a single-layer or multilayer structure including Al, Ag, Cu, Pb, Mo, and Ti or alloys thereof. For example, the first electrode 170 can be formed as a structure in which a transparent conductive layer, an opaque conductive layer, and a transparent conductive layer are sequentially stacked. However, this disclosure is not limited to this, and a structure in which the transparent conductive layer and the opaque conductive layer are sequentially stacked can also be formed.

[0111] Since the display device 100 according to the exemplary embodiment of this disclosure is a top-emitting display device, the first electrode 170 can be an anode. When the display device 100 is a bottom-emitting display device, the first electrode 170 disposed on the second planarization layer 118 can be a cathode.

[0112] A dam portion 180 may be disposed on the first electrode 170 and the second planarization layer 118. An opening for exposing the first electrode 170 may be formed in the dam portion 180. The dam portion 180 may define a light-emitting area of ​​the display device 100, and therefore may be referred to as a pixel defining layer. A spacer portion 190 may be further disposed on the dam portion 180. Furthermore, a light-emitting structure 200 including a light-emitting layer may be further disposed on the first electrode 170.

[0113] The light-emitting structure 200 can be formed by stacking a hole layer, a light-emitting layer, and an electron layer in a sequential or reverse order on the first electrode 170. Furthermore, the light-emitting structure 200 may include a first light-emitting structure and a second light-emitting structure facing each other, with a charge-generating layer inserted between them. In this case, the light-emitting layer of either the first or second light-emitting structure generates blue light, while the light-emitting layer of the other light-emitting structure generates yellow-green light, thereby generating white light through the first and second light-emitting structures. The white light generated by the light-emitting structure 200 can be incident on a color filter (not shown) located on the light-emitting structure 200 to achieve a color image. Furthermore, a color image can be achieved by generating colored light corresponding to each sub-pixel in each light-emitting structure 200 without a separate color filter. That is, the light-emitting structure 200 for the red (R) sub-pixel can generate red light, the light-emitting structure 200 for the green (G) sub-pixel can generate green light, and the light-emitting structure 200 for the blue (B) sub-pixel can generate blue light.

[0114] The second electrode 210 may be further disposed on the light-emitting structure 200. The second electrode 210 may be disposed on the light-emitting structure 200 facing the first electrode 170, with the light-emitting structure 200 inserted therebetween. In the display device 100 according to an exemplary embodiment of the present disclosure, the second electrode 210 may be a cathode. Encapsulation units 220a, 220b, and 220c for suppressing moisture penetration may be further disposed on the second electrode 210.

[0115] Encapsulation units 220a, 220b, and 220c may include a first inorganic encapsulation layer 220a, a second organic encapsulation layer 220b, and a third inorganic encapsulation layer 220c. The first inorganic encapsulation layer 220a of encapsulation units 220a, 220b, and 220c may be disposed on the second electrode 210. Furthermore, the second organic encapsulation layer 220b may be disposed on the first inorganic encapsulation layer 220a. Furthermore, the third inorganic encapsulation layer 220c may be disposed on the second organic encapsulation layer 220b. The first inorganic encapsulation layer 220a and the third inorganic encapsulation layer 220c of encapsulation units 220a, 220b, and 220c may be formed of inorganic materials such as silicon nitride (SiNx) or silicon oxide (SiOx). The second organic encapsulation layer 220b of encapsulation units 220a, 220b, and 220c may be formed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0116] Figure 6 This is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure.

[0117] Combining Figure 5 It is described herein, and redundant descriptions will be omitted or simplified. For example, the substrate 110, the first buffer layer 111, the first gate insulating layer 112, the first interlayer insulating layer 113, the second buffer layer 114, the second gate insulating layer 115, the second interlayer insulating layer 116, the first planarization layer 117, the second planarization layer 118, the connecting electrode 150, the auxiliary electrode 160, the first electrode 170, the dam portion 180, the spacer portion 190, the light-emitting structure 200, the second electrode 210, the packaging units 220a, 220b and 220c, the first thin-film transistor 120 and the second thin-film transistor 130 are substantially the same. Therefore, the omitted or simplified descriptions are essentially the same as those of the first thin-film transistor 120 and the second thin-film transistor 130. Figure 5 Basically the same Figure 6 Redundant description of components.

[0118] Reference Figure 6According to another exemplary embodiment of the present disclosure, the display device 100 may include a substrate 110, a first buffer layer 111, a first thin-film transistor 120, a second thin-film transistor 130, a first gate insulating layer 112, a first interlayer insulating layer 113, a second buffer layer 114, a second gate insulating layer 115, a second interlayer insulating layer 116, a first planarization layer 117, a second planarization layer 118, a storage capacitor 140, a light-blocking layer 310, a protrusion pattern 320, a connecting electrode 150, a dam 180, an auxiliary electrode 160, a first electrode 170, a spacer 190, a light-emitting structure 200, a second electrode 210, and packaging units 220a, 220b, and 220c. Furthermore, the first active layer 121 of the first thin-film transistor 120 may be formed of LTPS, and the second active layer 131 of the second thin-film transistor 130 may be formed of oxide semiconductor.

[0119] The display device 100 according to an exemplary embodiment of the present disclosure may further include a light-blocking layer 310 in the region overlapping with the second active layer 131 of the second thin-film transistor 130 to block external light capable of altering the characteristics of the second active layer 131 of the second thin-film transistor 130 formed of oxide semiconductor, and / or light refracted and incident from the light-emitting structure 200. In the process of forming the second capacitor electrode 142 of the storage capacitor 140, the light-blocking layer 310 may be formed together with the second capacitor electrode 142 of the storage capacitor 140. In one embodiment, the light-blocking layer 310 includes a first portion located below the second active layer 131 of the second thin-film transistor 130 and a second portion extending upward to horizontally overlap at least a portion of the second active layer 131, thereby blocking external light.

[0120] The protrusion pattern 320 may also be included in the region overlapping with the light-blocking layer 310 below the light-blocking layer 310. The protrusion pattern 320 may include a first protrusion pattern 321 and a second protrusion pattern 322 spaced apart from the first protrusion pattern 321. The first protrusion pattern 321 and the second protrusion pattern 322 may be formed together in the process of forming the first gate 124 of the first thin-film transistor 120. That is, the first protrusion pattern 321 and the second protrusion pattern 322 may be formed together in the process of forming the first capacitor electrode 141 of the storage capacitor 140. The distance between the first protrusion pattern 321 and the second protrusion pattern 322 may be formed to be greater than the width of the second channel region 131a of the second active layer 131. That is, the first protrusion pattern 321 and the second protrusion pattern 322 may be formed to not overlap with the second channel region 131a of the second active layer 131. For example, the first protrusion pattern 321 may be formed to overlap with the second source region 131b or the second drain region 131c of the second active layer 131. In addition, the second protrusion pattern 322 may be formed to overlap with the second drain region 131c or the second source region 131b of the second active layer 131.

[0121] Because of the first protrusion pattern 321 and the second protrusion pattern 322, the first interlayer insulating layer 113 sequentially formed on the first protrusion pattern 321 and the second protrusion pattern 322, and / or a portion of the light blocking layer 310 corresponding to the first protrusion pattern 321 and the second protrusion pattern 322, steps resembling the shape of the first protrusion pattern 321 and the second protrusion pattern 322 can be formed in the direction of the second active layer 131. For example, a portion of the first interlayer insulating layer 113 can be disposed on the first gate insulating layer 112, extending along the side surface of the first protrusion pattern 321 or the second protrusion pattern 322 and forming a step shape on the top surface of the first protrusion pattern 321 or the second protrusion pattern 322. The light blocking layer 310 may include a first portion disposed below the second active layer 131 and a second portion extending upward to horizontally overlap with the channel region 131a of the second active layer 131. The first and second portions of the light-blocking layer 310 can be disposed in a stepped manner on a portion of the first interlayer insulating layer 113. In one embodiment, the stepped manner can also be formed along the first interlayer insulating layer 113. (See reference...) Figure 6 The light blocking layer 310 may further include a third portion extending upward from the other end of the first portion, such that the first, second, and third portions of the light blocking layer 310 form a recess or groove. Because a step is formed in the light blocking layer 310, the light blocking layer 310 can block external light incident on the second channel region 131a of the second active layer 131 through the lower and side surfaces of the second active layer 131, and / or light emitted from the light-emitting structure 200.

[0122] In addition, such as Figure 6As shown, the second lower buffer layer 114a can be formed on the light blocking layer 310 and can have a recess or groove. The channel region 131a of the second active layer 131 can be disposed on the bottom surface of the recess, such that the light blocking layer 310 and the side surface of the channel region 131a of the second active layer 131 horizontally overlap. At least one or both of the source region 131b or the drain region 131c can extend from the channel region 131a (at the bottom surface of the recess) to the top surface of the second lower buffer layer 114a.

[0123] The light-blocking layer 310 can be electrically connected to the second capacitor electrode 142. Charge can be applied to the light-blocking layer 310. To prevent the charge charged in the light-blocking layer 310 from transferring to the second active layer 131 of the second thin-film transistor 130, the second buffer layer 114 is preferably formed of multiple layers. When the second buffer layer 114 is formed of multiple layers, the uppermost layer of the second buffer layer 114 in contact with the second active layer 131 can be formed of a silicon oxide (SiOx) material with a low hydrogen content. For example, the uppermost layer of the second buffer layer 114 can be formed of a silicon dioxide (SiO2) material. Furthermore, at least one silicon nitride (SiNx) material layer with high insulating properties can be disposed between the uppermost layer formed of the silicon oxide (SiOx) material and the light-blocking layer 310. For example, as... Figure 6 As shown, when the second buffer layer 114 is formed as a double layer, the second buffer layer 114 may include a second lower buffer layer 114a disposed on the photoblocking layer 310 and a second upper buffer layer 114b disposed on the second lower buffer layer 114a. The second upper buffer layer 114b, which is in direct contact with the lower surface of the second active layer 131, may have a relatively lower hydrogen content than the second lower buffer layer 114a. Furthermore, the second lower buffer layer 114a disposed between the photoblocking layer 310 and the second upper buffer layer 114b may have higher insulation properties than the second upper buffer layer 114b. The second upper buffer layer 114b, which is in direct contact with the second active layer 131 of the second thin-film transistor 130, may be formed of silicon oxide (SiOx). For example, the second upper buffer layer 114b may be formed of silicon dioxide (SiO2). Furthermore, the second lower buffer layer 114a disposed between the second upper buffer layer 114b and the photoblocking layer 310 may be formed of silicon nitride (SiNx).

[0124] As described above, since the first protrusion pattern 321 and the second protrusion pattern 322 are formed beneath the light-blocking layer 310, steps corresponding to the first protrusion pattern 321 and the second protrusion pattern 322 are formed in the light-blocking layer. Furthermore, these steps can block external light incident on the second channel region 131a of the second active layer 131 through the lower and side surfaces of the second active layer 131, and / or light emitted from the light-emitting structure 200. Therefore, by preventing changes in the oxide semiconductor element due to light, a highly reliable display device can be provided.

[0125] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and are not limiting of the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0126] Cross-references to related applications

[0127] This application claims the benefit and priority of Korean Patent Application No. 10-2020-0173032, filed in Korea on December 11, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. An organic light-emitting display device, the organic light-emitting display device comprising: A substrate, the substrate comprising a first substrate, a second substrate, and an inorganic insulating layer disposed between the first substrate and the second substrate; A first transistor is disposed on the substrate, and the first transistor includes a first active layer, a first gate, a first source, and a first drain. The second transistor is disposed on the substrate and includes a second active layer disposed in a different layer from the first active layer, a second gate, and a second source and a second drain disposed in the same layer as the first source and the first drain. A storage capacitor, the storage capacitor including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode and the first gate are disposed on the same layer; A first planarization layer is disposed on the first source, the first drain, the second source, and the second drain; An auxiliary electrode is disposed on the first planarization layer and is connected to the second drain electrode through a contact hole in the first planarization layer. A second planarization layer is disposed on the auxiliary electrode; A light-emitting element is disposed on the second planarization layer and includes a light-emitting layer, a cathode, and an anode connected to the auxiliary electrode through a contact hole in the second planarization layer; as well as The encapsulation unit is disposed on the light-emitting element and includes a first inorganic layer, a second organic layer and a third inorganic layer.

2. The organic light-emitting display device according to claim 1, further comprising: A color filter is located on the light-emitting structure corresponding to each sub-pixel.

3. The organic light-emitting display device according to claim 1, further comprising: Touch sensing unit and display panel driving circuit, and The display panel driving circuit includes a touch sensing driving unit.

4. The organic light-emitting display device according to claim 1, further comprising: A dam section, wherein the dam section is disposed on the anode and the second planarization layer, and The embankment includes an opening for exposing a portion of the anode.

5. The organic light-emitting display device according to claim 4, further comprising: A spacer portion is provided on the embankment.

6. The organic light-emitting display device according to claim 5, in, The light-emitting structure is configured to cover the spacer portion.

7. The organic light-emitting display device according to claim 1, further comprising: A light-blocking layer, wherein the light-blocking layer is configured to overlap with the second active layer of the second transistor, and The light-blocking layer and the second capacitor electrode are disposed on the same layer.

8. The organic light-emitting display device according to claim 7, in, The light-blocking layer is formed of the same material as the second capacitor electrode.

9. The organic light-emitting display device according to claim 8, in, The first capacitor electrode is formed of the same material as the second capacitor electrode.

10. An organic light-emitting display device, the organic light-emitting display device comprising: A substrate, the substrate comprising a first substrate, a second substrate, and an inorganic insulating layer disposed between the first substrate and the second substrate; A first transistor, the first transistor being disposed on the substrate and including a first active layer; The second transistor is disposed on the substrate and includes a second active layer; as well as A storage capacitor, comprising a first capacitor electrode and a second capacitor electrode, In this configuration, the first active layer of the first transistor and the second active layer of the second transistor are disposed in different layers. The first capacitor electrode and the first gate of the first transistor are disposed on the same layer, and The storage capacitor is disposed below the second active layer of the second transistor.

11. The organic light-emitting display device according to claim 10, further comprising: A light-emitting element is disposed on the first transistor and the second transistor, and includes an anode, a light-emitting layer and a cathode; as well as A color filter, wherein the color filter is configured to overlap with the light-emitting structure.

12. The organic light-emitting display device according to claim 10, further comprising: Touch sensing unit and display panel driving circuit, and The display panel driving circuit includes a touch sensing driving unit.

13. The organic light-emitting display device according to claim 11, further comprising: A dam section, the dam section being disposed on the anode and the second planarization layer, and The embankment includes an opening for exposing a portion of the anode.

14. The organic light-emitting display device according to claim 13, further comprising: A spacer portion is provided on the embankment.

15. The organic light-emitting display device according to claim 14, in, The light-emitting structure is configured to cover the spacer portion.

16. The organic light-emitting display device according to claim 10, further comprising: A light-blocking layer, wherein the light-blocking layer is configured to overlap with the second active layer of the second transistor, and The light-blocking layer and the second capacitor electrode are disposed on the same layer.

17. The organic light-emitting display device according to claim 16, in, The light-blocking layer is formed of the same material as the second capacitor electrode.

18. The organic light-emitting display device according to claim 17, in, The first capacitor electrode is formed of the same material as the second capacitor electrode.

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