Display device

Abstract

This disclosure relates to a display device, the display device comprising: a first thin-film transistor, the first thin-film transistor including a first semiconductor layer comprising silicon semiconductor and a first gate electrode insulated from the first semiconductor layer; a first interlayer insulating layer covering the first gate electrode; a second thin-film transistor disposed on the first interlayer insulating layer and including a second semiconductor layer comprising oxide semiconductor and a second gate electrode insulated from the second semiconductor layer; a second interlayer insulating layer covering the second gate electrode; a first power supply voltage line disposed on the second interlayer insulating layer; a first planarization layer covering the first power supply voltage line; and a data line disposed on the first planarization layer and at least partially overlapping the first power supply voltage line.

Description

[0001] This application is a divisional application of the invention patent application filed on January 14, 2021, with application number 202110048614.7 and entitled "Display Device".

[0002] Cross-references to related applications

[0003] This application claims priority and benefit to Korean Patent Application No. 10-2020-0015203, filed on February 7, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0004] This disclosure relates to display devices, and more specifically, to display devices driven by thin-film transistors comprising silicon semiconductors and thin-film transistors comprising oxide semiconductors. Background Technology

[0005] Generally, a display device includes a display element capable of emitting light and a driving circuit for controlling the electrical signals applied to the display element. The driving circuit includes thin-film transistors, storage capacitors, and multiple wirings.

[0006] To precisely control the light emission of display elements and the brightness level of the light emitted from them, the number of thin-film transistors electrically connected to a single display element has been increased. Therefore, active research has been conducted to achieve higher integration and reduced power consumption in display devices. Summary of the Invention

[0007] Exemplary embodiments of this disclosure include a display device driven by thin-film transistors comprising silicon semiconductors and thin-film transistors comprising oxide semiconductors, thereby improving the integration of the display device while reducing the power consumption of the display device.

[0008] Additional aspects will be set forth in part in the following description, and will be partly apparent from the description or may be learned by practicing the exemplary embodiments provided in this disclosure.

[0009] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate including a display area in which display elements are disposed; a first thin-film transistor disposed in the display area and including a first semiconductor layer comprising silicon semiconductor and a first gate electrode insulated from the first semiconductor layer; a first interlayer insulating layer covering the first gate electrode; a second thin-film transistor disposed on the first interlayer insulating layer and including a second semiconductor layer comprising oxide semiconductor and a second gate electrode insulated from the second semiconductor layer; a second interlayer insulating layer covering the second gate electrode; a first power supply voltage line disposed on the second interlayer insulating layer; a first planarization layer covering the first power supply voltage line; and a data line disposed on the first planarization layer and at least partially overlapping the first power supply voltage line.

[0010] The display device may further include: a node connection line disposed on the second interlayer insulating layer, and the node connection line may have one end electrically connected to the first gate electrode and another end electrically connected to the second semiconductor layer.

[0011] The display device may further include: a second power supply voltage line, which is disposed on the first planarization layer and electrically connected to the first power supply voltage line.

[0012] The second power supply voltage line may overlap with the second semiconductor layer.

[0013] When viewed in a plan view, a portion of the second power supply voltage line may be positioned between the data line and the node connection line.

[0014] The second thin-film transistor may further include a third gate electrode disposed below the second semiconductor layer, and the third gate electrode may overlap with the second semiconductor layer.

[0015] The display device may further include: a first capacitor, the first capacitor including a lower electrode disposed on the same layer as the first gate electrode and an upper electrode disposed above the lower electrode, wherein the upper electrode may be disposed on the same layer as the third gate electrode.

[0016] The upper electrode of the first capacitor can be electrically connected to the first power supply voltage line.

[0017] The display device may further include a second capacitor, the second capacitor including a lower electrode disposed on the same layer as the first gate electrode and an upper electrode disposed on the same layer as the second semiconductor layer.

[0018] The upper electrode of the second capacitor may include an oxide semiconductor.

[0019] The upper electrode of the second capacitor may extend from the second semiconductor layer.

[0020] The display device may further include: a second planarization layer covering the data line, and the display element may be an organic light-emitting diode (OLED) disposed on the second planarization layer.

[0021] According to an exemplary embodiment of the present disclosure, the display device includes: a substrate including a display area in which display elements are disposed; a first thin-film transistor disposed in the display area and including a first semiconductor layer comprising silicon semiconductor and a first gate electrode insulated from the first semiconductor layer; a first interlayer insulating layer covering the first gate electrode; a second thin-film transistor disposed on the first interlayer insulating layer and including a second semiconductor layer comprising oxide semiconductor and a second gate electrode insulated from the second semiconductor layer; a first power supply voltage line disposed in the display area and extending in a first direction; a second power supply voltage line extending in the first direction and electrically connected to the first power supply voltage line; and a data line spaced apart from the second power supply voltage line, extending in the first direction, and at least partially overlapping the first power supply voltage line.

[0022] The first power supply voltage line can be arranged between the data line and the first gate electrode.

[0023] The second power supply voltage line may overlap with the second semiconductor layer.

[0024] The display device may further include: a node connection line having one end electrically connected to the first gate electrode and another end electrically connected to the second semiconductor layer.

[0025] When viewed in a plan view, a portion of the second power supply voltage line may be positioned between the data line and the node connection line.

[0026] The second thin-film transistor may further include a third gate electrode disposed below the second semiconductor layer, and the third gate electrode may overlap with the second semiconductor layer.

[0027] The display device may further include a capacitor, the capacitor including a lower electrode disposed on the same layer as the first gate electrode and an upper electrode disposed on the same layer as the second semiconductor layer.

[0028] The upper electrode of the capacitor may extend from the second semiconductor layer.

[0029] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate including a first region, a second region, and a curved region positioned between the first region and the second region, the first region including a display region and a peripheral region surrounding the display region, the second region also including the peripheral region, the substrate being curved; a driver disposed in the second region to supply scan signals and data signals to respective scan lines and data lines positioned in the display region; a display member disposed in the display region to display an image and including a plurality of pixels, each including a display element and pixel circuitry, the pixel circuitry including at least one first thin-film transistor and at least one second thin-film transistor different from the first thin-film transistor, and receiving scan signals and data signals supplied from the driver to control the light emission of the display element; a sensing member disposed on the display member to sense external input; and a polarizing member disposed on the sensing member, the polarizing member including an anti-reflection layer to reduce the reflectivity of light incident from the outside toward the display member, or the polarizing member including a lens layer to enhance the light output efficiency of light emitted from the display member or reduce chromatic aberration. The first thin-film transistor may include a first semiconductor layer comprising silicon semiconductor and a first gate electrode insulated from the first semiconductor layer, a first interlayer insulating layer may cover the first gate electrode, and the second thin-film transistor may be disposed on the first interlayer insulating layer, and the second thin-film transistor may include a second semiconductor layer comprising oxide semiconductor and a second gate electrode insulated from the second semiconductor layer.

[0030] The display device may further include: a second interlayer insulating layer covering the second gate electrode; a first power supply voltage line disposed on the second interlayer insulating layer; a first planarization layer covering the first power supply voltage line; and a data line disposed on the first planarization layer and at least partially overlapping the first power supply voltage line. Attached Figure Description

[0031] The above and other aspects and features of this disclosure will become more apparent from the following description of exemplary embodiments taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0033] Figure 2 This is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present disclosure;

[0034] Figure 3 This is a schematic layout diagram showing the positions of a plurality of thin-film transistors and capacitors arranged in a pair of pixel circuits of a display device according to an exemplary embodiment of the present disclosure;

[0035] Figure 4 It is along Figure 3 A schematic cross-sectional view of the display device taken by line I-I', and Figure 5 It is along Figure 3 A schematic cross-sectional view of the display device taken from line II-II';

[0036] Figures 6A to 6G It is for each layer Figure 3 A schematic layout diagram of the components;

[0037] Figure 7 and Figure 8 Is only shown Figure 3 A layout diagram of the local configuration;

[0038] Figure 9 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0039] Figures 10A to 10C It is intercepted along line III-III' Figure 9 A schematic cross-sectional view of the display device;

[0040] Figure 11 It is a schematic representation of what appears after bending. Figure 9 A perspective view of a portion of the display device; and

[0041] Figure 12 It is along Figure 11 The line IV-IV' intercepted Figure 11 A schematic cross-sectional view of the display device.

[0042] because Figures 1 to 12 The accompanying drawings are for illustrative purposes only, and therefore the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. Detailed Implementation

[0043] Now, reference will be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this respect, the exemplary embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, exemplary embodiments are described below only with reference to the accompanying drawings to explain aspects of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the present disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0044] It will be understood that while the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0045] As used herein, unless otherwise explicitly stated in the context, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well.

[0046] It will be understood that terms such as “comprising,” “including,” and “having” as used herein indicate the presence of the said features and elements, but do not preclude the presence or addition of one or more other features or elements.

[0047] It will be understood that when a layer, region, or element is referred to as being “on” another layer, region, or element, that layer, region, or element may be “directly on” the other layer, region, or element, or may be “indirectly on” the other layer, region, or element, with one or more intermediate layers, regions, or elements between the layer, region, or element and the other layer, region, or element.

[0048] In this specification, the expression "A and / or B" means only A, only B, or both A and B. Throughout this disclosure, the expression "at least one of A and B" means only A, only B, or both A and B.

[0049] In the following exemplary embodiments, the expression "the line extends in a first direction or a second direction" as used herein may include not only the case where the line extends in a straight line shape, but also the case where the line extends in a zigzag or curved shape along the first or second direction.

[0050] In the following exemplary embodiments, the expression "when viewed in a plan view," as used herein, can refer to the case where the object is viewed from above, and the expression "when viewed in a cross-sectional view," as used herein, can refer to the case where a cross-section obtained by vertically cutting the object is viewed from the side. In the following exemplary embodiments, the expression "the first element overlaps with the second element" can mean that the first element is arranged above or below the second element. In other words, the first element overlaps with the second element in a direction perpendicular to the top surface of the substrate.

[0051] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure.

[0052] The display device according to exemplary embodiments of this disclosure can be implemented as an electronic device, such as a smartphone, mobile phone, smartwatch, navigation device, game console, television (TV), vehicle head unit, vehicle dashboard, notebook computer, laptop computer, tablet computer, personal media player (PMP), and personal digital assistant (PDA). Furthermore, the electronic device can be a flexible device.

[0053] The substrate 100 can be divided into a display area DA in which an image is displayed and a peripheral area PA arranged around the display area DA.

[0054] The substrate 100 may comprise various materials, such as glass, metal, or plastic. According to exemplary embodiments of the present disclosure, the substrate 100 may comprise a flexible material. A substrate 100 comprising the flexible material refers to a substrate that is well-bendable, foldable, or rollable. The flexible substrate 100 may comprise, for example, ultrathin glass, metal, or plastic. For example, the substrate 100 may comprise, for example, glass materials and / or polymer resins, and may have a multilayer structure.

[0055] Each pixel PX, including a display element such as an organic light-emitting diode (OLED), can be arranged in the display area DA of the substrate 100. Multiple pixels PX can be provided. The pixels PX can be arranged in various forms, such as stripes, pentiles, or mosaics, and can realize images.

[0056] When viewed in a plan view, the display area DA can have the following characteristics: Figure 1 The rectangular shape shown is illustrated. In exemplary embodiments of this disclosure, the display area DA may have, for example, a polygonal shape (e.g., a triangular shape, a pentagonal shape, a hexagonal shape, etc.), a circular shape, an elliptical shape, or an irregular shape. In exemplary embodiments of this disclosure, the display area DA may approximately have a quadrilateral shape, and the four corner portions of the display area DA may each have a circular shape with a predetermined curvature.

[0057] The peripheral region PA of the substrate 100 is the area arranged around the display area DA, and may be an area in which no image is displayed. The peripheral region PA may surround the display area DA, and may also have a rectangular shape on the outside. However, this disclosure is not limited thereto, and the shapes of the display area DA and the peripheral region PA may have various shapes and may be designed relative to each other. Various lines and pads, etc., may be positioned in the peripheral region PA, said various lines being configured to transmit electrical signals to be applied to the display area DA, and a printed circuit board or driver integrated circuit (IC) chip is attached to said pads.

[0058] In the following description, for convenience, display devices incorporating organic light-emitting diodes (OLEDs) as display elements will be described. However, this disclosure is not limited thereto. For example, display devices may include various types of display devices, such as liquid crystal displays, electrophoretic displays, field emission displays, surface conduction electron emission displays, plasma displays, cathode ray displays, and inorganic electroluminescent (EL) displays.

[0059] Figure 2 This is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present disclosure.

[0060] Reference Figure 2 A pixel PX may include an organic light-emitting diode (OLED) as a display element and pixel circuitry connected to the OLED. The pixel circuitry may include a plurality of transistors, a first capacitor Cst, and a second capacitor Cbt, such as a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The pixel circuitry may be connected to signal lines, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a power supply voltage line PL. The signal lines may include a data line DL, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and an emission control line EL. In an exemplary embodiment of this disclosure, at least one of the signal lines, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and / or the power supply voltage line PL may be shared with adjacent pixels.

[0061] The power supply voltage line PL can be configured to transmit a first power supply voltage ELVDD to a first transistor T1. The first initialization voltage line VIL1 can be configured to transmit a first initialization voltage Vint1, used to initialize the first transistor T1, to the pixel PX. The second initialization voltage line VIL2 can be configured to transmit a second initialization voltage Vint2, used to initialize the organic light-emitting diode (OLED), to the pixel PX.

[0062] The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the transmit control line EL, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 can extend along the first direction DR1 and can be spaced apart from each other in each row. The data line DL and the power supply voltage line PL can extend along the second direction DR2 and can be spaced apart from each other in each column.

[0063] Figure 2 It is shown that the third transistor T3 and the fourth transistor T4 in the first transistor T1 to the seventh transistor T7 are each implemented as an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (NMOS) and the other transistors in the first transistor T1 to the seventh transistor T7 are each implemented as a p-channel MOSFET (PMOS).

[0064] The first transistor T1 can be connected to the power supply voltage line PL via the fifth transistor T5, and can be electrically connected to the anode of the organic light-emitting diode (OLED) via the sixth transistor T6. The first transistor T1 functions as a driving transistor and can be configured to receive the data signal DATA and supply a driving current I to the OLED according to the switching operation of the second transistor T2, which functions as a switching transistor. OLED .

[0065] The gate electrode of the first transistor T1 can be connected to the first electrode CE1 of the first capacitor Cst, the source electrode of the first transistor T1 can be connected to the power supply voltage line PL via the fifth transistor T5, and the drain electrode of the first transistor T1 can be electrically connected to the anode of the organic light-emitting diode OLED via the sixth transistor T6.

[0066] The second transistor T2 can be connected to the first scan line SL1 and the data line DL, and is connected to the power supply voltage line PL through the fifth transistor T5. The second transistor T2 can be turned on according to the first scan signal Sn received through the first scan line SL1 to perform a switching operation to transmit the data signal DATA to the data line DL to the node N1. For example, the gate electrode of the second transistor T2 can be connected to the first scan line SL1, the source electrode of the second transistor T2 can be connected to the data line DL, and the drain electrode of the second transistor T2 can be connected to the node N1 and the source electrode of the first transistor T1.

[0067] The third transistor T3, used as a compensation transistor, can be connected to the fourth scan line SL4 and can be connected to the organic light-emitting diode (OLED) via the sixth transistor T6. The third transistor T3 can be turned on according to the fourth scan signal Sn' received through the fourth scan line SL4 to connect the gate electrode and drain electrode of the first transistor T1, so as to connect the first transistor T1 in a diode manner.

[0068] A fourth transistor T4, used as an initialization transistor, can be connected to a third scan line SL3, which is a previous scan line, and a first initialization voltage line VIL1. It can be turned on according to a third scan signal Sn-1, which is a previous scan signal received via the third scan line SL3, to transfer the first initialization voltage Vint1 from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1, thereby initializing the voltage at the gate electrode of the first transistor T1. For example, the drain electrode of the fourth transistor T4 can be connected to the gate electrode of the first transistor T1 and the drain electrode of the third transistor T3. The third transistor T3 and the fourth transistor T4 can each be configured to have a dual-gate structure to cut off leakage current.

[0069] The fifth transistor T5, used as the operation control transistor, and the sixth transistor T6, used as the light emission control transistor, can be connected to the emitter control line EL and can be simultaneously turned on according to the emitter control signal En received through the emitter control line EL to form a current path, thereby driving the current I. OLED The power supply voltage line PL flows to the organic light-emitting diode (OLED).

[0070] The seventh transistor T7 can be connected to the second scan line SL2, which is the next scan line, and the second initialization voltage line VIL2. It can be turned on according to the second scan signal Sn+1 received via the second scan line SL2 as the next scan signal, to transmit the second initialization voltage Vint2 from the second initialization voltage line VIL2 to the organic light-emitting diode (OLED) to initialize the OLED. The seventh transistor T7 can be configured differently. For example, in an exemplary embodiment of this disclosure, the drain electrode of the seventh transistor T7 can be connected to the first initialization voltage line VIL1 (not the second initialization voltage line VIL2) and the source electrode of the fourth transistor T4. In an exemplary embodiment of this disclosure, the gate electrode of the seventh transistor T7 can be connected to the third scan line SL3 instead of the second scan line SL2, and the drain electrode of the seventh transistor T7 can be connected to the first initialization voltage line VIL1 (not the second initialization voltage line VIL2) and the source electrode of the fourth transistor T4. In an exemplary embodiment of this disclosure, the seventh transistor T7 can be omitted.

[0071] The first capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 may be connected to the gate electrode of the first transistor T1, and the second electrode CE2 may be connected to the power supply voltage line PL. The first capacitor Cst may be configured to store and hold a voltage corresponding to the difference between the voltage of the power supply voltage line PL and the voltage of the gate electrode of the first transistor T1, so as to maintain the voltage applied to the gate electrode of the first transistor T1.

[0072] The second capacitor Cbt may include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 may be connected to the gate electrode of the first scan line SL1 and the second transistor T2. The fourth electrode CE4 may be connected to the gate electrode of the first transistor T1 and the first electrode CE1 of the first capacitor Cst. The second capacitor Cbt is a boost capacitor. When the first scan signal Sn of the first scan line SL1 is a voltage used to turn off the second transistor T2, the second capacitor Cbt may increase the voltage at node N2 to reduce the voltage that displays black (black voltage). Although a structure with seven transistors and two capacitors is shown in the exemplary embodiments of this disclosure above, this disclosure is not limited thereto, and the number of transistors and the number of capacitors may be varied.

[0073] An organic light-emitting diode (OLED) may include a pixel electrode and a counter electrode, and the counter electrode may be configured to receive a second power supply voltage ELVSS. The pixel electrode may be the anode of the OLED, and the counter electrode may be the cathode of the OLED. The OLED may be configured to receive a drive current I from a first transistor T1. OLED It also emits light to display images.

[0074] The specific operation of each pixel PX according to an exemplary embodiment of this disclosure is as follows.

[0075] During the first initialization period, when the third scan signal Sn-1 is supplied through the third scan line SL3, the fourth transistor T4 can be turned on in response to the third scan signal Sn-1, and the first transistor T1 can be initialized by the first initialization voltage Vint1 supplied from the first initialization voltage line VIL1 through the fourth transistor T4 to the first transistor T1.

[0076] During the data programming period, when the first scan signal Sn and the fourth scan signal Sn' are supplied through the first scan line SL1 and the fourth scan line SL4, respectively, the second transistor T2 and the third transistor T3 can be turned on in response to the first scan signal Sn and the fourth scan signal Sn'. In this case, since the first transistor T1 has already been initialized during the first initialization period, the first transistor T1 can be connected to the turned-on third transistor T3 in a diode manner and forward biased. The voltage in the data signal DATA supplied from the data line DL through the second transistor T2, the first transistor T1, and the third transistor T3, which compensates for the threshold voltage (Vth) of the first transistor T1, can be applied to the gate electrode of the first transistor T1. The first power supply voltage ELVDD and the compensation voltage can be applied to the two terminals of the first capacitor Cst, and the charge corresponding to the voltage difference between the two terminals of the first capacitor Cst can be stored in the first capacitor Cst.

[0077] During the emission period, the fifth transistor T5 and the sixth transistor T6 can be turned on by the emission control signal En supplied from the emission control line EL. In this operation, the first power supply voltage ELVDD supplied from the power supply voltage line PL can be directed toward the organic light-emitting diode (OLED) through the fifth transistor T5, the first transistor T1, and the sixth transistor T6. A drive current I is generated based on the voltage difference between the gate electrode voltage of the first transistor T1 and the first power supply voltage ELVDD. OLED And drive current I OLED The organic light-emitting diode (OLED) can be supplied through the sixth transistor T6.

[0078] During the second initialization period, when the second scan signal Sn+1 is supplied through the second scan line SL2, the seventh transistor T7 can be turned on in response to the second scan signal Sn+1, and the organic light-emitting diode OLED can be initialized by the second initialization voltage Vint2 supplied from the second initialization voltage line VIL2 to the organic light-emitting diode OLED through the seventh transistor T7.

[0079] In this exemplary embodiment, at least one of the first transistors T1 to the seventh transistor T7 may include a semiconductor layer comprising an oxide semiconductor, and the other transistors of the first transistor T1 to the seventh transistor T7 may include a semiconductor layer comprising silicon (Si). Specifically, the first transistor T1, which directly affects the brightness of the display device, may be configured to include a semiconductor layer comprising polycrystalline silicon (p-Si) with high reliability, thereby realizing a high-resolution display device.

[0080] Because oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not large even when the driving time is long. That is, low-frequency driving is possible because the color change of the image due to the voltage drop is small even during low-frequency driving. Thus, oxide semiconductors have small leakage current. Therefore, when at least one of the third transistors T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 comprises oxide semiconductor, leakage current that may flow into the gate electrode of the first transistor T1 can be prevented, and power consumption can be reduced. In an exemplary embodiment of this disclosure, the semiconductor layer for each of the third transistor T3 and the fourth transistor T4 may comprise oxide semiconductor.

[0081] Figure 3 This is a schematic layout diagram showing the positions of a plurality of thin-film transistors and capacitors arranged in a pair of pixel circuits of a display device according to an exemplary embodiment of the present disclosure. Figure 4 It is along Figure 3 A schematic cross-sectional view of the display device taken by line I-I', and Figure 5 It is along Figure 3 A schematic cross-sectional view of the display device taken from line II-II'. Figures 6A to 6G It is for each layer Figure 3 A schematic layout diagram of the components. Figure 7 and Figure 8 Is only shown Figure 3 A layout diagram of a partial configuration. For example, Figure 7 It is a schematic layout diagram that includes a combination of three layers, the three layers including Figure 6E Schematic layout diagram Figure 6D Schematic layout diagram and Figure 6C Part of the schematic layout diagram. Figure 8 It is a schematic layout diagram that includes a combination of three layers, the three layers including Figure 6G Part of the schematic layout diagram Figure 6F A portion of the schematic layout diagram and Figure 6D A schematic layout diagram.

[0082] Figure 3 The pixel circuitry is shown for a pair of pixels (PX) arranged in the same row of adjacent columns. Figure 3 In the image, the pixel circuits of the pixels arranged in the left pixel region CA1 and the pixel circuits of the pixels arranged in the right pixel region CA2 have a bilaterally symmetrical structure.

[0083] Reference Figure 3According to an exemplary embodiment of the present disclosure, the pixel circuit of the display device can be connected to a first scan line 133 (SL1), a second scan line 133' (SL2), a third scan line SL3, a fourth scan line SL4, an emission control line 135 (EL), and an initialization voltage line extending in a first direction DR1, and can also be connected to a data line 181 (DL) and power supply voltage lines 172 (PL1) and 183 (PL2) extending in a second direction DR2 intersecting the first direction DR1. The initialization voltage line may include a first initialization voltage line 147 (VIL1) and a second initialization voltage line 174 (VIL2).

[0084] The pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor Cst, and a second capacitor Cbt.

[0085] In exemplary embodiments of this disclosure, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may each include a thin-film transistor comprising silicon semiconductor. The third transistor T3 and the fourth transistor T4 may each include a thin-film transistor comprising oxide semiconductor.

[0086] The second scan line 133' can be the first scan line SL1 in the next row. That is, Figure 3 The first scan line 133 shown can be the second scan line SL2 of the previous row. Figure 3 The diagram shows a seventh transistor T7 connected to pixels in the previous row and arranged in the pixel region of the current row, and a seventh transistor T7 connected to pixels in the current row and arranged in the pixel region of the next row. In the following description, for ease of illustration and description, the seventh transistor T7 arranged in the pixel region of the current row will be described as an example.

[0087] The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be arranged on the same layer and can comprise the same material. For example, the semiconductor layer can comprise polycrystalline silicon (p-Si). The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be connected to each other and can be bent in various shapes. The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be integrally formed and therefore can each be part of an integrally formed layer. The integrally formed, co-located, and bent semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 will also be described later. Figure 6A As shown in the image.

[0088] The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may each include a channel region and source and drain regions located on either side of the channel region. For example, the source and drain regions may each be doped with impurities, and the impurities may include N-type or P-type impurities. The source and drain regions may correspond to the source electrode and drain electrode, respectively. The source and drain regions may vary from one another depending on the characteristics of the transistor. In the following text, the terms "source region" and "drain region" are used instead of source electrode and drain electrode.

[0089] The first transistor T1 may include a first semiconductor layer and a first gate electrode G1. The first semiconductor layer may include a first channel region A1 and a first source region S1 and a first drain region D1 located on both sides of the first channel region A1. Because the first semiconductor layer has a curved shape, the first channel region A1 may be longer than the other channel regions A2 to A7. For example, the first semiconductor layer may be bent multiple times, such as… " The first channel region A1 can be curved and may have a tortuous or zigzag shape. Because the first channel region A1 is formed long, the driving range of the gate voltage applied to the first gate electrode G1 can be widened. Moreover, by forming a curved first channel region A1, the first channel region A1 can be extended in a narrow space. Therefore, the color gradation of the light emitted from the organic light-emitting diode OLED can be controlled more precisely, thereby enhancing the display quality. In an exemplary embodiment of this disclosure, the first semiconductor layer may have a straight shape rather than a curved shape. The first gate electrode G1 is a separate pattern and may be provided to overlap with the first channel region A1, and the first gate insulating layer ( Figure 4 The first gate electrode 112 is disposed between the first gate electrode G1 and the first channel region A1. Thus, the first semiconductor layer may include silicon semiconductor, and the first gate electrode G1 may be insulated from the first semiconductor layer via the first gate insulating layer 112.

[0090] The first capacitor Cst can be arranged to overlap with the first transistor T1, and can include a first electrode CE1 and a second electrode CE2. The first gate electrode G1 can serve not only as the control electrode of the first transistor T1, but also as the first electrode CE1 of the first capacitor Cst. That is, the first gate electrode G1 and the first electrode CE1 can be integrally formed. The second electrode CE2 of the first capacitor Cst can be provided to overlap with the first electrode CE1, and a second gate insulating layer ( Figure 4 The second gate insulating layer 113 is disposed between the second electrode CE2 and the first electrode CE1 of the first capacitor Cst. The area of ​​the second electrode CE2 may be larger than the area of ​​the first gate electrode G1, and the second electrode CE2 may cover all or part of the first gate electrode G1. In this case, the second gate insulating layer 113 may serve as the dielectric layer of the first capacitor Cst. The second gate insulating layer 113 may include a dielectric material, and the storage capacitance may be determined by the charge charged into the first capacitor Cst and the voltage between the first electrode CE1 and the second electrode CE2.

[0091] Node connection line 171 can be electrically connected to the first electrode CE1 of the first capacitor Cst and the third semiconductor layer AO3 of the third transistor T3. Node connection line 171 can also be electrically connected to the fourth electrode CE4 of the second capacitor Cbt and the fourth semiconductor layer AO4 of the fourth transistor T4. The second electrode CE2 can be electrically connected to the first power supply voltage line 172, and the first power supply voltage line 172 can be electrically connected to the second power supply voltage line 183. The first power supply voltage line 172 and the second power supply voltage line 183 can extend in the second direction DR2. The second electrode CE2 can extend in the first direction DR1 and can be used to transmit the first power supply voltage ELVDD in the first direction DR1. Therefore, multiple first power supply voltage lines 172 and second power supply voltage lines 183 and multiple second electrodes CE2 in the display area DA can form a grid structure.

[0092] The second transistor T2 may include a second semiconductor layer and a second gate electrode G2. The second semiconductor layer may include a second channel region A2 and a second source region S2 and a second drain region D2 located on both sides of the second channel region A2. The second source region S2 may be electrically connected to the data line 181, and the second drain region D2 may be connected to the first source region S1. The second gate electrode G2 may be provided as a portion of the first scan line 133.

[0093] The fifth transistor T5 may include a fifth semiconductor layer AS5 and a fifth gate electrode G5. The fifth semiconductor layer AS5 may include a fifth channel region A5 and a fifth source region S5 and a fifth drain region D5 located on both sides of the fifth channel region A5. The fifth source region S5 may be electrically connected to the first power supply voltage line 172, and the fifth drain region D5 may be connected to the first source region S1. The fifth gate electrode G5 may be provided as a portion of the emitter control line 135.

[0094] The sixth transistor T6 may include a sixth semiconductor layer AS6 and a sixth gate electrode G6. The sixth semiconductor layer AS6 may include a sixth channel region A6 and a sixth source region S6 and a sixth drain region D6 located on either side of the sixth channel region A6. The sixth source region S6 may be connected to the first drain region D1, and the sixth drain region D6 may be electrically connected to the pixel electrode of an organic light-emitting diode (OLED). Figure 5 (310). The sixth gate electrode G6 can be provided as part of the emitter control line 135.

[0095] The seventh transistor T7 may include a seventh semiconductor layer and a seventh gate electrode G7. The seventh semiconductor layer may include a seventh channel region A7 and a seventh source region S7 and a seventh drain region D7 located on both sides of the seventh channel region A7. The seventh source region S7 may be electrically connected to the second initialization voltage line 174, and the seventh drain region D7 may be connected to the sixth drain region D6. The seventh gate electrode G7 may be provided as a portion of the second scan line 133'.

[0096] A first interlayer insulating layer can be disposed on each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, which are silicon semiconductors. Figure 4 (114), and a third transistor T3 and a fourth transistor T4, each comprising an oxide semiconductor, may be disposed on the first interlayer insulating layer 114.

[0097] The third semiconductor layer AO3 of the third transistor T3 and the fourth semiconductor layer AO4 of the fourth transistor T4 can be disposed on the same layer and can comprise the same material. For example, the third semiconductor layer AO3 and the fourth semiconductor layer AO4 can comprise oxide semiconductors.

[0098] The semiconductor layer may each include a channel region and source and drain regions located on either side of the channel region. For example, the source and drain regions may be regions in which carrier concentration is increased through plasma treatment. The source and drain regions may correspond to source electrodes and drain electrodes, respectively. In the following, the terms "source region" and "drain region" are used instead of source electrode and drain electrode.

[0099] The third transistor T3 may include a third semiconductor layer AO3 comprising an oxide semiconductor and a third gate electrode G3. The third semiconductor layer AO3 may include a third channel region A3 and a third source region S3 and a third drain region D3 located on either side of the third channel region A3. The third source region S3 can be bridged to the first gate electrode G1 via node connection line 171. Furthermore, the third source region S3 may be connected to a fourth drain region D4 disposed on the same layer. The third drain region D3 may be electrically connected to the first semiconductor layer AS1 of the first transistor T1 and the sixth semiconductor layer AS6 of the sixth transistor T6. For example, one end of the connecting electrode 173 may be connected to the third drain region D3 of the third transistor T3, and the other end of the connecting electrode 173 may be connected to the sixth source region S6 of the sixth transistor T6. The third gate electrode G3 may be provided as a portion of the fourth scan line SL4.

[0100] The fourth transistor T4 may include a fourth semiconductor layer AO4 comprising an oxide semiconductor and a fourth gate electrode G4. The fourth semiconductor layer AO4 may include a fourth channel region A4 and a fourth source region S4 and a fourth drain region D4 located on either side of the fourth channel region A4. The fourth source region S4 can be connected via electrode 177 (see...). Figure 4 The fourth drain region D4 is electrically connected to the first initialization voltage line 147, and can be bridged to the first gate electrode G1 via node connection line 171. The fourth gate electrode G4 can be provided as a portion of the third scan line SL3.

[0101] Third gate insulating layer ( Figure 4 and Figure 5The third gate insulating layer 115 can be arranged to correspond to the channel region between the third semiconductor layer AO3 and the third gate electrode G3, and the channel region between the fourth semiconductor layer AO4 and the fourth gate electrode G4. Thus, the third semiconductor layer AO3 and the fourth semiconductor layer AO4 can each comprise an oxide semiconductor, and the third gate electrode G3 and the fourth gate electrode G4 can be insulated from the third semiconductor layer AO3 and the fourth semiconductor layer AO4 respectively via the third gate insulating layer 115.

[0102] The third electrode CE3 of the second capacitor Cbt can be provided as a portion of the first scan line 133 and can be connected to the second gate electrode G2. For example, the third electrode CE3 can be disposed on the same layer as the first gate electrode G1 (see...). Figure 6B The fourth electrode CE4 of the second capacitor Cbt can be arranged to overlap with the third electrode CE3 and can include an oxide semiconductor. The fourth electrode CE4 can be provided on the same layer as the third semiconductor layer AO3 of the third transistor T3 and the fourth semiconductor layer AO4 of the fourth transistor T4, and can be the region between the third semiconductor layer AO3 and the fourth semiconductor layer AO4 (see reference). Figure 4 , Figure 5 and Figure 6D Alternatively, the fourth electrode CE4 can be provided by extending from the fourth semiconductor layer AO4. Alternatively, the fourth electrode CE4 can be provided by extending from the third semiconductor layer AO3.

[0103] A second interlayer insulating layer can be disposed on each of the third transistor T3 and the fourth transistor T4, which are respectively oxide semiconductors. Figure 4 and Figure 5 (116), and a first power supply voltage line 172 and a node connection line 171 can be arranged on the second interlayer insulation layer 116.

[0104] A first planarization layer can be arranged on the first power supply voltage line 172. Figure 4 and Figure 5 (118), and the data line 181 and the second power supply voltage line 183 can extend in the second direction DR2 and be arranged on the first planarization layer 118.

[0105] In an exemplary embodiment of this disclosure, the first scan line 133, the second scan line 133', and the emission control line 135 may be arranged on the same layer as the first gate electrode G1 and may comprise the same material.

[0106] In exemplary embodiments of this disclosure, some lines may include two conductive layers disposed on two different layers. For example, the third scan line SL3 may include a lower scan line 143 and an upper scan line 163 disposed on different layers. The lower scan line 143 may be disposed on the same layer as the second electrode CE2 of the first capacitor Cst, and may include the same material as the second electrode CE2 of the first capacitor Cst. The upper scan line 163 may be disposed on the third gate insulating layer (… Figure 5 On (115). The lower scan line 143 can be arranged to at least partially overlap with the upper scan line 163. The lower scan line 143 and the upper scan line 163 correspond to portions of the third gate electrode G3 of the third transistor T3. Therefore, the third transistor T3 can have a dual-gate structure, which includes control electrodes located above and below the third semiconductor layer AO3, respectively.

[0107] The fourth scan line SL4 may include a lower scan line 145 and an upper scan line 165 disposed on different layers. The lower scan line 145 may be disposed on the same layer as the second electrode CE2 of the first capacitor Cst, and may include the same material as the second electrode CE2 of the first capacitor Cst. The upper scan line 165 may be disposed on the third gate insulating layer (…). Figure 4 On (115). The lower scan line 145 can be arranged to at least partially overlap with the upper scan line 165. The lower scan line 145 and the upper scan line 165 correspond to portions of the fourth gate electrode G4 of the fourth transistor T4. Therefore, the fourth transistor T4 can have a dual-gate structure, which includes control electrodes located above and below the semiconductor layer, respectively. The dual-gate structure can reduce leakage current due to the unique property of the electrical coupling between its two gates.

[0108] The initialization voltage line VIL may include a first initialization voltage line 147 and a second initialization voltage line 174 disposed on different layers. The first initialization voltage line 147 may be disposed on the same layer as the second electrode CE2 of the first capacitor Cst, and may contain the same material as the second electrode CE2 of the first capacitor Cst. The second initialization voltage line 174 may be disposed on the same layer as the first power supply voltage line 172, and may contain the same material as the first power supply voltage line 172.

[0109] In the following text, reference will be made to Figure 4 and Figure 5 The stacking order is described in detail in the structure of the display device according to exemplary embodiments of the present disclosure.

[0110] Figure 4 and Figure 5The cross-sections of the parts corresponding to the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the first capacitor Cst, the second capacitor Cbt, and the organic light-emitting diode OLED are shown, and some components may be omitted.

[0111] The substrate 100 may include, for example, glass, ceramic, metal, or flexible or bendable materials. When the substrate 100 includes a flexible or bendable material, it may include a polymer resin, such as polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), or cellulose acetate propionate (CAP).

[0112] The substrate 100 may have a single-layer or multi-layer structure comprising the materials described above. In the case of a multi-layer structure, in addition to the layer comprising a polymer resin, the substrate 100 may also include an inorganic layer. For example, the substrate 100 may include a first base layer 101, a first barrier layer 103, a second base layer 105, and a second barrier layer 107 sequentially stacked on a third-direction DR3. The first base layer 101 and the second base layer 105 may each comprise a polymer resin. For example, the first base layer 101 and the second base layer 105 may each comprise a transparent polymer resin. The first barrier layer 103 and the second barrier layer 107 are each barrier layers for preventing the penetration of external foreign matter. For example, the first barrier layer 103 and the second barrier layer 107 may each be a single layer or multiple layers comprising an inorganic material, such as silicon nitride (SiN). x ), silicon dioxide (SiO) x For example, silicon oxynitride (SiON) and / or silicon oxynitride (SiON).

[0113] A buffer layer 111 may be disposed on the substrate 100. The buffer layer 111 can be used to improve the smoothness of the upper surface of the substrate 100, and may include materials such as silicon oxide (SiO2). x The oxide layer and / or such as silicon nitride (SiN) x Nitride layers, such as silicon oxynitride (SiON).

[0114] A barrier layer may also be included between the substrate 100 and the buffer layer 111. The barrier layer may be used to prevent impurities from penetrating from the substrate 100 into the semiconductor layer, or to minimize the penetration of impurities from the substrate 100 into the semiconductor layer. The buffer layer 111 may include inorganic and / or organic materials such as oxides or nitrides, and may have a single-layer or multi-layer structure including inorganic and organic materials.

[0115] like Figure 6A As shown, the semiconductor layer AS of the first transistor T1, the semiconductor layer AS of the second transistor T2, the semiconductor layer AS of the fifth transistor T5, the semiconductor layer AS of the sixth transistor T6, and the semiconductor layer AS of the seventh transistor T7 can be arranged on the buffer layer 111.

[0116] The semiconductor layer AS may include: a first channel region A1, a first source region S1, and a first drain region D1 of the first semiconductor layer AS1 as the first transistor T1; a second channel region A2, a second source region S2, and a second drain region D2 of the second semiconductor layer AS2 as the second transistor T2; a fifth channel region A5, a fifth source region S5, and a fifth drain region D5 of the fifth semiconductor layer AS5 as the fifth transistor T5; a sixth channel region A6, a sixth source region S6, and a sixth drain region D6 of the sixth semiconductor layer AS6 as the sixth transistor T6; and a seventh channel region A7, a seventh source region S7, and a seventh drain region D7 of the seventh semiconductor layer as the seventh transistor T7. That is, each channel region, each source region, and each drain region of the first transistor T1 to the second transistor T2 and the fifth transistor T5 to the seventh transistor T7 may be a portion of the semiconductor layer AS. For example, the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be integrally formed, may be arranged on the same layer, and may be bent in various shapes. Figure 6A In this context, the semiconductor layer of the seventh transistor T7 can be a portion of the semiconductor layer extending from the previous row.

[0117] The first gate insulating layer 112 may be disposed on the semiconductor layer AS. The first gate insulating layer 112 may include an inorganic material comprising an oxide or a nitride. For example, the first gate insulating layer 112 may include, for example, silicon oxide (SiO2). x Silicon nitride (SiN) x It is selected from at least one of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), lanthanum oxide (La2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0118] like Figure 6B As shown, the gate electrode G1 of the first transistor T1, the gate electrode G2 of the second transistor T2, the gate electrode G5 of the fifth transistor T5, the gate electrode G6 of the sixth transistor T6, and the gate electrode G7 of the seventh transistor T7 can be arranged on the first gate insulating layer 112. Furthermore, the first scan line 133 and the emitter control line 135 can extend on the first gate insulating layer 112 in the first direction DR1. A portion of the first scan line 133 can be the third electrode CE3 of the second capacitor Cbt.

[0119] The gate electrode G1 of the first transistor T1 can be provided as an island. The gate electrode G2 of the second transistor T2 can be the part of the first scan line 133 that intersects with the semiconductor layer AS, for example, it can be the portion of the first scan line 133 that overlaps with the second channel region A2. The gate electrode G7 of the seventh transistor T7 can be the portion of the first scan line 133 that intersects with the semiconductor layer AS, or it can be a second scan line that is the first scan line in the next row. Figure 3 (133') of the part. Figure 6B An example is shown in which the gate electrode G7 of the seventh transistor T7, arranged in the previous row, is the portion of the first scan line 133 that intersects with the semiconductor layer AS, for example, the portion of the first scan line 133 that overlaps with the seventh channel region A7. The gate electrodes G5 of the fifth transistor T5 and G6 of the sixth transistor T6 can be the portions of the emission control line 135 that intersect with the semiconductor layer AS, for example, the portions of the emission control line 135 that overlap with the fifth channel region A5 and the sixth channel region A6, respectively.

[0120] The gate electrode G1 of the first transistor T1 can be used not only as the control electrode of the first transistor T1, but also as the first electrode CE1 of the first capacitor Cst.

[0121] The gate electrodes of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or copper (Cu), and may be single-layer or multi-layer containing one or more materials.

[0122] The second gate insulating layer 113 may be disposed on the gate electrode. The second gate insulating layer 113 may comprise an inorganic material comprising an oxide or a nitride. For example, the second gate insulating layer 113 may comprise, for example, silicon oxide (SiO2). x Silicon nitride (SiN) x It is selected from at least one of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), lanthanum oxide (La2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0123] As in Figure 6CAs shown, the second electrode CE2 can be disposed on the second gate insulating layer 113 to overlap with the first electrode CE1. The area of ​​the second electrode CE2 can be larger than the area of ​​the first electrode CE1. The second electrode CE2 may include an opening SOP. The opening SOP can be defined by removing a portion of the second electrode CE2 and can have a closed shape.

[0124] The second gate insulating layer 113 can be used as the dielectric layer of the first capacitor Cst. The second electrodes CE2 of adjacent pixels can be connected to each other via bridge 141. Bridge 141 can be a portion protruding from the second electrode CE2 in the first direction DR1, and can be integrally formed with the second electrode CE2.

[0125] The second electrode CE2 of the first capacitor Cst can be a single layer or multiple layers, wherein the single layer or multiple layers include at least one selected from, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0126] The first initialization voltage line 147, the lower scan line 143 of the third scan line SL3, and the lower scan line 145 of the fourth scan line SL4 may contain the same material as the second electrode CE2 of the first capacitor Cst, may extend in the first direction DR1, and may be disposed on the second gate insulating layer 113. The portion of the lower scan line 143 of the third scan line SL3 that overlaps with the semiconductor layer AO (e.g., overlaps with the fourth channel region A4) may be the lower gate electrode G4a of the fourth transistor T4. The portion of the lower scan line 145 of the fourth scan line SL4 that overlaps with the semiconductor layer AO (e.g., overlaps with the third channel region A3) may be the lower gate electrode G3a of the third transistor T3. For example, the first capacitor Cst may contain the first electrode CE1 disposed on the same layer as the first gate electrode G1 (see reference). Figure 6B The first gate electrode G1 is used as the first electrode CE1) and the second electrode CE2 is disposed above the first electrode CE1, wherein the second electrode CE2 is disposed on the same layer as the lower gate electrode G3a of the third transistor T3 and the lower gate electrode G4a of the fourth transistor T4 (see reference). Figure 6C ).

[0127] The first interlayer insulating layer 114 may be disposed on the second electrode CE2 of the first capacitor Cst, and may comprise an inorganic material containing oxides or nitrides. For example, the first interlayer insulating layer 114 may comprise, for example, silicon oxide (SiO2). x Silicon nitride (SiN) xIt is selected from at least one of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), lanthanum oxide (La2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0128] like Figure 6D As shown, the semiconductor layer AO, comprising an oxide semiconductor, can be disposed on the first interlayer insulating layer 114 and can include a zinc oxide (Zn) based material, such as zinc oxide, indium zinc oxide, and gallium indium zinc oxide. In exemplary embodiments of this disclosure, the semiconductor layer AO can include an In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO) semiconductor, wherein a metal such as indium (In), gallium (Ga), or tin (Sn) is contained in zinc oxide (ZnO).

[0129] The semiconductor layers of the third transistor T3 and the fourth transistor T4 may each include a channel region and source and drain regions located on either side of the channel region. The source and drain regions of the third transistor T3 and the fourth transistor T4 can be formed by adjusting the carrier concentration of the oxide semiconductor to make the source and drain regions conductive. For example, the source and drain regions of the third transistor T3 and the fourth transistor T4 can be formed by increasing the carrier concentration by performing plasma treatment on the oxide semiconductor using hydrogen (H)-based gas, fluorine (F)-based gas, or a combination thereof.

[0130] The semiconductor layer AO may include the channel region A3, source region S3, and drain region D3 of the third semiconductor layer AO3 as the third transistor T3, and the channel region A4, source region S4, and drain region D4 of the fourth semiconductor layer AO4 as the fourth transistor T4. That is, each channel region, each source region, and each drain region of the third transistor T3 and the fourth transistor T4 may be a portion of the semiconductor layer AO. For example, the semiconductor layers AO of the third transistor T3 and the fourth transistor T4 (i.e., the third semiconductor layer AO3 and the fourth semiconductor layer AO4) may be integrally formed, may be arranged on the same layer, and may be bent in various shapes. The source region S4 of the fourth transistor T4 may overlap with the first initialization voltage line 147 and may be electrically connected to the first initialization voltage line 147 via the connecting electrode 177 (see...). Figure 4 ).

[0131] The semiconductor layer AO may further include a fourth electrode CE4 of the second capacitor Cbt. The fourth electrode CE4 of the second capacitor Cbt may be disposed between the third semiconductor layer AO3 of the third transistor T3 and the fourth semiconductor layer AO4 of the fourth transistor T4. The fourth electrode CE4 may be provided to extend from the third semiconductor layer AO3 of the third transistor T3 or the fourth semiconductor layer AO4 of the fourth transistor T4. For example, the fourth electrode CE4 may be a portion of the semiconductor layer AO. That is, the fourth electrode CE4 may include an oxide semiconductor and may be disposed on the first interlayer insulating layer 114. The second gate insulating layer 113 and the first interlayer insulating layer 114 may be disposed between the third electrode CE3 and the fourth electrode CE4 of the second capacitor Cbt, and the second gate insulating layer 113 and the first interlayer insulating layer 114 may serve as the dielectric layer of the second capacitor Cbt.

[0132] like Figure 6E As shown, the upper scan line 163 of the third scan line SL3 and the upper scan line 165 of the fourth scan line SL4 can extend in the first direction DR1 and can be arranged on the semiconductor layer AO. That is, the third scan line SL3 and the fourth scan line SL4 can each include two conductive layers arranged on different layers.

[0133] The upper scan line 163 of the third scan line SL3 can be arranged to at least partially overlap with the lower scan line 143. The upper scan line 165 of the fourth scan line SL4 can be arranged to at least partially overlap with the lower scan line 145. A third gate insulating layer 115 can be disposed between the semiconductor layer AO and the upper scan line 163 of the third scan line SL3, and between the semiconductor layer AO and the upper scan line 165 of the fourth scan line SL4. The third gate insulating layer 115 can be formed by patterning in a shape corresponding to the upper scan line 163 of the third scan line SL3 and the upper scan line 165 of the fourth scan line SL4.

[0134] The portion of the upper scan line 163 of the third scan line SL3 that overlaps with the fourth semiconductor layer AO4 (e.g., overlaps with the fourth channel region A4) can be the upper gate electrode G4b of the fourth transistor T4. The portion of the upper scan line 165 of the fourth scan line SL4 that overlaps with the third semiconductor layer AO3 (e.g., overlaps with the third channel region A3) can be the upper gate electrode G3b of the third transistor T3. That is, the third transistor T3 and the fourth transistor T4 can have a dual-gate structure in which control electrodes are provided above and below the semiconductor layers. The dual-gate structure reduces leakage current due to the unique property of the electrical coupling between its two gates.

[0135] The third gate insulating layer 115 may include an inorganic material comprising oxides or nitrides. For example, the third gate insulating layer 115 may include materials derived from, for example, silicon oxide (SiO2). x Silicon nitride (SiN) x The transistor T3 may be disposed on the third gate insulating layer 115, and may be a single layer or multiple layers comprising at least one of, for example, molybdenum (Mo), copper (Cu), and titanium (Ti). The upper gate electrode G3b of the third transistor T3 and the upper gate electrode G4b of the fourth transistor T4 may be disposed on the third gate insulating layer 115, and may be a single layer or multiple layers comprising at least one of, for example, molybdenum (Mo), copper (Cu), and titanium (Ti).

[0136] Figure 7 It includes Figure 6E Schematic layout diagram Figure 6D Schematic layout diagram and Figure 6C A schematic layout diagram of a combination of three layers, representing a portion of the schematic layout diagram. For example... Figure 7 As shown, the lower scan line 143 of the third scan line SL3 may include a protrusion 143p. The protrusion 143p may be arranged in the fourth semiconductor layer of the fourth transistor T4. Figure 4 The channel region A4 covers the fourth semiconductor layer AO4 below AO4 and can be used to block light that may be applied from the bottom of the substrate 100.

[0137] The lower scan line 145 of the fourth scan line SL4 may have a protrusion 145p. The protrusion 145p may be arranged in the third semiconductor layer of the third transistor T3. Figure 5 The channel region A3 covers the third semiconductor layer AO3 below AO3 and can be used to block light that may be applied from the bottom of the substrate 100.

[0138] The second interlayer insulating layer 116 can be arranged while covering the third transistor T3 and the fourth transistor T4, and can be arranged on the upper gate electrode G3b of the third transistor T3 and the upper gate electrode G4b of the fourth transistor T4. For example... Figure 6F As shown, the first power supply voltage line 172, the second initialization voltage line 174, the node connection line 171, and the connection electrodes 173, 175, 177, and 179 can be arranged on the second interlayer insulation layer 116.

[0139] The second interlayer insulating layer 116 may include an inorganic material comprising oxides or nitrides. For example, the second interlayer insulating layer 116 may include materials derived from, for example, silicon oxide (SiO2). x Silicon nitride (SiN) xIt is selected from at least one of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), lanthanum oxide (La2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0140] The first power supply voltage line 172, the second initialization voltage line 174, the node connection line 171, and the connecting electrodes 173, 175, 177, and 179 may each comprise a material with high conductivity, such as a metal or a conductive oxide. For example, the first power supply voltage line 172, the second initialization voltage line 174, the node connection line 171, and the connecting electrodes 173, 175, 177, and 179 may each be a single layer or multiple layers, comprising at least one selected from, for example, aluminum (Al), copper (Cu), and titanium (Ti). In an exemplary embodiment of this disclosure, the first power supply voltage line 172, the second initialization voltage line 174, the node connection line 171, and the connecting electrodes 173, 175, 177, and 179 may each comprise three layers in which titanium, aluminum, and titanium (Ti / Al / Ti) are arranged sequentially.

[0141] The first power supply voltage line 172 can be connected to the second electrode CE2 of the first capacitor Cst through contact holes 41 formed in the first interlayer insulation layer 114 and the second interlayer insulation layer 116 (see...). Figure 4 The first power supply voltage line 172 can be connected to the fifth source region S5 of the fifth transistor T5 (see) through contact holes 42 formed in the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116. Figure 5 ).

[0142] The second initialization voltage line 174 can be connected to the seventh drain region D7 of the seventh transistor T7 through contact holes 43 formed in the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116.

[0143] One end of the node connection line 171 can be connected to the first gate electrode G1 through the contact hole 31 (see...) Figure 4 The contact hole 31 can penetrate the second interlayer insulating layer 116, the first interlayer insulating layer 114, and the second gate insulating layer 113, and can expose the first gate electrode G1. A portion of the node connection line 171 can be inserted into the contact hole 31 for electrical connection to the first gate electrode G1.

[0144] The contact hole 31 can be spaced apart from the edge of the opening SOP of the second electrode CE2, and the node connection line 171 inserted into the contact hole 31 can be electrically insulated from the second electrode CE2.

[0145] The other end of the node connection line 171 can be electrically connected to the oxide semiconductor layer AO through the contact hole 32. For example, it can be electrically connected to the fourth electrode CE4 of the second capacitor Cbt, the fourth semiconductor layer AO4, or the third semiconductor layer AO3 through the contact hole 32. For example, the first gate electrode G1, which also serves as the first electrode CE1 of the first capacitor Cst, can be electrically connected to the fourth electrode CE4 of the second capacitor Cbt, the fourth drain region D4 of the fourth transistor T4, and the third source region S3 of the third transistor T3 through the node connection line 171. The contact hole 32 can penetrate the second interlayer insulating layer 116 to expose the oxide semiconductor layer.

[0146] The fourth electrode CE4 of the second capacitor Cbt can be connected to the node connection line 171 to electrically connect to the first gate electrode G1. Therefore, when the first scan signal Sn supplied to the first scan line 133 (SL1) is turned off, the second capacitor Cbt can raise the node ( Figure 2 The voltage of N2 is adjusted to clearly render the black levels.

[0147] One end of the connecting electrode 173 can be connected via the contact hole 33 to the first drain region D1 of the first transistor T1 and the sixth source region S6 of the sixth transistor T6 (see...). Figure 5 Contact hole 33 can penetrate the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116 to expose the silicon semiconductor layer. The other end of the connection electrode 173 can be connected to the third drain region D3 of the third transistor T3 through contact hole 34. For example, the first drain region D1 of the first transistor T1 and the sixth source region S6 of the sixth transistor T6 in the silicon semiconductor layer AS can be electrically connected to the third drain region D3 of the third transistor T3 in the oxide semiconductor layer AO through connection electrode 173. Contact hole 34 can penetrate the second interlayer insulating layer 116 to expose the oxide semiconductor layer.

[0148] The connection electrode 175 can be connected to the second source region S2 of the second transistor T2 through the contact holes 35 formed in the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114 and the second interlayer insulating layer 116.

[0149] The portion of connecting electrode 177 can be connected to the fourth source region S4 of the fourth transistor T4 (see [reference]) through contact hole 36 formed in the second interlayer insulating layer 116. Figure 4 Another component connecting electrode 177 can be connected to the first initialization voltage line 147 through contact holes 37 formed in the first interlayer insulation layer 114 and the second interlayer insulation layer 116.

[0150] The connection electrode 179 can be connected to the sixth drain region D6 of the sixth transistor T6 (see [link to contact hole]) through contact holes 38 formed in the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116. Figure 5 ).

[0151] A first planarization layer 118 may be arranged on the first power supply voltage line 172, the second initialization voltage line 174, the node connection line 171, and the connection electrodes 173, 175, 177, and 179.

[0152] like Figure 6G As shown, a data line 181, a second power supply voltage line 183, and a connection electrode 185 can be arranged on the first planarization layer 118.

[0153] The data line 181 can be connected to the connection electrode 175 through the contact hole 61 formed in the first planarization layer 118 so as to be connected to the second source region S2 of the second transistor T2. Figure 8 It is a schematic layout diagram that includes a combination of three layers, the three layers including Figure 6G Part of the schematic layout diagram Figure 6F A portion of the schematic layout diagram and Figure 6D A schematic layout diagram. (For example...) Figure 8 As shown, data line 181 can be arranged to partially overlap with the first power supply voltage line 172. Figure 4 As shown, when viewed in a cross-sectional view, the first power supply voltage line 172 can be arranged between the first gate electrode G1 of the first transistor T1 and the data line 181. When viewed in a plan view, a portion P1 of the first power supply voltage line 172 (see...) Figure 4 The first power supply voltage line 172 can be positioned between the data line 181 and the node connection line 171. Therefore, the first power supply voltage line 172 can reduce the coupling between the data line 181 and the first gate electrode G1, as well as between the node connection line 171 and the data line 181.

[0154] The second power supply voltage line 183 can be connected to the first power supply voltage line 172 through a contact hole 62 formed in the first planarization layer 118 (see...). Figure 5 ).like Figure 3 , Figure 4 and Figure 8As shown, the second power supply voltage line 183 may cover the third semiconductor layer AO3 of the third transistor T3 and the fourth semiconductor layer AO4 of the fourth transistor T4. For example, the second power supply voltage line 183 may overlap with the third semiconductor layer AO3 of the third transistor T3 and the fourth semiconductor layer AO4 of the fourth transistor T4. Therefore, the second power supply voltage line 183 can be used to block light that may be applied from above the substrate 100. Furthermore, a portion of the second power supply voltage line 183 may overlap with the node connection line 171. When viewed in a plan view, another portion of the second power supply voltage line 183 may be arranged between the data line 181 and the node connection line 171. Therefore, the second power supply voltage line 183 can reduce the coupling between the node connection line 171 and the data line 181.

[0155] Connection electrode 185 can be connected to connection electrode 179 through contact hole 63 formed in first planarization layer 118, so as to be connected to drain region D6 of sixth transistor T6 (see...). Figure 5 The connection electrode 185 can be connected to the pixel electrode 310 through a contact hole 64 formed in a second planarization layer 119 located above the first planarization layer 118, and can be configured to transmit a signal applied by a sixth transistor T6 to the pixel electrode 310.

[0156] The first planarization layer 118 and the second planarization layer 119 may each comprise an organic material, such as acrylic resin, benzocyclobutene (BCB), polyimide (PI), or hexamethyl disiloxane (HMDSO). Alternatively, the first planarization layer 118 and the second planarization layer 119 may each comprise an inorganic insulating material. For example, the inorganic insulating material may include, for example, silicon oxide (SiO₂). x Silicon nitride (SiN) x The first planarization layer 118 and the second planarization layer 119 can be used as protective layers covering the first transistor T1 to the seventh transistor T7, and can be provided such that the upper portion of the first planarization layer 118 and the upper portion of the second planarization layer 119 are planarized. The first planarization layer 118 and the second planarization layer 119 can each be a single layer or multiple layers.

[0157] A pixel defining layer 120 can be disposed on the second planarization layer 119. Because the pixel defining layer 120 includes an opening corresponding to each pixel, i.e., an opening exposing at least the central portion of the pixel electrode 310, the pixel defining layer 120 can be used to define pixels and can cover the edges of the pixel electrode 310. Furthermore, the pixel defining layer 120 can increase the distance between the edge of the pixel electrode 310 and the opposing electrode 330 located above the pixel electrode 310, thus preventing arcing at the edge of the pixel electrode 310. For example, the pixel defining layer 120 can comprise an organic material such as polyimide (PI) or hexamethyldisiloxane (HMDSO).

[0158] The intermediate layer 320 of an organic light-emitting diode (OLED) may include low-molecular-weight or high-molecular-weight materials, each emitting light of a predetermined color. When the intermediate layer 320 includes low-molecular-weight materials, it may have a single-layer or multi-layer structure, including a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). In exemplary embodiments of this disclosure, the EML may include at least one material that emits red, green, or blue light, and may include fluorescent or phosphorescent materials. The intermediate layer 320 may include various organic materials, such as phthalocyanine blue (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenylbenzidine (NPB), and aluminum tri-8-hydroxyquinoline (Alq3). These layers may be formed by vacuum deposition.

[0159] When the interlayer 320 comprises a high molecular weight material, the interlayer 320 may have a structure including HTL and EML. For example, in addition to EML, the interlayer 320 may also include at least one of HTL, HIL, EIL, and ETL. In this case, HTL may comprise poly(3,4-vinyldioxythiophene) (PEDOT), and EML may comprise a poly(p-phenylacetylene)-based polymer or a polyfluorene-based polymer. The interlayer 320 may be formed by screen printing, inkjet printing, or laser-induced thermal imaging (LITI).

[0160] The intermediate layer 320 is not limited to this. The intermediate layer 320 can have various structures. The intermediate layer 320 may include a monolithic layer covering a plurality of pixel electrodes 310, or it may include a layer patterned to correspond to the pixel electrodes 310.

[0161] The relative electrode 330 can be integrally formed relative to a plurality of organic light-emitting diodes (OLEDs) and can correspond to the pixel electrode 310. The relative electrode 330 can include a transparent electrode or a reflective electrode, and can include at least one of, for example, silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), calcium (Ca), copper (Cu), lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), magnesium-silver (MgAg), and calcium-silver (CaAg).

[0162] Organic light-emitting diodes (OLEDs) can be easily damaged by external moisture or oxygen. Therefore, a thin-film encapsulation layer or sealing substrate can be disposed on the OLED to cover it and protect it. The thin-film encapsulation layer can cover the display area DA and can extend beyond the display area DA. The thin-film encapsulation layer can include at least one inorganic encapsulation layer containing inorganic material and at least one organic encapsulation layer containing organic material. In an exemplary embodiment of this disclosure, the thin-film encapsulation layer can have a structure in which a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer are stacked. In an exemplary embodiment of this disclosure, a second inorganic encapsulation layer can be deposited to directly contact the first inorganic encapsulation layer located in an edge region of the display device. The second inorganic encapsulation layer can seal the organic encapsulation layer so that the organic encapsulation layer is not exposed to the outside. Therefore, external moisture or oxygen can be prevented or reduced from penetrating into the display area DA through the organic encapsulation layer. The sealing substrate can be disposed facing the substrate 100 and can be bonded to the substrate 100 in the peripheral region PA by a sealing member such as a sealant or glass frit.

[0163] The pixel-defining layer 120 may also include spacers for preventing mask scratches, and various functional layers may be provided on the thin-film encapsulation layer, such as a polarizing layer for reducing external light reflection, a black matrix, a color filter layer, and / or a touch screen layer including touch electrodes.

[0164] Figure 9 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figures 10A to 10C It is intercepted along line III-III' Figure 9 A schematic cross-sectional view of the display device. Figure 11 It is a schematic representation of what appears after bending. Figure 9 A perspective view of a portion of the display device. Figure 12 It is along Figure 11 The line IV-IV' intercepted Figure 11 A schematic cross-sectional view of the display device.

[0165] Reference Figure 9The substrate 100 may include a display area DA in which an image is displayed and a peripheral area PA disposed around the display area DA. Furthermore, the substrate 100 may include a first area AA1, a second area AA2, and a curved area BA positioned between the first area AA1 and the second area AA2. A driver 500 may be disposed in the second area AA2 and / or the peripheral area PA.

[0166] The first region AA1 may include a display region DA and a peripheral region PA that serves as a non-display area surrounding the display region DA. The second region AA2 may also include the peripheral region PA.

[0167] The substrate 100 may have a curved region BA extending in a first direction DR1. The curved region BA may be included within a peripheral region PA and may be positioned between the first region AA1 and the second region AA2 in a second direction DR2 intersecting the first direction DR1. Figure 11 As shown, the substrate 100 can be bent about a bending axis BAX extending in the first direction DR1. Inorganic insulating layer ( Figure 10A The trench TR of the IL can be provided in the peripheral region PA along the first direction DR1 of the curved region BA. The substrate 100 may also include a fan-out line FL extending from the display region DA and traversing the curved region BA.

[0168] The substrate 100 may include a first base layer 101, a first barrier layer 103, a second base layer 105, and a second barrier layer 107. The first base layer 101 and the second base layer 105 may each include a polymer resin. The first barrier layer 103 and the second barrier layer 107 may each be a single layer or multiple layers containing inorganic materials.

[0169] Each of the inorganic material buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116 can be collectively referred to as the inorganic insulating layer IL. Figure 10A , Figure 10B and Figure 10C An inorganic insulating layer IL located in a peripheral region PA including a curved region BA is shown, comprising a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, a first interlayer insulating layer 114, and a second interlayer insulating layer 116 sequentially stacked on a third-direction DR3. However, this disclosure is not limited thereto. For example, in an exemplary embodiment of this disclosure, the inorganic insulating layer IL may include at least one selected from the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116.

[0170] The inorganic insulating layer IL may include a trench TR corresponding to the bending region BA. The trench TR may be formed in the bending region BA through at least one layer selected from the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116 of the inorganic insulating layer IL.

[0171] In exemplary embodiments of this disclosure, such as Figure 10A As shown, the trench TR can penetrate the first gate insulating layer 112, the second gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 116. The trench TR may include openings 112a in the first gate insulating layer 112, 113a in the second gate insulating layer 113, 114a in the first interlayer insulating layer 114, and 116a in the second interlayer insulating layer 116, corresponding to the curved region BA. Figure 10A The inner surfaces of the opening 112a of the first gate insulating layer 112, the opening 113a of the second gate insulating layer 113, the opening 114a of the first interlayer insulating layer 114, and the opening 116a of the second interlayer insulating layer 116 are shown to overlap with each other. However, this disclosure is not limited thereto. For example, in an exemplary embodiment of this disclosure, the inner surfaces of the openings 112a, 113a, 114a, and 116a may not overlap with each other, and the sizes of the openings 112a, 113a, 114a, and 116a may be different from each other. The trench TR may be filled with a first planarization layer 118. The fan-out line FL, the second planarization layer 119, the pixel defining layer 120, and the bend protection layer 600 may be sequentially formed on the first planarization layer 118 above the trench TR.

[0172] In exemplary embodiments of this disclosure, such as Figure 10B As shown, the trench TR may include an opening 111a in the buffer layer 111, an opening 112a in the first gate insulating layer 112, an opening 113a in the second gate insulating layer 113, an opening 114a in the first interlayer insulating layer 114, and an opening 116a in the second interlayer insulating layer 116.

[0173] In exemplary embodiments of this disclosure, such as Figure 10C As shown, the trench TR may also include an opening 107a in the second barrier layer 107 corresponding to the bending region BA. The opening 107a in the second barrier layer 107 may correspond to the openings 111a, 112a, 113a, 114a and 116a in the inorganic insulating layer IL.

[0174] The groove TR corresponding to the curved region BA can indicate that the groove TR overlaps with the curved region BA. In this case, the area of ​​the groove TR can be larger than the area of ​​the curved region BA. Figures 10A to 10CIt is shown that the width OW of the groove TR is greater than the width of the curved region BA in the first direction DR1. The area of ​​the groove TR can be defined as the area of ​​the bottom surface with the smallest area when the groove TR is viewed from above.

[0175] like Figure 11 As shown, a display device according to an exemplary embodiment of the present disclosure may have a shape in which a portion of the substrate 100, which is part of the display device, is bent, and thus, a portion of the display device is bent like the substrate 100.

[0176] Reference Figure 11 and Figure 12 The display device according to this exemplary embodiment may include: a substrate 100 having a first region AA1, a second region AA2, and a curved region BA located between the first region AA1 and the second region AA2; a display member 200, a sensing member 300, and a polarizing member 400 disposed in the first region AA1 of the substrate 100; and a driver 500 disposed in the second region AA2 of the substrate 100. A window may be attached to the upper part of the polarizing member 400. The window may extend not only to the display region AA1 but also to the peripheral region PA including the curved region BA. Therefore, the window can protect the curved region BA from external impacts.

[0177] A display component 200 configured to display an image may be arranged in a display area DA of a first region AA1. The display component 200 may include a plurality of pixels PX, and each pixel PX may include a display element and pixel circuitry, the pixel circuitry including a thin-film transistor configured to control the light emission of the display element. Therefore, the display element and the thin-film transistor are arranged in the display area DA. The display element may include, for example, an organic light-emitting diode (OLED). In an exemplary embodiment of this disclosure, the pixel circuitry controlling the light emission of the OLED may include at least one thin-film transistor comprising a silicon semiconductor and at least one thin-film transistor comprising an oxide semiconductor, thereby providing a high-resolution display device with low power consumption. The display component 200 may be a display panel including an encapsulation component. The encapsulation component may cover the display element and thin-film transistor located in the display area DA and may extend outside the display area DA. In an exemplary embodiment of this disclosure, the encapsulation component may include an encapsulation substrate and a sealant for bonding the substrate 100 to the encapsulation substrate. In an exemplary embodiment of this disclosure, the encapsulation component may be an encapsulation layer. The encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Encapsulation layers can compensate for the characteristics of display elements that are susceptible to oxygen and moisture by blocking and sealing organic light-emitting diodes (OLEDs) from the outside.

[0178] Sensing component 300 may be provided on display component 200. Sensing component 300 can detect external touch information and obtain coordinate information about an input point by using the detected external touch information as an input signal. Sensing component 300 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. Sensing component 300 can sense external input using mutual capacitance and / or self-capacitance methods. For example, sensing component 300 can obtain information about external input through the change in capacitance between two sensing electrodes.

[0179] The sensing component 300 can be directly formed and embedded in the display component 200, or it can be provided as a separate component and mounted on the display component 200. For example, the sensing component 300 can be formed continuously after the process of forming the display component 200. In this case, the sensing component 300 can be understood as a part of the display component 200. No adhesive layer may be disposed between the sensing component 300 and the display component 200. The sensing component 300 can be bonded to the display component 200 via an adhesive layer. Figure 11 The illustration shows a sensing element 300 arranged between a display element 200 and a polarizing element 400, but this disclosure is not limited thereto. For example, in an exemplary embodiment of this disclosure, the sensing element 300 may be arranged on the polarizing element 400.

[0180] A polarizing member 400 may be disposed on a sensing member 300. An adhesive layer may be disposed between the polarizing member 400 and the sensing member 300. Similarly, an adhesive layer may also be disposed between the sensing member 300 and the display member 200. The adhesive layer may be a transparent adhesive layer. For example, the adhesive layer may be an optically transparent adhesive (OCA). However, this disclosure is not limited thereto. For example, an optically transparent resin (OCR) may be applied. Furthermore, in exemplary embodiments of this disclosure, the adhesive layer may include a pressure-sensitive adhesive (PSA). The PSA may include a polymer-cured product. The PSA may be formed in the form of a film including the adhesive and may perform an adhesive function in response to pressure applied from the outside. The PSA may include an acrylic resin-based or rubber-based adhesive or an adhesive in which particles such as zirconium oxide (ZrO2) are included in the adhesive.

[0181] The polarizing member 400 may include an anti-reflective layer. The anti-reflective layer can reduce the reflectivity of light (external light) incident from the outside toward the display member 200 by means of a window attached to the upper part of the polarizing member 400. The anti-reflective layer may include a phase retarder and a polarizer. The phase retarder may be a film-type retarder or a liquid crystal-coated retarder, and may include a λ / 2 retarder and / or a λ / 4 retarder. In an exemplary embodiment of this disclosure, the polarizing member 400 may include two layers of retarders, a first layer having a λ / 2 retardation value, and a second layer positioned below the first layer having a λ / 4 retardation value. The polarizer may also be a film-type polarizer or a liquid crystal-coated polarizer. A film-type polarizer may include a stretched synthetic resin film, and a liquid crystal-coated polarizer may include liquid crystal arranged in a specific array. A film-type polarizer may be a uniaxially stretched film or a biaxially stretched film. The retarder and polarizer may each also include a protective film. For example, the polarizer may be located between two protective films. The protective film of the retarder and the protective film of the polarizer can be defined as the base layer of the anti-reflective layer.

[0182] In exemplary embodiments of this disclosure, the antireflective layer may include a black matrix and color filters. The color filters may be arranged considering the color of light emitted from the pixels of the display component 200. Therefore, a desired color can be achieved by filtering the light emitted by each pixel using appropriate color filters. Each color filter may each include a red pigment or dye, a green pigment or dye, or a blue pigment or dye. Alternatively, in addition to pigments or dyes, each color filter may also include quantum dots. Alternatively, some color filters may not include pigments or dyes and may include scattering particles such as titanium dioxide (TiO2) particles.

[0183] In exemplary embodiments of this disclosure, the antireflective layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. First reflected light and second reflected light reflected from the first reflective layer and the second reflective layer, respectively, can interfere destructively with each other, thereby reducing the reflectivity of external light.

[0184] The polarizing member 400 may include a lens layer. The lens layer may enhance the light output efficiency of light emitted from the display member 200, or may reduce chromatic aberration. The lens layer may include a layer having a concave lens shape or a convex lens shape, and / or may include multiple layers with different refractive indices. In exemplary embodiments of this disclosure, an array of lenses in the lens layer may cover an array of pixels, wherein at least one lens may cover at least one pixel. The polarizing member 400 may include either or both of an anti-reflective layer and a lens layer.

[0185] In an exemplary embodiment of this disclosure, the polarizing member 400 may be formed sequentially after the processes forming the display member 200 and / or the sensing member 300. In this case, an adhesive layer may not be disposed between the polarizing member 400 and the display member 200 and / or the sensing member 300.

[0186] The display component 200, sensing component 300, and polarizing component 400 may each include an opening located in the display area DA. In an exemplary embodiment of this disclosure, the display component 200, sensing component 300, and polarizing component 400 may each include an opening, and these openings may overlap each other. In an exemplary embodiment of this disclosure, one or more display components 200, sensing component 300, and polarizing component 400 may not include an opening. The opening may be a hole penetrating an element or a transmissive region without an aperture. In an exemplary embodiment of this disclosure, the openings of the display component 200, sensing component 300, and polarizing component 400 may each be transmissive regions including apertures. In an exemplary embodiment of this disclosure, the openings of the display component 200, sensing component 300, and polarizing component 400 may each be transmissive regions without apertures. Components for adding various functions to the display device may be positioned within the openings. Components may be positioned within the openings or may be arranged below the display component 200. For example, a component may be configured to overlap with the opening, and therefore, the component may be easily connected to the outside through the opening.

[0187] The component may include electronic elements. For example, the component may be an electronic element that uses light or sound. For example, the electronic element may be a sensor (e.g., an infrared sensor) configured to output and / or receive light, a camera configured to receive light and capture images, a sensor configured to output and sense light or sound to measure distance or identify fingerprints, a small lamp configured to output light, and a speaker configured to output sound, etc. When the component is an electronic element that uses light, the component may use light of various wavelengths, such as visible light, infrared light, and ultraviolet light. In exemplary embodiments of this disclosure, the opening can be understood as a transmission area through which light and / or sound output from the component to the outside or traveling from the outside toward the electronic element can be transmitted. For example, the component may include at least one of a camera, a speaker, a lamp, a light detection sensor, and a thermal detection sensor. The component may detect external objects received through the opening, or may provide sound signals, such as speech, to the outside through the opening.

[0188] In exemplary embodiments of this disclosure, when the display device is used as a smartwatch or a dashboard for a motor vehicle, the component may be a clock hand or pointer that indicates specific information (e.g., vehicle speed). When the display device includes a clock hand or dashboard for a vehicle, the component may be exposed to the outside through a window, and the window may include an opening.

[0189] The components may include those related to the functionality of the display device as described above, or may include accessories such as those that enhance the aesthetics of the display device.

[0190] Driver 500 can be arranged in the second region AA2. Driver 500 can be connected to the pad area of ​​substrate 100 to supply scan signals and data signals to scan lines and data lines. The pixel circuit of display component 200 can receive the scan signals and data signals supplied through driver 500. Driver 500 can be, for example, a driver IC chip, or it can be mounted on the pad area of ​​substrate 100. In this case, the pad area can be directly electrically connected to the driver IC chip.

[0191] In an exemplary embodiment of this disclosure, a flexible printed circuit board (FPCB) 800 can be mounted on the pad area of ​​the substrate 100, and a driver IC chip can be mounted on the FPCB 800. As the FPCB 800, chip-on-film (COF) or flexible printed circuit (FPC) can be applied. The FPCB 800 can be bent and can be electrically connected to the display member 200. A driver IC chip can be mounted on the FPCB 800, which supplies signals for causing a plurality of pixels PX of the display member 200 to emit light.

[0192] A bending protection layer 600 may be disposed on the peripheral region PA of the substrate 100. The bending protection layer 600 may be positioned from the end of the display member 200 through the bending region BA to near the end of the driver 500. However, this disclosure is not limited thereto. For example, various deformable structures capable of covering the bending region BA may be used.

[0193] The bending protection layer 600 can adjust the position of the neutral plane (NP), which is a position where the strain is essentially zero during bending, so that the strain applied to the substrate 100 is compressive stress rather than tensile strain. For example, by arranging the NP near the wiring located in the bending region BA by applying the bending protection layer 600 located at the bending region BA, the tensile stress applied to the wiring located in the bending region BA can be minimized. Therefore, the bending protection layer 600 covers the bending region BA of the substrate 100, thereby minimizing damage to the wiring located in the bending region BA of the substrate 100.

[0194] The bend protection layer 600 may comprise an acrylic-based resin or a silicone-based resin, and may also comprise microparticles within the resin. These microparticles may comprise polymer-based nanoparticles or microparticles such as those from a silica-containing rubber, epoxy resin, or epoxy mixture. Furthermore, the bend protection layer 600 may also comprise various films comprising polyethylene terephthalate (PET).

[0195] exist Figure 12 In this embodiment, the ends of the display member 200, the sensing member 300, and the polarizing member 400 are formed equally, but this disclosure is not limited thereto. As described above, the display member 200 may include an organic light-emitting diode (OLED), a thin-film transistor (TFT), and an encapsulation layer covering the OLED and TFT. Specifically, the ends of the encapsulation layer may be arranged over a wider area than the sensing member 300 and the polarizing member 400. In an exemplary embodiment of this disclosure, the polarizing member 400 may be arranged to contact or adjacent to the bending protection layer 600. The polarizing member 400 may extend to the bending region BA to serve as a bending protection layer.

[0196] The substrate 100 may have one surface and another surface positioned on the opposite side of the one surface, and the display member 200 may be positioned on said one surface of the substrate 100. The protective film 700 may be positioned on the other surface of the substrate 100 opposite to the one surface on which the display member 200 is positioned.

[0197] The protective film 700 can be attached to another surface of the substrate 100 and can be used to protect the display device. The protective film 700 can be attached to the other surface of the substrate 100 via an adhesive layer. The protective film 700 may include a first protective film 701 and a second protective film 703 spaced apart from each other. The first protective film 701 can be attached to a position corresponding to a first region AA1 of the substrate 100. The second protective film 703 can be attached to a position corresponding to a second region AA2 of the substrate 100. That is, the protective film 700 may not be attached to the position corresponding to the bending region BA. Therefore, the stress applied to the substrate 100 and the protective film 700 during bending of the substrate 100 can be minimized to prevent damage to the substrate 100 in the bending region BA during bending. In this exemplary embodiment, the protective film 700 has a structure that does not attach to the bending region BA of the substrate 100, but this disclosure is not limited thereto. For example, the protective film 700 can be positioned on another surface (i.e., the front surface) of the substrate 100, and the protective film 700 can be attached to positions corresponding to the first region AA1, the second region AA2, and the curved region BA of the substrate 100. Alternatively, a groove can be formed in the protective film 700 at the position corresponding to the curved region BA of the substrate 100.

[0198] According to an exemplary embodiment of the present disclosure, the driving circuit for driving the display element is configured to include a first thin-film transistor comprising a silicon semiconductor and a second thin-film transistor comprising an oxide semiconductor, thereby providing a high-resolution display device with low power consumption.

[0199] The gate electrode and data line of the first thin-film transistor (i.e., the driving thin-film transistor) are spaced apart from the node connection lines and data lines connected to the first thin-film transistor via multiple insulating layers in the vertical direction, and when viewed in a plan view, an additional voltage layer is provided between the gate electrode and data line of the first thin-film transistor and the node connection lines and data lines connected to the first thin-film transistor, thereby minimizing the effects caused by coupling capacitance.

[0200] Because a boost capacitor is provided, black levels can be clearly achieved.

[0201] According to an exemplary embodiment of the present disclosure, the driving circuit (i.e., pixel circuit) for driving the display element includes a first thin-film transistor comprising silicon semiconductor and a second thin-film transistor comprising oxide semiconductor, thereby providing a high-resolution display device with low power consumption.

[0202] It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments. Although specific exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A display device, comprising: First transistor; The second transistor is connected to the data line and the first transistor; The third transistor is connected to the node and the first transistor; A fourth transistor is connected to the node and the first initialization voltage line; The fifth transistor is connected to the power supply voltage line and the first transistor; The sixth transistor is connected to the first transistor and the light-emitting device; The seventh transistor is connected to the light-emitting device and the second initialization voltage line; as well as The first capacitor is connected to the power supply voltage line and the node. Each of the first to the seventh transistors includes a semiconductor layer and a gate electrode, wherein the semiconductor layer includes a source region, a drain region, and a channel region overlapping the gate electrode. The gate electrode of the first transistor is connected to the node. Wherein, each of the semiconductor layers of the third transistor and the fourth transistor comprises an oxide semiconductor, and The power supply voltage line overlaps with the channel region of the semiconductor layer of the third transistor and the channel region of the semiconductor layer of the fourth transistor.

2. The display device according to claim 1, wherein, The first capacitor includes a first electrode and a second electrode, and the first capacitor overlaps with the channel region of the semiconductor layer of the first transistor.

3. The display device according to claim 2, wherein, A portion of the first electrode of the first capacitor is the gate electrode of the first transistor, and The second electrode of the first capacitor and the gate electrode of the third transistor are arranged on the same layer.

4. The display device according to claim 2, wherein, The second electrode of the first capacitor is electrically connected to the power supply voltage line.

5. The display device according to claim 1, wherein, The first capacitor is disposed on a layer between the semiconductor layer of the first transistor and the semiconductor layer of the third transistor.

6. The display device according to claim 1, further comprising: The node connection line is electrically connected to the gate electrode of the first transistor and the semiconductor layer of the fourth transistor.

7. The display device according to claim 1, further comprising: A second capacitor is connected to the gate electrode of the second transistor and the gate electrode of the first transistor.

8. The display device according to claim 7, wherein, The second capacitor includes a third electrode and a fourth electrode. Wherein, the third electrode of the second capacitor and the gate electrode of the first transistor are arranged on the same layer, and The fourth electrode of the second capacitor and the semiconductor layer of the third transistor are arranged on the same layer.

9. The display device according to claim 8, wherein, The fourth electrode of the second capacitor comprises an oxide semiconductor.

10. The display device according to claim 9, wherein, The fourth electrode of the second capacitor is a portion extending from the semiconductor layer of the third transistor.

11. The display device according to claim 7, wherein, The power supply voltage line overlaps with the second capacitor.

12. The display device according to claim 1, further comprising: The first scan line overlaps with the channel region of the semiconductor layer of the second transistor; The second scan line overlaps with the channel region of the semiconductor layer of the third transistor; The third scan line overlaps with the channel region of the semiconductor layer of the fourth transistor; The fourth scan line overlaps with the channel region of the semiconductor layer of the seventh transistor; as well as The emitter control line overlaps with the channel region of the semiconductor layer of the fifth transistor and the channel region of the semiconductor layer of the sixth transistor.

13. The display device according to claim 12, wherein, The transmit control line and the first scan line are arranged on the same layer, while the first scan line and the second scan line are arranged on different layers.

14. The display device according to claim 12, wherein, The third scan line includes lower scan lines and upper scan lines arranged on different layers.

15. The display device according to claim 12, wherein, The second scan line includes a lower scan line and an upper scan line arranged on different layers.

16. The display device according to claim 1, wherein, The power supply voltage line overlaps with a portion of the channel region of the semiconductor layer of the first transistor.

17. The display device according to claim 1, wherein, The power supply voltage line and the data line are arranged on the same layer.

18. The display device according to claim 17, wherein, The power supply voltage line is arranged on the layer between the light-emitting device and the first capacitor.

19. The display device according to claim 1, further comprising: The connecting electrode is electrically connected to the semiconductor layer of the first transistor and the semiconductor layer of the third transistor.

20. The display device according to claim 1, wherein, The semiconductor layer of the first transistor is curved.

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