Display device

Abstract

A display device is disclosed. The display device of this disclosure includes: a substrate; pixels above the substrate and including a first transistor and a second transistor, the first transistor including a channel in a first active layer separated from the substrate by a first distance, the second transistor including a channel in a second active layer separated from the substrate by a second distance greater than the first distance; and valley structures between some pixels, penetrating an insulating layer, and having a lower portion separated from the substrate by a third distance less than the second distance and different from the first distance.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0048291, filed on April 14, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device and an electronic device. Background Technology

[0003] With the development of information technology, display devices, as the connection medium between users and information, have become increasingly important. Therefore, display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) are being used more and more frequently.

[0004] To achieve narrow bezels, one or more sides of the display device can be bent. Additionally, various display devices with at least partially foldable structures (such as foldable and rollable displays) are being developed. In this case, there is a risk of the display device breaking due to the stress applied to it. Summary of the Invention

[0005] This disclosure provides a display device and electronic device that can increase or maximize stress dispersion and reduce or minimize crack occurrence.

[0006] A display device according to one or more embodiments of the present disclosure includes: a substrate; pixels above the substrate and including a first transistor and a second transistor, the first transistor including a channel in a first active layer separated from the substrate by a first distance, the second transistor including a channel in a second active layer separated from the substrate by a second distance greater than the first distance; and valley structures between some of the pixels, penetrating an insulating layer, and having a lower portion separated from the substrate by a third distance less than the second distance and different from the first distance.

[0007] The lower part of the valley structure can contact the upper part of the first active layer.

[0008] The lower part of the valley structure can contact the upper part of the first conductive layer between the substrate and the first active layer.

[0009] The lower part of the valley structure can contact the upper part of the second conductive layer between the first active layer and the second active layer.

[0010] The second conductive layer may include a scan line containing the gate electrode of the first transistor.

[0011] The upper part of the valley structure can be separated from the base by a fourth distance greater than the second distance.

[0012] The valley structure may include an upper part, a lower part, and sidewalls covering the valley structure and a covering layer of conductive material.

[0013] The overlay can be configured to receive the initialization voltage.

[0014] The display device may further include a plurality of valley structures comprising valley structures, wherein pixels are arranged in a first direction and a second direction substantially perpendicular to the first direction, wherein the plurality of valley structures extend in at least one of the first and second directions, and wherein the length of the plurality of valley structures is greater than the length of the pixel.

[0015] The display device may further include a plurality of valley structures comprising valley structures, wherein pixels are arranged in a first direction and a second direction substantially perpendicular to the first direction, wherein the plurality of valley structures extend in at least one of the first and second directions, and wherein the length of the plurality of valley structures is less than the length of the pixel.

[0016] An electronic device according to one or more embodiments of the present disclosure includes: a processor for providing image data; and a display device for displaying an image in grayscale based on the image data, and the display device includes: a substrate; pixels above the substrate and including a first transistor and a second transistor, the first transistor including a channel in a first active layer separated from the substrate by a first distance, the second transistor including a channel in a second active layer separated from the substrate by a second distance greater than the first distance; and valley structures between some of the pixels, penetrating an insulating layer, and having a lower portion separated from the substrate by a third distance less than the second distance and different from the first distance.

[0017] The lower part of the valley structure can contact the upper part of the first active layer.

[0018] The lower part of the valley structure can contact the upper part of the first conductive layer between the substrate and the first active layer.

[0019] The lower part of the valley structure can contact the upper part of the second conductive layer between the first active layer and the second active layer.

[0020] The second conductive layer may include a scan line containing the gate electrode of the first transistor.

[0021] The upper part of the valley structure can be separated from the base by a fourth distance greater than the second distance.

[0022] The valley structure may include an upper part, a lower part, and sidewalls covering the valley structure and a covering layer of conductive material.

[0023] The overlay can be configured to receive the initialization voltage.

[0024] The display device may include a plurality of valley structures, wherein pixels are arranged in a first direction and a second direction substantially perpendicular to the first direction, wherein the plurality of valley structures extend in at least one of the first and second directions, and wherein the length of the plurality of valley structures is greater than the length of the pixels.

[0025] The display device may include a plurality of valley structures, wherein pixels are arranged in a first direction and a second direction substantially perpendicular to the first direction, wherein the plurality of valley structures extend in at least one of the first and second directions, and wherein the length of the plurality of valley structures is less than the length of the pixel.

[0026] The display device and electronic device according to this disclosure can increase or maximize stress dispersion, and can reduce or minimize crack occurrence. Attached Figure Description

[0027] Figure 1 This is a diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0028] Figure 2 This is a diagram illustrating pixels according to one or more embodiments of the present disclosure.

[0029] Figures 3 to 6 This is a diagram illustrating the change of display frequency according to one or more embodiments of the present disclosure.

[0030] Figure 7 This is a diagram illustrating an address scan period according to one or more embodiments of the present disclosure.

[0031] Figure 8 This is a diagram illustrating a self-scanning period according to one or more embodiments of the present disclosure.

[0032] Figure 9 This is a diagram illustrating the auxiliary scanning period according to one or more embodiments of the present disclosure.

[0033] Figure 10 and Figure 11 This is a diagram illustrating the relationship between pads, connecting wires, and signal lines according to one or more embodiments of the present disclosure.

[0034] Figures 12 to 22 This is a diagram illustrating the layout of pixel units according to one or more embodiments of the present disclosure.

[0035] Figures 23 to 26 This is a diagram illustrating a valley structure according to one or more other embodiments of the present disclosure.

[0036] Figures 27 to 32This is a diagram illustrating the relationship between pixels and valley structures according to embodiments of the present disclosure.

[0037] Figure 33 It is a block diagram of an electronic device according to one or more embodiments.

[0038] Figures 34 to 36 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0039] Aspects of some embodiments of this disclosure and methods of implementing them can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments or are not essential for a full understanding of aspects of this disclosure by those skilled in the art may be omitted. Unless otherwise stated, the same reference numerals, symbols, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated description may be omitted.

[0040] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. In describing embodiments, the use of “may,” “may,” or “may not” corresponds to one or more embodiments of this disclosure.

[0041] In view of the full contents of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, the various embodiments may be implemented independently of each other or in combination with each other in any suitable way.

[0042] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, the disclosure is not limited thereto because the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of description. Additionally, crosshairs and / or shading are typically used in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities among the elements shown, and / or any other characteristics, properties, etc.

[0043] Various embodiments are described herein with reference to cross-sectional views as schematic illustrations of examples and / or intervening structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances will be expected. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the illustrated shapes of elements, layers, or regions, but will include deviations in shape due to, for example, manufacturing processes.

[0044] For example, an injection zone shown as rectangular will typically have circular or curved features and / or a gradient of injection concentration at its edges, rather than a binary variation from the injection zone to the non-injection zone. Similarly, an embedded zone formed by injection can induce some injection in the area between the embedded zone and the surface through which the injection occurs.

[0045] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “upper,” “above,” “higher,” “upper side,” “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element or feature. It will be understood that, in addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to also encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged on the upper or lower side of the second part, and is not limited to the upper side of the second part based on the direction of gravity.

[0046] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting the portion of the object from the side. The terms "overlapping with" or "overlapping" mean that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term "overlapping with" can include stacking, facing or oriented, extending over, covering or partially covering, or any other suitable terms as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping with" can include meanings such as "separated from," "offset from," or "deviation from," and any other suitable equivalents as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" can mean that the first object may be directly or indirectly opposite the second object. In cases where a third object is placed between the first and second objects, although the first and second objects still face each other, they can be understood as being indirectly opposite each other.

[0047] It will be understood that when a component, layer, region, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "(operationally, functionally, or communicatively) incorporated into" another component, layer, region, or assembly, it can be directly formed on, directly on, directly connected to, or directly incorporated into the other component, layer, region, or assembly, or indirectly formed on, indirectly on, indirectly connected to, or indirectly incorporated into the other component, layer, region, or assembly, such that one or more intermediary components, layers, regions, or assemblies may be present. Furthermore, this can collectively mean direct or indirect incorporation or connection, as well as integral or non-integral incorporation or connection. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, it can be directly electrically connected or directly bonded to said other layer, region, and / or component, or one or more intermediary layers, regions, or components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, the connection is not limited to the connections shown in the accompanying drawings or detailed description, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for connection indicates an electrical connection, and "directly connected / directly bonded" or "directly on" means that a component is directly connected or directly bonded to another component or directly on another component without an intermediary component.

[0048] Furthermore, in this specification, when a portion of a layer, film, region, plate, etc., is formed on another portion, the formation direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, plate, etc., is formed "below" another portion, this includes not only the case where the portion is "directly" "below" the other portion, but also the case where there is another portion between the portion and the other portion. On the other hand, other expressions describing the relationship between components can be interpreted similarly, such as "between," "immediately adjacent to," or "adjacent to" and "directly adjacent to." It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0049] For the purposes of this disclosure, expressions such as “at least one of…” or “any one of…” or “one or more of…” modify the entire list of elements when following a list of elements, without modifying any individual element in that list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when expressions such as “at least one of…”, “multiple (species / beings)…”, “one of…”, and other prepositional phrases follow (before) a list of elements, they modify the entire list of elements, not individual elements within that list. When “C to D” is stated, unless otherwise specified, it means C or greater and D or less.

[0050] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are used only to distinguish one element, component, assembly, region, area, layer, part, or component from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, first assembly, first region, first layer, or first part described below may be designated as a second element, second assembly, second region, second layer, or second part. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0051] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2, and / or the third direction DR3.

[0052] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms, and the plural forms are intended to include the singular forms. It will also be understood that when the terms “comprising,” “having,” “including,” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0053] When one or more embodiments can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0054] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to explain the inherent bias in a measured or calculated value as would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of + / - 5% of the corresponding value. As used herein, “about” or “approximately” includes the stated value and means: within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, the use of “may” when describing embodiments of this disclosure refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that is tolerable to one of ordinary skill in the art. Other expressions may also be those from which “substantially” has been omitted.

[0055] In some embodiments, well-known structures and arrangements may be described in conjunction with one or more functional blocks (e.g., block diagrams), units, and / or modules in the accompanying drawings to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and processors performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, in some embodiments, blocks, units, and / or modules may be physically separated into two or more interacting individual blocks, units, and / or modules without departing from the scope of this disclosure. In addition, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of this disclosure.

[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or in the context of this specification, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0057] Figure 1 This is a diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0058] Reference Figure 1 The display device 10 according to one or more embodiments of the present disclosure may include a timing controller 11, a data driver 12, a scan driver 13, a pixel unit 14, and an emission driver 15.

[0059] The timing controller 11 can receive the grayscale of the input image (or input frame). The grayscale can include a first color grayscale, a second color grayscale, and a third color grayscale. The first color grayscale can be a grayscale used to represent a first color, the second color grayscale can be a grayscale used to represent a second color, and the third color grayscale can be a grayscale used to represent a third color.

[0060] In addition, the timing controller 11 can receive control signals for the image. The control signals may include a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal. The vertical synchronization signal may include multiple pulses, and the time of generation of each pulse may indicate the end of the previous frame period and the start of the current frame period. The interval between adjacent pulses of the vertical synchronization signal may correspond to one frame period. The horizontal synchronization signal may include multiple pulses, and the time of generation of each pulse may indicate the end of the previous horizontal period and the start of a new horizontal period. The interval between adjacent pulses of the horizontal synchronization signal may correspond to one horizontal period. The data enable signal may have an enabled level during a specific horizontal period and a disabled level during other periods. When the data enable signal has an enabled level, this indicates that color grayscale is supplied during the corresponding period.

[0061] The timing controller 11 can provide the data driver 12 with grayscale values ​​rendered or corrected to fit the specifications of the display device 10. Furthermore, the timing controller 11 can provide the scan driver 13 with clock signals, scan start signals, etc. The timing controller 11 can also provide the transmit driver 15 with clock signals, transmit stop signals, etc.

[0062] The data driver 12 can use the grayscale and control signals received from the timing controller 11 to generate the data voltages to be supplied to the data lines DL1, ..., DLj, ..., DLq. For example, the data driver 12 can sample the grayscale using a clock signal and apply the data voltage corresponding to the grayscale to the data lines DL1, ..., DLj, ..., DLq on a pixel-by-pixel basis. Here, q can be an integer greater than 1, and j can be an integer greater than 0 and less than q.

[0063] Scan driver 13 may include a first scan driver 13GW, a second scan driver 13GB, a third scan driver 13GI, and a fourth scan driver 13GC. The first scan driver 13GW can provide a first scan signal to first scan lines GW1, ..., GWi, ..., and GWp. Here, p can be an integer greater than 1, and i can be an integer greater than 0 and less than p. The second scan driver 13GB can provide a second scan signal to second scan lines GB1, ..., GBi, ..., and GBp. The third scan driver 13GI can provide a third scan signal to third scan lines GI1, ..., Gii, ..., GIp. The fourth scan driver 13GC can provide a fourth scan signal to fourth scan lines GC1, ..., GCI, ..., and GCp.

[0064] For example, the first scan driver 13GW can generate a first scan signal to be supplied to the first scan lines GW1 to GWp by receiving at least one scan clock signal or scan start signal from the timing controller 11. The first scan driver 13GW can sequentially provide the first scan signal, which consists of pulses with an on-level, to the first scan lines GW1 to GWp. For example, the first scan driver 13GW can be configured as a shift register and, under the control of the scan clock signal, generate the first scan signal in such a way that the scan start signal, in the form of pulses with an on-level, is sequentially transmitted to the next scan stage.

[0065] Each of the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC can be constructed similarly to the first scan driver 13GW, therefore, repeated descriptions will be omitted. In some embodiments, at least some of the first scan driver 13GW, the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC can be integrated.

[0066] Transmit driver 15 can generate transmit signals to be provided to transmit lines EM1, ..., EMi, ... and EMp by receiving at least one transmit clock signal or transmit stop signal from timing controller 11. Transmit driver 15 can sequentially provide transmit signals with cutoff-level pulses to transmit lines EM1 to EMp. For example, transmit driver 15 can be configured as a shift register and can generate transmit signals in the form of cutoff-level pulses, under the control of the transmit clock signal, in a manner that sequentially transmits transmit stop signals to the next transmit stage.

[0067] exist Figure 1 The diagram shows that the number of each of the first scan lines GW1 to GWp, the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the emission lines EM1 to EMp is p. However, in one or more other embodiments, the number of at least one of the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the emission lines EM1 to EMp may be p / 2 or less. For example, two adjacent pixel rows may share a second scan line. Similarly, two adjacent pixel rows may share a third scan line, a fourth scan line, or an emission line. The same pixel row means pixels connected to the same first scan line.

[0068] Pixel unit 14 (or display panel) may include pixels PXij. Each pixel PXij may be connected to a corresponding data line DLj, a corresponding scan line GWi, GBi, GIi, and GCI, and a corresponding emission line EMi. Each pixel PXij may include a light-emitting element that emits light based on the received data voltage.

[0069] Pixel unit 14 may include a first pixel emitting light of a first color, a second pixel emitting light of a second color, and a third pixel emitting light of a third color. The first color, second color, and third color may be different colors. For example, the first color may be one of red, green, and blue; the second color may be another color among red, green, and blue that is not the first color; and the third color may be another color among red, green, and blue that is not the first color or the second color. Alternatively, magenta, cyan, and yellow may be used instead of red, green, and blue as the first to third colors.

[0070] The pixels PXij of pixel unit 14 can be in various forms (such as diamond PENTILE). ® RGB stripes, S-stripes, true RGB and standard Pentium ® (PENTILE) ® (This is a registered trademark of Samsung Display Co., Ltd. of South Korea)

[0071] Figure 2 This is a diagram illustrating pixels according to one or more embodiments of the present disclosure.

[0072] Reference Figure 2 Pixel PXij may include pixel circuit PXC and light-emitting element LD. Pixel circuit PXC may include transistors T1, T2, T3, T4, T5, T6, T7 and T8 and storage capacitor Cst.

[0073] Pixel PXij can be located in the i-th pixel row and the j-th pixel column. Pixel PXij can be the first pixel used to represent the first color. The second pixel used to represent the second color and the third pixel used to represent the third color can be constructed similarly or identically to the first pixel; therefore, repeated descriptions will be omitted.

[0074] P-type transistors can be polycrystalline silicon semiconductor transistors. In polycrystalline silicon semiconductor transistors, the channel of the active layer can also include polycrystalline silicon semiconductor. For example, a polycrystalline silicon semiconductor transistor can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. Polycrystalline silicon semiconductor transistors have high electron mobility and, due to this high electron mobility, exhibit fast drive characteristics.

[0075] N-type transistors can be oxide semiconductor transistors. In oxide semiconductor transistors, the channel of the active layer can also be oxide semiconductor. For example, an oxide semiconductor transistor can be a low-temperature polycrystalline silicon oxide (LTPO) thin-film transistor. Compared to polycrystalline silicon semiconductor transistors, oxide semiconductor transistors have lower charge mobility. Therefore, the amount of leakage current generated in the off-state of an oxide semiconductor transistor can be smaller than that of a polycrystalline silicon semiconductor transistor.

[0076] The gate electrode of the first transistor T1 can be connected to a first node N1, the first electrode of the first transistor T1 can be connected to a second node N2, and the second electrode of the first transistor T1 can be connected to a third node N3. The first transistor T1 can be a driving transistor. The first transistor T1 can be a P-type transistor. According to one or more embodiments, the first transistor T1 may include a sub-gate electrode (or a back gate electrode, body), and the sub-gate electrode can receive a first power voltage ELVDD. According to one or more embodiments, the sub-gate electrode of the first transistor T1 can be connected to a gate electrode (e.g., the first node N1). According to one or more embodiments, the sub-gate electrode of the first transistor T1 may not exist.

[0077] The gate electrode of the second transistor T2 can be connected to the first scan line GWi, the first electrode of the second transistor T2 can be connected to the data line DLj, and the second electrode of the second transistor T2 can be connected to the second node N2.

[0078] The first scan driver 13GW can provide a first scan signal that determines the timing of the data voltage received by pixel PXij. For example, a second transistor T2 for receiving the first scan signal of the conduction level can be turned on. The second transistor T2 can apply the data voltage applied to data line DLj to the second node N2.

[0079] The gate electrode of the third transistor T3 can be connected to the fourth scan line GCI, the first electrode of the third transistor T3 can be connected to the first node N1, and the second electrode of the third transistor T3 can be connected to the third node N3. The third transistor T3 can be a diode-connected transistor. The third transistor T3 can be an N-type transistor.

[0080] The gate electrode of the fourth transistor T4 can be connected to the third scan line GIi, the first electrode of the fourth transistor T4 can be connected to the first node N1, and the second electrode of the fourth transistor T4 can receive the first initialization voltage VINT. The fourth transistor T4 can be a gate initialization transistor. The fourth transistor T4 can be an N-type transistor.

[0081] The gate electrode of the fifth transistor T5 can be connected to the emitter line EMi, the first electrode of the fifth transistor T5 can receive the first power voltage ELVDD, and the second electrode of the fifth transistor T5 can be connected to the second node N2. The fifth transistor T5 can be the first emitter control transistor. The fifth transistor T5 can be a P-type transistor.

[0082] The gate electrode of the sixth transistor T6 can be connected to the emitter line EMi, the first electrode of the sixth transistor T6 can be connected to the third node N3, and the second electrode of the sixth transistor T6 can be connected to the fourth node N4. The sixth transistor T6 can be the second emitter control transistor. The sixth transistor T6 can be a P-type transistor.

[0083] The gate electrode of the seventh transistor T7 can be connected to the second scan line GBi, the first electrode of the seventh transistor T7 can receive the second initialization voltage VAINT (or anode initialization voltage), and the second electrode of the seventh transistor T7 can be connected to the fourth node N4. The seventh transistor T7 can be an anode initialization transistor. The seventh transistor T7 can be a P-type transistor.

[0084] The second scan driver 13GB can provide a second scan signal that controls the timing of providing the second initialization voltage VAINT (or anode initialization voltage). For example, the second transistor T7, which receives the second scan signal at the on level, can be turned on, and the second initialization voltage VAINT can be applied to the anode electrode of the light-emitting element LD, so that the anode voltage of the light-emitting element LD is initialized to the second initialization voltage VAINT.

[0085] The gate electrode of the eighth transistor T8 can be connected to the second scan line GBi, the first electrode of the eighth transistor T8 can receive the bias voltage VOBS, and the second electrode of the eighth transistor T8 can be connected to the second node N2. The eighth transistor T8 can be a bias transistor. The eighth transistor T8 can be a P-type transistor.

[0086] The first electrode of the storage capacitor Cst can receive a first electrical voltage ELVDD, and the second electrode of the storage capacitor Cst can be connected to the first node N1.

[0087] The anode electrode of the light-emitting element (LD) can be connected to the fourth node N4, and the cathode electrode of the LD can receive the second electrical voltage ELVSS. The LD can emit light of one of a first color, a second color, and a third color. The LD can be a light-emitting diode (LED). The LD can be constructed as an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot / well light-emitting diode, etc. One LD is disposed in each pixel PXij. However, in one or more other embodiments, multiple LDs can be disposed in each pixel PXij. Multiple LDs can be connected in series, parallel, series / parallel, etc.

[0088] Figures 3 to 6 This is a diagram illustrating the change of display frequency according to one or more embodiments of the present disclosure.

[0089] Display device 10 may support variable refresh rate (VRR). Refresh rate is the frequency at which data voltage is written to pixel PXij, and is also called screen scan rate or screen refresh rate. Refresh rate can represent the number of image frames reproduced per second.

[0090] Pixel unit 14 can display an image at a first frequency AHz in the first mode (see...) Figure 3 And it can display images at a second frequency BHz, which is lower than the first frequency AHz, in the second mode (see...). Figure 4 ).

[0091] For example, each frame period 1F in the first mode may include an address scan period AS and a self-scan period SS relative to each pixel PXij. For example, each frame period 1F in the second mode may include an address scan period AS and multiple self-scan periods SS relative to each pixel PXij. When the second frequency BHz decreases, the number of self-scan periods SS included in a frame period 1F can be increased. In another example, each frame period 1F in a particular mode may include only an address scan period AS relative to each pixel PXij, without including self-scan periods SS.

[0092] The address scan period AS is the period during which data voltage is written to pixel PXij. The address scan period AS can also be referred to as the data programming period for receiving data voltage from data line DLj.

[0093] The self-scanning period SS is the period during which data voltage is not written to pixel PXij. During the emission period of the self-scanning period SS, pixel PXij can emit light using the data voltage written in the address scan period AS. For example, the length of the self-scanning period SS can be equal to the length of the address scan period AS.

[0094] Pixel unit 14 can display an image at a third frequency CHz in the third mode (see...) Figure 5 ), and can display images in the fourth mode at a fourth frequency DHz, which is less than the third frequency CHz (see Figure 6 ).

[0095] In the third and fourth modes, an auxiliary scan period XS following the address scan period AS and an auxiliary scan period XS following the self-scan period SS may be included.

[0096] Because the auxiliary scan period XS is the period during which the data voltage is not written to pixel PXij, it can be similar to the self-scan period SS. During the emission period of the auxiliary scan period XS, pixel PXij can emit light using the data voltage written in the address scan period AS. For example, the length of the auxiliary scan period XS can be the same as the length of the address scan period AS. However, the auxiliary scan period XS differs from the self-scan period SS in that a second scan signal with a conduction level is not supplied. For this purpose, refer to the description below. Figure 8 and Figure 9 .

[0097] The display device 10 does not necessarily have to be driven in all of the first, second, third, and fourth modes. The display device 10 may also be driven in only at least one of the first, second, third, and fourth modes. For example, the display device 10 may be driven in only one of the first, second, third, and fourth modes. Alternatively, the display device 10 may be driven only in the first and second modes, and may not be driven in the third and fourth modes. On the other hand, the display device 10 may be driven only in the third and fourth modes, and may not be driven in the first and second modes.

[0098] Figure 7 This is a diagram illustrating an address scan period according to one or more embodiments of the present disclosure. In the explanation... Figure 7 At that time, refer to Figure 2 The pixel PXij.

[0099] At time point t1a, when the cutoff level (high level) transmit signal is provided to the transmit line EMi, the fifth transistor T5 and the sixth transistor T6 are turned off, and the pixel PXij is in a non-transmitting state.

[0100] At time point t2a, when the second scan signal with a low conduction level is provided to the second scan line GBi, the seventh transistor T7 and the eighth transistor T8 are turned on. Conversely, when the fourth scan signal with a high conduction level is provided to the fourth scan line GCI, the third transistor T3 is turned on. At this time, the first transistor T1 can be biased by providing a bias voltage VOBS higher than that of its gate electrode (first node N1) to its source electrode (first electrode, second node N2). When the first transistor T1 is biased, the data voltage of the subsequent input current frame can be lower than the bias voltage VOBS. Therefore, hysteresis can be reduced or prevented, regardless of the magnitude of the data voltage of the previous frame.

[0101] For reference, hysteresis refers to the phenomenon that the source-drain current curve of a transistor relative to the gate-source voltage differs when the data voltage of the current frame is higher than that of the previous frame, compared to the source-drain current curve of a transistor relative to the gate-source voltage when the data voltage of the current frame is lower than that of the previous frame.

[0102] At time point t3a, when the third scan signal with a high conduction level is provided to the third scan line GIi, the fourth transistor T4 is turned on. Therefore, the first initialization voltage VINT is provided to the first node N1. The first initialization voltage VINT is low enough to cause the first transistor T1 to enter the on state.

[0103] At time t4a, when the fourth scan signal with a high conduction level is provided to the fourth scan line GCI, the third transistor T3 is turned on. Therefore, the first transistor T1 is in a diode connection state where the drain electrode (second electrode) and the gate electrode are connected.

[0104] At time point t5a, when a low-level scan signal is provided to the first scan line GWi, the second transistor T2 is turned on. Therefore, the data voltage of the data line DLj can be supplied to the first node N1 through the on-state second transistor T2, first transistor T1, and third transistor T3. At this time, the voltage of the first node N1 can be a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The storage capacitor Cst can maintain the difference between the first power voltage ELVDD and the compensation voltage.

[0105] At time point t6a, when a low-level scan signal is provided to the second scan line GBi, the seventh transistor T7 and the eighth transistor T8 are turned on. When the seventh transistor T7 is turned on, the second initialization voltage VAINT can be provided to the anode electrode of the light-emitting element LD, and the light-emitting element LD can be initialized with a charge corresponding to the voltage difference between the second initialization voltage VAINT and the second power voltage ELVSS. Therefore, low grayscale performance of the light-emitting element LD can be promoted.

[0106] At time t7a, when a low-level transmit signal is provided to the transmit line EMi, the fifth transistor T5 and the sixth transistor T6 can be turned on. Therefore, a path is formed for the drive current flowing from the first power voltage ELVDD through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting element LD to the second power voltage ELVSS.

[0107] The drive current can be adjusted based on the voltage held in the storage capacitor Cst. The light-emitting element LD emits light at a brightness corresponding to the drive current. The light-emitting element LD can emit light until a cutoff level emission signal is provided to the emission line EMi.

[0108] Figure 8 This is a diagram illustrating a self-scanning period according to one or more embodiments of the present disclosure. In the explanation... Figure 8 At that time, refer to Figure 2 The pixel PXij.

[0109] At time point t1b, when the cutoff level (high level) transmit signal is provided to the transmit line EMi, the fifth transistor T5 and the sixth transistor T6 are turned off, and the pixel PXij is in a non-transmitting state.

[0110] During the self-scanning period (from time point t1b to time point t3b), the scan signals maintain a cutoff level in the first scan line GWi, the third scan line GIi, and the fourth scan line GCI. Therefore, the voltage of the first node N1 remains unchanged.

[0111] At time point t2b, when a low-level scan signal is provided to the second scan line GBi, the seventh transistor T7 and the eighth transistor T8 are turned on. When the seventh transistor T7 is turned on, the second initialization voltage VAINT can be provided to the anode electrode of the light-emitting element LD, and the light-emitting element LD can be initialized with a charge corresponding to the voltage difference between the second initialization voltage VAINT and the second power voltage ELVSS. Therefore, low grayscale performance of the light-emitting element LD can be promoted.

[0112] At time point t3b, when a low-level transmit signal is provided to the transmit line EMi, the fifth transistor T5 and the sixth transistor T6 can be turned on. Therefore, a path is formed for the drive current flowing from the first power voltage ELVDD through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting element LD to the second power voltage ELVSS.

[0113] The drive current can be adjusted based on the voltage held in the storage capacitor Cst. Because the voltage of the first node N1, recorded during the address scan period AS, is maintained during the self-scan period SS, the brightness of the light-emitting element LD during the self-scan period SS can be the same as the brightness of the light-emitting element LD during the address scan period AS.

[0114] Figure 9 This is a diagram illustrating the auxiliary scanning period according to one or more embodiments of the present disclosure.

[0115] Figure 9 The auxiliary scanning period is Figure 5 and Figure 6 An example of the auxiliary scan period XS. Figure 9 During the auxiliary scan period starting from time point t1c, the transmitted signal in the transmit line EMi can have the same characteristics as... Figure 7 The signals in the address scan period have the same waveform. However, the first scan signal to the fourth scan signal can remain at the cutoff level. Therefore, the voltage of the first node N1 remains unchanged, and the voltage difference between the two ends of the storage capacitor Cst can be maintained. Therefore, the light-emitting element LD in Figure 9 The brightness after the auxiliary scan period can be the same as the brightness of the light-emitting element (LD) after the address scan period immediately preceding it.

[0116] Figure 10 and Figure 11 This is a diagram illustrating the relationship between pads, connecting wires, and signal lines according to one or more embodiments of the present disclosure.

[0117] Reference Figure 10 The substrate SUB of the display device 10 may include a display area DA and a non-display area NDA. The display area DA may be an area where pixels are located, and the non-display area NDA may be an area where no pixels are located. Additionally, according to one or more embodiments, when the display device 10 includes an optical sensor, the substrate SUB may include a sensing area SA and a non-sensing area NSA. The sensing area SA is an area where the optical sensor is located, and the non-sensing area NSA may be an area where no optical sensor is located.

[0118] For example, the size and shape of the display area DA can be the same as the size and shape of the sensing area SA. Similarly, the size and shape of the non-display area NDA can be the same as the size and shape of the non-sensing area NSA. However, in one or more other embodiments, the sensing area SA can be larger or smaller than the display area DA. Depending on the size of the sensing area SA, the non-sensing area NSA can be smaller or larger than the non-display area NDA.

[0119] In the following text, the planar orientation of the substrate SUB is defined relative to a first direction DR1 and a second direction DR2 that is substantially perpendicular to the first direction DR1, and the vertical orientation of the substrate SUB is defined relative to a third direction DR3. However, for ease of explanation, the substrate SUB can be bent. For example, the portion of the substrate SUB that protrudes toward the first direction DR1 includes a pad region PADA, wherein the protruding portion can be bent to reduce or minimize the ineffective area. Furthermore, by also bending other side surfaces of the substrate SUB, a display device 10 including a narrow bezel that reduces or minimizes the non-display area NDA can be achieved.

[0120] The substrate SUB may include a first connection region BRSA1 and a second connection region BRSA2. The first connection region BRSA1 and the second connection region BRSA2 may commonly include signal lines SL1 and SL2 extending in a first direction DR1, and first connection lines BRSV1 and BRSV2. The first connection region BRSA1 may include a second connection line BRSH1 extending in a second direction DR2. Conversely, the second connection region BRSA2 may include a second connection line BRSH2 extending in the second direction DR2.

[0121] Signal lines SL1 and SL2 may include data lines DL1 to DLq. If the display device 10 includes an optical sensor, signal lines SL1 and SL2 may include readout lines of the optical sensor. Signal lines SL1 and SL2 may extend continuously in the first direction DR1 without interruption in the middle.

[0122] On the other hand, the first connecting lines BRSV1 and BRSV2 and the second connecting lines BRSH1 and BRSH2 can be appropriately disconnected in the middle. The first connecting lines BRSV1 and BRSV2 and the second connecting lines BRSH1 and BRSH2 can transmit signals to signal lines SL1 and SL2 by connecting them to the corresponding pads in the pad area PADA.

[0123] like Figure 10 As shown, the corners of the base SUB can be angular or curved. The curved shape of the corners makes it difficult to implement traditional fan-out wiring structures. The second connection area BRSA2 enables a fanless structure.

[0124] On the other hand, the first connection area BRSA1 can be a readout connection area. For example, the second connection line BRSH1 of the first connection area BRSA1 can be a second readout connection line connected to the readout line of the optical sensor. For example, the first signal line SL1 can be a readout line. In this case, the first connection line BRSV1 connected to the second connection line BRSH1 in the first connection area BRSA1 can be a first readout connection line. One of the readout lines, one of the first readout connection lines, and one of the second readout connection lines can be connected to each other. Their connection order can be irrelevant, and "connected to each other" can mean connected to the "same electrical node". Lines connected to the same electrical node will have the same voltage. By connecting the first connection line BRSV1 to the corresponding pad, the sensed current received from the optical sensor can be transmitted to the integrated chip (IC) connected to the pad.

[0125] Additionally, the second connection area BRSA2 can be a data connection area. For example, the second connection line BRSH2 of the second connection area BRSA2 can be a data line DL1 to DLq connected to a pixel (see...). Figure 1 The second data connection line is the second data connection line. For example, the second signal line SL2 can be data lines DL1 to DLq. In this case, the first connection line BRSV2, which is connected to the second connection line BRSH2 in the second connection area BRSA2, can be the first data connection line. One of the data lines, one of the first data connection lines, and one of the second data connection lines can be connected to each other. Their connection order can be irrelevant, and "connected to each other" can mean connected to the "same electrical node". Lines connected to the same electrical node will have the same voltage. By connecting the first connection line BRSV2 to the corresponding pad, the data voltage received from the IC can be transmitted to the pixel.

[0126] exist Figure 10 In the diagram, the second connecting region BRSA2 is shown positioned from the first connecting region BRSA1 in the first direction DR1. However, this is only one example. In another example, the first connecting region BRSA1 could also be configured to be positioned from the second connecting region BRSA2 in the first direction DR1.

[0127] On the other hand, the first connecting region BRSA1 and the second connecting region BRSA2 do not necessarily have to be separated from each other in the first direction DR1. (Refer to...) Figure 11 The first connecting region BRSA1 and the second connecting region BRSA2 can also be separated from each other in the second direction DR2.

[0128] Additionally, in one or more other embodiments, there may be no distinction between the first connection region BRSA1 and the second connection region BRSA2. For example, the distinction between the readout connection region and the data connection region may become meaningless by placing a second readout connection line and a second data connection line alternately arranged on the first direction DR1.

[0129] However, in one or more embodiments, the display device 10 may further include an additional sensor layer on top of the layer in which pixels and optical sensors are formed (e.g., on the third-direction DR3). The additional sensor layer may be a sensor layer for sensing user touch and an active pen, and may be formed in various forms such as resistive, capacitive, electromagnetic induction (EMI), electromagnetic resonance (EMR), optical, etc. In one or more other embodiments, the additional sensor layer may also be located below the layer in which pixels and optical sensors are formed (e.g., in the direction opposite to the third-direction DR3).

[0130] Figures 12 to 22 This is a diagram illustrating the layout of pixel units according to one or more embodiments of the present disclosure.

[0131] Reference Figure 12 According to one or more embodiments of the present disclosure, the pixel unit 14 may include a substrate SUB, a first insulating layer INS1 on the substrate SUB, a first conductive layer CEL1 on the first insulating layer INS1, a second insulating layer INS2 on the first conductive layer CEL1, a first active layer ACT1 on the second insulating layer INS2, a third insulating layer INS3 on the first active layer ACT1, a second conductive layer CEL2 on the third insulating layer INS3, a fourth insulating layer INS4 on the second conductive layer CEL2, a third conductive layer CEL3 on the fourth insulating layer INS4, a fifth insulating layer INS5 on the third conductive layer CEL3, and so on. The second active layer ACT2 on the fifth insulating layer INS5, the sixth insulating layer INS6 on the second active layer ACT2, the fourth conductive layer CEL4 on the sixth insulating layer INS6, the seventh insulating layer INS7 on the fourth conductive layer CEL4, the fifth conductive layer CEL5 on the seventh insulating layer INS7, the eighth insulating layer INS8 on the fifth conductive layer CEL5, the sixth conductive layer CEL6 on the eighth insulating layer INS8, the ninth insulating layer INS9 on the sixth conductive layer CEL6, and the seventh conductive layer CEL7 on the ninth insulating layer INS9 (as used herein, "on" or "located on" may mean "above").

[0132] The substrate SUB can be made of various materials such as glass, polymers, and metals. Depending on the applicable product, the substrate SUB can be selected as either a rigid substrate or a flexible substrate. When the substrate SUB is constructed to include a high molecular weight organic material, it can be composed of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. Alternatively, the substrate SUB can be made of glass, fiberglass reinforced plastic (FRP), etc.

[0133] The first active layer ACT1 and the second active layer ACT2 can be semiconductor layers. For example, the first active layer ACT1 can be composed of polysilicon semiconductor, and the second active layer ACT2 can be composed of oxide semiconductor. The first active layer ACT1 may include polysilicon semiconductor transistors (e.g., transistors T1, T2, T5, T6, T7, and T8) (see...). Figure 2 The second active layer ACT2 may include the channel, first electrode, and second electrode of an oxide semiconductor transistor (e.g., transistors T3 and T4). The first and second electrodes of each transistor may be doped with impurities for conductivity.

[0134] The conductive layers CEL1 to CEL7 can be composed of a single layer or multiple layers, and can be made of known conductive materials such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and platinum (Pt)).

[0135] Insulating layers INS1 to INS9 can be inserted to electrically separate or insulate adjacent active layers ACT1 and ACT2 and conductive layers CEL1 to CEL7. Suitable electrode patterns can be connected to each other through contact holes formed in each insulating layer INS1 to INS9. Insulating layers INS1 to INS9 can consist of organic, inorganic, or organic / inorganic insulating layers, and can be a single layer or multiple layers. For example, insulating layers INS1 to INS9 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y It is at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0136] Reference Figure 13 The diagram shows a plan view of the first conductive layer CEL1. For example, the first electrical voltage ELVDD (see...) Figure 2This can be provided to the first conductive layer CEL1. The first conductive layer CEL1 may include the sub-gate electrode of the first transistor T1.

[0137] Reference Figure 14 The diagram shows a plan view of the first active layer ACT1. For example, the first active layer ACT1 may include the channel T1ch of the first transistor T1, the channel T2ch of the second transistor T2, the channel T5ch of the fifth transistor T5, the channel T6ch of the sixth transistor T6, the channel T7ch of the seventh transistor T7, and the channel T8ch of the eighth transistor T8.

[0138] According to one or more embodiments of this disclosure, the first active layer ACT1 may include an etch stop pattern VA_ETS. For example, the etch stop pattern VA_ETS may extend in the second direction DR2. The etch stop pattern VA_ETS may have a different etch rate than the insulating layers INS3 to INS7, or may include materials etched under different etch conditions.

[0139] This can reduce or minimize cracks appearing beneath the etch stop pattern VA_ETS. Additionally, the first active layer ACT1 can correspond to the optimal depth used to position the etch stop pattern VA_ETS. The deeper the inorganic layer is etched, the more the stress generated by bending can be reduced or minimized. Therefore, the etch stop pattern VA_ETS can also be configured to be located within the first conductive layer CEL1. However, to etch up to the top of the first conductive layer CEL1, the etching process can be applied two or more times (see...). Figure 19 The second contact hole (CNT2). Therefore, in the display device 10 including the first active layer ACT1 and the second active layer ACT2, the etch stop pattern VA_ETS included in the first active layer ACT1 is of technical significance for its position.

[0140] Reference Figure 15 The diagram shows a plan view of the second conductive layer CEL2. For example, the second conductive layer CEL2 may include a first scan line GWi and a second scan line GBi extending in the second direction DR2. Additionally, the second conductive layer CEL2 may include a storage capacitor Cst (see...). Figure 2 Part of ).

[0141] Reference Figure 16 The diagram shows a plan view of the third conductive layer CEL3. The third conductive layer CEL3 may include a storage capacitor Cst (see...). Figure 2 Part of ).

[0142] Reference Figure 17The diagram shows a plan view of the second active layer ACT2. For example, the second active layer ACT2 may include the channel T3ch of the third transistor T3 and the channel T4ch of the fourth transistor T4.

[0143] Reference Figure 18 The diagram shows a plan view of the fourth conductive layer CEL4. For example, the fourth conductive layer CEL4 may include a third scan line GIi, a fourth scan line GCI, an emitter line EMi, and a bias voltage line VOBSL extending in the second direction DR2. The bias voltage VOBS (see...) Figure 2 It can provide bias voltage line VOBSL.

[0144] Some patterns of the fourth conductive layer CEL4 can be connected to the lower conductive layer (e.g., the first conductive layer CEL1, the second conductive layer CEL2, and the third conductive layer CEL3) or the first active layer ACT1 through the first contact hole CNT1.

[0145] Reference Figure 19 The diagram shows a plan view of the fifth conductive layer CEL5. For example, the fifth conductive layer CEL5 may include a second connection line BRSH21, a second initialization voltage line VAINT_R, and a cover layer VA_CLD. For example, the second initialization voltage line VAINT_R and the cover layer VA_CLD may extend in the second direction DR2. The second connection line BRSH21 may correspond to... Figure 10 and Figure 11 Part of the second connecting line BRSH2 in the middle.

[0146] Some patterns on the fifth conductive layer CEL5 can be connected to the first active layer ACT1 through the second contact hole CNT2. Additionally, some patterns on the fifth conductive layer CEL5 can be connected to the second active layer ACT2 through the third contact hole CNT3. Some patterns on the fifth conductive layer CEL5 can be connected to the sixth conductive layer CEL6 through the fourth contact hole CNT4.

[0147] The capping layer VA_CLD can contact the upper part of the etch stop pattern VA_ETS of the first active layer ACT1 through the second contact hole CNT2. At this time, the second contact hole CNT2 can extend along the extension direction of the capping layer VA_CLD (e.g., the second direction DR2).

[0148] According to one or more embodiments, the overlay VA_CLD can reduce the occurrence of longitudinal beams (e.g., unintended metal protrusions) on the upper part of the valley structure, thereby reducing or preventing the possibility of undesirable short circuits.

[0149] Additionally, the overlay layer VA_CLD can be used as the second initialization voltage line VAINT_GB. For example, the second initialization voltage line VAINT_R can supply the second initialization voltage VAINT to pixels of the first color, and the second initialization voltage line VAINT_GB can supply the second initialization voltage VAINT to pixels of the second and third colors. For example, the first color can be red, the second color can be green, and the third color can be blue. The total number of pixels of the second and third colors can be greater than the total number of pixels of the first color. Compared to the second initialization voltage line VAINT_R, the overlay layer VA_CLD has a larger vertical area, which makes it suitable for supplying the second initialization voltage VAINT to a larger number of pixels of the second and third colors. For example, the second initialization voltage VAINT supplied to the second initialization voltage line VAINT_R and the second initialization voltage VAINT supplied to the second initialization voltage line VAINT_GB can be the same or different from each other. Whether the second initialization voltage VAINT is the same can depend on the characteristics of the light-emitting elements emitting the first to third colors.

[0150] Reference Figure 20 The diagram shows a plan view of the sixth conductive layer CEL6. For example, the sixth conductive layer CEL6 may include data lines DLj and DL(j+1) extending in the first direction DR1, and first connection lines BRSV21 and BRSV22. The first connection lines BRSV21 and BRSV22 may correspond to... Figure 10 and Figure 11 The first connecting line BRSV2 in the diagram. Data line DLj can be a data line connected to a pixel located in column j. Data line DL(j+1) can be a data line connected to a pixel located in column j+1.

[0151] Some patterns on the sixth conductive layer CEL6 can be connected to the fifth conductive layer CEL5 through the fourth contact hole CNT4. Some patterns on the sixth conductive layer CEL6 can be connected to the seventh conductive layer CEL7 through the fifth contact hole CNT5.

[0152] Reference Figure 21 , showing that Figures 13 to 20 The layout of the floor plan is stacked.

[0153] Reference Figure 22 It shows along Figure 21 The sectional view taken by line A-A' in the description. Figure 22 When, omission and Figures 12 to 21 Description of repeated content.

[0154] The third transistor T3, comprising the channel T3ch located in the second active layer ACT2, is illustrated in the illustration (see [reference]). Figure 2 ) and the sixth transistor T6, including channel T6ch located in the first active layer ACT1 (see Figure 2 The cross-section of the sixth transistor T6. The second electrode of the sixth transistor T6, located in the first active layer ACT1, can be connected to the anode electrode ANE of the light-emitting element LD through the second contact hole CNT2, the fourth contact hole CNT4, and the fifth contact hole CNT5.

[0155] The valley structure VAS can be located between at least some of the pixels and can penetrate multiple insulating layers INS3, INS4, INS5, INS6, and INS7. For example, the insulating layers INS3, INS4, INS5, INS6, and INS7 can be composed of inorganic layers. Even if the display device 10 is bent through the valley structure VAS, the occurrence of cracks can be reduced or minimized by increasing stress dispersion or maximizing stress dispersion.

[0156] The channel T6ch of the sixth transistor T6 can be separated from the substrate SUB by a first distance. For example, the substrate SUB and the first active layer ACT1 can be separated by a first distance.

[0157] The channel T3ch of the third transistor T3 can be separated from the substrate SUB by a second distance. For example, the substrate SUB and the second active layer ACT2 can be separated by a second distance.

[0158] The lower part of the valley structure VAS can be separated from the base SUB by a third distance. In this case, the second distance can be greater than both the first and third distances. Furthermore, the first and third distances can be different from each other.

[0159] For example, a valley-structured VAS may include a second contact hole CNT2. As described above, the second contact hole CNT2 is an etched hole formed to connect some patterns of the fifth conductive layer CEL5 to the first active layer ACT1. Therefore, a separate additional process can be eliminated to produce the valley-structured VAS.

[0160] Therefore, the lower part of the valley structure VAS can contact the upper part of the first active layer ACT1. Figure 22In this context, the third distance can be equal to the distance between the upper part of the first active layer ACT1 (e.g., the upper part of the etch stop pattern VA_ETS) and the substrate SUB. The first distance can be equal to the distance between the bottom of the first active layer ACT1 and the substrate SUB. Therefore, the first and third distances can be different. For example, the third distance can be greater than the first distance. The first active layer ACT1 may include the etch stop pattern VA_ETS. The etch stop pattern VA_ETS can reduce or minimize cracks that appear below the etch stop pattern VA_ETS. In addition, the first active layer ACT1 can correspond to an optimal depth for positioning the etch stop pattern VA_ETS. The deeper the inorganic layer is etched, the more the stress caused by bending can be reduced or minimized. Therefore, the etch stop pattern VA_ETS can also be configured to be located in the first conductive layer CEL1. However, in order to etch up to the top of the first conductive layer CEL1, the etching process can be applied two or more times (see...). Figure 19 The second contact hole (CNT2). Therefore, in the display device 10 including the first active layer ACT1 and the second active layer ACT2, the etch stop pattern VA_ETS included in the first active layer ACT1 is of technical significance for its position.

[0161] The upper part of the valley structure VAS can be separated from the substrate SUB by a fourth distance. This fourth distance can be equal to the distance between the fifth conductive layer CEL5 and the substrate SUB. Therefore, the fourth distance can be greater than the second distance.

[0162] The valley structure VAS may include a cover layer VA_CLD that covers the upper, lower, and sidewalls of the valley structure VAS and includes a conductive material. According to one or more embodiments, the cover layer VA_CLD can reduce the generation or occurrence of longitudinal beams (e.g., unintended metal protrusions) on the upper part of the valley structure VAS, thereby reducing or preventing the possibility of unwanted electrical short circuits.

[0163] As described above, the initialization voltage can be provided to the overlay layer VA_CLD. The overlay layer VA_CLD can be used as a second initialization voltage line VAINT_GB (see...). Figure 19For example, the second initialization voltage line VAINT_R can supply the second initialization voltage VAINT to pixels of the first color, and the second initialization voltage line VAINT_GB can supply the second initialization voltage VAINT to pixels of the second and third colors. For example, the first color can be red, the second color can be green, and the third color can be blue. The total number of pixels of the second and third colors can be greater than the total number of pixels of the first color. Compared to the second initialization voltage line VAINT_R, the overlay layer VA_CLD has a larger vertical area, which makes the overlay layer VA_CLD suitable for supplying the second initialization voltage VAINT to a larger number of pixels corresponding to the second and third colors. For example, the second initialization voltage VAINT provided to the second initialization voltage line VAINT_R and the second initialization voltage VAINT provided to the second initialization voltage line VAINT_GB can be the same or different from each other. Whether the second initialization voltage VAINT is the same can depend on the characteristics of the light-emitting elements emitting the first to third colors.

[0164] Figures 23 to 26 This is a diagram illustrating a valley structure according to one or more other embodiments of the present disclosure. (Refer to...) Figures 23 to 26 When describing, the part related to Figure 22 Repeated descriptions of the same content.

[0165] Reference Figure 23 The lower part of the valley structure VASa can contact the upper part of the first conductive layer CEL1 located between the substrate SUB and the first active layer ACT1. Some patterns of the first conductive layer CEL1 can be included as an etch stop pattern VA_ETSa. The capping layer VA_CLDa can contact the upper part of the etch stop pattern VA_ETSa through the second contact hole CNT2a. The second contact hole CNT2a can penetrate to the second insulating layer INS2, which serves as an inorganic layer, thus providing more effective stress dispersion in the display device 10.

[0166] Reference Figure 24 The lower part of the valley structure VASb can contact the upper part of the second conductive layer CEL2 located between the first active layer ACT1 and the second active layer ACT2. Some patterns of the second conductive layer CEL2 can be included as etch stop patterns VA_ETSb. The capping layer VA_CLDb can contact the upper part of the etch stop pattern VA_ETSb through the second contact hole CNT2b. Various conductive layers can be included as etch stop patterns VA_ETSb.

[0167] Reference Figure 25The lower part of the valley structure VASc can contact the upper part of the third conductive layer CEL3 located between the first active layer ACT1 and the second active layer ACT2. Some patterns of the third conductive layer CEL3 can be included as the etch stop pattern VA_ETSc. The capping layer VA_CLDc can contact the upper part of the etch stop pattern VA_ETSc through the second contact hole CNT2c. Various conductive layers can be included as the etch stop pattern VA_ETSc.

[0168] Reference Figure 26 The display device 10 may not include or may omit the etch stop pattern. As described above, more than two etch processes can be suitable for etching from the seventh insulating layer INS7 to the second insulating layer INS2. Therefore, even without an etch stop pattern, the lower part of the valley structure VASd can be positioned on the third-direction DR3 of the first conductive layer CEL1, even if the second contact hole CNT2d is etched only once. In this case, the cover layer VA_CLDd can contact the second insulating layer INS2 through the second contact hole CNT2d.

[0169] Reference Figures 22 to 25 This explains that various conductive or active layers can include etch stop patterns. Additionally, other conductive or active layers may also include etch stop patterns.

[0170] Additionally, refer to Figures 22 to 26 The valley structure is described as a capping layer included in the fifth conductive layer CEL5. Alternatively, other conductive or active layers may also include capping layers. However, in one or more other embodiments, the display device 10 may not include a capping layer, or the capping layer may be omitted.

[0171] Figures 27 to 32 This is a diagram illustrating the relationship between pixels and valley structures according to embodiments of the present disclosure.

[0172] The display device 10 may include multiple valley structures VAS(i-1), VASi, VAS(i+1), VAS(i-1)', VASi', VAS(i+1)', VAS(j-1), VASj, VAS(j+1), VAS(j-1)', VASj', and VAS(j+1)'. Pixels PXij, PXi(j+1), PX(i+1)j, and PX(i+1)(j+1) may be arranged on the first direction DR1 and the second direction DR2.

[0173] Multiple valley structures VAS(i-1) to VAS(j+1)' can extend over at least one of the first direction DR1 and the second direction DR2. For example, refer to Figure 27 and Figure 28The valley structures VAS(i-1), VASi, VAS(i+1), VAS(i-1)', VASi', and VAS(i+1)' can extend along the second direction DR2. On the other hand, referring to... Figure 29 and Figure 30 The valley structures VAS(j-1), VASj, VAS(j+1), VAS(j-1)', VASj', and VAS(j+1)' can extend along the first direction DR1. On the other hand, referring to... Figure 31 and Figure 32 The valley structures VAS(i-1), VASi, VAS(i+1), VAS(i-1)', VASi', VAS(i+1)', VAS(j-1), VASj, VAS(j+1), VAS(j-1)', VASj' and VAS(j+1)' can (e.g., respectively) extend in the first direction DR1 and in the second direction DR2.

[0174] Reference Figure 27 , Figure 29 and Figure 31 The length of each of the multiple valley structures VAS(i-1), VASi, VAS(i+1), VAS(j-1), VASj and VAS(j+1) can be greater than the length of each of the pixels (e.g., in a planar graph) relative to the direction along which the multiple valley structures VAS(i-1), VASi, VAS(i+1), VAS(j-1), VASj and VAS(j+1) extend.

[0175] Reference Figure 28 , Figure 30 and Figure 32 The length of each of the multiple valley structures VAS(i-1)', VASi', VAS(i+1)', VAS(j-1)', VASj' and VAS(j+1)' can be less than the length of each of the pixels (e.g., in a planar graph).

[0176] exist Figures 27 to 32 In one embodiment, the spacing between adjacent valley structures is configured to include one pixel. However, in one or more other embodiments, the spacing between adjacent valley structures may be configured to include two or more pixels.

[0177] Figure 33 This is a block diagram of an electronic device according to one or more embodiments. (Refer to...) Figure 33An electronic device 10ET according to one or more embodiments may include a display module 11ET, a processor 12ET, a memory 13ET, and a power module 14ET. The display module 11ET may also be referred to as a display device.

[0178] The processor 12ET may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In one or more embodiments, from a functional or structural point of view, the processor 12ET may be configured to be divided into two or more components. For example, the processor 12ET may include a main processor in the form of a first driver chip including a central processing unit and an auxiliary processor in the form of a second driver chip including a controller that receives image signals from the main processor and processes the image signals to conform to the interface specifications of the display module 11ET. The processor 12ET can provide image data. The display module 11ET can display an image based on the grayscale of the image data.

[0179] The memory 13ET may include at least one of non-volatile memory and volatile memory. The memory 13ET may store data information suitable for the operation of the processor 12ET or the display module 11ET. When the processor 12ET runs an application stored in the memory 13ET, image data signals and / or input control signals may be sent to the display module 11ET, and the display module 11ET may process the provided signals and output image information through a display screen.

[0180] The power module 14ET may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate power suitable for the operation of the electronic device 10ET. The power conversion through the power conversion module may include, but is not limited to, DC-DC conversion, AC-DC conversion, and DC-AC conversion.

[0181] The electronic device 10ET may also include an input module 15ET, a non-image output module 16ET, and / or a communication module 17ET.

[0182] Input module 15ET can provide input information to processor 12ET and / or display module 11ET. Input module 15ET may include various sensor modules as well as physical buttons, keyboards, and microphones. Examples of sensor modules may include biometric sensors (such as blood pressure sensors, blood glucose sensors, electrocardiogram sensors, heart rate sensors, etc.) as well as touch sensors, pressure sensors, distance sensors, position sensors, digitizers, motion recognition sensors, camera sensors, photoelectric sensors, photoelectric conversion sensors, and temperature sensors.

[0183] The non-image output module 16ET can receive information other than the image transmitted from the processor 12ET and provides it to the user. Examples of non-image output modules 16ET may include acoustic modules, spectral modules, light emission modules, etc., and may include other functional modules specific to electronic devices (e.g., cooling modules of a refrigerator).

[0184] The communication module 17ET can be a module responsible for sending and receiving information between the electronic device 10ET and an external device, and may include a receiver and a transmitter. The communication module 17ET may include various wireless communication modules, such as mobile communication modules, Wi-Fi modules, etc. ® Module or Bluetooth ® Module (Wi-Fi) ® It is a registered trademark of the non-profit Wi-Fi Alliance, and Bluetooth ® (These are registered trademarks of Bluetooth Sig, Inc., Kirkland, WA, etc., but may also include various wired communication modules.)

[0185] At least one of the components of the electronic device 10ET described above may be included within the display device according to the above embodiments. Additionally, some modules functionally included within the electronic device 10ET may be included within the display device, while other modules may be disposed separately from the display device. For example, the display device may include a display module 11ET, and the processor 12ET, memory 13ET, and power module 14ET may be disposed within the electronic device 10ET in the form of other devices not being a display device. As another example, the power module 14ET may be disposed within the display device and may also supply power to the processor 12ET and memory 13ET disposed within the electronic device 10ET, which are not display devices, but is not limited to the above examples.

[0186] Figures 34 to 36 These are schematic diagrams of electronic devices according to various embodiments. Figures 34 to 36 Examples of various electronic devices that utilize a display device according to an embodiment are shown.

[0187] Figure 34 Examples of electronic devices shown include a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e.

[0188] In addition to the display module, the smartphone 10_1a may also include an input module such as a touch sensor and a communication module. The smartphone 10_1a can process information received through the communication module or other input modules and display the information through the display module of the display device.

[0189] Similar to the smartphone 10_1a, the tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, and desktop monitor 10_1e may also include a display module and an input module, and in some cases, a communication module.

[0190] Figure 35 An example of applying an electronic device, including a display module, to a wearable electronic device is shown. The wearable electronic device may be smart glasses 10_2a, a head-mounted display 10_2b, a smartwatch 10_2c, etc.

[0191] The smart glasses 10_2a and the head-mounted display 10_2b may include a display module that emits a display image and a reflector that reflects the emitted display image and provides it to the user's eyes, thereby providing the user with a virtual reality or augmented reality image.

[0192] The smartwatch 10_2c may include a biometric sensor as an input device and can provide the user with biometric information identified by the biometric sensor through a display module.

[0193] Figure 36 Examples of applying electronic devices, including a display module, to a car are shown. For example, electronic device 10_3 can be applied to the car's dashboard, center dashboard, etc., or to a central information display (CID) placed on the car's dashboard or an interior mirror display that replaces the side mirrors.

[0194] In one or more embodiments, the electronic device using the display device according to the embodiments may include not only devices primarily concerned with screen display (such as billboards, light panels, game consoles, etc.), but also various household appliances (such as refrigerators, washing machines, dryers, air conditioners, robotic cleaners, etc.) that display information via a display module. Furthermore, where the display module has the function of transmitting light, a smart window or transparent display device for displaying a background can be applied to the electronic device along with the displayed image. The type of electronic device according to one or more embodiments is not limited to the types of electronic devices described above, and applications of various other electronic devices not described are also possible.

[0195] The accompanying drawings and detailed descriptions of the disclosure described so far are merely illustrative and are intended to describe the purpose of this disclosure only, and are not intended to limit its meaning or the scope of the disclosure as set forth in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible. Consequently, the true technical scope of this disclosure must be determined by the technical concept of the appended claims (and their functional equivalents are included therein).

Claims

1. A display device, the display device comprising: Base; A pixel, above the substrate, and comprising: a first transistor including a channel in a first active layer separated from the substrate by a first distance; and a second transistor including a channel in a second active layer separated from the substrate by a second distance greater than the first distance; and The valley structure penetrates the insulating layer between some of the pixels and has a lower portion separated from the substrate by a third distance, which is smaller than the second distance and different from the first distance.

2. The display device according to claim 1, wherein, The lower part of the valley structure contacts the upper part of the first active layer.

3. The display device according to claim 1, wherein, The lower part of the valley structure contacts the upper part of the first conductive layer between the substrate and the first active layer.

4. The display device according to claim 1, wherein, The lower part of the valley structure contacts the upper part of the second conductive layer between the first active layer and the second active layer.

5. The display device according to claim 4, wherein, The second conductive layer includes a scan line containing the gate electrode of the first transistor.

6. The display device according to claim 1, wherein, The upper part of the valley structure is separated from the base by a fourth distance greater than the second distance.

7. The display device according to claim 6, wherein, The valley structure includes a capping layer that covers the upper part, the lower part, and the sidewalls of the valley structure and includes a conductive material.

8. The display device according to claim 7, wherein, The overlay is configured to receive an initialization voltage.

9. The display device according to claim 1, further comprising a plurality of valley structures including the valley structure. in, The pixels are arranged in a first direction and in a second direction perpendicular to the first direction. The plurality of valley structures extend in at least one of the first direction and the second direction, and The length of the plurality of valley structures is greater than the length of the pixel.

10. The display device according to claim 1, further comprising a plurality of valley structures including the valley structure. in, The pixels are arranged in a first direction and in a second direction perpendicular to the first direction. The plurality of valley structures extend in at least one of the first direction and the second direction, and The length of the plurality of valley structures is less than the length of the pixel.

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