Display device having uniform driving voltage and electronic device including the same

Abstract

This application relates to display devices and electronic devices including the same. The display panel of the electronic device includes: a substrate including a display area and a non-display area, the non-display area including a scan area; pixels; a pixel defining layer including openings; a partition wall disposed on the pixel defining layer and including a first pattern overlapping the display area and a second pattern extending from the first pattern and overlapping the non-display area; a signal line receiving a voltage associated with operation of the display panel; and a protection electrode overlapping the scan area, wherein the protection electrode and the second pattern are connected to the signal line through contact holes.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0046469, filed on April 10, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The presented embodiments relate to display devices and electronic devices including display devices, and more specifically, to display devices having uniform driving voltages. Background Technology

[0004] Electronic devices such as smartphones, digital cameras, laptops, navigation systems, and smart TVs use display devices to present images to users. The display device generates images from image data and provides the generated images to the user through the display panel of the device.

[0005] The electronic device includes multiple pixels for generating images and multiple signal lines connected to these pixels. The pixels are driven by drivers that provide drive signals through the signal lines.

[0006] As display panels become larger and more complex, the deviation in the driving voltage delivered to each pixel has increased. This voltage inconsistency can cause uneven brightness, color shift, or image artifacts on the display panel. Furthermore, drivers are increasingly exposed to external electrical noise or electrostatic discharge, which can lead to instability, malfunctions, or long-term reliability issues in the display device. Summary of the Invention

[0007] At least one embodiment provides a display device capable of providing uniform driving voltages to its pixels, and an electronic device including the display device. In other embodiments, the display device may also protect driver circuitry (e.g., a scan driver) from external electrical noise or electrostatic discharge.

[0008] According to an embodiment, an electronic device is provided. The electronic device includes a display panel. The display panel includes a display area and a non-display area adjacent to the display area. The non-display area includes a scan area in which a scan driver is disposed. The display panel includes: a substrate including a light-emitting area disposed in the display area and a peripheral area disposed between the light-emitting areas; a plurality of pixels overlapping the display area; a pixel defining layer overlapping the peripheral area and defining an opening that exposes at least a portion of the light-emitting area; a partition wall disposed on the pixel defining layer, the partition wall including a first pattern overlapping the display area and a second pattern extending from the first pattern to overlap the non-display area; a signal line disposed between the display area and the scan area, wherein the signal line is configured to receive a driving voltage for driving the pixels; and a protection electrode overlapping the scan area and the scan driver, wherein the protection electrode and the second pattern are respectively connected to the signal line through contact holes.

[0009] In this embodiment, the protective electrode and the electrode of the light-emitting element of the pixel are disposed on the same layer, and the signal line is disposed below the electrode.

[0010] The first pattern may be disposed on the pixel-defining layer and have a grid shape spaced apart from the opening; and the second pattern may include a normal pattern extending from the first pattern and having a shape similar to that of the first pattern, and a plurality of connecting patterns extending from the normal pattern in the direction toward the signal line and spaced apart from each other.

[0011] The protection electrode may include: a first electrode arranged along a first direction and extending along a second direction intersecting the first direction; a second electrode arranged along the second direction and disposed between the first electrodes adjacent to each other along the first direction; and a third electrode arranged along the second direction and protruding from the first electrode adjacent to the signal line in the direction toward the signal line.

[0012] An adjacent first electrode that is adjacent to each other along a first direction and a second electrode disposed between the adjacent first electrodes can define an electrode aperture.

[0013] The electrode holes can be configured as a plurality of electrode holes arranged along a second direction to define a hole group, and the electrode holes in adjacent hole groups that are adjacent to each other along a first direction and included in the hole group can be shifted along the second direction.

[0014] The connecting pattern and the third electrode can be arranged alternately along the second direction on the signal line.

[0015] The connecting pattern and the third electrode can be arranged regularly.

[0016] The display panel may also include an interlayer insulating layer disposed between the third electrode and the signal line and comprising an organic material, wherein a first contact hole in the contact hole can be defined by penetrating the interlayer insulating layer, and the third electrode can be connected to the signal line through the first contact hole.

[0017] The partition wall may include: a first insulating pattern disposed on the pixel defining layer; a second insulating pattern disposed on the first insulating pattern; a first partition wall pattern disposed on the second insulating pattern; and a second partition wall pattern disposed on the first partition wall pattern.

[0018] The first insulating pattern may include at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide; and the second insulating pattern may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0019] The first partition wall pattern may include aluminum, and the second partition wall pattern may include titanium.

[0020] The thickness of the first partition wall pattern can be greater than the thickness of the second partition wall pattern, the width of the second partition wall pattern can be greater than the width of the first partition wall pattern, and a portion of the lower surface of the second partition wall pattern can protrude from and be exposed from the first partition wall pattern.

[0021] The display panel may also include a dummy pattern disposed on the upper surface of the second partition wall pattern, wherein the dummy pattern may be made of the same material as the common layer disposed between the multiple electrodes of the light-emitting elements of the pixel.

[0022] One of the multiple electrodes can extend from one of the light-emitting areas to the peripheral area and cover the side surface of the first partition wall pattern, a portion of the lower surface of the second partition wall pattern, and the dummy pattern.

[0023] The display panel may further include an interlayer insulating layer disposed between the second pattern and the signal line and comprising an organic material, wherein the second contact hole in the contact hole penetrates the interlayer insulating layer and the pixel defining layer, the first insulating pattern and the second insulating pattern disposed in the second contact hole may include an insulating opening overlapping the second contact hole, and the first partition wall pattern disposed in the second contact hole may be connected to the signal line through the insulating opening and the second contact hole.

[0024] The pixel may include: a first pixel that provides red light; a second pixel that is spaced apart from the first pixel along a first direction and provides blue light; and a third pixel and a fourth pixel that are disposed between the first pixel and the second pixel, spaced apart from each other along a second direction intersecting the first direction, and provide green light.

[0025] The light-emitting region may include: a first light-emitting region overlapping with a first pixel; a second light-emitting region overlapping with a second pixel; and a third light-emitting region and a fourth light-emitting region overlapping with a third pixel and a fourth pixel, and the area of ​​the first light-emitting region may be smaller than the area of ​​the second light-emitting region and larger than the area of ​​each of the third and fourth light-emitting regions.

[0026] The display panel may further include spacers disposed on the pixel defining layer, wherein at least a portion of the spacers is surrounded by and spaced apart from the partition walls, wherein the thickness of the partition walls from the upper surface of the pixel defining layer may be less than the thickness of the spacers from the upper surface of the pixel defining layer.

[0027] According to an embodiment, a display device is provided. The display device includes a display panel having a display area and a non-display area adjacent to the display area. The non-display area includes a driver area in which driver circuitry is disposed. The display panel includes: a substrate including a light-emitting area disposed in the display area and a peripheral area disposed between the light-emitting areas; a plurality of pixels overlapping the display area; a pixel defining layer overlapping the peripheral area and defining an opening that exposes at least a portion of the light-emitting area; a partition wall disposed on the pixel defining layer, the partition wall including: a first pattern having a grid shape in the display area overlapping the pixels; and a second pattern extending from the first pattern into the non-display area and having protrusions extending from the outer portion of the grid shape in the non-display area toward the driver area; and a protection electrode disposed in the driver area and electrically connected to the second pattern and configured to provide a predetermined voltage power line.

[0028] According to an embodiment, an electronic device is provided. The electronic device includes a display panel and a voltage generator. The display panel includes a display area and a non-display area adjacent to the display area. The non-display area includes a driver area in which driver circuitry is disposed. The display panel includes: a substrate including a light-emitting area disposed in the display area and a peripheral area disposed between the light-emitting areas; a plurality of pixels overlapping the display area; a pixel defining layer overlapping the peripheral area and defining an opening that exposes at least a portion of the light-emitting area; a partition wall disposed on the pixel defining layer, the partition wall including: a first pattern having a grid shape in the display area overlapping the pixels; and a second pattern extending from the first pattern into the non-display area and having a protrusion extending from the outer portion of the grid shape in the non-display area toward the driver area; and a protection electrode disposed in the driver area and electrically connected to the second pattern. The voltage generator is configured to provide voltage to the protection electrode and the plurality of pixels.

[0029] According to at least one embodiment of the electronic device, a partition wall is provided in the display area of ​​the electronic device to insulate the electrodes from each other, thereby reducing interference and increasing signal stability. In another embodiment, a driver (e.g., a scan driver) in a non-display area of ​​the electronic device is protected from external electrical noise or electrostatic discharge by overlapping a protective electrode connected to a partition wall that receives an equivalent voltage (e.g., a voltage equal to or the same as the voltage of another component in the display area of ​​the electronic device used to operate or drive it). Attached Figure Description

[0030] Figure 1A This is a block diagram of an electronic device according to an embodiment of the present invention.

[0031] Figure 1B This is a schematic diagram of an electronic device according to various embodiments of the present invention.

[0032] Figure 1C This is a perspective view of an electronic device according to an embodiment of the present invention.

[0033] Figure 2 This is a cross-sectional view of an electronic device according to an embodiment of the present invention.

[0034] Figure 3 This is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0035] Figure 4A This is a block diagram of a display module according to an embodiment of the present invention.

[0036] Figure 4B yes Figure 4A The equivalent circuit of one pixel in the pixel diagram.

[0037] Figure 5 This is a plan view of a portion of the display area according to an embodiment of the present invention.

[0038] Figure 6 It is along Figure 5 The sectional view taken from I-I'.

[0039] Figure 7 It is along Figure 5 The sectional view taken from section II-II'.

[0040] Figure 8A It is along Figure 5 The sectional view taken from section III-III'.

[0041] Figure 8B This is a cross-sectional view of the display area according to an embodiment of the present invention.

[0042] Figure 9 This is a plan view of a display panel according to an embodiment of the present invention.

[0043] Figure 10 It is along Figure 9 A sectional view taken from IV-IV'.

[0044] Figure 11 It is along Figure 9 A cross-sectional view taken from V-V'.

[0045] Figure 12 It is along Figure 9 The sectional view taken from VI-VI'.

[0046] Figure 13 This is a plan view of a display panel according to an embodiment of the present invention. Detailed Implementation

[0047] It will be understood that when a component (or region, layer, section, etc.) is referred to as being "on" another component, "connected to" or "attached to" another component, it can be placed directly on, directly connected to, or directly attached to another component, or other components can be placed between them.

[0048] The same reference numerals or symbols always denote the same elements. In the drawings, measurements such as the thickness, scale, and dimensions of elements indicate exemplary embodiments, but these measurements may be varied in alternative embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed elements.

[0049] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below may be referred to as a second element without departing from the scope of the inventive concept. Similarly, a second element may be referred to as a first element. In this specification, the singular expressions “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0050] In addition, the terms "below," "under," "on the lower side," "above," "above," "on the upper side," etc., can be used to describe the relationship between the elements shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the accompanying drawings.

[0051] It will also be understood that the terms “comprises,” “includes,” “has,” and / or “comprising,” “including,” “having,” when used in this specification, specify the presence of the stated features, quantities, steps, operations, elements, components, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof.

[0052] In the following description, embodiments of the inventive concept are illustrated with reference to the accompanying drawings.

[0053] At least one embodiment relates to a display device for enhancing signal stability and pixel driving uniformity, and an electronic device including the display device. A partition wall can be provided in the display area of ​​the display device to insulate the electrodes from each other, thereby reducing interference and enhancing signal integrity. Furthermore, a protective electrode can be provided in the non-display area of ​​the display device to overlap with a driver (e.g., a scan driver) used to drive the pixels of the display device. The protective electrode can be connected to a partition wall for receiving an equivalent voltage. The equivalent voltage can be the same or equivalent voltage used to operate the display device or drive the pixels of the display device. This configuration can protect the driver from external electrical noise or electrostatic discharge and ensure a uniform driving voltage is provided to the pixels in the display area.

[0054] Figure 1A This is a block diagram of an electronic device according to an embodiment. Figure 1B These are schematic diagrams of electronic devices according to various embodiments.

[0055] refer to Figure 1A The electronic device ED according to the embodiments may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0056] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0057] The data required for the operation of the processor 12 or the display module 11 can be stored in the memory 13. When the processor 12 executes the application program stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the provided signals and output image information through the display screen.

[0058] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device ED.

[0059] At least one of the components of the electronic device ED described above may be included in the display device according to the embodiments described above. Furthermore, some of the discrete modules functionally included in a single module may be included in the display device, and other discrete modules may be provided separately from the display device. For example, the display device may include display module 11, and processor 12, memory 13, and power module 14 may be provided as another device in the electronic device ED that is not a display device.

[0060] refer to Figure 1B Various electronic devices to which the display device according to the embodiment is applied may include not only electronic devices for displaying images (such as smartphones ED_1a, tablet PCs ED_1b, laptop computers ED_1c, televisions (TVs) ED_1d, and desktop displays ED_1e), but also wearable electronic devices that include display modules (such as smart glasses ED_2a, head-mounted displays ED_2b, and smartwatches ED_2c), and automotive electronic devices that include display modules (such as central information displays (CIDs) and interior mirror displays installed on the instrument panel, central dashboard, and dashboard of a car).

[0061] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to the embodiments may include the display device described above, and may also include another module or device with additional functions in addition to the display device.

[0062] Figure 1C This is a perspective view of an electronic device according to an embodiment of the present invention. Figure 1A and Figure 1B The electronic device described herein can be applied to [the following]: Figure 1C The electronic device ED described in [the document]. For example... Figure 1B The smart phone ED_1a described in the document can correspond to Figure 1C Electronic devices ED.

[0063] refer to Figure 1CAccording to an embodiment of the present invention, the electronic device ED may have a long side extending parallel to a first direction DR1 and a short side extending parallel to a second direction DR2 intersecting the first direction DR1. The corner connecting the long and short sides of the electronic device ED may have a curved shape. The curved corner of the electronic device ED may be defined as a rounded corner. Such a shape of the electronic device ED may be defined as a quadrilateral with a rounded corner. However, this is merely an example of the shape of an electronic device ED and is not limited to a quadrilateral with a rounded corner.

[0064] In the following text, the direction that intersects substantially perpendicularly with the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. Furthermore, the term "in a plan view" in this document may indicate the state viewed from the third direction DR3.

[0065] The front surface of the electronic device ED can be defined as a display surface DS, and the display surface DS can have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated in the electronic device ED can be provided to the user through the display surface DS.

[0066] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image IM, and the non-display area NDA may not display an image IM. The non-display area NDA may surround the display area DA and define an edge of the electronic device ED printed in a predetermined color.

[0067] The display area DA can have a quadrilateral shape with rounded corners, depending on the shape of the electronic device ED. For example, the display area DA may include sides of the quadrilateral extending in a first direction DR1 and a second direction DR2, and rounded corners connecting the sides. The side extending in the first direction DR1 may be defined as the long side, and the side extending in the second direction DR2 may be defined as the short side. The non-display area NDA may be a display panel DP disposed therein for driving the electronic device ED (see...). Figure 2 The area of ​​signal lines and driving components.

[0068] The electronic device ED can sense input applied from outside the electronic device ED. For example, the electronic device ED can sense a first input made by a stylus PEN or a second input made by a touch TOC. The stylus PEN can be defined as an input device.

[0069] The stylus (PEN) can be an active pen that outputs signals. Secondary inputs via the touch TOC can include various types of external inputs, such as a part of the user's body, light, heat, or pressure.

[0070] The electronic device (ED) and the stylus (PEN) can communicate bidirectionally. The ED can provide uplink signals to the stylus (PEN). For example, the uplink signals may include information such as panel information and protocol version, but are not particularly limited to this.

[0071] The stylus pen (PEN) can provide downlink signals to the electronic device (ED). The downlink signals may include synchronization signals or status information of the stylus pen (PEN). For example, the downlink signals may include coordinate information of the stylus pen (PEN), battery information of the stylus pen (PEN), tilt information of the stylus pen (PEN), and various information stored in the stylus pen (PEN), but are not specifically limited to these.

[0072] Electronic devices (EDs) can be used in large electronic devices such as televisions, monitors, or billboards. Furthermore, electronic devices (EDs) can be used in small to medium-sized electronic devices such as personal computers, laptops, personal digital terminals, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are presented only as exemplary embodiments, and electronic devices (EDs) can also be used in other electronic devices unless departing from the inventive concept.

[0073] Figure 2 This is a cross-sectional view of an electronic device according to an embodiment of the present invention. Figure 3 This is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0074] Figure 2 It is shown Figure 1C The cross-sectional view of the electronic device shown is provided as an example. Figure 2 The cross-section of the electronic device ED as observed in the second direction DR2 is shown as an example.

[0075] refer to Figure 2 The electronic device ED may include a display panel DP, an input sensor ISP, an anti-reflective layer RPL, a window WIN, a panel protective film PPF, and a first adhesive layer AL1 and a second adhesive layer AL2.

[0076] The display panel DP according to embodiments of the present invention can be an emitting display panel. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The emitting layer of an organic light-emitting display panel can include organic light-emitting materials. The emitting layer of an inorganic light-emitting display panel can include quantum dots, quantum rods, etc. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0077] An input sensor ISP can be disposed on a display panel DP. The input sensor ISP may include multiple sensing portions (not shown) for capacitively sensing external input. When manufacturing an electronic device ED, the input sensor ISP can be directly fabricated on the display panel DP. Therefore, according to the embodiment, the input sensor ISP can be directly disposed on the display panel DP. However, the input sensor ISP is not limited to this, and can be manufactured as a panel separate from the display panel DP, and can be attached to the display panel DP via an adhesive layer.

[0078] An anti-reflective layer (RPL) can be applied to the input sensor (ISP). When manufacturing an electronic device (ED), the RPL can be directly fabricated on the ISP. However, the RPL is not limited to this and can be manufactured as a separate panel and attached to the ISP via an adhesive layer.

[0079] An anti-reflective layer (RPL) can be defined as an external light anti-reflective film. The RPL reduces the reflectivity of external light incident on the display panel (DP) from above the electronic device (ED). Due to the RPL, external light may not be visible to the user.

[0080] When external light travels towards the display panel (DP), reflects away from the DP, and returns to the user, the user can perceive the reflected light, much like looking in a mirror. By way of example, the anti-reflective layer (RPL) can include multiple color filters that display the same colors as the pixels of the display panel (DP) to prevent this phenomenon.

[0081] Color filters can filter out external light that has the same color as a pixel. In this case, the external light may not be visible to the user. However, the anti-reflective layer RPL is not limited to this configuration and may include a retarder and / or a polarizer to reduce the reflectivity of external light.

[0082] The WIN window can be installed on the anti-reflective layer RPL. The WIN window can protect the display panel DP, input sensor ISP, and anti-reflective layer RPL from external scratches and impacts.

[0083] A panel protective film (PPF) can be placed below the display panel (DP). The PPF protects the lower portion of the display panel (DP). The PPF can comprise flexible plastic materials, such as polyethylene terephthalate (PET).

[0084] The first adhesive layer AL1 can be disposed between the display panel DP and the panel protective film PPF, and the display panel DP and the panel protective film PPF can be bonded to each other through the first adhesive layer AL1. The second adhesive layer AL2 can be disposed between the window WIN and the anti-reflective layer RPL, and the window WIN and the anti-reflective layer RPL can be bonded to each other through the second adhesive layer AL2.

[0085] According to at least one embodiment, the sensor may be positioned below the display panel DP to overlap with the display area DA. The sensor may include at least one of a camera sensor, a speaker sensor, an infrared (IR) sensor, an illuminance sensor, and a thermal sensor.

[0086] Figure 3 It is shown Figure 2 The cross-sectional view of the display panel shown is provided as an example. Figure 3 The image shows a cross-section of the display panel DP as an example, viewed in the second direction DR2.

[0087] refer to Figure 3 The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0088] The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may include glass or a flexible plastic material such as polyimide. The display element layer DP-OLED may be disposed on the substrate SUB within the display area DA.

[0089] Multiple pixels can be disposed in the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor disposed in the circuit element layer DP-CL and a light-emitting element disposed in the display element layer DP-OLED and connected to the transistor.

[0090] A thin-film encapsulation layer (TFE) can be applied to the circuit element layer (DP-CL) to cover the display element layer (DP-OLED). The TFE protects the pixels from moisture, oxygen, and external contaminants.

[0091] The thin-film encapsulation layer TFE can be applied to the light-emitting element OLED (see [reference]). Figure 4B The thin-film encapsulation layer TFE may be disposed on the pixel PXij (see [link to TFE]). Figure 4B The first inorganic layer on the first inorganic layer, the second inorganic layer disposed on the first inorganic layer, and the organic layer disposed between the first inorganic layer and the second inorganic layer.

[0092] The first and second inorganic layers may include inorganic materials and protect the pixel PXij (see [link to documentation]). Figure 4B ) to protect from moisture / oxygen. The organic layer may include organic materials and protect the pixel PXij (see Figure 4B It is protected from foreign objects such as dust particles. The organic layer can be formed through solution processes such as spin coating, slot coating, and inkjet printing.

[0093] Figure 4A This is a block diagram of a display module according to an embodiment of the present invention. Figure 4B yes Figure 4A The equivalent circuit of one pixel in the pixel diagram.

[0094] refer to Figure 4A The electronic device ED may include a display panel DP, a timing controller TC (e.g., a control circuit), a scan driver SDV (e.g., a first driver circuit), a data driver DDV (e.g., a second driver circuit), a light-emitting driver EDV (e.g., a third driver circuit), and a voltage generator VG.

[0095] According to the implementation method, the scan driver SDV can be set to... Figure 3 In the non-display area NDA of the display panel DP described herein. According to the current embodiment, the area of ​​the non-display area NDA in which the scan driver SDV is disposed can be defined as the scan area SCA (see [link]). Figure 9 ).

[0096] A scan driver SDV may include multiple transistors. A scan driver SDV located in the non-display area NDA may be exposed to external electrical stimulation and may therefore require protection against such electrical effects.

[0097] According to the implementation method, the scanning area SCA (see...) can be scanned. Figure 9 The protective electrode NAE is set in the (see) Figure 9 The protective electrode NAE is subjected to an equivalent voltage to protect the scan driver SDV from external electrical stimulation. A detailed description will be provided later.

[0098] The display panel DP may include multiple scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm and GBL1 to GBLm, multiple light-emitting lines EML1 to EMLm, multiple data lines DL1 to DLn and multiple pixels PX. Here, m and n can be natural numbers greater than 0.

[0099] Each pixel PX can be electrically connected to scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm, light emission lines EML1 to EMLm, and data lines DL1 to DLn. Each pixel PX can also be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding light emission line.

[0100] Scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm may include multiple initialization scan lines GIL1 to GILm, multiple compensation scan lines GCL1 to GCLm, multiple write scan lines GWL1 to GWLm, and multiple bias scan lines GBL1 to GBLm.

[0101] Each pixel PX can be connected to a corresponding one of the initialization scan lines GIL1 to GILm, a corresponding one of the compensation scan lines GCL1 to GCLm, a corresponding one of the write scan lines GWL1 to GWLm, and a corresponding one of the bias scan lines GBL1 to GBLm.

[0102] Scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm can be connected to the scan driver SDV, extending in the first direction DR1 and arranged in the second direction DR2. Emission lines EML1 to EMLm can be connected to the emission driver EDV, extending in the first direction DR1 and arranged in the second direction DR2. Data lines DL1 to DLn can be connected to the data driver DDV, extending in the second direction DR2 and arranged in the first direction DR1.

[0103] The scan driver (SDV), the light emission driver (EDV), and the data driver (DDV) can be essentially set in the display panel (DP).

[0104] The timing controller TC can receive image signals RGB and control signals CTRL. The timing controller TC can generate image data signals DAS by converting the RGB data format to conform to the interface specification of the data driver DDV. The timing controller TC can output scan control signals SCS, data control signals DCS, and illumination control signals ECS in response to the control signal CTRL.

[0105] The voltage generator VG generates the voltages used in the operation of the display panel DP. The voltage generator VG generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage VAINT. These voltages can be applied to pixels PX.

[0106] The scan driver SDV can receive scan control signals SCS from the timing controller TC. In response to the scan control signals SCS, the scan driver SDV can output scan signals to scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm. The scan signals can be applied to pixels PX through scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm.

[0107] The data driver DDV receives data control signals DCS and image data signals DAS from the timing controller TC. The data driver DDV converts the image data signals DAS into data signals and outputs them. The data signals can be defined as analog voltages corresponding to the grayscale levels of the image data signals DAS. The data signals can be applied to pixels PX via data lines DL1 to DLn.

[0108] The EDV (Emitting Driver) can receive the ECS (Emitting Control Signal) from the timing controller TC. In response to the ECS, the EDV can output emitting signals to the emitting lines EML1 to EMLm. These emitting signals can be applied to the pixel PX through the emitting lines EML1 to EMLm.

[0109] A pixel PX can receive a data voltage in response to a scan signal and display an image by emitting light with a brightness corresponding to the data voltage in response to a light emission signal.

[0110] Figure 4B It is shown Figure 4A A diagram of the equivalent circuit of one of the pixels shown.

[0111] As an example, Figure 4B The image shows a pixel PXij connected to the j-th data line DLj, the i-th scan lines GWLi, GCLi, GILi, and GBLi, and the i-th emission line EMLi. Here, i and j can be natural numbers greater than 0.

[0112] refer to Figure 4B A pixel PXij may include a pixel circuit PC and a light-emitting element OLED connected to the pixel circuit PC. The pixel circuit PC can drive the light-emitting element OLED.

[0113] The pixel circuit PC may include multiple transistors T1 to T8 and a capacitor CST. Transistors T1 to T8 and capacitor CST can control the amount of current flowing in the light-emitting element OLED. The light-emitting element OLED can generate light with a predetermined brightness based on the amount of current received.

[0114] The i-th write scan line GWLi can receive the i-th write scan signal GWi, and the i-th compensation scan line GCLi can receive the i-th compensation scan signal GCI. The i-th initialization scan line GILi can receive the i-th initialization scan signal GIi, and the i-th bias scan line GBLi can receive the i-th bias scan signal GBi. The i-th emission line EMLi can receive the i-th emission signal EMi.

[0115] Pixel PXij can be connected to the j-th data line DLj, the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, the i-th bias scan line GBLi, the i-th emission line EMLi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0116] The first initialization line VIL1 can receive the first initialization voltage VINT, and the second initialization line VIL2 can receive the second initialization voltage VAINT. The bias line VBL can receive the bias voltage VBIAS. The first power line PL1 can receive the first drive voltage ELVDD, and the second power line PL2 can receive the second drive voltage ELVSS.

[0117] Transistors T1 through T8 may each include a source electrode, a drain electrode, and a gate electrode. In the following text, in... Figure 4B In this context, for convenience, one of the source electrode and the drain electrode is referred to as the first electrode, and the other as the second electrode. Additionally, the gate electrode can be referred to as the control electrode.

[0118] Transistors T1 to T8 may include first transistor T1 to eighth transistor T8. First transistor T1, second transistor T2, and fifth transistor T5 to eighth transistor T8 may be PMOS transistors. Third transistor T3 and fourth transistor T4 may be NMOS transistors.

[0119] The first transistor T1 can be called the driving transistor, and the second transistor T2 can be called the switching transistor. The third transistor T3 can be called the compensation transistor. The fourth transistor T4 and the seventh transistor T7 can each be called the initialization transistor. The fifth transistor T5 and the sixth transistor T6 can each be called the light-emitting control transistor. The eighth transistor T8 can be called the bias transistor.

[0120] The light-emitting element (OLED) can be defined as an organic light-emitting element. The OLED may include a first electrode AE ​​and a second electrode CE. The first electrode AE ​​can receive a first driving voltage ELVDD through a sixth transistor T6, a first transistor T1, and a fifth transistor T5. The first driving voltage ELVDD can be applied to the pixel circuit PC through a first power line PL1.

[0121] The second electrode CE can receive a second driving voltage ELVSS that is lower than the first driving voltage ELVDD. The second driving voltage ELVSS can be applied to the pixel circuit PC through the second power line PL2.

[0122] The first transistor T1 can be disposed between and connected to the fifth transistor T5 and the sixth transistor T6. The first transistor T1 can be connected to the first power line PL1 through the fifth transistor T5, and to the first electrode AE ​​through the sixth transistor T6.

[0123] The first transistor T1 may include a first electrode connected to the first power line PL1 via a fifth transistor T5, a second electrode connected to the first electrode AE ​​via a sixth transistor T6, and a control electrode connected to the first node N1.

[0124] The first electrode of the first transistor T1 can be connected to the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the sixth transistor T6. The first transistor T1 can control the amount of current flowing in the light-emitting element OLED according to the voltage applied to the first node N1 of the control electrode of the first transistor T1.

[0125] The second transistor T2 can be disposed between the first transistor T1 and the j-th data line DLj, and connected to the first transistor T1 and the j-th data line DLj. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th write scan line GWLi.

[0126] The second transistor T2 can be turned on by the i-th write scan signal GWi applied through the i-th write scan line GWLi, and is electrically connected to the j-th data line DLj and the first electrode of the first transistor T1. The second transistor T2 can perform a switching operation to provide the first electrode of the first transistor T1 with a data voltage VD (corresponding to the data signal described above) applied through the j-th data line DLj.

[0127] The third transistor T3 can be connected to the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCLi.

[0128] The third transistor T3 can be turned on by the i-th compensation scan signal GCI applied through the i-th compensation scan line GCLi, and is electrically connected to the second electrode of the first transistor T1 and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 can be connected in a diode configuration.

[0129] A fourth transistor T4 can be connected to a first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to a first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GILi. The fourth transistor T4 can be turned on by an i-th initialization scan signal GIi applied through the i-th initialization scan line GILi, and provides a first initialization voltage VINT applied through the first initialization line VIL1 to the first node N1.

[0130] The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th light-emitting line EMLi.

[0131] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first electrode AE, and a control electrode connected to the i-th light-emitting line EMLi.

[0132] The fifth transistor T5 and the sixth transistor T6 can be turned on by the i-th emission signal EMi applied through the i-th emission line EMi. The first driving voltage ELVDD can be provided to the light-emitting element OLED by the turned-on fifth transistor T5 and sixth transistor T6, and the driving current Id can flow in the light-emitting element OLED. Therefore, the light-emitting element OLED can emit light.

[0133] The seventh transistor T7 may include a first electrode connected to the first electrode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBLi. The seventh transistor T7 can be turned on by the i-th bias scan signal GBi applied through the i-th bias scan line GBLi, and can provide the second initialization voltage VAINT received through the second initialization line VIL2 to the first electrode AE ​​of the light-emitting element OLED.

[0134] In the implementation, the second initialization voltage VAINT may have a different level than the first initialization voltage VINT, but is not limited thereto, and may have the same level as the first initialization voltage VINT.

[0135] The seventh transistor T7 enhances the black level performance of pixel PXij. When the seventh transistor T7 is turned on, the parasitic capacitance of the OLED light-emitting element can discharge. Therefore, when achieving black brightness, the OLED light-emitting element can avoid emitting light due to the leakage current of the first transistor T1, and thus, the black level performance can be enhanced.

[0136] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing in the first transistor T1 can be determined based on the voltage stored in the capacitor CST.

[0137] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBLi.

[0138] The eighth transistor T8 can be turned on by the i-th bias scan signal GBi and provides the bias voltage VBIAS applied through the bias line VBL to the first electrode of the first transistor T1. However, the transistors included in pixel PXij are not limited to this.

[0139] Figure 5 This is a plan view of a portion of the display area according to an embodiment of the present invention.

[0140] refer to Figure 5 In the current implementation, a pixel unit PXU may include Figure 4A and Figure 4B The pixels described herein. Pixel units PXU can be configured in multiples and arranged in the display area DA along the first direction DR1 and the second direction DR2.

[0141] According to the implementation method, the pixel unit PXU may include a first pixel PX-R, a second pixel PX-B, a third-first pixel PX-G1, and a third-second pixel PX-G2.

[0142] The first pixel PX-R can provide red light. The light generated in the first pixel PX-R can be provided to the display area DA through the first emitting region PXA-R. The first emitting region PXA-R can be spaced apart from the second emitting region PXA-B along the first direction DR1. The first emitting region PXA-R can be spaced apart from the third-first emitting region PXA-G1 along the second diagonal direction CDR2, and can be spaced apart from the third-second emitting region PXA-G2 along the first diagonal direction CDR1. In the current embodiment, the first emitting region PXA-R can have a diagonal octagonal shape. According to the embodiment, the first emitting region PXA-R can have a circular shape or an elliptical shape.

[0143] The second pixel PX-B can provide blue light. The light generated in the second pixel PX-B can be provided to the display area DA through the second light-emitting area PXA-B. The second light-emitting area PXA-B can be spaced apart from the third-first light-emitting area PXA-G1 along the first diagonal direction CDR1, and can be spaced apart from the third-second light-emitting area PXA-G2 along the second diagonal direction CDR2. In the current embodiment, the second light-emitting area PXA-B can have a diagonally rectangular octagonal shape. According to an embodiment, the second light-emitting area PXA-B can have a circular shape or an elliptical shape.

[0144] The 3-1st pixel PX-G1 can provide green light. The light generated in the 3-1st pixel PX-G1 can be provided to the display area DA through the 3-1st emitting region PXA-G1. In the current embodiment, the 3-1st emitting region PXA-G1 can have an octagonal shape extending along the second diagonal direction CDR2. According to the embodiment, the 3-1st emitting region PXA-G1 can have a circular shape or an elliptical shape.

[0145] The 3-2nd pixel PX-G2 can provide green light like the 3-1st pixel PX-G1. The light generated in the 3-2nd pixel PX-G2 can be provided to the display area DA through the 3-2nd emitting region PXA-G2. The 3-2nd emitting region PXA-G2 can be spaced apart from the 3-1st emitting region PXA-G1 along the second direction DR2. In the current embodiment, the 3-2nd emitting region PXA-G2 can have an octagonal shape extending along the first diagonal direction CDR1. According to the embodiment, the 3-2nd emitting region PXA-G2 can have a circular or elliptical shape.

[0146] According to the implementation method, the area of ​​the first light-emitting region PXA-R can be larger than the area of ​​each of the third-1 light-emitting regions PXA-G1 and the third-2 light-emitting regions PXA-G2, and smaller than the area of ​​the second light-emitting region PXA-B.

[0147] The area between the first luminescent region PXA-R, the second luminescent region PXA-B, the third-1 luminescent region PXA-G1, and the third-2 luminescent region PXA-G2 can be defined as the outer region NPXA.

[0148] The peripheral region NPXA according to the embodiment may include a normal region A0, a partition wall region A1, and a support region A2. The partition wall region A1 and the support region A2 may be surrounded by the normal region A0. The partition wall region A1 and the support region A2 may be spaced apart from each other, with the normal region A0 located between them.

[0149] The partition wall region A1 can be defined as the partition wall WA (see [link]). Figure 6 ) is set in the pixel-limited layer PDL (see Figure 6 The area on the support region A2 can be defined as the spacer SP (see...). Figure 8A ) is set in the pixel-limited layer PDL (see Figure 6 The area on the ). Spacer SP (see Figure 8A ) can be a support mask MS (see Figure 8A The structure of ). A more detailed description will be provided later.

[0150] Figure 6 It is along Figure 5 The sectional view taken from I-I'. Figure 7 It is along Figure 5 The sectional view taken from section II-II'. Figure 8A It is along Figure 5 The sectional view taken from section III-III'. Figure 8B This is a cross-sectional view of the display area according to the implementation method.

[0151] Figure 6 It shows Figure 5 A cross-sectional view of pixel 3-1, PX-G1, and the region adjacent to pixel 3-1, PX-G1. (See reference) Figure 6 The light-emitting element OLED-G1 according to the embodiment can correspond to Figure 4B One of the light-emitting elements shown in the OLED diagram may include a first electrode AE-G1, a second electrode CE, and a common layer CL. The common layer CL may include a hole control layer, an electron control layer, an emission layer, etc.

[0152] The second electrode CE can be disposed on the first electrode AE-G1, and the common layer CL can be disposed between the first electrode AE-G1 and the second electrode CE. According to an embodiment, the light-emitting element OLED-G1 may further include a protective layer disposed on the second electrode CE. The protective layer may include an organic material and prevent components disposed beneath the protective layer from being damaged in subsequent processes. According to an embodiment, the protective layer may be omitted.

[0153] The first transistor T1, the fourth transistor T4, and the sixth transistor T6, along with the light-emitting element OLED-G1, can be disposed on the substrate SUB. The display area DA may include components corresponding to pixels PXij (see...). Figure 4B The first luminescent region PXA-R and the peripheral region NPXA adjacent to the first luminescent region PXA-R.

[0154] The substrate SUB may include glass or a flexible plastic material such as polyimide (PI). The circuit element layer DP-CL, the display element layer DP-OLED, and the thin-film encapsulation layer TFE may be disposed on the substrate SUB. The circuit element layer DP-CL may include an insulating layer and conductive patterns. The display element layer DP-OLED may include a light-emitting element OLED-G1 and a pixel defining layer PDL.

[0155] A barrier layer (BRL) can be disposed on a substrate (SUB). The barrier layer (BRL) can increase the bonding force between the substrate (SUB) and the semiconductor pattern included in the transistor. The barrier layer (BRL) can include inorganic materials.

[0156] A metal layer BML can be disposed on the barrier layer BRL. The metal layer BML can overlap with the first transistor T1. According to an embodiment, the metal layer BML can receive a constant voltage or a direct current (DC) voltage. When a constant voltage is applied to the metal layer BML, the threshold voltage (Vth) of the first transistor T1 disposed on the metal layer BML can be maintained without change.

[0157] The metal layer BML can block light incident on the first transistor T1 from below the metal layer BML. The metal layer BML may include reflective metal. According to an embodiment, the metal layer BML may be omitted.

[0158] The buffer layer BFL can be disposed on the barrier layer BRL and covered by the metal layer BML. The buffer layer BFL may include inorganic materials.

[0159] The semiconductor layers S1, Ac1, and D1 of the first transistor T1 and the semiconductor layers S6, Ac6, and D6 of the sixth transistor T6 can be disposed on the buffer layer BFL. The semiconductor layers S1, Ac1, D1, S6, Ac6, and D6 can comprise polycrystalline silicon. However, the semiconductor layers S1, Ac1, D1, S6, Ac6, and D6 are not limited thereto and can comprise amorphous silicon.

[0160] Semiconductor layers S1, Ac1, D1, S6, Ac6, and D6 may be doped with N-type or P-type dopant. Semiconductor layers S1, Ac1, D1, S6, Ac6, and D6 may include heavily doped and lightly doped regions. The conductivity of the heavily doped regions may be higher than that of the lightly doped regions, and they can essentially serve as the source and drain electrodes of the first transistor T1 and the sixth transistor T6. The lightly doped regions may essentially correspond to the active portions (or channels) of the first transistor T1 and the sixth transistor T6.

[0161] The first source region S1, the first channel region Ac1, and the first drain region D1 of the first transistor T1 can be formed by semiconductor layers S1, Ac1, and D1. The sixth source region S6, the sixth channel region Ac6, and the sixth drain region D6 of the sixth transistor T6 can be formed by semiconductor layers S6, Ac6, and D6. The first channel region Ac1 can be disposed between the first source region S1 and the first drain region D1. The sixth channel region Ac6 can be disposed between the sixth source region S6 and the sixth drain region D6.

[0162] A first insulating layer INS1 (e.g., a first interlayer insulating layer) may be disposed on a buffer layer BFL to cover semiconductor layers S1, Ac1, D1, S6, Ac6, and D6. The first gate electrode G1 (or control electrode) of the first transistor T1 and the sixth gate electrode G6 (or control electrode) of the sixth transistor T6 may be disposed on the first insulating layer INS1. In a plan view, the first gate electrode G1 may overlap with the first channel region Ac1, and the sixth gate electrode G6 may overlap with the sixth channel region Ac6.

[0163] The source region, channel region, drain region, and gate electrode structure of each of the second transistor T2, the fifth transistor T5, and the seventh transistor T7 can be substantially the same as those of the first transistor T1 and the sixth transistor T6.

[0164] A second insulating layer INS2 (e.g., a second interlayer insulating layer) may be disposed on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. A dummy electrode DME may be disposed on the second insulating layer INS2. The dummy electrode DME may be disposed on the first gate electrode G1 and overlap with the first gate electrode G1 in a plan view. The dummy electrode DME may form the capacitor described above together with the first gate electrode G1.

[0165] A third insulating layer INS3 (e.g., a third interlayer insulating layer) may be disposed on the second insulating layer INS2 to cover the dummy electrode DME. Semiconductor layers S4, Ac4, and D4 of the fourth transistor T4 may be disposed on the third insulating layer INS3. Semiconductor layers S4, Ac4, and D4 may comprise oxide semiconductors formed of metal oxides. The oxide semiconductors may comprise crystalline or amorphous oxide semiconductors.

[0166] Semiconductor layers S4, Ac4, and D4 may include multiple regions divided according to whether the metal oxide is reduced. Regions in which the metal oxide is reduced (hereinafter, reduced regions) may have higher conductivity than regions in which the metal oxide is not reduced (hereinafter, non-reduced regions). The reduced regions may essentially serve as the source or drain electrode of the fourth transistor T4. The non-reduced regions may essentially correspond to the active portion (or channel) of the fourth transistor T4.

[0167] The fourth source region S4, the fourth channel region Ac4, and the fourth drain region D4 of the fourth transistor T4 can be formed from the semiconductor layers S4, Ac4, and D4. The fourth channel region Ac4 can be disposed between the fourth source region S4 and the fourth drain region D4.

[0168] A fourth insulating layer INS4 (e.g., a fourth interlayer insulating layer) may be disposed on the third insulating layer INS3 to cover semiconductor layers S4, Ac4, and D4. The fourth gate electrode G4 of the fourth transistor T4 may be disposed on the fourth insulating layer INS4. In a plan view, the fourth gate electrode G4 may overlap with the fourth channel region Ac4.

[0169] The fifth insulating layer INS5 (e.g., the fifth interlayer insulating layer) can be disposed on the fourth insulating layer INS4 to cover the fourth gate electrode G4. The structure of the source region, channel region, drain region, and gate electrode of the third transistor T3 can be substantially the same as that of the fourth transistor T4.

[0170] The barrier layer BRL, buffer layer BFL, and first insulating layers INS1 to fifth insulating layers INS5 may comprise inorganic materials. By way of example, the barrier layer BRL, buffer layer BFL, and first insulating layers INS1 to fifth insulating layers INS5 may comprise one of silicon oxide and silicon nitride, or an insulating layer may comprise multiple inorganic layers and is not limited to any one embodiment. The multiple inorganic layers may have a structure comprising multiple layers of silicon nitride and silicon oxide stacked alternately. According to an embodiment, in addition to the first insulating layers INS1 to fifth insulating layers INS5, an insulating layer comprising inorganic materials may be additionally provided, or one of the first insulating layers INS1 to fifth insulating layers INS5 may be omitted.

[0171] The connecting electrode CNE can be disposed between the sixth transistor T6 and the light-emitting element OLED-G1. The connecting electrode CNE can electrically connect the sixth transistor T6 and the light-emitting element OLED-G1. The connecting electrode CNE can include a first connecting electrode CNE1 and a second connecting electrode CNE2 disposed on the first connecting electrode CNE1.

[0172] The first connecting electrode CNE1 can be disposed on the fifth insulating layer INS5 and connected to the sixth drain region D6 through a first contact hole CH1 defined in the first insulating layer INS1 to the fifth insulating layer INS5. The sixth insulating layer INS6 (e.g., a sixth interlayer insulating layer) can be disposed on the fifth insulating layer INS5 to cover the first connecting electrode CNE1.

[0173] The second connecting electrode CNE2 can be disposed on the sixth insulating layer INS6. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the second contact hole CH2 defined in the sixth insulating layer INS6.

[0174] A seventh insulating layer INS7 (e.g., a seventh interlayer insulating layer) may be disposed on the sixth insulating layer INS6 to cover the second connecting electrode CNE2. The sixth insulating layer INS6 and the seventh insulating layer INS7 may comprise organic materials. According to embodiments, in addition to the sixth insulating layer INS6 and the seventh insulating layer INS7, an additional insulating layer comprising organic materials may be provided, or one of the sixth insulating layer INS6 and the seventh insulating layer INS7 may be omitted. The first electrode AE-G1 may be disposed on the seventh insulating layer INS7 and may be connected to the second connecting electrode CNE2 through a third contact hole CH3 defined in the seventh insulating layer INS7.

[0175] The pixel-defining layer (PDL) can be disposed on the seventh insulating layer (INS7). An opening (PDL-OP) exposing at least a portion of the first electrode AE-G1 can be defined within the pixel-defining layer (PDL). Multiple openings (PDL-OP) can be provided depending on the number of first electrodes AE-G1, and each opening (PDL-OP) can correspond to the first light-emitting region PXA-R, the second light-emitting region PXA-B, the third-first light-emitting region PXA-G1, and the third-second light-emitting region PXA-G2 as described above.

[0176] In the current embodiment, the pixel defining layer (PDL) may include an organic material. Furthermore, the PDL may have a predetermined color, but is not limited to any particular embodiment.

[0177] The common layer CL and the second electrode CE included in the light-emitting element OLED-G1 can be disposed on the first electrode AE-G1 exposed by the opening PDL-OP of the pixel-defining layer PDL.

[0178] The second electrode CE can be a single pattern commonly set in multiple pixels. The second electrodes CE can be connected to each other via separator walls WA. The common layer CL can be disconnected via separator walls WA.

[0179] The separator wall WA can be set on the pixel limiting layer PDL. The region where the pixel limiting layer PDL is set can be referred to as the peripheral region NPXA, and the area where the separator wall WA is set on the pixel limiting layer PDL can be referred to as the separator wall region A1. The separator wall WA will refer to... Figure 7 Detailed description.

[0180] A thin-film encapsulation layer (TFE) can be disposed on and cover the light-emitting element OLED-G1. The TFE can be disposed over the entire display area DA. The TFE can comprise an inorganic film and an organic film disposed between the inorganic films. The inorganic film protects the pixels from moisture / oxygen. The organic film protects the pixels from foreign matter such as dust particles.

[0181] like Figure 7 As shown, the partition wall WA can be disposed on the pixel definition layer PDL. More specifically, the partition wall WA can be disposed entirely on the pixel definition layer PDL excluding the support region A2 within the peripheral region NPXA. For example, the support region A2 can be omitted from the peripheral region NPXA.

[0182] According to the embodiments, the partition wall WA may include a first insulating pattern IN1, a second insulating pattern IN2, a first partition wall pattern W1, and a second partition wall pattern W2.

[0183] The first insulating pattern IN1 can be directly disposed on the pixel defining layer PDL. The second insulating pattern IN2 can be disposed on the first insulating pattern IN1. In an embodiment, the first insulating pattern IN1 and the second insulating pattern IN2 comprise different materials from each other.

[0184] For example, the first insulating pattern IN1 may include at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide. The second insulating pattern IN2 may include at least one of silicon oxide, silicon oxynitride, and silicon nitride. The second insulating pattern IN2 may have a multilayer structure of stacked silicon oxide and silicon nitride.

[0185] In the current embodiment, the first insulating pattern IN1 may be a component for disconnecting the P-type hole injection layer among the multiple layers included in the common layer CL. In this embodiment, the first insulating pattern IN1 has a thickness greater than the P-type hole injection layer among the multiple layers included in the common layer CL.

[0186] According to an embodiment, in a cross-sectional view, the width of the first insulating pattern IN1 is smaller than the width of the second insulating pattern IN2. This width difference may be caused by the different etching rates of the first insulating pattern IN1 and the second insulating pattern IN2 relative to the etchant.

[0187] The common layer CL of different pixels can be disconnected from each other by a first insulating pattern IN1 and a second insulating pattern IN2, with a separator wall WA between them. The disconnected common layer CL can contact the side surface of each of the first insulating pattern IN1 and the second insulating pattern IN2, as well as the top surface of the second insulating pattern IN2. According to an embodiment, the common layer CL contacts the side surface W1-S of the first separator wall pattern W1.

[0188] A first separator pattern W1 is disposed on a second insulating pattern IN2. The first separator pattern W1 may include a metal. For example, the first separator pattern W1 may include aluminum. When the first separator pattern W1 includes aluminum, the side surface W1-S of the first separator pattern W1 may be oxidized and lose its conductivity. Therefore, the inner portion W1-I of the side surface W1-S of the first separator pattern W1 may be defined as a non-conductive region.

[0189] The second partition wall pattern W2 can be disposed on the first partition wall pattern W1. The second partition wall pattern W2 may include a metal different from the first partition wall pattern W1. For example, the second partition wall pattern W2 may include titanium.

[0190] According to the current embodiment, the thickness of the first partition wall pattern W1 can be greater than the thickness of the second partition wall pattern W2, while the width of the first partition wall pattern W1 can be smaller than the width of the second partition wall pattern W2.

[0191] According to an embodiment, a portion of the second partition wall pattern W2 may protrude from and be exposed from the first partition wall pattern W1. Therefore, the lower surface W2-B of the second partition wall pattern W2 may be exposed from the first partition wall pattern W1. This exposure may be due to the difference in etching rates of the etchant to the first partition wall pattern W1 and the second partition wall pattern W2. The shapes of the first partition wall pattern W1 and the second partition wall pattern W2 may be defined as "tip structures".

[0192] According to an embodiment, a mask MS can be used in the process of forming the common layer CL. The mask MS can be a fine metal mask (FMM). According to an embodiment, during the deposition process, the separator wall WA disposed in the separator wall region A1 can be spaced apart from the mask MS by a predetermined space SS. Therefore, since the separator wall WA will not be damaged during the process using the mask MS, the tip structure of the separator wall WA disposed in the separator wall region A1 can be stably maintained.

[0193] The second electrode CE can extend from the 3-1 light-emitting region PXA-G1 to the peripheral region NPXA and can contact the partition wall WA. The second electrode CE overlapping the partition wall WA can contact the side surface W1-S of the first partition wall pattern W1, the lower surface W2-B of the second partition wall pattern W2 exposed from the first partition wall pattern W1, and the side surface W2-S of the second partition wall pattern W2.

[0194] According to an embodiment, the dummy pattern CL-P can be disposed on the separator wall WA. More specifically, the dummy pattern CL-P can be disposed between the upper surface of the second separator wall pattern W2 and the second electrode CE. The dummy pattern CL-P can be a portion of the common layer CL that is broken off by the separator wall WA during the process of forming the common layer CL.

[0195] As described above, the inner portion W1-I of the first partition wall pattern W1 is oxidized and includes a non-conductive region lacking conductivity. As a result, the second electrode CE covering the partition wall WA can be connected to another portion of the second electrode CE via the lower surface W2-B exposed from the first partition wall pattern W1 by the second partition wall pattern W2 and via the side surface W2-S of the second partition wall pattern W2.

[0196] According to one embodiment, the first thickness of the second electrode CE disposed on the common layer CL is greater than the second thickness of the second electrode CE covering the partition wall WA. According to another embodiment, the second electrode CE may only contact a portion of the side surface W1-S of the first partition wall pattern W1, and remain disconnected from the remaining portion of the side surface W1-S. The remaining portion of the second electrode CE may contact the side surface W2-S of the second partition wall pattern W2 and the dummy pattern CL-P. Since the second electrode CE, disconnected on the partition wall WA, remains in contact with the partition wall WA, which includes conductive material, the disconnected portion of the second electrode CE can be electrically connected through the partition wall WA.

[0197] Figure 8A A cross-sectional view of a support region A2 of the peripheral region NPXA is shown.

[0198] refer to Figure 8A Spacers SP overlapping the support region A2 can be provided on the pixel-defined layer PDL. Multiple spacers SP can be provided in the peripheral region NPXA, and they can be randomly arranged within the peripheral region NPXA. For example, the spacers SP can be distributed in a non-uniform pattern, such that some portions of the peripheral region NPXA include closely spaced spacers, while other portions include spacers positioned slightly further apart. According to an embodiment, the spacers SP can be surrounded by a partition wall WA, while being spaced apart from the partition wall WA by a predetermined distance.

[0199] The spacer SP can be covered by the common layer CL and the second electrode CE. This is included in the thin-film encapsulation layer TFE (see [link to encapsulation layer]). Figure 6 The inorganic layer in the structure can be placed on the second electrode CE covering the partition wall WA and the spacer SP.

[0200] In one implementation, the pixel defining layer (PDL) may comprise a colored organic material with light-blocking properties. For example, the PDL may be black. In this case, the spacer SP may comprise a transparent organic material, such as polyimide.

[0201] According to an implementation, the separator wall WA may have a first thickness TH1 extending from the upper surface of the pixel defining layer PDL (see [implementation details]). Figure 7 Furthermore, the spacer SP may have a second thickness TH2 extending from the upper surface of the pixel defining layer PDL. The second thickness TH2 of the spacer SP may be greater than the first thickness TH1 of the separator wall WA.

[0202] Therefore, in the process using the mask MS, the partition wall WA can be spaced apart from the mask MS with a predetermined space SS between them, and the mask MS can be supported by the spacer SP. The process of forming the common layer CL can be performed with the mask MS supported by the spacer SP. Therefore, since the mask MS and the partition wall WA are spaced apart from each other during the use of the mask MS, the tip structure of the partition wall WA can be stably maintained.

[0203] Figure 8B It is along Figure 5 The III-III' cut and Figure 8A A cross-sectional view of the same area.

[0204] refer to Figure 8B In the current embodiment, the thickness of the pixel defining layer PDLa in the normal region A0 and the support region A2 may differ from each other. The pixel defining layer PDLa may include a first portion P1 disposed across the peripheral region NPXA and a second portion P2 disposed in the support region A2. The shapes of the first portion P1 and the second portion P2 may be formed on a single organic layer by a halftone process. According to an embodiment, the pixel defining layer PDLa may include a transparent organic material, such as polyimide.

[0205] The separator wall WA may have a first thickness TH1 extending from the upper surface of the pixel defining layer PDLa, and the second portion P2 may have a third thickness TH3 extending from the upper surface of the first portion P1. In an embodiment, the separator wall WA may be disposed on the first portion P1. The third thickness TH3 of the second portion P2 may be greater than the first thickness TH1 of the separator wall WA.

[0206] Therefore, during the process using the mask MS, the partition wall WA can be spaced apart from the mask MS by a predetermined space SS, and the mask MS can be supported by the second portion P2. The process of forming the common layer CL can be performed with the mask MS supported by the second portion P2. Therefore, since the mask MS and the partition wall WA are spaced apart from each other when the mask MS is used, the tip structure of the partition wall WA can be stably maintained.

[0207] Figure 9 This is a plan view of a display panel according to an embodiment of the present invention. Figure 10 It is along Figure 9 A sectional view taken from IV-IV'. Figure 11 It is along Figure 9 A cross-sectional view taken from V-V'. Figure 12 It is along Figure 9 The sectional view taken from VI-VI'.

[0208] refer to Figures 9 to 12 According to the embodiments, the display panel DP may include a display area DA and a non-display area NDA adjacent to the display area DA. The display area DA includes light-emitting areas PXA (e.g., a first light-emitting area PXA-R, a second light-emitting area PXA-B, a third-first light-emitting area PXA-G1, and a third-second light-emitting area PXA-G2) and a peripheral area NPXA. The display area DA and the non-display area NDA may correspond to those described above. The first light-emitting area PXA-R, the second light-emitting area PXA-B, the third-first light-emitting area PXA-G1, the third-second light-emitting area PXA-G2, and the peripheral area NPXA may correspond to those described above.

[0209] According to an implementation, the non-display area NDA may include a first non-display area NDA1 adjacent to the display area DA, and a second non-display area NDA2 spaced apart from the display area DA, with the first non-display area NDA1 located therebetween.

[0210] The partition wall WA can be disposed in a portion of the non-display area NDA and the display area DA. The partition wall WA may include a first pattern WA-D disposed in the display area DA and a second pattern WA-N connected to the first pattern WA-D and extending from the first pattern WA-D to the first non-display area NDA1.

[0211] The first pattern WA-D can be disposed on the pixel-defining layer PDL. In an embodiment, the first pattern WA-D does not overlap with the first light-emitting area PXA-R, the second light-emitting area PXA-B, the third-first light-emitting area PXA-G1, and the third-second light-emitting area PXA-G2, and can have a grid shape.

[0212] Figure 8A The spacer SP described herein can be disposed on a pixel-defining layer PDL that overlaps with the display area DA. At least a portion of the spacer SP can be surrounded by and spaced apart from the first pattern WA-D.

[0213] According to the embodiment, the area of ​​the peripheral region NPXA in which the first pattern WA-D is provided can be defined as the partition wall region A1, and the area in which the spacer SP is provided can be defined as the support region A2. The area of ​​the peripheral region NPXA other than the partition wall region A1 and the support region A2 can be defined as the normal region A0.

[0214] The second pattern WA-N can be disposed in the first non-display area NDA1. The second pattern WA-N may include a normal pattern WP1 extending from the first pattern WA-D, and a connecting pattern WP2 extending from the normal pattern WP1 toward the signal line PL and spaced apart from each other. The connecting pattern WP2 may be a protrusion extending from the outer portion of the grid in the first non-display area NDA1.

[0215] The normal pattern WP1 may have a grid shape extending from the first pattern WA-D. The normal pattern WP1 may be a portion extending from the first pattern WA-D in the direction toward the first non-display area NDA1 and having the same pattern to prevent the shape of the first pattern WA-D from being broken. For example, as... Figure 9 As shown, the normal pattern WP1 can form a grid in which the outer diagonal portions of adjacent segments of the normal pattern WP1 extend toward and connect with one of the connecting patterns WP2. According to an embodiment, the normal pattern WP1 can be omitted, and the connecting pattern WP2 can extend together with the first pattern WA-D.

[0216] Signal lines PL and SD2 can be located in the first non-display area NDA1. Signal lines PL and SD2 in the first non-display area NDA1 can be... Figure 6 The second connecting electrode CNE2 described herein is disposed on the same layer as the line. Therefore, signal lines PL and SD2 can be disposed on the sixth insulating layer INS6 and covered by the seventh insulating layer INS7. The connecting pattern WP2 can cross or intersect with signal lines PL and SD2.

[0217] According to an implementation, an equivalent voltage can be applied to one of the signal lines PL and SD2, signal line PL. In this implementation, the equivalent voltage is a voltage used to operate the display device or drive pixels. For example, signal line PL may correspond to... Figure 4B One of the first power line PL1 and the second power line PL2 is shown. Therefore, either the first drive voltage ELVDD or the second drive voltage ELVSS can be applied to the signal line PL.

[0218] Figure 4A The scan driver SDV described herein can be located in a second non-display area NDA2 of the non-display area NDA. The scan driver SDV may include... Figure 4B The transistors T1 to T8 described herein are transistors formed using the same process. In an embodiment, the area of ​​the second non-display area NDA2 in which the scan driver SDV is disposed can be defined as the scan area SCA (also known as the driver area).

[0219] According to one embodiment, a protection electrode NAE can be disposed in the scanning area SCA. Since the protection electrode NAE is positioned to overlap with the scan driver SDV and an equivalent voltage is applied to it, the protection electrode NAE can protect the scan driver SDV from electrical stimulation introduced into the non-display area NDA. Therefore, an electronic device ED with enhanced display quality can be provided. The protection electrode NAE can receive an equivalent voltage because it is connected to the signal line PL. Further description of this will be provided later.

[0220] The protection electrode NAE may include: a first electrode NA-E, which is arranged along a first direction DR1 and each extends along a second direction DR2; a second electrode NA-C, which is disposed between two adjacent first electrodes NA-E along the first direction DR1 and arranged along the second direction DR2; and a third electrode NA-B, which protrudes from the first electrode NA-E adjacent to the signal line PL toward the signal line PL and is arranged along the second direction DR2. The first electrode NA-E, the second electrode NA-C, and the third electrode NA-B are a connected integral pattern, but for ease of description, they will be described separately. The protection electrode NAE may include one or more holes (e.g., electrode holes). In some embodiments, the electrode hole may be rectangular in shape, but is not limited thereto.

[0221] According to the implementation method, the protection electrode NAE can be with Figure 6 The first electrode AE-G1 described herein is disposed on the same layer. Therefore, the guard electrode NAE can be patterned using the same process as the first electrode AE-G1 and comprises the same material as the first electrode AE-G1.

[0222] According to an embodiment, the protective electrode NAE can be disposed on the same layer as the second electrode CE. Therefore, the protective electrode NAE can be patterned using the same process as the second electrode CE, and both electrodes can comprise the same material.

[0223] Two first electrodes NA-E that are adjacent to each other along the first direction DR1 and two second electrodes NA-C that are disposed between the two first electrodes NA-E and arranged along the second direction DR2 can define an electrode hole H1 or H2.

[0224] According to the current embodiment, a first electrode hole H1 arranged along the second direction DR2 can be defined as a first hole group, and a second electrode hole H2 arranged along the second direction DR2 can be defined as a second hole group. The first hole group and the second hole group can be spaced apart from each other along the first direction DR1, with a first electrode NA-E between them. The first electrode hole H1 included in the first hole group and the second electrode hole H2 included in the second hole group can be shifted along the second direction DR2. For example, the first electrode hole H1 can be laterally offset from the second electrode hole H2 by a predetermined distance along the second direction DR2 to facilitate alignment or increase structural uniformity.

[0225] According to one embodiment, a portion of each of the third electrodes NA-B and a portion of each of the connection patterns WP2 may overlap with the signal line PL. According to another embodiment, the third electrodes NA-B and the connection patterns WP2 may be alternately arranged on the signal line PL along the second direction DR2.

[0226] exist Figure 9 The illustration shows an embodiment in which a third electrode NA-B and a connection pattern WP2 are arranged alternately along the second direction DR2, but is not limited thereto. Instead, the third electrode NA-B and the connection pattern WP2 can be regularly arranged to overlap with the signal line PL.

[0227] The third electrode NA-B can be connected to the signal line PL through the first contact hole CN1, and the connection pattern WP2 can be connected to the signal line PL through the second contact hole CN2.

[0228] refer to Figure 10 The first contact hole CN1 can be defined as the first contact portion CNT1 that overlaps with the first non-display area NDA1 and penetrates the seventh insulating layer INS7. Signal line PL (e.g., Figure 10 A portion of the second power line PL2 can be exposed through the first contact hole CN1, and the third electrode NA-B can contact the portion of the signal line PL exposed by the first contact hole CN1.

[0229] refer to Figure 11 The electrode pattern AE-P and the second electrode CE can be in contact with each other in the first non-display area NDA1. The electrode pattern AE-P can be connected to the first electrode AE ​​disposed in the display area DA (see...). Figure 6 The pattern of the protective electrode NAE set in the second non-display area NDA2.

[0230] refer to Figure 12 The first electrode NA-E and the second electrode CE can be connected to each other in the second non-display area NDA2 via a contact portion CNT-P, in which the pixel definition layer PDL overlapping with the second non-display area NDA2 is penetrated. Therefore, the second electrode CE and the first electrode NA-E can be connected to each other in the non-display area NDA.

[0231] According to the embodiment, the protection electrode NAE can receive an equivalent voltage (e.g., a second drive voltage ELVSS) because the protection electrode NAE is connected to the signal line PL through the first contact hole CN1. Since the protection electrode NAE, to which the equivalent voltage is applied, is located in the scan area SCA, the scan driver SDV can be protected from external electrical influences. Therefore, an electronic device ED with enhanced display quality can be provided.

[0232] The second contact hole CN2 can be defined as a second contact portion CNT2 overlapping the first non-display area NDA1. The second contact portion CNT2 may include a first side portion C1 penetrating the seventh insulating layer INS7 and a second side portion C2 penetrating the pixel defining layer PDL. Signal line PL (e.g., Figure 10 A portion of the second power line (PL2) can be exposed through the second contact hole CN2.

[0233] The first insulating pattern IN1 and the second insulating pattern IN2 of the connection pattern WP2 disposed in the second contact hole CN2 may include insulating openings I-OP1 and I-OP2 that overlap with the second contact hole CN2. The first partition wall pattern W1 of the connection pattern WP2 disposed in the second contact hole CN2 may contact the portion of the signal line PL exposed by the second contact hole CN2.

[0234] According to the implementation, the partition wall WA can receive an equivalent voltage (e.g., a second drive voltage ELVSS) because the partition wall WA is connected to the signal line PL (e.g., a second power line PL2) via the second contact hole CN2. Figure 6 As shown, since the second electrode CE is disposed throughout the display area DA and contacts the partition wall WA, the second electrode CE can direct light to pixel PX (see [reference]). Figure 4A This provides a second driving voltage, ELVSS. Therefore, it is possible to provide electronic devices (EDs) with enhanced display quality.

[0235] Figure 13 This is a plan view of a display panel according to an embodiment of the present invention. Figures 9 to 12 Components that are identical or similar to those described herein are represented by identical or similar reference numerals or symbols, and repeated descriptions thereof are omitted.

[0236] refer to Figure 13 According to the embodiment, the display panel DP-1 may include a display area DA and a non-display area NDA adjacent to the display area DA. The display area DA includes a light-emitting area PXA (e.g., a first light-emitting area PXA-R, a second light-emitting area PXA-B, a third-first light-emitting area PXA-G1, and a third-second light-emitting area PXA-G2) and a peripheral area NPXA.

[0237] According to the embodiment, the first light-emitting region PXA-R, the second light-emitting region PXA-B, the third-first light-emitting region PXA-G1, and the third-second light-emitting region PXA-G2 can each have a circular shape. The areas of the first light-emitting region PXA-R, the second light-emitting region PXA-B, the third-first light-emitting region PXA-G1, and the third-second light-emitting region PXA-G2 can be different from each other. However, the shape of each of the first light-emitting region PXA-R, the second light-emitting region PXA-B, the third-first light-emitting region PXA-G1, and the third-second light-emitting region PXA-G2 can correspond to... Figure 9 The shape described herein is not limited to any one embodiment.

[0238] The partition wall WA can be disposed in a portion of the non-display area NDA and the display area DA. The partition wall WA may include a first pattern WA-D disposed in the display area DA and a second pattern WA-N connected to the first pattern WA-D and extending from the first pattern WA-D to the first non-display area NDA1.

[0239] The normal pattern WP1 of the first pattern WA-D and the second pattern WA-N can have a grid shape. The connecting pattern WP2 of the second pattern WA-N can each extend from the normal pattern WP1 to the signal line PL in the first direction DR1, and can be spaced apart from each other along the second direction DR2.

[0240] Signal lines PL and SD2 can be located in the first non-display area NDA1. An equivalent voltage can be applied to one of the signal lines PL and SD2. For example, signal line PL can correspond to... Figure 4B One of the first power line PL1 and the second power line PL2 described herein. Therefore, either the first drive voltage ELVDD or the second drive voltage ELVSS can be applied to the signal line PL.

[0241] The protection electrode NAE-1 can be disposed in the scan area SCA of the second non-display area NDA2. The protection electrode NAE-1 may include: a first electrode NA-E, which is arranged along a first direction DR1 and each extends along a second direction DR2; a second electrode NA-C, which is disposed between two first electrodes NA-E that are adjacent to each other along the first direction DR1 and is arranged along the second direction DR2; and a third electrode NA-B, which protrudes from the first electrode NA-E that is most adjacent to the signal line PL in the direction toward the signal line PL and is arranged along the second direction DR2.

[0242] According to the implementation method, on the signal line PL, the third electrode NA-B and the connection pattern WP2 can be arranged alternately and irregularly.

[0243] For example, the third electrode NA-B may not be positioned between two adjacent connection patterns WP2 along the second direction DR2, and two third electrodes NA-B may be positioned between two other adjacent connection patterns WP2 along the second direction DR2. For example, along the second direction DR2, there may be no third electrode NA-B between two adjacent connection patterns WP2, or two third electrodes NA-B may be positioned between two adjacent connection patterns WP2. One third electrode NA-B can be connected to the signal line PL through the first contact hole CN1-1, and the other third electrode NA-B can be connected to the signal line PL through the first contact hole CN1-2.

[0244] According to the embodiment, the shapes of the electrode holes H1 and H2 disposed in the second non-display area NDA2 adjacent to the first non-display area NDA1 can be different from the shapes of the adjacent electrode holes H1 and H2.

[0245] Although this specification relates to various embodiments, those skilled in the art will understand that this disclosure can be modified and changed in various ways without departing from the spirit of this disclosure. Therefore, the technical scope of this disclosure should not be limited to what is described in the detailed description herein.

Claims

1. Electronic devices, including: A display panel includes a display area and a non-display area adjacent to the display area, wherein the non-display area includes a scanning area; as well as A scan driver, disposed in the non-display area of ​​the display panel, receives scan control signals from a timing controller and overlaps with the scan area. The display panel includes: The substrate includes a light-emitting region disposed in the display area and a peripheral region disposed between the light-emitting regions; Multiple pixels overlap with the display area; A pixel defining layer overlaps with the peripheral region and defines an opening corresponding to the light-emitting region; A partition wall is disposed on the pixel defining layer, the partition wall comprising a first pattern overlapping the display area and a second pattern extending from the first pattern to overlap the non-display area; A signal line is disposed between the display area and the scanning area, wherein the signal line is configured to receive a driving voltage for driving the pixel; and The protective electrode overlaps with the scanning area and the scanning driver. The protective electrode and the second pattern are respectively connected to the signal line through contact holes.

2. The electronic device according to claim 1, wherein, The protective electrode and the electrode of the light-emitting element of the pixel are disposed on the same layer, and the signal line is disposed below the electrode.

3. The electronic device according to claim 1, wherein: The first pattern is disposed on the pixel defining layer and has a grid shape spaced apart from the opening; as well as The second pattern includes a normal pattern extending from the first pattern and having a shape similar to the first pattern, and a plurality of connecting patterns extending from the normal pattern and spaced apart from each other in the direction toward the signal line.

4. The electronic device according to claim 3, wherein, The protective electrode includes: The first electrode is arranged along a first direction and extends along a second direction that intersects the first direction; The second electrode is arranged along the second direction and disposed between the first electrodes that are adjacent to each other along the first direction; and The third electrode is arranged along the second direction and protrudes from one of the first electrodes adjacent to the signal line in the direction toward the signal line.

5. The electronic device according to claim 4, wherein, An electrode hole is defined by an adjacent first electrode that is adjacent to each other along the first direction and a second electrode disposed between the adjacent first electrodes.

6. The electronic device according to claim 5, wherein: The electrode holes are configured as a plurality of electrode holes arranged along the second direction to define a hole group; as well as Electrode holes in adjacent hole groups that are adjacent to each other along the first direction, including the hole group, are shifted along the second direction.

7. The electronic device according to claim 4, wherein, The connection pattern and the third electrode are arranged alternately along the second direction on the signal line.

8. The electronic device according to claim 4, wherein, The connection pattern and the third electrode are arranged regularly.

9. The electronic device according to claim 4, wherein, The display panel further includes an interlayer insulating layer disposed between the third electrode and the signal line, and comprising an organic material. The third electrode is connected to the signal line through a first contact hole that penetrates the interlayer insulation layer in the contact hole.

10. The electronic device according to claim 1, wherein, The partition wall includes: A first insulating pattern is disposed on the pixel defining layer; The second insulating pattern is disposed on the first insulating pattern; A first partition pattern is disposed on the second insulating pattern; and The second partition wall pattern is set on the first partition wall pattern.

11. The electronic device according to claim 10, wherein: The first insulating pattern includes at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide; and The second insulating pattern includes at least one of silicon oxide, silicon oxynitride, and silicon nitride.

12. The electronic device according to claim 10, wherein: The first partition wall pattern includes aluminum; and The second partition wall pattern includes titanium.

13. The electronic device according to claim 10, wherein: The thickness of the first partition wall pattern is greater than the thickness of the second partition wall pattern; The width of the second partition wall pattern is greater than the width of the first partition wall pattern; as well as A portion of the lower surface of the second partition wall pattern protrudes from and is exposed to the first partition wall pattern.

14. The electronic device according to claim 13, wherein, The display panel also includes: A dummy pattern is placed on the upper surface of the second partition wall pattern. The dummy pattern and the common layer between the multiple electrodes of the light-emitting element of the pixel comprise the same material.

15. The electronic device according to claim 14, wherein, One of the plurality of electrodes extends from one of the light-emitting areas into the peripheral area and covers a portion of the side surface of the first partition wall pattern, the lower surface of the second partition wall pattern, and the dummy pattern.

16. The electronic device according to claim 11, wherein, The display panel further includes an interlayer insulating layer disposed between the second pattern and the signal line, and comprising an organic material. The second contact hole in the contact hole penetrates both the interlayer insulating layer and the pixel defining layer. The first insulating pattern and the second insulating pattern disposed in the second contact hole include an insulating opening overlapping the second contact hole, and The first partition wall pattern of the second pattern disposed in the second contact hole is connected to the signal line through the insulating opening and the second contact hole.

17. The electronic device according to claim 1, wherein, The pixels include: The first pixel provides red light; The second pixel, spaced apart from the first pixel along a first direction, provides blue light; and The third and fourth pixels are positioned between the first and second pixels, spaced apart from each other along a second direction intersecting the first direction, and provide green light.

18. The electronic device according to claim 17, wherein, The luminescent region includes: The first luminescent area overlaps with the first pixel; The second light-emitting area overlaps with the second pixel; and The third and fourth light-emitting regions overlap with the third and fourth pixels. The area of ​​the first luminescent region is smaller than the area of ​​the second luminescent region and larger than the area of ​​each of the third and fourth luminescent regions.

19. A display device including a display panel, the display panel comprising: A display area and a non-display area adjacent to the display area, wherein the non-display area includes a driver area and a driver circuit is provided in the driver area; The substrate includes a light-emitting region disposed in the display area and a peripheral region disposed between the light-emitting regions; Multiple pixels overlap with the display area; A pixel-defining layer overlaps with the peripheral region and defines an opening that exposes at least a portion of the light-emitting region; A partition wall, disposed on the pixel defining layer, the partition wall comprising: a first pattern having a grid shape in the display area overlapping the plurality of pixels; and a second pattern extending from the first pattern into the non-display area, and having a protrusion extending from the outer portion of the grid shape in the non-display area toward the driver region; and A protective electrode is disposed in the driver region and electrically connected to the second pattern and configured to provide a predetermined voltage power line.

20. Electronic devices, including: Display panel and voltage generator, The display panel includes: A display area and a non-display area adjacent to the display area, wherein the non-display area includes a driver area and a driver circuit is provided in the driver area; The substrate includes a light-emitting region disposed in the display area and a peripheral region disposed between the light-emitting regions; Multiple pixels overlap with the display area; A pixel-defining layer overlaps with the peripheral region and defines an opening that exposes at least a portion of the light-emitting region; A partition wall, disposed on the pixel defining layer, the partition wall comprising: a first pattern having a grid shape in the display area overlapping the plurality of pixels; and a second pattern extending from the first pattern into the non-display area, and having a protrusion extending from the outer portion of the grid shape in the non-display area toward the driver region; and A protective electrode is disposed in the driver region and electrically connected to the second pattern, and The voltage generator is configured to provide voltage to the protection electrode and the plurality of pixels.

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