Display device, method for manufacturing a display device, and electronic device comprising a display device

Abstract

This disclosure relates to a display device, a method for manufacturing a display device, and an electronic device including a display device. The display device includes: a substrate including a display area and a peripheral region surrounding at least a portion of the display area; a plurality of sub-pixels on the substrate in the display area; a first transistor with a gate driver on the substrate in the peripheral region; a second transistor with a gate driver on the first transistor in the peripheral region; and an inorganic insulating layer covering the second transistor and defining a plurality of vias adjacent to and spaced apart from the second transistor.

Description

Technical Field

[0001] Some aspects of this disclosure relate to display devices, methods for manufacturing display devices, and electronic devices including display devices. Background Technology

[0002] With the development of information technology, display devices, which provide a communication medium between users and information, are becoming increasingly important. Therefore, the use of display devices such as liquid crystal displays, organic light-emitting diode displays, and plasma displays is also increasing.

[0003] A display device can display an image (e.g., a set or predetermined image) by including a driving transistor and a light-emitting element, wherein the light-emitting element receives driving current from the driving transistor and emits light. In order to provide driving current to the light-emitting element, drivers, wires, etc. can be arranged in the peripheral area of ​​the display device.

[0004] The peripheral area without a positioning light-emitting element does not display an image. This peripheral area where no image is displayed can be called a dead zone. Recently, there has been a growing demand for reducing dead zones in display devices.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0006] Some aspects of this disclosure relate to display devices, methods for manufacturing display devices, and electronic devices including display devices. For example, some aspects of this disclosure relate to display devices that provide visual information, methods for manufacturing display devices, and electronic devices including display devices.

[0007] Some aspects of implementation include display devices for relatively reducing dead zones and preventing or reducing transistor characteristic degradation.

[0008] Some aspects of implementation include methods for manufacturing display devices.

[0009] Some aspects of implementation include electronic devices that include a display device.

[0010] A display device according to some embodiments of the present disclosure includes: a substrate including a display area and a peripheral region surrounding at least a portion of the display area; a plurality of sub-pixels on the substrate in the display area; a first transistor with a gate driver on the substrate in the peripheral region; a second transistor with a gate driver on the first transistor in the peripheral region; and an inorganic insulating layer covering the second transistor and defining a plurality of vias adjacent to and spaced apart from the second transistor.

[0011] According to some implementation methods, the multiple through holes can be filled with insulating material.

[0012] According to some embodiments, the display device may also include a via insulating layer on an inorganic insulating layer, the via insulating layer filling the interior of a plurality of vias and including an organic material.

[0013] According to some implementations, the first transistor and the second transistor may include metal-oxide-semiconductor.

[0014] According to some embodiments, the second transistor may include: an upper active pattern, including a metal-oxide-semiconductor; and an upper gate electrode that overlaps with the channel region of the upper active pattern in a planar view.

[0015] According to some embodiments, the display device may further include an intermediate connection pattern that is connected in the peripheral region to the conductive area of ​​the upper active pattern through a contact hole penetrating the inorganic insulating layer.

[0016] According to some embodiments, the display device may further include: a first interlayer insulating layer covering the first transistor; a second interlayer insulating layer on the first interlayer insulating layer; and a buffer layer between the second interlayer insulating layer and the second transistor, wherein each of the plurality of vias may expose at least a portion of the buffer layer.

[0017] According to some implementations, the spacing between two adjacent vias in a plurality of vias can be in the range of 10 micrometers (μm) or greater and 15 micrometers (μm) or less.

[0018] According to some embodiments, the plurality of vias may include a plurality of first vias that are adjacent to and spaced apart from each other in the peripheral region and a plurality of second vias that are spaced apart from each other in the display region.

[0019] According to some implementations, each of the plurality of sub-pixels may include a plurality of transistors comprising a metal-oxide-semiconductor.

[0020] According to some implementations, each of the plurality of transistors may include a first lower active pattern, and the first transistor includes a second lower active pattern in the same layer as the first lower active pattern.

[0021] A method for manufacturing a display device according to some embodiments of the present disclosure includes: forming a plurality of sub-pixels in a display area on a substrate including a display area and a peripheral area surrounding at least a portion of the display area; forming a first transistor with a gate driver in the peripheral area on the substrate; forming a second transistor with a gate driver in the peripheral area on the first transistor; forming an inorganic insulating layer covering the second transistor; and forming a plurality of through-holes adjacent to and spaced apart from the second transistor by penetrating the inorganic insulating layer.

[0022] According to some embodiments, the method may also include forming a via insulating layer on an inorganic insulating layer, with an interior filled with a plurality of through holes and comprising an organic material.

[0023] According to some implementations, the first transistor and the second transistor may include metal-oxide-semiconductor.

[0024] According to some embodiments, forming a second transistor may include: forming an upper active pattern comprising a metal-oxide-semiconductor; and forming an upper gate electrode in a planar view that overlaps with a channel region of the upper active pattern.

[0025] According to some embodiments, the method may further include: forming a contact hole that penetrates the inorganic insulating layer and exposes a conductive region of the upper active pattern; and forming an intermediate connection pattern that connects to the conductive region of the upper active pattern through the contact hole.

[0026] According to some implementations, multiple through holes can be formed using the same process as contact holes.

[0027] According to some embodiments, the plurality of vias may include a plurality of first vias that are adjacent to and spaced apart from each other in the peripheral region and a plurality of second vias that are spaced apart from each other in the display region.

[0028] An electronic device according to some embodiments of the present disclosure includes: a processor that provides image data signals and input control signals; and a display device that outputs image information based on the image data signals and input control signals. The display device includes: a substrate that includes a display area and a peripheral area surrounding at least a portion of the display area; a plurality of sub-pixels on the substrate in the display area; a first transistor with a gate driver on the substrate in the peripheral area and comprising a metal-oxide-semiconductor; a second transistor with a gate driver on the first transistor in the peripheral area and comprising a metal-oxide-semiconductor; and an inorganic insulating layer that covers the second transistor and defines a plurality of vias adjacent to and spaced apart from the second transistor.

[0029] According to some embodiments, the display device may also include a via insulating layer on an inorganic insulating layer, the via insulating layer filling the interior of a plurality of vias and including an organic material.

[0030] In a display device according to some embodiments of the present disclosure, in a peripheral region, in a structure in which a first transistor comprising a metal-oxide-semiconductor (MOS) in a first circuit layer and a second MOS in a second circuit layer are stacked along the thickness direction, a plurality of vias spaced apart from each other can be defined in an inorganic insulating layer (i.e., a third interlayer insulating layer) included in the second circuit layer. Therefore, hydrogen generated from the insulating layer included in the first circuit layer and which can be used as charge carriers when absorbed into the lower active pattern of the first transistor can diffuse (or be released) to the outside (i.e., the second circuit layer) through the plurality of vias. In this case, the characteristics of the lower element included in the first circuit layer may not deteriorate, and the variation of the lower element may be relatively reduced. Attached Figure Description

[0031] The illustrative and non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0032] Figure 1 This is a plan view showing a display device according to some embodiments of the present disclosure.

[0033] Figure 2 It is shown Figure 1 A circuit diagram of the circuit structure of a sub-pixel.

[0034] Figure 3 It is an illustrative representation of including Figure 1 Circuit diagram of the stage in the first gate driver or the second gate driver.

[0035] Figure 4 It is along Figure 1 A sectional view taken by line I-I'.

[0036] Figure 5 It is shown Figure 1 and Figure 4 A magnified plan of the outer area.

[0037] Figure 6 It is shown Figure 1 and Figure 4 A magnified view of the display area.

[0038] Figures 7 to 20 It is used to explain the manufacturing process. Figure 4 A cross-sectional view of the method of displaying the device.

[0039] Figure 21 This is a graph used to explain the variation of the threshold voltage of the upper element in the comparative examples and embodiments according to the spacing between the vias.

[0040] Figure 22 This is a graph used to explain the variation of the threshold voltage of the lower element in the comparative examples and embodiments according to the spacing between the vias.

[0041] Figure 23 This is a graph used to explain the variation of the drain-source current in the comparative example with the gate-source voltage of the underlying element.

[0042] Figure 24 This is a graph used to explain the variation of drain-source current with respect to the gate-source voltage of the underlying element according to some implementations.

[0043] Figure 25 This is a block diagram illustrating an electronic device according to some embodiments of the present disclosure.

[0044] Figure 26 This is a schematic diagram illustrating an electronic device according to various embodiments. Detailed Implementation

[0045] In the following, some aspects of embodiments of this disclosure will be explained in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components may be omitted.

[0046] In this specification, it can be determined by the first direction D1 (see...) Figure 1 ) and the second direction D2 intersecting the first direction D1 (see Figure 1 The plane is defined by a first direction D1. For example, the first direction D1 can be perpendicular to the second direction D2. Furthermore, the third direction D3 (see...) Figure 1 () can be the normal direction of the plane. That is, the third direction D3 can be perpendicular to the plane.

[0047] Figure 1 This is a plan view showing a display device according to some embodiments of the present disclosure.

[0048] refer to Figure 1 According to some embodiments of the present disclosure, the display device DD may include a plurality of sub-pixels SPX located on a substrate SUB, a first gate driver GDV1, a second gate driver GDV2, a first gate signal line GL1, a second gate signal line GL2, a data line DL, a power line PL, a first control signal line CSL1, a second control signal line CSL2, a display panel driver DPD, and a circuit board CB. Although in Figure 1 The diagram shows a single sub-pixel SPX, a single first gate signal line GL1, a single second gate signal line GL2, a single data line DL, and a single power line PL. However, as those skilled in the art will understand, the display device DD may include any suitable number of the above components depending on the design and size of the display device DD.

[0049] The substrate SUB may include a display area DA and a peripheral area PA. The display area DA may be an area capable of displaying an image by generating light or controlling the transmittance of light supplied from an external light source. The peripheral area PA may be an area where no image is displayed. The peripheral area PA may surround at least a portion of the display area DA. For example, the peripheral area PA may completely surround the display area DA.

[0050] The peripheral region PA may include a pad region PDA. The pad region PDA may be located at one end of the peripheral region PA adjacent to the lower side of the display region DA. The pad region PDA may have a shape extending along one side of the display device DD. For example, the pad region PDA may have a shape extending along a first direction D1.

[0051] Multiple sub-pixels (SPXs) can be arranged in the display area DA. Each of the multiple sub-pixels (SPXs) may include a driving element (e.g., a thin-film transistor) that generates a driving current, and a light-emitting element (e.g., an organic light-emitting diode or an inorganic light-emitting diode) electrically connected to the driving element and generating light based on the driving current. Therefore, each of the multiple sub-pixels (SPXs) can generate light according to the driving current. The multiple sub-pixels (SPXs) can be arranged in a matrix in the display area DA along a first direction D1 and a second direction D2.

[0052] The drivers used to drive multiple sub-pixels (SPX) can be located in the peripheral region PA. For example, the first gate driver GDV1, the second gate driver GDV2, and the display panel driver DPD can be located in the peripheral region PA.

[0053] The data line DL, the first gate signal line GL1, the second gate signal line GL2, and the power line PL connected to multiple sub-pixels SPX can be located in the display area DA. Furthermore, the first control signal line CSL1 connected to the first gate driver GDV1 and the second control signal line CSL2 connected to the second gate driver GDV2 can be located in the peripheral area PA.

[0054] A first gate signal line GL1 may be electrically connected to a first gate driver GDV1 and may extend along a first direction D1. The first gate signal line GL1 may receive a first gate signal from the first gate driver GDV1 and provide the first gate signal to a plurality of sub-pixels SPX. For example, the first gate signal may include... Figure 2 At least one of the gate signals GW, GR and GI.

[0055] The second gate signal line GL2 can be electrically connected to the second gate driver GDV2 and can extend along the first direction D1. The second gate signal line GL2 can receive a second gate signal from the second gate driver GDV2 and provide the second gate signal to a plurality of sub-pixels SPX. For example, the second gate signal may include Figure 2 At least one of the gate signals GW, GR and GI.

[0056] The data cable DL can be electrically connected to the display panel driver DPD and can extend along the second direction D2. The data cable DL can receive data voltage from the display panel driver DPD (e.g., Figure 2 The data voltage is supplied via the VDATA line and the data line DL. The data line DL can supply data voltage to multiple sub-pixels (SPX).

[0057] The power line PL can be electrically connected to the display panel driver DPD and can extend along the second direction D2. The power line PL can receive power voltage from the display panel driver DPD (e.g., Figure 2 The driving voltage (ELVDD) is used to supply power voltage to multiple sub-pixels (SPX). For example, the power voltage could be a high power voltage used to drive multiple sub-pixels (SPX).

[0058] The first control signal line CSL1 can be electrically connected to the display panel driver DPD. The first control signal line CSL1 can receive a first control signal from the display panel driver DPD and provide the first control signal to the first gate driver GDV1.

[0059] The second control signal line CSL2 can be electrically connected to the display panel driver DPD. The second control signal line CSL2 can receive the second control signal from the display panel driver DPD and provide the second control signal to the second gate driver GDV2.

[0060] The display panel driver (DPD) can be located within the pad area of ​​the PDA. The display panel driver (DPD) can be formed as an integrated circuit (IC). For example, if the substrate SUB of the display device (DD) comprises glass, the display panel driver (DPD) can be a chip-on-glass (COG) structure directly on the substrate SUB. Alternatively, if the substrate SUB comprises plastic, the display panel driver (DPD) can be a chip-on-plastic (COP) structure directly on the substrate SUB. Embodiments of this disclosure are not necessarily limited thereto.

[0061] Display panel driver (DPD) can transmit various signals and / or voltages. For example, a display panel driver (DPD) can transmit a first control signal, a second control signal, power voltage, data voltage, etc. That is, a display panel driver (DPD) may include a data driver for transmitting data voltage, a timing controller for transmitting the first and second control signals, and a power supply for transmitting power voltage. Alternatively, the timing controller and power supply may be located externally to the display panel driver (DPD).

[0062] The first gate driver GDV1 can be located in the peripheral region PA. For example, the first gate driver GDV1 can be located in the peripheral region PA adjacent to the left edge of the display region DA. The first gate driver GDV1 can receive a first control signal from the display panel driver DPD and can generate a first gate signal based on the first control signal.

[0063] The second gate driver GDV2 can be located in the peripheral region PA. For example, the second gate driver GDV2 can be located in the peripheral region PA adjacent to the right edge of the display region DA. The second gate driver GDV2 can receive a second control signal from the display panel driver DPD and can generate a second gate signal based on the second control signal.

[0064] The first gate driver GDV1 and the second gate driver GDV2 may each include a plurality of transistors. According to some embodiments, each of the plurality of transistors included in the first gate driver GDV1 and the second gate driver GDV2 may include a metal-oxide-semiconductor.

[0065] The display device DD may also include an emission driver located in the peripheral region PA and generating an emission control signal. The emission driver can provide the emission control signal to multiple sub-pixels SPX. For example, the emission control signal may include... Figure 2 At least one of the transmit control signals EM and EMB.

[0066] The circuit board CB can be located within the pad area PDA. Specifically, the circuit board CB can partially overlap with the pad area PDA. That is, a first portion of the circuit board CB can overlap with the pad area PDA, and a second portion of the circuit board CB other than the first portion can not overlap with the pad area PDA. The circuit board CB can be bonded to the pad area PDA using an adhesive component (e.g., anisotropic conductive film). The circuit board CB can provide voltage, control signals, etc., to the display panel driver DPD.

[0067] For example, the circuit board CB may include a printed circuit board (PCB), a flexible printed circuit board (FPCB), or a flexible flat cable (FFC). Embodiments of this disclosure are not necessarily limited thereto.

[0068] Figure 2 It is shown Figure 1 A circuit diagram of the circuit structure of a sub-pixel. Although Figure 2 Various components in a subpixel according to some embodiments are shown, but the embodiments of this disclosure are not limited thereto, and according to various embodiments, a subpixel may include additional or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0069] refer to Figure 2 A sub-pixel SPX may include a pixel driving circuit section PC and a light-emitting element LED electrically connected to the pixel driving circuit section PC. The pixel driving circuit section PC can generate a driving current, and the light-emitting element LED can generate light based on the driving current.

[0070] According to some implementations, the pixel driving circuit portion PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0071] According to some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can all be NMOS transistors. However, the embodiments of this disclosure are not necessarily limited thereto, and some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be NMOS transistors, while the others can be PMOS transistors.

[0072] In the case where the pixel driving circuit PC includes NMOS transistors and PMOS transistors, the active pattern of the NMOS transistor may include metal-oxide-semiconductor (MODS) and the active pattern of the PMOS transistor may include silicon semiconductor. However, embodiments of this disclosure are not necessarily limited thereto, and the active pattern of the NMOS transistor may include silicon semiconductor and the active pattern of the PMOS transistor may include MODS.

[0073] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a fifth transistor T5. The second electrode of the first transistor T1 may be connected to a second node N2. The first transistor T1 may provide driving current to a light-emitting element (LED).

[0074] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the second transistor T2 may receive a first gate signal GW. The first electrode of the second transistor T2 may receive a data voltage VDATA. The second electrode of the second transistor T2 may be connected to a first node N1.

[0075] The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, when the first gate signal GW has an active level, the second transistor T2 can be turned on. In this case, the second transistor T2 can provide the data voltage VDATA to the first node N1. Conversely, when the first gate signal GW has an inactive level, the second transistor T2 can be turned off. In this case, the second transistor T2 can block the provision of the data voltage VDATA.

[0076] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the third transistor T3 may receive a second gate signal GR. The first electrode of the third transistor T3 may receive a reference voltage VREF. The second electrode of the third transistor T3 may be connected to a first node N1. For example, the reference voltage VREF may have a voltage level that is different from or the same as the common voltage ELVSS.

[0077] The third transistor T3 can be turned on or off in response to the second gate signal GR. For example, when the second gate signal GR has an active level, the third transistor T3 can be turned on. In this case, the third transistor T3 can provide the reference voltage VREF to the first node N1. Conversely, when the second gate signal GR has an inactive level, the third transistor T3 can be turned off. In this case, the third transistor T3 can block the provision of the reference voltage VREF.

[0078] The fourth transistor T4 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fourth transistor T4 may receive a third gate signal GI. The first electrode of the fourth transistor T4 may receive an initialization voltage VINT. The second electrode of the fourth transistor T4 may be connected between the sixth transistor T6 and the light-emitting element LED. For example, the initialization voltage VINT may have a voltage level that is different from or the same as the common voltage ELVSS.

[0079] The fourth transistor T4 can be turned on or off in response to the third gate signal GI. For example, when the third gate signal GI has an active level, the fourth transistor T4 can be turned on. In this case, the fourth transistor T4 can provide the initialization voltage VINT to the node between the sixth transistor T6 and the light-emitting element LED. Conversely, when the third gate signal GI has an inactive level, the fourth transistor T4 can be turned off. In this case, the fourth transistor T4 can block the provision of the initialization voltage VINT.

[0080] The fifth transistor T5 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fifth transistor T5 may receive a first transmit control signal EM. The first electrode of the fifth transistor T5 may receive a drive voltage ELVDD. The second electrode of the fifth transistor T5 may be connected to the first transistor T1.

[0081] The fifth transistor T5 can be turned on or off in response to the first transmit control signal EM. For example, when the first transmit control signal EM has an active level, the fifth transistor T5 can be turned on. In this case, the fifth transistor T5 can supply the drive current generated in the first transistor T1 to the anode electrode of the light-emitting element LED. Conversely, when the first transmit control signal EM has an inactive level, the fifth transistor T5 can block the supply of the drive current generated in the first transistor T1.

[0082] The sixth transistor T6 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the sixth transistor T6 may receive a second transmit control signal EMB. The first electrode of the sixth transistor T6 may be connected to a second node N2. The second electrode of the sixth transistor T6 may be connected to the anode electrode of the light-emitting element LED.

[0083] The sixth transistor T6 can be turned on or off in response to the second transmit control signal EMB. For example, when the second transmit control signal EMB is active, the sixth transistor T6 can be turned on. In this case, the sixth transistor T6 can supply the drive current generated in the first transistor T1 to the anode electrode of the light-emitting element LED. Conversely, when the second transmit control signal EMB is inactive, the sixth transistor T6 can be turned off. In this case, the sixth transistor T6 can block the supply of the drive current generated in the first transistor T1.

[0084] According to some embodiments, the first electrode of each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 may be a drain electrode, and the second electrode of each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 may be a source electrode. However, the embodiments of this disclosure are not necessarily limited thereto.

[0085] The first capacitor C1 may include a first electrode and a second electrode. The first electrode of the first capacitor C1 may be connected to a first node N1. The second electrode of the first capacitor C1 may be connected to a second node N2. The first capacitor C1 can store the voltage corresponding to the difference between the voltage at the first node N1 and the voltage at the second node N2. Therefore, the first capacitor C1 can be referred to as a storage capacitor.

[0086] The second capacitor C2 may include a first electrode and a second electrode. The first electrode of the second capacitor C2 may receive a drive voltage ELVDD. The second electrode of the second capacitor C2 may be connected to the second node N2. The second capacitor C2 may be a capacitor used to maintain the voltage of the second node N2. Therefore, the second capacitor C2 may be referred to as a holding capacitor.

[0087] A light-emitting element (LED) may include an anode electrode and a cathode electrode. The anode electrode of the LED may be connected to the second electrode of a fourth transistor T4 and the second electrode of a sixth transistor T6. The cathode electrode of the LED may receive a common voltage ELVSS. For example, the common voltage ELVSS may have a voltage level lower than the drive voltage ELVDD.

[0088] Despite Figure 2 The pixel driving circuit portion PC is shown as including six transistors and two capacitors, but embodiments of this disclosure are not necessarily limited thereto.

[0089] Figure 3 It is an illustrative representation of including Figure 1 Circuit diagram of the stage in the first gate driver or the second gate driver.

[0090] refer to Figure 3 The first gate driver GDV1 or the second gate driver GDV2 may include a stage ST. For example, there may be multiple stages ST included in the first gate driver GDV1 or the second gate driver GDV2.

[0091] A stage ST may include a logic circuit section RC and a buffer circuit section BC electrically connected to the logic circuit section RC. The logic circuit section RC can control the buffer circuit section BC, and the buffer circuit section BC can output a drive signal (i.e., the gate signal GS).

[0092] The logic circuit section RC includes a first transistor M1, and the buffer circuit section BC may include a second transistor M2. According to some embodiments, the first transistor M1 and the second transistor M2 may include metal-oxide-semiconductor (MODS). For ease of explanation, in... Figure 3 In the diagram, each of the logic circuit section RC and the buffer circuit section BC is shown as including one transistor, but the logic circuit section RC may include multiple transistors, and the buffer circuit section BC may include at least one transistor.

[0093] The RC logic circuit section can receive various control signals CS1, CS2, and CS3, as well as voltages V1 and V2, and can output a carry signal CS4. The carry signal CS4 can be provided to subsequent stages. The BC buffer circuit section can output the gate signal GS.

[0094] Figure 4 It is along Figure 1 A sectional view taken by line I-I'. Figure 5 It is shown Figure 1 and Figure 4 A magnified plan of the outer area. Figure 6 It is shown Figure 1 and Figure 4 A magnified view of the display area.

[0095] refer to Figures 4 to 6 According to some embodiments of the present disclosure, the display device DD may include a substrate SUB, a first circuit layer CRL1 located on the substrate SUB, a second circuit layer CRL2 located on the first circuit layer CRL1, and a light-emitting element layer located on the second circuit layer CRL2.

[0096] The first circuit layer CRL1 may include a barrier layer BAR, a first lower metal layer LBL1 and a second lower metal layer LBL2, a first buffer layer BUF1, a transistor TR, a first transistor M1, a first gate insulating layer GI1, a first interlayer insulating layer ILD1, a first lower connection pattern LCP1, a second lower connection pattern LCP2 and a third lower connection pattern LCP3, a first gate connection pattern GCP1 and a second gate connection pattern GCP2, and a second interlayer insulating layer ILD2.

[0097] The second circuit layer CRL2 may include a third lower metal layer UBL1 and a fourth lower metal layer UBL2, a second buffer layer BUF2, a second transistor M2, a second gate insulating layer GI2, a first conductive pattern CP1, a third interlayer insulating layer ILD3, a second conductive pattern CP2, a first intermediate connection pattern MCP1 and a second intermediate connection pattern MCP2, a third gate connection pattern GCP3, a first via insulating layer VIA1, a first upper connection pattern UCP1 and a second upper connection pattern UCP2, and a second via insulating layer VIA2.

[0098] The light-emitting element layer may include a pixel defining layer (PDL) and a light-emitting element (LED). The light-emitting element (LED) may include a pixel electrode (PE), a light-emitting layer (EML), and a common electrode (CME).

[0099] The substrate SUB may include a glass substrate, a metal substrate, a plastic substrate, etc. However, the embodiments disclosed herein are not necessarily limited to these. For example, the substrate SUB may include an inorganic layer, an organic layer, or a composite material layer. Furthermore, the substrate SUB may include a flexible substrate.

[0100] The barrier layer (BAR) can be located on the substrate (SUB). The barrier layer (BAR) can be located in the display area (DA) and the peripheral area (PA). The barrier layer (BAR) prevents or reduces the entry of contaminants or impurities from the outside. The barrier layer (BAR) can include inorganic insulating materials, such as silicon dioxide (SiO₂). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. Barrier layers (BARs) can have a single-layer structure or a multi-layer structure in which multiple layers are stacked.

[0101] The first lower metal layer LBL1 and the second lower metal layer LBL2 may be located on the barrier layer BAR. The first lower metal layer LBL1 may be located in the display area DA, and the second lower metal layer LBL2 may be located in the peripheral area PA. The first lower metal layer LBL1 can block light from entering the transistor TR from the outside, and the second lower metal layer LBL2 can block light from entering the first transistor M1 from the outside. For example, the first lower metal layer LBL1 and the second lower metal layer LBL2 may include molybdenum (Mo), molybdenum-containing alloys, titanium (Ti), titanium-containing alloys, etc. These can be used individually or in combination with each other. However, the embodiments of this disclosure are not necessarily limited thereto. Each of the first lower metal layer LBL1 and the second lower metal layer LBL2 may have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0102] The first lower metal layer LBL1 and the second lower metal layer LBL2 can be located in the same layer. That is, the first lower metal layer LBL1 and the second lower metal layer LBL2 can include the same material and can be formed by the same process.

[0103] The first buffer layer BUF1 may be located on the barrier layer BAR. The first buffer layer BUF1 may cover the first lower metal layer LBL1 and the second lower metal layer LBL2. The first buffer layer BUF1 can prevent or reduce the diffusion of contaminants, such as metal atoms or impurities from the substrate SUB, into the transistor TR and the first transistor M1. Furthermore, in the case of surface non-uniformity of the substrate SUB, the first buffer layer BUF1 can relatively improve the surface smoothness of the substrate SUB. For example, the first buffer layer BUF1 may include an inorganic insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination. The first buffer layer BUF1 can have a single-layer structure or a multi-layer structure in which multiple layers are stacked.

[0104] The first lower active pattern LAP1 and the second lower active pattern LAP2 can be located on the first buffer layer BUF1. The first lower active pattern LAP1 can be located in the display area DA, and the second lower active pattern LAP2 can be located in the peripheral area PA. According to some embodiments, the first lower active pattern LAP1 and the second lower active pattern LAP2 can include metal oxide semiconductors. For example, the metal oxide semiconductor can include zinc oxide (e.g., ZnO or ZnO2), gallium oxide (GaO) x ), Tin oxide (SnO) x Indium oxide (InO) x Indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), etc. These can be used individually or in combination with each other. According to some embodiments, the first lower active pattern LAP1 and the second lower active pattern LAP2 may include indium gallium zinc oxide (IGZO).

[0105] The first lower active pattern LAP1 and the second lower active pattern LAP2 can be located in the same layer. That is, the first lower active pattern LAP1 and the second lower active pattern LAP2 can include the same material and can be formed by the same process.

[0106] The first lower active pattern LAP1 may include a first conductive region DR1, a second conductive region DR2, and a first channel region CH1 between the first conductive region DR1 and the second conductive region DR2. The first conductive region DR1 and the second conductive region DR2 may have higher conductivity than the first channel region CH1.

[0107] The second lower active pattern LAP2 may include a third conductive region DR3, a fourth conductive region DR4, and a second channel region CH2 between the third conductive region DR3 and the fourth conductive region DR4. The third conductive region DR3 and the fourth conductive region DR4 may have higher conductivity than the second channel region CH2.

[0108] The first gate insulating layer GI1 may be located on the first lower active pattern LAP1 and the second lower active pattern LAP2. The first gate insulating layer GI1 may be located in the display area DA and the peripheral area PA, respectively, and may be patterned to overlap with the first channel region CH1 and the second channel region CH2 in a planar view. For example, the first gate insulating layer GI1 may include an inorganic insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. The first gate insulating layer GI1 can have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0109] The first lower gate electrode LGE1 and the second lower gate electrode LGE2 can be located on the first gate insulating layer GI1. The first lower gate electrode LGE1 can be located on the first gate insulating layer GI1 in the display area DA, and can overlap with the first channel region CH1 in the plan view. The second lower gate electrode LGE2 can be located on the first gate insulating layer GI1 in the peripheral area PA, and can overlap with the second channel region CH2 in the plan view.

[0110] The first lower gate electrode LGE1 and the second lower gate electrode LGE2 can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. Examples of metals include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), etc. Examples of conductive metal oxides include indium tin oxide, indium zinc oxide, etc. Examples of metal nitrides include aluminum nitride (AlN). x ), Tungsten nitride (WN) x ), Chromium nitride (CrN) xThese can be used individually or in combination with each other. The first lower gate electrode LGE1 and the second lower gate electrode LGE2 can each have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0111] The first lower gate electrode LGE1 and the second lower gate electrode LGE2 can be located in the same layer. That is, the first lower gate electrode LGE1 and the second lower gate electrode LGE2 can include the same material and can be formed by the same process.

[0112] Therefore, a transistor TR including a first lower active pattern LAP1 and a first lower gate electrode LGE1 can be formed in the display area DA, and a first transistor M1 including a second lower active pattern LAP2 and a second lower gate electrode LGE2 can be formed in the peripheral area PA. For example, Figure 4 The transistor TR can correspond to Figure 2 The first transistor T1, and Figure 4 The first transistor M1 can correspond to Figure 3 The first transistor M1.

[0113] The first interlayer insulating layer ILD1 may be located on the first buffer layer BUF1. The first interlayer insulating layer ILD1 may be located within the display area DA and the peripheral area PA. The first interlayer insulating layer ILD1 may cover the first transistor M1 and the transistor TR. For example, the first interlayer insulating layer ILD1 may include an inorganic insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. The first interlayer insulation layer ILD1 can have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0114] The first lower connection pattern LCP1, the second lower connection pattern LCP2, and the third lower connection pattern LCP3, as well as the first gate connection pattern GCP1 and the second gate connection pattern GCP2, can be located on the first interlayer insulating layer ILD1. The first lower connection pattern LCP1, the second lower connection pattern LCP2, and the first gate connection pattern GCP1 can be located in the display area DA, and the third lower connection pattern LCP3 and the second gate connection pattern GCP2 can be located in the peripheral area PA.

[0115] The first lower connection pattern LCP1 can be connected to the second conductive region DR2 of the first lower active pattern LAP1 through a contact hole penetrating the first interlayer insulating layer ILD1, and can also be connected to the first lower metal layer LBL1 through contact holes penetrating the first buffer layer BUF1 and the first interlayer insulating layer ILD1. The second lower connection pattern LCP2 can be connected to the first conductive region DR1 of the first lower active pattern LAP1 through a contact hole penetrating the first interlayer insulating layer ILD1. The first gate connection pattern GCP1 can be connected to the first lower gate electrode LGE1 through a contact hole penetrating the first interlayer insulating layer ILD1.

[0116] Furthermore, the third lower connection pattern LCP3 can be connected to the fourth conductive region DR4 of the second lower active pattern LAP2 through a contact hole penetrating the first interlayer insulating layer ILD1. The second gate connection pattern GCP2 can be connected to the second lower gate electrode LGE2 through a contact hole penetrating the first interlayer insulating layer ILD1, and can also be connected to the second lower metal layer LBL2 through contact holes penetrating the first buffer layer BUF1 and the first interlayer insulating layer ILD1.

[0117] For example, the first lower connection pattern LCP1, the second lower connection pattern LCP2, and the third lower connection pattern LCP3, as well as the first gate connection pattern GCP1 and the second gate connection pattern GCP2, may include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These can be used individually or in combination with each other. The first lower connection pattern LCP1, the second lower connection pattern LCP2, and the third lower connection pattern LCP3, as well as the first gate connection pattern GCP1 and the second gate connection pattern GCP2, may each have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0118] The first lower connection pattern LCP1, the second lower connection pattern LCP2, and the third lower connection pattern LCP3, as well as the first gate connection pattern GCP1 and the second gate connection pattern GCP2, may contain the same material and may be located in the same layer. That is, the first lower connection pattern LCP1, the second lower connection pattern LCP2, and the third lower connection pattern LCP3, as well as the first gate connection pattern GCP1 and the second gate connection pattern GCP2, can be formed by the same process.

[0119] The second interlayer insulating layer ILD2 can be located on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 can be located in the display area DA and the peripheral area PA. The second interlayer insulating layer ILD2 can cover the first lower connection pattern LCP1, the second lower connection pattern LCP2, and the third lower connection pattern LCP3, as well as the first gate connection pattern GCP1 and the second gate connection pattern GCP2. For example, the second interlayer insulating layer ILD2 can include an inorganic insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. The second interlayer insulation layer (ILD2) can have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0120] The first circuit layer CRL1 may also include multiple switching transistors and storage capacitors located in the display area DA. The switching transistors may include... Figure 2 The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The storage capacitor can correspond to... Figure 2 The first capacitor C1. The storage capacitor may be configured with a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially along the third direction D3 on the substrate SUB. In this case, the first conductive layer may be located in the same layer as the first lower metal layer LBL1 and the second lower metal layer LBL2, the second conductive layer may be located in the same layer as the first lower gate electrode LGE1 and the second lower gate electrode LGE2, and the third conductive layer may be located in the same layer as the first lower connection pattern LCP1, the second lower connection pattern LCP2, the third lower connection pattern LCP3, the first gate connection pattern GCP1, and the second gate connection pattern GCP2.

[0121] The third lower metal layer UBL1 and the fourth lower metal layer UBL2 can be located on the second interlayer insulating layer ILD2. The third lower metal layer UBL1 can be located in the display area DA, and the fourth lower metal layer UBL2 can be located in the peripheral area PA. The fourth lower metal layer UBL2 can block light from entering the second transistor M2 from the outside. For example, the third lower metal layer UBL1 and the fourth lower metal layer UBL2 can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These can be used individually or in combination with each other. The third lower metal layer UBL1 and the fourth lower metal layer UBL2 can each have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0122] The third lower metal layer UBL1 and the fourth lower metal layer UBL2 can be located in the same layer. That is, the third lower metal layer UBL1 and the fourth lower metal layer UBL2 can include the same material and can be formed by the same process.

[0123] The second buffer layer BUF2 can be located on the second interlayer insulating layer ILD2. The second buffer layer BUF2 can be located in the display area DA and the peripheral area PA. The second buffer layer BUF2 can prevent or reduce the diffusion of contaminants such as metal atoms or impurities from the substrate SUB into the capacitor CAP and the second transistor M2. For example, the second buffer layer BUF2 may include an inorganic insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. The second buffer layer BUF2 can have a single-layer structure or a multi-layer structure in which multiple layers are stacked.

[0124] The upper active pattern UAP can be located on the second buffer layer BUF2 in the peripheral region PA. According to some embodiments, the upper active pattern UAP may include a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)).

[0125] The upper active pattern UAP may include a fifth conductive region DR5, a sixth conductive region DR6, and a third channel region CH3 between the fifth conductive region DR5 and the sixth conductive region DR6. The fifth conductive region DR5 and the sixth conductive region DR6 may have higher conductivity than the third channel region CH3.

[0126] The second gate insulating layer GI2 can be located on the second buffer layer BUF2. The second gate insulating layer GI2 can be located in both the display area DA and the peripheral area PA. Specifically, the second gate insulating layer GI2 can be arranged in a patterned form in the display area DA, and can also be arranged in a patterned form in the peripheral area PA to overlap with the third channel region CH3 in a planar view. For example, the second gate insulating layer GI2 may include an inorganic insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. The second gate insulating layer GI2 can have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0127] The first conductive pattern CP1 and the upper gate electrode UGE can be located on the second gate insulating layer GI2. In the plan view, the first conductive pattern CP1 can overlap with the third lower metal layer UBL1, and in the plan view, the upper gate electrode UGE can overlap with the third channel region CH3.

[0128] For example, the first conductive pattern CP1 and the upper gate electrode UGE may include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These can be used individually or in combination. Each of the first conductive pattern CP1 and the upper gate electrode UGE may have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0129] The first conductive pattern CP1 and the upper gate electrode UGE can be located in the same layer. That is, the first conductive pattern CP1 and the upper gate electrode UGE can include the same material and can be formed by the same process.

[0130] Therefore, a second transistor M2, including an upper active pattern UAP and an upper gate electrode UGE, can be formed in the peripheral region PA.

[0131] The third interlayer insulating layer ILD3 can be located on the second buffer layer BUF2. The third interlayer insulating layer ILD3 can be located within the display area DA and the peripheral area PA. The third interlayer insulating layer ILD3 can cover the second transistor M2 and the first conductive pattern CP1. For example, the third interlayer insulating layer ILD3 can include an inorganic insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. The third interlayer insulating layer ILD3 can have a single-layer structure or a multilayer structure in which multiple layers are stacked. In this specification, the third interlayer insulating layer ILD3 can be referred to as an inorganic insulating layer.

[0132] According to some embodiments, a plurality of vias TH can be defined in the third interlayer insulating layer ILD3, adjacent to and spaced apart from the second transistor M2. Through the plurality of vias TH, hydrogen generated in the insulating layer included in the first circuit layer CRL1 and absorbed into the lower active pattern (e.g., the first lower active pattern LAP1 and / or the second lower active pattern LAP2) and acting as charge carriers can diffuse (or release) to the outside (i.e., diffuse (or release) into the second circuit layer CRL2). In other words, the plurality of vias TH can be used as degassing pores for releasing hydrogen that affects the characteristics of the lower elements (e.g., the first transistor M1 and / or the transistor TR) included in the first circuit layer CRL1.

[0133] According to some embodiments, a plurality of vias TH may be located in the peripheral region PA and adjacent to the second transistor M2. However, the embodiments of this disclosure are not necessarily limited to this, and the plurality of vias TH may include a plurality of first vias adjacent to and spaced apart from the second transistor M2 in the peripheral region PA, and a plurality of second vias spaced apart from each other in the display region DA.

[0134] According to some implementations, at least a portion of the upper surface of the second buffer layer BUF2 can be exposed because multiple through-holes TH are formed by penetrating the third interlayer insulating layer ILD3.

[0135] For example, in a planar diagram, multiple vias TH may not overlap with the first transistor M1 and the second transistor M2.

[0136] Multiple vias TH can be spaced apart from each other with a constant pitch PT along a first direction D1 and a second direction D2. According to some embodiments, the pitch PT between two adjacent vias TH can be in the range of 10 micrometers (μm) to 15 micrometers (μm) (or about 10 micrometers (μm) to about 15 micrometers (μm)). When the pitch PT is less than 10 μm or greater than 15 μm (or less than about 10 μm or greater than about 15 μm), the characteristics of the lower components included in the first circuit layer CRL1 may deteriorate.

[0137] According to some embodiments, in the peripheral region PA, at least two vias TH can be located in a region adjacent to the upper active pattern UAP. For example, in a plan view, the shortest distance IT between each of the plurality of vias TH and the second lower gate electrode LGE2 can be 1.1 μm (or about 1.1 μm). For example, the size of each of the plurality of vias TH can be 1.8 μm × 1.8 μm (or about 1.8 μm × about 1.8 μm). The above-mentioned values ​​of the shortest distance IT and the above-mentioned values ​​of the size of each of the plurality of vias TH can be optimal values ​​to prevent or reduce the degradation of the characteristics of the lower component. However, the embodiments of this disclosure are not necessarily limited thereto.

[0138] The first intermediate connection pattern MCP1, the second intermediate connection pattern MCP2, the third gate connection pattern GCP3, and the second conductive pattern CP2 can be located on the third interlayer insulating layer ILD3. The first intermediate connection pattern MCP1 and the second conductive pattern CP2 can be located in the display area DA, and the second intermediate connection pattern MCP2 and the third gate connection pattern GCP3 can be located in the peripheral area PA.

[0139] The first intermediate connection pattern MCP1 can be connected to the first lower connection pattern LCP1 through contact holes penetrating the second interlayer insulating layer ILD2, the second buffer layer BUF2, and the third interlayer insulating layer ILD3. The second intermediate connection pattern MCP2 can be connected to the third lower connection pattern LCP3 through contact holes penetrating the second interlayer insulating layer ILD2, the second buffer layer BUF2, and the third interlayer insulating layer ILD3, and can also be connected to the sixth conductive region DR6 of the upper active pattern UAP through contact holes penetrating the third interlayer insulating layer ILD3. Furthermore, the third gate connection pattern GCP3 can be connected to the fourth lower metal layer UBL2 through contact holes penetrating the second buffer layer BUF2 and the third interlayer insulating layer ILD3, and can also be connected to the upper gate electrode UGE through contact holes penetrating the third interlayer insulating layer ILD3.

[0140] In the plan view, the second conductive pattern CP2 can overlap with the first conductive pattern CP1. Therefore, the second conductive pattern CP2 and the first conductive pattern CP1 can form a first sub-capacitor, and the first conductive pattern CP1 and the third lower metal layer UBL1 can form a second sub-capacitor. Furthermore, the third lower metal layer UBL1 and the third conductive pattern located beneath it can form a third sub-capacitor. The third conductive pattern can be electrically connected to the first conductive pattern CP1, and the third lower metal layer UBL1 can be electrically connected to the second conductive pattern CP2. In this case, the third conductive pattern can be located in the same layer as the first lower connecting pattern LCP1, the second lower connecting pattern LCP2, and the third lower connecting pattern LCP3. Therefore, the first sub-capacitor, the second sub-capacitor, and the third sub-capacitor can form a capacitor CAP.

[0141] For example, the first intermediate connection pattern MCP1, the second intermediate connection pattern MCP2, the third gate connection pattern GCP3, and the second conductive pattern CP2 may include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These can be used individually or in combination with each other. Each of the first intermediate connection pattern MCP1, the second intermediate connection pattern MCP2, the third gate connection pattern GCP3, and the second conductive pattern CP2 may have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0142] The first intermediate connection pattern MCP1, the second intermediate connection pattern MCP2, the third gate connection pattern GCP3, and the second conductive pattern CP2 can all be made of the same material and can be located in the same layer. That is, the first intermediate connection pattern MCP1, the second intermediate connection pattern MCP2, the third gate connection pattern GCP3, and the second conductive pattern CP2 can be formed by the same process.

[0143] The first via insulating layer VIA1 may be located on the third interlayer insulating layer ILD3. The first via insulating layer VIA1 may be located in the display area DA and the peripheral area PA. The first via insulating layer VIA1 may have a substantially flat upper surface to fully cover the first intermediate connection pattern MCP1 and the second intermediate connection pattern MCP2, the third gate connection pattern GCP3, and the second conductive pattern CP2. For example, the first via insulating layer VIA1 may include organic insulating materials such as photoresist, polyacrylic resin, polyimide resin, polyamide resin, silicone resin, acrylic resin, epoxy resin, etc. These may be used individually or in combination with each other. The first via insulating layer VIA1 may have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0144] According to some embodiments, the first via insulating layer VIA1 can fill the interior of the plurality of vias TH. That is, insulating material can fill the interior of the plurality of vias TH. In other words, conductive material may not fill the interior of the plurality of vias TH.

[0145] The first upper connection pattern UCP1 and the second upper connection pattern UCP2 can be located on the first via insulating layer VIA1. The first upper connection pattern UCP1 can be located in the display area DA, and the second upper connection pattern UCP2 can be located in the peripheral area PA.

[0146] The first upper connection pattern UCP1 can be connected to the first intermediate connection pattern MCP1 through a contact hole penetrating the first through-hole insulating layer VIA1. Furthermore, the second upper connection pattern UCP2 can be connected to the second intermediate connection pattern MCP2 through a contact hole penetrating the first through-hole insulating layer VIA1.

[0147] For example, the first upper connection pattern UCP1 and the second upper connection pattern UCP2 may include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These can be used individually or in combination with each other. Each of the first upper connection pattern UCP1 and the second upper connection pattern UCP2 may have a single-layer structure or a multi-layer structure in which multiple layers are stacked.

[0148] The first upper connecting pattern UCP1 and the second upper connecting pattern UCP2 may contain the same material and may be located in the same layer. That is, the first upper connecting pattern UCP1 and the second upper connecting pattern UCP2 may be formed by the same process.

[0149] The second via insulating layer VIA2 may be located on the first via insulating layer VIA1. The second via insulating layer VIA2 may be located in the display area DA and the peripheral area PA. The second via insulating layer VIA2 may have a substantially flat upper surface to fully cover the first upper connection pattern UCP1 and the second upper connection pattern UCP2. For example, the second via insulating layer VIA2 may include organic insulating materials such as photoresist, polyacrylic resin, polyimide resin, polyamide resin, silicone resin, acrylic resin, epoxy resin, etc. These may be used alone or in combination with each other. The second via insulating layer VIA2 may have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0150] The pixel electrode PE can be located on the second via insulating layer VIA2 within the display area DA. The pixel electrode PE can be connected to the first upper connection pattern UCP1 through contact holes penetrating the second via insulating layer VIA2. The pixel electrode PE can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. For example, the pixel electrode PE can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These can be used individually or in combination. The pixel electrode PE can be used as an anode. The pixel electrode PE can have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0151] The pixel defining layer (PDL) may be located on the second via insulating layer (VIA2) within the display area (DA). A pixel opening may be defined in the PDL, exposing at least a portion of the upper surface of the pixel electrode (PE). The PDL may comprise an inorganic or organic insulating material. For example, the PDL may comprise organic insulating materials such as photoresist, polyacrylic resin, polyimide resin, polyamide resin, silicone resin, acrylic resin, epoxy resin, etc. These may be used individually or in combination with each other. Alternatively, the PDL may comprise an organic or inorganic insulating material containing a light-blocking material (such as a black pigment or black dye).

[0152] The light-emitting layer (EML) can be located on the pixel electrode (PE). Specifically, the EML can be located within the pixel opening of the pixel limiting layer (PDL). For example, the EML can include an organic or inorganic light-emitting material that generates a preset light. Hole injection layers, hole transport layers, electron injection layers, electron transport layers, etc., can be additionally arranged between the EMLs.

[0153] The common electrode CME can be located on the second via insulating layer VIA2, pixel limiting layer PDL, and light-emitting layer EML. The common electrode CME can be located entirely within the display area DA, and can also be located within at least a portion of the peripheral area PA.

[0154] The common electrode CME can be a transmitting electrode, a semi-transmitting electrode, or a reflecting electrode. For example, the common electrode CME can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These can be used individually or in combination. The common electrode CME can be used as a cathode. The common electrode CME can have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0155] Therefore, a light-emitting element (LED) including a pixel electrode (PE), a light-emitting layer (EML), and a common electrode (CME) can be formed in the display area (DA).

[0156] The encapsulation layer may be additionally located on the common electrode CME. The encapsulation layer may be located in the display area DA and the peripheral area PA, and may include at least one inorganic layer and at least one organic layer. The inorganic layer of the encapsulation layer protects the LED from external moisture, and the organic layer of the encapsulation layer prevents or reduces damage to the LED due to contaminants or impurities introduced during the manufacturing process.

[0157] As described above, the first circuit layer CRL1 may include a first transistor M1 located in the peripheral region PA and comprising a metal-oxide-semiconductor, and the second circuit layer CRL2 located on the first circuit layer CRL1 may include a second transistor M2 located in the peripheral region PA and comprising a metal-oxide-semiconductor. That is, in the peripheral region PA, the first transistor M1 and the second transistor M2 may have a stacked structure along the thickness direction (e.g., the third direction D3). Therefore, the dead zone of the display device DD can be relatively reduced.

[0158] During the manufacturing process of the display device DD, hydrogen generated in the insulating layer included in the first circuit layer CRL1 can be absorbed into the lower active patterns (e.g., the first lower active pattern LAP1 and / or the second lower active pattern LAP2) and can act as charge carriers. On the other hand, in the peripheral region PA, in the stacked structure where the first transistor M1 and the second transistor M2 are stacked along the thickness direction, the amount of hydrogen absorbed by the lower active patterns may be relatively excessive. In this case, the characteristics of the lower elements included in the first circuit layer CRL1 (e.g., the first transistor M1 and / or the transistor TR) may deteriorate, and the variation of the lower elements may increase.

[0159] In a display device DD according to some embodiments of the present disclosure, in the peripheral region PA, in a structure in which a first transistor M1 comprising a metal-oxide-semiconductor in a first circuit layer CRL1 and a second transistor M2 comprising a metal-oxide-semiconductor in a second circuit layer CRL2 are stacked along the thickness direction, a plurality of vias TH spaced apart from each other can be defined in the inorganic insulating layer (i.e., the third interlayer insulating layer ILD3) included in the second circuit layer CRL2. Therefore, through the plurality of vias TH, hydrogen generated in the insulating layer included in the first circuit layer CRL1 and absorbed into the lower active pattern of the first transistor M1, acting as charge carriers, can diffuse (or be released) to the outside (i.e., diffuse (or be released) to the second circuit layer CRL2). In this case, the characteristics of the lower elements included in the first circuit layer CRL1 may not deteriorate, and the variation of the lower elements can be relatively reduced.

[0160] Figures 7 to 20 It is used to explain the manufacturing process. Figure 4 A cross-sectional view of a method for displaying a device. In the following text, details related to the reference are omitted or simplified. Figure 4 Any content that overlaps with the content of the described display device DD.

[0161] refer to Figure 7 A barrier layer (BAR) can be formed on the substrate (SUB) in the display area (DA) and the peripheral area (PA). For example, the barrier layer (BAR) may include an inorganic insulating material.

[0162] A first lower metal layer LBL1 and a second lower metal layer LBL2 can be formed on the barrier layer BAR. The first lower metal layer LBL1 can be formed in the display area DA, and the second lower metal layer LBL2 can be formed in the peripheral area PA.

[0163] refer to Figure 8 A first buffer layer BUF1 can be formed on the barrier layer BAR in the display area DA and the peripheral area PA. The first buffer layer BUF1 can be formed to cover a first lower metal layer LBL1 and a second lower metal layer LBL2. For example, the first buffer layer BUF1 may include an inorganic insulating material.

[0164] A first lower active pattern LAP1' and a second lower active pattern LAP2' can be formed on the first buffer layer BUF1. The first lower active pattern LAP1' can be formed in the display area DA, and the second lower active pattern LAP2' can be formed in the peripheral area PA. According to some embodiments, the first lower active pattern LAP1' and the second lower active pattern LAP2' can include metal-oxide-semiconductor (MODS).

[0165] refer to Figures 9 to 11A preliminary first gate insulating layer GI1' can be formed on the first buffer layer BUF1 in the display area DA and the peripheral area PA. The preliminary first gate insulating layer GI1' can be formed to cover the first lower active pattern LAP1' and the second lower active pattern LAP2'. For example, the preliminary first gate insulating layer GI1' may include an inorganic insulating material.

[0166] A gate electrode layer LGE' can be formed on the initial first gate insulating layer GI1' in the display area DA and the peripheral area PA.

[0167] A first photosensitive organic pattern and a second photosensitive organic pattern can be formed on the gate electrode layer LGE'. The first photosensitive organic pattern may correspond to the region where the first lower gate electrode LGE1 will be formed, and the second photosensitive organic pattern may correspond to the region where the second lower gate electrode LGE2 will be formed. For example, the first and second photosensitive organic patterns may include positive or negative photoresist.

[0168] The first etching process allows the removal of a portion of the gate electrode layer LGE' using a first and a second photosensitive organic pattern as a mask. Specifically, the first etching process removes portions of the gate electrode layer LGE' that do not overlap with the first and second photosensitive organic patterns. Therefore, a first lower gate electrode LGE1 can be formed in the region corresponding to the first photosensitive organic pattern, and a second lower gate electrode LGE2 can be formed in the region corresponding to the second photosensitive organic pattern.

[0169] After forming the first lower gate electrode LGE1 and the second lower gate electrode LGE2, a portion of the preliminary first gate insulating layer GI1' can be removed using a second etching process, employing the first and second photosensitive organic patterns as masks. Specifically, the second etching process removes portions of the preliminary first gate insulating layer GI1' that do not overlap with the first and second photosensitive organic patterns. Therefore, the first gate insulating layer GI1 can be formed in a patterned form in regions corresponding to each of the first and second photosensitive organic patterns.

[0170] During the removal of a portion of the preliminary first gate insulating layer GI1' by a second etching process, hydrogen contained in the preliminary first gate insulating layer GI1' can flow into the first lower active pattern LAP1' and the second lower active pattern LAP2'. The portion of the first lower active pattern LAP1' with introduced hydrogen has an increased carrier concentration due to the introduced hydrogen, thereby becoming conductive, and thus can become the first conductive region DR1 and the second conductive region DR2. Therefore, a first lower active pattern LAP1 comprising the first conductive region DR1, the second conductive region DR2, and the first channel region CH1 can be formed.

[0171] Similarly, the hydrogen-introduced portion of the second lower active pattern LAP2' has an increased carrier concentration due to the introduced hydrogen, thus becoming conductive, and therefore can become the third conductive region DR3 and the fourth conductive region DR4. Therefore, a second lower active pattern LAP2 comprising the third conductive region DR3, the fourth conductive region DR4, and the second channel region CH2 can be formed.

[0172] Therefore, a transistor TR including a first lower active pattern LAP1 and a first lower gate electrode LGE1 can be formed in the display area DA, and a first transistor M1 including a second lower active pattern LAP2 and a second lower gate electrode LGE2 can be formed in the peripheral area PA.

[0173] refer to Figure 12 A first interlayer insulating layer ILD1 can be formed on the first buffer layer BUF1 in the display area DA and the peripheral area PA. The first interlayer insulating layer ILD1 can be formed to cover the transistor TR and the first transistor M1. For example, the first interlayer insulating layer ILD1 may include an inorganic insulating material.

[0174] By penetrating the first interlayer insulating layer ILD1, a first contact hole exposing the first conductive region DR1, a second contact hole exposing the second conductive region DR2, a third contact hole exposing the fourth conductive region DR4, a fourth contact hole exposing the first lower gate electrode LGE1, and a fifth contact hole exposing the second lower gate electrode LGE2 can be formed. Simultaneously, by penetrating the first buffer layer BUF1 and the first interlayer insulating layer ILD1, a sixth contact hole exposing the first lower metal layer LBL1 and a seventh contact hole exposing the second lower metal layer LBL2 can be formed.

[0175] Next, a conductive layer can be completely formed on the first interlayer insulating layer ILD1 to fill the interiors of the first contact hole, second contact hole, third contact hole, fourth contact hole, fifth contact hole, sixth contact hole, and seventh contact hole. By etching the conductive layer, a first lower connection pattern LCP1 can be formed, which is connected to the second conductive region DR2 and the first lower metal layer LBL1 through the second contact hole and the sixth contact hole, a second lower connection pattern LCP2 is connected to the first conductive region DR1 through the first contact hole, a third lower connection pattern LCP3 is connected to the fourth conductive region DR4 through the third contact hole, a first gate connection pattern GCP1 is connected to the first lower gate electrode LGE1 through the fourth contact hole, and a second gate connection pattern GCP2 is connected to the second lower gate electrode LGE2 and the second lower metal layer LBL2 through the fifth contact hole and the seventh contact hole, respectively.

[0176] A second interlayer insulating layer ILD2 can be formed on the first interlayer insulating layer ILD1 in the display area DA and the peripheral area PA. The second interlayer insulating layer ILD2 can be formed to cover the first lower connection pattern LCP1, the second lower connection pattern LCP2, the third lower connection pattern LCP3, the first gate connection pattern GCP1, and the second gate connection pattern GCP2. For example, the second interlayer insulating layer ILD2 may include an inorganic insulating material.

[0177] Therefore, a first circuit layer CRL1 can be formed, including a barrier layer BAR, a first lower metal layer LBL1 and a second lower metal layer LBL2, a first buffer layer BUF1, a transistor TR, a first transistor M1, a first gate insulating layer GI1, a first interlayer insulating layer ILD1, a first lower connection pattern LCP1, a second lower connection pattern LCP2 and a third lower connection pattern LCP3, a first gate connection pattern GCP1 and a second gate connection pattern GCP2, and a second interlayer insulating layer ILD2.

[0178] refer to Figure 13 A third lower metal layer UBL1 and a fourth lower metal layer UBL2 can be formed on the second interlayer insulating layer ILD2. The third lower metal layer UBL1 can be formed in the display area DA, and the fourth lower metal layer UBL2 can be formed in the peripheral area PA.

[0179] A second buffer layer BUF2 can be formed on the second interlayer insulating layer ILD2 in the display area DA and the peripheral area PA. The second buffer layer BUF2 can be formed to cover the third lower metal layer UBL1 and the fourth lower metal layer UBL2. For example, the second buffer layer BUF2 may include an inorganic insulating material.

[0180] refer to Figure 14 and Figure 15 An upper active pattern UAP' can be formed in the peripheral region PA on the second buffer layer BUF2. According to some embodiments, the upper active pattern UAP' may include a metal-oxide-semiconductor.

[0181] Using a photosensitive organic pattern as a mask, an upper gate electrode UGE that overlaps with the upper active pattern UAP in the planar view and a first conductive pattern CP1 that overlaps with the third lower metal layer UBL1 in the planar view can be formed. Therefore, the first conductive pattern CP1 can form a sub-capacitor of capacitor CAP together with the third lower metal layer UBL1.

[0182] Next, using a photosensitive organic pattern as a mask, a second gate insulating layer GI2 can be formed in a patterned form under each of the upper gate electrode UGE and the first conductive pattern CP1.

[0183] During the formation of the second gate insulating layer GI2, hydrogen contained in the second gate insulating layer GI2 can flow into the upper active pattern UAP'. The portion of the upper active pattern UAP' with introduced hydrogen has an increased carrier concentration due to the introduced hydrogen, thus becoming conductive, and therefore can become the fifth conductive region DR5 and the sixth conductive region DR6. Therefore, an upper active pattern UAP including the fifth conductive region DR5, the sixth conductive region DR6, and the third channel region CH3 can be formed.

[0184] Therefore, a second transistor M2, including an upper active pattern UAP and an upper gate electrode UGE, can be formed in the peripheral region PA.

[0185] refer to Figure 16 A third interlayer insulating layer (ILD3) can be formed on the second buffer layer (BUF2) in the display area (DA) and the peripheral area (PA). The third interlayer insulating layer (ILD3) can be formed to cover the second transistor (M2) and the first conductive pattern (CP1). For example, the third interlayer insulating layer (ILD3) can include an inorganic insulating material.

[0186] refer to Figure 17 Through a third etching process, by penetrating the second interlayer insulating layer ILD2, the second buffer layer BUF2, and the third interlayer insulating layer ILD3, a first contact hole CNT1 exposing the first lower connection pattern LCP1 and a third contact hole CNT3 exposing the third lower connection pattern LCP3 can be formed. Furthermore, through the third etching process, by penetrating the second buffer layer BUF2 and the third interlayer insulating layer ILD3, a second contact hole CNT2 exposing the fourth lower metal layer UBL2 can be formed. In other words, the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 can be formed simultaneously using the same process.

[0187] refer to Figure 18 Through a fourth etching process, by penetrating the third interlayer insulating layer ILD3, a fourth contact hole CNT4 exposing the upper gate electrode UGE and a fifth contact hole CNT5 exposing the sixth conductive region DR6 can be formed. According to some embodiments, through the fourth etching process, multiple vias TH exposing the second buffer layer BUF2 can be formed by penetrating the third interlayer insulating layer ILD3. That is, multiple vias TH, the fourth contact hole CNT4, and the fifth contact hole CNT5 can be formed simultaneously using the same process.

[0188] refer to Figure 19A conductive layer can be completely formed on the third interlayer insulating layer ILD3. By etching the conductive layer, a first intermediate connection pattern MCP1 can be formed, connecting to the first lower connection pattern LCP1 via the first contact hole CNT1; a third gate connection pattern GCP3 can be formed, connecting to the fourth lower metal layer UBL2 and the upper gate electrode UGE via the second contact hole CNT2 and the fourth contact hole CNT4 respectively; and a second intermediate connection pattern MCP2 can be formed, connecting to the third lower connection pattern LCP3 and the sixth conductive region DR6 via the third contact hole CNT3 and the fifth contact hole CNT5 respectively. Furthermore, by etching the conductive layer, a second conductive pattern CP2 can be formed that overlaps with the first conductive pattern CP1 in the planar view. That is, the second conductive pattern CP2, the first intermediate connection pattern MCP1, the second intermediate connection pattern MCP2, and the third gate connection pattern GCP3 can be formed simultaneously using the same process.

[0189] Therefore, the second conductive pattern CP2 can be combined with the first conductive pattern CP1 to form a sub-capacitor of capacitor CAP.

[0190] refer to Figure 20 A first via insulating layer VIA1 can be formed on the third interlayer insulating layer ILD3 in the display area DA and the peripheral area PA. The first via insulating layer VIA1 can fully cover the first intermediate connection pattern MCP1 and the second intermediate connection pattern MCP2, the third gate connection pattern GCP3 and the second conductive pattern CP2. For example, the first via insulating layer VIA1 can include an organic insulating material.

[0191] A first contact hole exposing a first intermediate connection pattern MCP1 and a second contact hole exposing a second intermediate connection pattern MCP2 can be formed by penetrating the first via insulating layer VIA1. Next, a conductive layer can be completely formed on the first via insulating layer VIA1 to fill the first and second contact holes. By etching the conductive layer, a first upper connection pattern UCP1 connected to the first intermediate connection pattern MCP1 through the first contact hole and a second upper connection pattern UCP2 connected to the second intermediate connection pattern MCP2 through the second contact hole can be formed.

[0192] A second via insulating layer VIA2 can be formed on the first via insulating layer VIA1 in the display area DA and the peripheral area PA. The second via insulating layer VIA2 can be formed to fully cover the first upper connection pattern UCP1 and the second upper connection pattern UCP2. For example, the second via insulating layer VIA2 may include an organic insulating material.

[0193] Therefore, a second circuit layer CRL2 can be formed on the first circuit layer CRL1. The second circuit layer CRL2 includes a third lower metal layer UBL1 and a fourth lower metal layer UBL2, a second buffer layer BUF2, a second transistor M2, a second gate insulating layer GI2, a first conductive pattern CP1, a third interlayer insulating layer ILD3, a second conductive pattern CP2, a first intermediate connection pattern MCP1 and a second intermediate connection pattern MCP2, a third gate connection pattern GCP3, a first via insulating layer VIA1, a first upper connection pattern UCP1 and a second upper connection pattern UCP2, and a second via insulating layer VIA2.

[0194] Return to reference Figure 4 A pixel electrode PE can be formed in the display area DA on the second via insulating layer VIA2. The pixel electrode PE can be connected to the first upper connection pattern UCP1 through a contact hole penetrating the second via insulating layer VIA2.

[0195] A pixel defining layer (PDL) can be formed in the display area DA on the second via insulating layer VIA2. A pixel opening can be defined in the PDL, exposing at least a portion of the upper surface of the pixel electrode PE. For example, the PDL can comprise an inorganic or organic insulating material.

[0196] A light-emitting layer (EML) can be formed on the pixel electrode (PE). Specifically, the EML can be formed within the pixel opening of the pixel defining layer (PDL). A common electrode (CME) can be formed on the second via insulating layer (VIA2), the pixel defining layer (PDL), and the EML. Therefore, a light-emitting element (LED) including the pixel electrode (PE), the EML, and the common electrode (CME) can be formed in the display area (DA).

[0197] Therefore, it is possible to manufacture Figure 4 The display device DD shown is shown.

[0198] Figure 21 This is a graph used to explain the variation of the threshold voltage of the upper element in the comparative examples and embodiments according to the spacing between the vias. Figure 22 This is a graph used to explain the variation of the threshold voltage of the lower element with respect to the spacing between vias in the comparative examples and embodiments. Here, the upper element refers to... Figure 4 The second transistor M2, and the lower component refers to Figure 4 The first transistor M1.

[0199] refer to Figure 4 , Figure 21 and Figure 22In Comparative Example 1, no vias TH are formed in the third interlayer insulating layer ILD3. In Comparative Example 2, vias TH are formed in the third interlayer insulating layer ILD3, spaced apart by a spacing of 5 micrometers (μm) (or approximately 5 micrometers (μm)). In Comparative Example 3, vias TH are formed in the third interlayer insulating layer ILD3, spaced apart by a spacing of 20 micrometers (μm) (or approximately 20 micrometers (μm)). In Embodiment 1, vias TH are formed in the third interlayer insulating layer ILD3, spaced apart by a spacing of 10 micrometers (μm) (or approximately 10 micrometers (μm)). In Embodiment 2, vias TH are formed in the third interlayer insulating layer ILD3, spaced apart by a spacing of 15 micrometers (μm) (or approximately 15 micrometers (μm)).

[0200] Therefore, as Figure 21 As shown, it can be confirmed that the threshold voltage Vth of the upper element is substantially the same or similar in Embodiment 1 and Embodiment 2, as well as Comparative Examples 1, 2, and 3. In this way, it can be confirmed that even if a via TH is formed in the third interlayer insulating layer ILD3, it will not affect the characteristics of the upper element.

[0201] Therefore, as Figure 22 As shown, it can be confirmed that the threshold voltage Vth of the lower element in Embodiments 1 and 2 is greater than the threshold voltage Vth of the lower element in Comparative Examples 1, 2, and 3. In this way, when vias TH are formed in the third interlayer insulating layer ILD3 as in Embodiments 1 and 2, spaced apart by each other with a pitch PT of 10 micrometers (μm) or greater and 15 micrometers (μm) or less (or about 10 micrometers (μm) or greater and about 15 micrometers (μm) or less), it can be confirmed that the threshold voltage Vth of the lower element has a positive shift compared to Comparative Examples 1, 2, and 3. That is, it can be confirmed that the characteristics of the lower element do not deteriorate when Embodiments 1 and 2 are satisfied.

[0202] Figure 23 This is a graph used to explain the variation of the drain-source current in the comparative example with the gate-source voltage of the underlying element. Figure 24 This is a graph used to explain the variation of the drain-source current with respect to the gate-source voltage of the underlying element according to some embodiments. Here, the underlying element refers to... Figure 4 The first transistor M1. In Figure 23 and Figure 24 middle, I DS Represents the drain-source current, and V GS This represents the gate-source voltage.

[0203] Figure 23A comparative example is shown in which no via TH is formed in the third interlayer insulating layer ILD3. Figure 23 The multiple lines shown in the figure correspond to any selected lower element among the lower elements located in the outer region PA.

[0204] Figure 24 An embodiment is shown in which vias TH are formed in the third interlayer insulating layer ILD3, spaced apart from each other by a pitch PT of 10 micrometers (μm) to 15 micrometers (μm) (or about 10 micrometers (μm) to about 15 micrometers (μm)). Figure 24 The multiple lines shown in the figure correspond to any selected lower element among the lower elements located in the outer region PA.

[0205] Therefore, it can be confirmed that in the comparative example, the threshold voltage Vth of the lower element is excessively negatively offset. Furthermore, it can be confirmed that, compared to the comparative example, the threshold voltage Vth of the lower element in the implementation is relatively positively offset. In this way, it can be confirmed that the characteristics of the lower element will not deteriorate when the implementation is satisfied.

[0206] Figure 25 This is a block diagram illustrating an electronic device according to some embodiments of the present disclosure.

[0207] refer to Figure 25 The electronic device 10 according to some embodiments of the present disclosure may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0208] Display devices according to some embodiments of the present disclosure (e.g., Figure 1 The display device (DD) can be applied to various electronic devices 10. The electronic device 10 may include a display device, and in addition to the display device, it may also include modules or devices with other additional functions.

[0209] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0210] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the provided signals to output image information through the display screen.

[0211] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0212] At least one of the components of the electronic device 10 described above may be included in the display device according to the above embodiment. Furthermore, some of the modules functionally included in a single module may be included in the display device, while other components may be disposed separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be disposed within the electronic device 10 as other devices besides the display device.

[0213] Figure 26 This is a schematic diagram illustrating an electronic device according to various embodiments.

[0214] refer to Figure 25 and Figure 26 The various electronic devices 10 that apply display devices according to some embodiments may include not only image display electronic devices such as smartphones 10_1a, tablet computers 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices that include display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, and vehicle electronic devices 10_3 that include display modules such as CID (Central Information Display) and interior mirror displays located in the dashboard, center instrument panel, or instrument cluster of a vehicle.

[0215] As described above, while some aspects of this disclosure have been explained with reference to some embodiments, those skilled in the art will understand that various modifications and changes may be made thereto without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents.

[0216] The aspects of some embodiments of this disclosure can be applied to various electronic devices that can be equipped with a display device. For example, this disclosure can be applied to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet computers, vehicle navigation systems, televisions, computer monitors, and laptop computers.

Claims

1. A display device, comprising: The substrate includes a display area and a peripheral area surrounding at least a portion of the display area; Multiple sub-pixels are located on the substrate in the display area. A first transistor with a gate driver is located on the substrate in the peripheral region; The second transistor of the gate driver is located on the first transistor in the peripheral region; as well as An inorganic insulating layer covers the second transistor and defines a plurality of vias adjacent to and spaced apart from the second transistor.

2. The display device according to claim 1, wherein, The multiple through holes are filled with insulating material.

3. The display device according to claim 1, further comprising: The via insulating layer, on the inorganic insulating layer, fills the interior of the plurality of vias and includes an organic material.

4. The display device according to claim 1, wherein, The first transistor and the second transistor comprise metal-oxide-semiconductor.

5. The display device according to claim 1, wherein, The second transistor includes: The upper active pattern includes a metal-oxide-semiconductor; and The upper gate electrode overlaps with the channel region of the upper active pattern in the plan view.

6. The display device according to claim 5, further comprising: The intermediate connecting pattern is connected to the conductive area of ​​the upper active pattern in the peripheral region through contact holes that penetrate the inorganic insulating layer.

7. The display device according to claim 1, further comprising: A first interlayer insulating layer covers the first transistor; The second interlayer insulation layer is on top of the first interlayer insulation layer; as well as A buffer layer, located between the second interlayer insulating layer and the second transistor. Each of the plurality of through holes exposes at least a portion of the buffer layer.

8. The display device according to claim 1, wherein, The spacing between two adjacent through holes in the plurality of through holes is in the range of 10 micrometers or more and 15 micrometers or less.

9. The display device according to claim 1, wherein, The plurality of through holes include: A plurality of first vias are adjacent to and spaced apart from the second transistor in the peripheral region; and Multiple second through holes are spaced apart from each other in the display area.

10. The display device according to claim 1, wherein, Each of the plurality of sub-pixels includes a plurality of transistors, the plurality of transistors being metal-oxide-semiconductor.

11. The display device according to claim 10, wherein, Each of the plurality of transistors includes a first lower active pattern, and the first transistor includes a second lower active pattern in the same layer as the first lower active pattern.

12. A method for manufacturing a display device, the method comprising: A plurality of sub-pixels are formed in the display area on a substrate including a display area and a peripheral area surrounding at least a portion of the display area; A first transistor with a gate driver is formed on the substrate in the peripheral region; A second transistor for the gate driver is formed on the first transistor in the peripheral region; An inorganic insulating layer is formed to cover the second transistor; as well as Multiple vias are formed by penetrating the inorganic insulating layer, which are adjacent to and spaced apart from the second transistor.

13. The method of claim 12, further comprising: A via insulating layer is formed on the inorganic insulating layer, filling the interior of the plurality of through holes and including organic material.

14. The method according to claim 12, wherein, The first transistor and the second transistor comprise metal-oxide-semiconductor.

15. The method according to claim 12, wherein, Forming the second transistor includes: Forming an upper active pattern including a metal-oxide-semiconductor; and An upper gate electrode is formed in the planar view, overlapping the channel region of the upper active pattern.

16. The method of claim 15, further comprising: A contact hole is formed that penetrates the inorganic insulating layer and exposes the conductive area of ​​the upper active pattern; as well as An intermediate connection pattern is formed that connects to the conductive area of ​​the upper active pattern through the contact hole.

17. The method according to claim 16, wherein, The plurality of through holes are formed using the same process as the contact holes.

18. The method according to claim 12, wherein, The plurality of through holes include: A plurality of first vias are adjacent to and spaced apart from the second transistor in the peripheral region; and Multiple second through holes are spaced apart from each other in the display area.

19. An electronic device comprising: The processor is configured to provide image data signals and input control signals; as well as The display device is configured to output image information based on the image data signal and the input control signal. The display device includes: The substrate includes a display area and a peripheral area surrounding at least a portion of the display area; Multiple sub-pixels are located on the substrate in the display area. A first transistor with a gate driver is located on the substrate in the peripheral region and comprises a metal-oxide-semiconductor. The second transistor of the gate driver is located on the first transistor in the peripheral region and includes a metal-oxide-semiconductor; and An inorganic insulating layer covers the second transistor and defines a plurality of vias adjacent to and spaced apart from the second transistor.

20. The electronic device according to claim 19, wherein, The display device further includes: The via insulating layer, on the inorganic insulating layer, fills the interior of the plurality of vias and includes an organic material.

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