Display panel and its manufacturing method, display device

Abstract

This application relates to the field of display technology, and provides a display panel and its fabrication method, as well as a display device. The display panel includes a substrate, a first wiring layer, an insulating layer, a second wiring layer, a first planarization layer, a third wiring layer, and a second planarization layer. The first wiring layer is located on one side of the substrate; the insulating layer is located on the side of the first wiring layer facing away from the substrate; at least a portion of the second wiring layer is located on the side of the insulating layer facing away from the substrate and is electrically connected to the first wiring layer; the first planarization layer is located on the side of the second wiring layer facing away from the substrate and covers a portion of the surface of the insulating layer facing away from the substrate; the third wiring layer is located on the side of the first planarization layer facing away from the substrate and is electrically connected to the second wiring layer; the second planarization layer is located on the side of the first planarization layer facing away from the substrate; the orthographic projection of the second planarization layer on the substrate is within the outer contour of the orthographic projection of the first planarization layer on the substrate. This application aims to improve the process performance of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display technology, and more specifically, relates to a display panel and its manufacturing method, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are display devices that utilize the self-emissive principle of organic light-emitting materials to achieve display. They have advantages such as fast response speed, high brightness, and wide viewing angle, making them a highly competitive and promising type of display panel.

[0003] However, the current manufacturing process of OLED display products needs improvement. Summary of the Invention

[0004] This application provides a display panel and its manufacturing method, as well as a display device, to improve the process performance of the display panel to at least a certain extent.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, a display panel is provided, the display panel comprising a substrate, a first wiring layer, an insulating layer, a second wiring layer, a first planarization layer, a third wiring layer, and a second planarization layer, wherein the first wiring layer is located on one side of the substrate; at least a portion of the insulating layer is located on the side of the first wiring layer opposite to the substrate; at least a portion of the second wiring layer is located on the side of the insulating layer opposite to the substrate, and the second wiring layer is electrically connected to the first wiring layer; at least a portion of the first planarization layer is located on the side of the second wiring layer opposite to the substrate, and the first planarization layer is in contact with a portion of the surface of the insulating layer opposite to the substrate; at least a portion of the third wiring layer is located on the side of the first planarization layer opposite to the substrate, and the third wiring layer is electrically connected to the second wiring layer; at least a portion of the second planarization layer is located on the side of the first planarization layer opposite to the substrate.

[0006] Wherein, along the direction perpendicular to the plane where the substrate is located, the orthographic projection of the second planarization layer on the substrate is located within the outer contour of the orthographic projection of the first planarization layer on the substrate.

[0007] In the display panel provided in this application embodiment, by providing at least a portion of the first planarization layer located on the side of the second wiring layer facing away from the substrate and at least a portion of the surface of the insulating layer facing away from the substrate, the first planarization layer can protect the insulating layer. This can improve the situation in subsequent processes where the surface of the insulating layer located outside the non-target area is etched and thinned or damaged due to non-selective etching or over-etching, thereby reducing the possibility of display abnormalities in the display panel due to thinning of the insulating layer. This helps to improve the process performance and durability of the display panel, thereby extending the service life of the display panel.

[0008] Optionally, the display panel further includes a barrier wall located on the side of the insulating layer facing away from the substrate, along a direction parallel to the plane of the substrate, and the barrier wall is spaced apart from the first planarization layer;

[0009] The first planarization layer and the retaining wall have a first gap, and the second planarization layer and the retaining wall have a second gap, wherein the first gap is smaller than the second gap.

[0010] Optionally, the first spacing is greater than or equal to 30 μm.

[0011] Optionally, the display panel includes a display area and a non-display area, the barrier is located in the non-display area and surrounds the display area, and the first planarization layer and the second planarization layer are both located on the side of the barrier facing away from the display area.

[0012] Optionally, the non-display area includes a lower border area, and at least a portion of the first planarization layer and the second planarization layer are located in the lower border area.

[0013] Optionally, at least a portion of the first routing layer, the second routing layer, and the third routing layer are located in the lower border area.

[0014] Optionally, the second planarization layer has a first sidewall at the end near the barrier wall, and the first sidewall forms an angle with the plane of the substrate.

[0015] Optionally, the included angle is a right angle, and the first sidewall is perpendicular to the plane where the substrate is located; or, the included angle is an acute angle, and along a direction parallel to the plane where the substrate is located and pointing from the middle of the second planarization layer to the barrier, the distance between the side surface of the first sidewall facing away from the substrate and the substrate gradually decreases.

[0016] Optionally, the material of the first planarization layer includes an organic material.

[0017] Optionally, the material of the second planarization layer includes an organic material.

[0018] Optionally, in a direction perpendicular to the plane of the substrate, the orthographic projection of the first wiring layer on the substrate partially overlaps with the orthographic projection of the first planarization layer on the substrate.

[0019] Optionally, the first trace layer includes at least two parallel first traces, and at least one of the first traces has a portion of its orthographic projection on the substrate located within the orthographic projection of the first planarization layer on the substrate.

[0020] Optionally, at least one portion of the first trace on the substrate is projected onto the substrate within the projection of the second planarization layer onto the substrate.

[0021] Optionally, at least a portion of the orthographic projection of the second wiring layer on the substrate lies within the outer contour of the orthographic projection of the first planarization layer on the substrate.

[0022] Optionally, the second planarization layer covers at least a portion of the surface of the third wiring layer on the side facing away from the substrate.

[0023] Optionally, at least a portion of the orthographic projection of the third wiring layer on the substrate lies within the outer contour of the orthographic projection of the second planarization layer on the substrate.

[0024] In a second aspect, a method for manufacturing a display panel is provided, comprising:

[0025] A first wiring layer is prepared on one side of a substrate, and an insulating layer is prepared on the same side of the substrate after the first wiring layer is prepared, wherein at least a portion of the insulating layer is located on the side of the first wiring layer opposite to the substrate.

[0026] A second wiring layer is prepared on the side of the insulating layer facing away from the substrate, and the second wiring layer is electrically connected to the first wiring layer;

[0027] A first planarization layer is prepared on the side of the second wiring layer opposite to the insulating layer, and the first planarization layer is in contact with a portion of the surface of the insulating layer opposite to the substrate.

[0028] A third trace layer is prepared on the side of the first planarization layer opposite to the insulating layer, and the third trace layer is electrically connected to the second trace layer.

[0029] A second planarization layer is prepared on the side of the first planarization layer facing away from the substrate, and the orthographic projection of the second planarization layer on the substrate is located within the outer contour of the orthographic projection of the first planarization layer on the substrate.

[0030] In the display panel manufacturing method provided in this application embodiment, by setting the first planarization layer to contact a portion of the surface of the insulating layer facing away from the substrate, a certain degree of protection can be provided to the surface of the insulating layer facing away from the substrate, thereby reducing the etching damage suffered by the insulating layer during the etching process of the third wiring layer, helping to improve the reliability of the insulating layer, thereby reducing the possibility of display abnormalities caused by etching damage to the insulating layer, helping to improve the process performance and reliability of the display panel, and helping to extend the service life of the display panel.

[0031] Optionally, the step of fabricating a second wiring layer on the side of the insulating layer opposite to the substrate includes:

[0032] A second wiring material layer is prepared on the side of the insulating layer facing away from the substrate;

[0033] The second trace material layer is etched and patterned to form the second trace layer.

[0034] Optionally, the etching method for patterning is dry etching.

[0035] Optionally, the step of fabricating a third wiring layer on the side of the first planarization layer opposite to the insulating layer includes:

[0036] A third wiring material layer is prepared on the side of the first planarization layer facing away from the substrate;

[0037] The third wiring material layer is etched and patterned to form the third wiring layer.

[0038] Optionally, the etching method for patterning is dry etching.

[0039] Optionally, the second planarization layer covers at least a portion of the surface of the third wiring layer on the side opposite to the substrate;

[0040] Optionally, the second planarization layer is in contact with the side surface of the third wiring layer facing away from the substrate.

[0041] In a third aspect, a display device is provided, comprising a display panel as described in any of the preceding claims, or comprising the display panel prepared by the method for preparing the display panel as described in any of the preceding claims.

[0042] The display device provided in this application includes the above-mentioned display panel. Therefore, the display device has the beneficial effects of including at least one or more of the above-mentioned display panels. The specific effects are as described above and will not be repeated here.

[0043] The beneficial effects of the display panel, its preparation method, and the display device provided in this application are as follows: Compared with related technologies, the display panel provided in this application can protect the surface of the insulating layer facing away from the substrate by adjusting the distribution range of the first planarization layer and the second planarization layer without affecting the normal use of the display panel or changing the related process. This reduces the possibility of film thinning or even breakage on the surface of the insulating layer due to non-selective etching, thereby improving the process performance of the display panel and increasing its durability and service life. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of the structure of a display panel in related technologies;

[0046] Figure 2 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of this application;

[0047] Figure 3 for Figure 2 Enlarged view of the structure of the S-region;

[0048] Figure 4 for Figure 3 The diagram shows a sectional view of the display panel along line AA.

[0049] Figure 5 for Figure 3 Another AA-direction cross-sectional view of the display panel shown;

[0050] Figure 6 This is a flowchart illustrating the method for manufacturing a display panel as provided in an embodiment of this application.

[0051] Figure 7 This is a schematic diagram of the planar structure of the display device provided in the embodiments of this application.

[0052] The following are the labeling elements in the figure:

[0053] 100. Display device; 10. Display panel; AA. Display area; NA. Non-display area; NA1. Bottom border area; NA2. Top border area; NA3. Left border area; NA4. Right border area;

[0054] 1. Substrate; 2. First wiring layer; 21. First wiring; 3. Insulating layer; 4. Second wiring layer; 5. First planarization layer; 6. Third wiring layer; 7. Second planarization layer; 701. First sidewall; 8. Barrier. Detailed Implementation

[0055] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0056] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0057] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0058] Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features or their execution order, and the terms "first" and "second" are not necessarily different. Therefore, a feature defined with "first" and "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0059] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0060] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0061] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0062] As used herein, the term "substrate" refers to a material on which subsequent material layers are added to provide a support substrate for the layers above. In some embodiments, the substrate may be flexible, stretchable, foldable, bendable, or rollable, such that the display panel may be flexible, stretchable, foldable, bendable, or rollable. The substrate material may be formed from any suitable insulating material that is flexible, such as polyimide (PI), polycarbonate (P), polyethersulfone (PES), or polymeric materials such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyaryl compounds (PR), or glass fiber reinforced plastic (FRP). The substrate may be transparent, translucent, or opaque. In other embodiments, the substrate may also be rigid, made of a rigid insulating material, such as metal, ultrathin glass, plastic, or sapphire wafer. The substrate itself may be patterned. The material added to the substrate can be patterned, or it can remain unpatterned.

[0063] The terms "layer" or "element" used in this document can refer to a structural or functional layer of a certain thickness and covering a certain area, composed of different materials that make up the structure of a display panel. A layer or element can extend over a complete layer or element structure located below or above, or have a smaller extent than the layer or element structure located below or above. It should be noted that the dimensions of layers and areas may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when a layer or element is referred to as being "on" another layer or element, it can be directly on the other layer or element, or it can be a layer located between two structures. Additionally, it is understood that when a layer or element is referred to as being "below" another layer or element, it can be directly below the other layer or element, or it can be more than one intermediate layer or element. It is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between two layers or two elements, or it can be more than one intermediate layer or element. Moreover, a layer or element can be a region of a homogeneous or non-homogeneous continuous structure with a thickness less than the thickness of that continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layer may extend laterally, vertically, and / or along a tapered surface. The substrate may be a layer, and may include one or more layers. For example, the interconnect layer may include one or more conductor and contact layers (forming contacts, interconnects, and / or vias therein) and one or more dielectric layers.

[0064] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B can mean A or B. The term "and / or" in this application is merely a description of the relationship between the related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural.

[0065] With the development of display technology, the types of display panels on the market are gradually increasing, and their performance is constantly improving. From the overall structure of the panel, the display panel includes a display area and a non-display area. The non-display area includes a border area that surrounds the edge of the display area and is not used to display images. The border area is located on the outer peripheral edge of the display panel.

[0066] In related technologies, to achieve the normal display function of a display panel, a certain number of metal traces are arranged in the bezel area, especially the bottom bezel area. These metal traces are numerous and used for signal and current transmission. Taking the bottom bezel as an example, multiple film layers are arranged in this area to cover and protect the aforementioned metal traces. However, to prevent moisture intrusion from the external environment, this area is often designed with grooves; please refer to [reference needed]. Figure 1 In implementing the above solution, the inventors discovered that some traces had problems with poor signal conduction and / or poor current delivery. These problems would affect the display effect of the display panel to a certain extent and cause display abnormalities in some areas of the display panel, such as bright lines.

[0067] Based on this, embodiments of this application provide a display panel 10 and its manufacturing method, and a display device 100, so as to improve the process performance of the display panel 10 to at least a certain extent and reduce the possibility of display abnormalities in the display panel 10.

[0068] Please see Figure 2 and Figure 3 This application provides a display panel 10, which includes a substrate 1, a first wiring layer 2, an insulating layer 3, a first planarization layer 5, and a second planarization layer 7. The first wiring layer 2 is located on one side of the substrate 1, at least a portion of the insulating layer 3 is located on the side of the first wiring layer 2 facing away from the substrate 1, the first planarization layer 5 is located on the side of the insulating layer 3 facing away from the substrate 1 and is in contact with the surface of the insulating layer 3 facing away from the substrate 1, and the second planarization layer 7 is located on the side of the first planarization layer 5 facing away from the substrate 1. In a direction perpendicular to the plane of the substrate 1, the orthographic projection of the second planarization layer 7 on the substrate 1 is located within the outer contour of the orthographic projection of the first planarization layer 5 on the substrate 1.

[0069] It should be noted that the first planarization layer 5 and the second planarization layer 7 are both located in the non-display area NA of the display panel 10. Meanwhile, other film layers arranged in the same layer as the first planarization layer 5 are disposed in the display area AA of the display panel 10. These film layers can be prepared by the same process as the first planarization layer 5, or they can be prepared by a different process than the first planarization layer 5. This embodiment does not limit them.

[0070] Please see Figure 2 and Figure 3 The first wiring layer 2 is at least partially located in the non-display area NA and one end points to the display area AA. The insulating layer 3 is located on the side of the first wiring layer 2 facing away from the substrate 1 and covers at least part of the surface of the first wiring layer 2 facing away from the substrate 1, so as to wrap and protect the first wiring layer 2.

[0071] Please see Figure 2 and Figure 3 The display panel 10 also includes a barrier 8, which is located on the side of the insulating layer 3 facing away from the substrate 1. The barrier 8 and the first planarization layer 5 are spaced apart along a direction parallel to the plane of the substrate 1, and a groove structure exists between the barrier 8 and the first planarization layer 5.

[0072] In a direction perpendicular to the plane of substrate 1, the orthographic projection of the first wiring layer 2 on substrate 1 coincides with the orthographic projection of the groove on substrate 1. That is, the orthographic projection of the first wiring layer 2 on substrate 1 lies within the orthographic projection of the first planarization layer 5 on substrate 1, and partially lies between the orthographic projection of the baffle 8 on substrate 1 and the orthographic projection of the first planarization layer 5 on substrate 1. Of course, it is also possible that a portion of the orthographic projection of the first wiring layer 2 on substrate 1 coincides with a portion of the orthographic projection of the baffle 8 on substrate 1.

[0073] In the display panel 10 provided in this embodiment, since the orthographic projection of the second planarization layer 7 on the substrate 1 is located within the outer contour of the orthographic projection of the first planarization layer 5 on the substrate 1, this means that the area covered by the first planarization layer 5 on the side of the insulating layer 3 facing away from the substrate 1 is increased, and the area of ​​the insulating layer 3 exposed relative to the first planarization layer 5 is relatively reduced. At this time, the first planarization layer 5 can provide a certain degree of coverage and protection for the surface of the insulating layer 3, so as to improve the situation where the surface of the insulating layer 3 located outside the non-target area is etched and thinned or damaged due to non-selective etching or over-etching in subsequent partial etching processes, thereby reducing the possibility of display abnormalities in the display panel 10 due to the thinning of the insulating layer 3, and helping to improve the process performance and durability of the display panel 10, so as to extend the service life of the display panel 10.

[0074] The etching process described above can be any process involving patterning etching, including dry etching. The first planarization layer 5 covering part of the surface of the insulating layer 3 can provide a certain degree of protection for the insulating layer 3, thereby improving the defects of film thinning and reliability reduction caused by the dry etching process.

[0075] Specifically, the insulating layer 3 may include inorganic materials, the first planarization layer 5 may include organic materials, and the second planarization layer 7 may also include organic materials.

[0076] The first planarization layer 5 and the second planarization layer 7 can be prepared by using a mask.

[0077] In the display panel 10 provided in this application, the display panel 10 includes a display area AA and a non-display area NA. A barrier 8 is located in the non-display area NA and is disposed around the display area AA. The first planarization layer 5 and the second planarization layer 7 are both located on the side of the barrier 8 facing away from the display area AA, that is, the first planarization layer 5 and the second planarization layer 7 are both located in the non-display area NA.

[0078] Please see Figure 2 and Figure 3 The non-display area NA includes the lower border area NA1, and at least a portion of the first planarization layer 5 and the second planarization layer 7 are located in the lower border area NA1. Similarly, at least a portion of the first routing layer 2 is located in the lower border area NA1.

[0079] To prevent moisture and other contaminants from entering the display area AA through the lower bezel, the display panel 10 has at least two spaced-apart baffles 8, both of which are annular structures surrounding the display area AA (the baffles 8 are generally similar to hollow rectangles or hollow rounded rectangles). There is a gap between the first planarization layer 5 and either baffle 8, and the area of ​​the insulating layer 3 located between the first planarization layer 5 and the baffle 8 is exposed through this gap. Since the distribution range of the first planarization layer 5 is larger than that of the second planarization layer 7, and the second planarization layer 7 is prepared after the first planarization layer 5 is prepared, adjusting the distribution range of the first planarization layer 5 to increase its size can provide better protection for the side of the insulating layer 3 facing away from the substrate 1. This reduces the extent and area of ​​etching thinning of the insulating layer 3 during subsequent non-selective etching, thereby reducing the possibility of defects such as insulation layer 3 breakage and display abnormalities caused by etching. This helps improve the process performance and durability of the display panel 10, extending its service life.

[0080] In some embodiments, the coverage area of ​​the second planarization layer 7 remains unchanged. In this case, the mask used to prepare the second planarization layer 7 remains unchanged. The mask used to prepare the first planarization layer 5 is then adjusted in shape to increase the distribution range of the first planarization layer 5, so that the orthographic projection of the second planarization layer 7 onto the substrate 1 falls within the outer contour of the orthographic projection of the first planarization layer 5 onto the substrate 1, thereby better protecting the insulating layer 3. At this time, the distance between the second planarization layer 7 and the barrier 8 remains unchanged, while the distance between the first planarization layer 5 and the barrier 8 is reduced.

[0081] In other similar embodiments, while increasing the distribution range of the first planarization layer 5, the distribution range of the second planarization layer 7 is reduced to a certain extent. This is to ensure that, without changing the actual distribution range and area of ​​the stacked first and second planarization layers 5 and 7 on the substrate 1, the orthographic projection of the second planarization layer 7 on the substrate 1 falls within the outer contour of the orthographic projection of the first planarization layer 5 on the substrate 1. In this case, the distance between the second planarization layer 7 and the barrier 8 increases, while the distance between the first planarization layer 5 and the barrier 8 decreases.

[0082] Please see Figure 3 and Figure 4 The first planarization layer 5 and the retaining wall 8 have a first spacing d1, and the second planarization layer 7 and the retaining wall 8 have a second spacing d2. The first spacing d1 is smaller than the second spacing d2.

[0083] Specifically, the first spacing d1 is greater than or equal to 30μm. The first spacing d1 can be any value among 30μm, 35μm, 40μm, 45μm, 50μm, etc., in which case the second spacing d2 needs to be greater than the first spacing d1.

[0084] Specifically, the absolute value of the difference between the first spacing d1 and the second spacing d2 is not less than 40 μm and does not exceed 80 μm.

[0085] For example, the absolute value of the difference between the first spacing d1 and the second spacing d2 can be set to any value among 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, etc.

[0086] It should be noted that, provided that there are at least two barrier walls 8, the first spacing d1 and the second spacing d2 are both the distances between the barrier wall 8 on the side away from the display area AA and the corresponding first planarization layer 5 and second planarization layer 7.

[0087] Please see Figure 3The groove formed between the retaining wall 8 and the first planarization layer 5 is a strip-shaped groove, and the side of the retaining wall 8 facing the first planarization layer 5 is basically parallel to the side of the first planarization layer 5 facing the retaining wall 8, so that the spacing between the various positions of the groove in its length direction is basically consistent.

[0088] At this time, the first wiring layer 2 is inclined relative to the barrier 8 and the first planarization layer 5, so that in the direction perpendicular to the plane of the substrate 1, the orthographic projection of the first wiring layer 2 on the substrate 1 overlaps with the orthographic projection of the first planarization layer 5 on the substrate 1.

[0089] Specifically, the first wiring layer 2 includes at least two parallel first traces 21, and at least one of the first traces 21 has a portion of its orthographic projection on the substrate 1 within the orthographic projection of the first planarization layer 5 on the substrate 1. Similarly, at least one of the first traces 21 has a portion of its orthographic projection on the substrate 1 within the orthographic projection of the barrier 8 on the substrate 1.

[0090] In some embodiments, the spacing between two adjacent first traces 21 is set to be approximately one to two times the width of the first trace 21. For example, if the width of the first trace 21 is defined as 'a', then the width between two adjacent first traces 21 is a to 2a. When 'a' is 5 μm, the width between two adjacent first traces 21 ranges from 5 μm to 10 μm, and its specific value can be any value among 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.

[0091] Specifically, the number of the first routing line 21 is at least four, and can be four, five or even more. The number can be adjusted according to the design requirements, which will not be elaborated here.

[0092] Please see Figure 3 The first trace 21, which is inclined relative to the groove, is at least partially located in the non-display area NA. In a direction parallel to the plane of the substrate 1, one end of the trace points to the display area AA (and may extend into the display area AA if the length allows), and the other end points to the side of the non-display area NA that is opposite to the display area AA.

[0093] Specifically, one end of a portion of the first trace 21 along its length is located below the first planarization layer 5, and the other end is located below the barrier 8. Similarly, at least one portion of the orthographic projection of the first trace 21 on the substrate 1 lies within the orthographic projection of the second planarization layer 7 on the substrate 1.

[0094] Please see Figure 4 The second planarization layer 7 has a first sidewall 701 at one end near the barrier 8. The orthographic projection of the first sidewall 701 on the substrate 1 is also located within the outer contour of the orthographic projection of the first planarization layer 5 on the substrate 1.

[0095] Specifically, the first sidewall 701 and the plane containing the substrate 1 have an angle α.

[0096] When the included angle α is a right angle, the first sidewall 701 is perpendicular to the plane of the substrate 1. When the included angle α is an acute angle, the distance between the surface of the first sidewall 701 facing away from the substrate 1 and the substrate 1 gradually decreases along the direction parallel to the plane of the substrate 1 and from the middle of the second planarization layer 7 to the baffle 8. At this time, the first sidewall 701 is a slope that is inclined relative to the plane of the substrate 1.

[0097] Please see Figure 4 When moisture from the external environment invades the lower frame area NA1 (for example, during high temperature and high humidity reliability verification), the moisture invades the second planarization layer 7 and causes the second planarization layer 7 to absorb moisture and expand. At this time, stress concentration will occur at the end of the second planarization layer 7 pointing towards the barrier wall 8 and will act on the relevant film layer located below it.

[0098] Taking an acute angle α between the plane containing the first sidewall 701 and the substrate 1 as an example, since the orthographic projection of the second planarization layer 7 onto the substrate 1 is within the orthographic projection range of the first planarization layer 5 onto the substrate 1, the stress generated at the end of the second planarization layer 7 (first sidewall 701) will directly act on the first planarization layer 5, rather than directly on the insulating layer 3 located below the first planarization layer 5. Under the protection of the first planarization layer 5, the insulating layer 3 located below the first sidewall 701 has sufficient thickness to resist the stress at the end of the second planarization layer 7, thereby reducing the possibility of abnormal defects such as cracks in the insulating layer 3 under stress, effectively improving the processing technology of the display panel 10, and increasing the reliability of the display panel 10. At the same time, the above structure can further extend the moisture intrusion path, blocking moisture from intruding into the first wiring layer 2 through the insulating layer 3, thereby reducing the possibility of wire breakage in the first wiring layer 2 due to moisture erosion, and helping to improve the display reliability of the display panel 10.

[0099] Please see Figure 5 The display panel 10 provided in this embodiment further includes a second wiring layer 4 and a third wiring layer 6. In related technologies, the insulating layer 3 is etched during the fabrication of the second wiring layer 4 and the third wiring layer 6, resulting in film thinning. However, in this embodiment, by adjusting the distribution range of the first planarization layer 5, the impact of the etching process of the third wiring layer 6 on the etching of the insulating layer 3 can be effectively reduced, thus helping to improve the reliability of the insulating layer 3.

[0100] In some embodiments, the insulating layer 3 covers the first wiring layer 2 and is in contact with the side surface of the first wiring layer 2 facing away from the substrate 1. At least a portion of the second wiring layer 4 is located on the side of the insulating layer 3 facing away from the substrate 1 and is electrically connected to the first wiring layer 2, and at least a portion of the first planarization layer 5 is located on the side of the second wiring layer 4 facing away from the substrate 1.

[0101] An insulating layer 3 has a first via hole. A portion of the surface of the first wiring layer 2 facing away from the substrate 1 is exposed relative to the first via hole. The second wiring layer 4 passes through the first via hole and contacts the first wiring layer 2 to achieve electrical connection. At this time, at least a portion of the orthographic projection of the second wiring layer 4 on the substrate 1 is located within the outer contour of the orthographic projection of the first planarization layer 5 on the substrate 1.

[0102] Alternatively, in other similar embodiments, the surface portion of the first wiring layer 2 facing away from the substrate 1 may not be covered by the insulating layer 3, and the second wiring layer 4 may extend along the surface of the insulating layer 3 and contact the surface portion of the first wiring layer 2 facing away from the substrate 1 to achieve electrical connection.

[0103] Specifically, in the embodiments of this application, the second wiring layer 4 is in contact with the side surface of the insulating layer 3 facing away from the substrate 1; similarly, the first planarization layer 5 is in contact with the side surface of the second wiring layer 4 facing away from the substrate 1.

[0104] After the second wiring layer 4 is etched, the first planarization layer 5 can simultaneously cover the insulating layer 3 and the second wiring layer 4, so as to provide a certain protection for the side surface of the insulating layer 3 and the second wiring layer 4 facing away from the substrate 1, and avoid damage to the surface of the insulating layer 3 and the second wiring layer 4 in subsequent etching processes.

[0105] In some embodiments, at least a portion of the third wiring layer 6 is located on the side of the first planarization layer 5 facing away from the substrate 1 and is electrically connected to the second wiring layer 4, and at least a portion of the second planarization layer 7 is located on the side of the first planarization layer 5 facing away from the substrate 1.

[0106] A second via is provided on the first planarization layer 5. A portion of the surface of the second wiring layer 4 facing away from the substrate 1 is exposed relative to the second via. The third wiring layer 6 passes through the second via and contacts the second wiring layer 4 to achieve electrical connection.

[0107] Alternatively, in other similar embodiments, the second wiring layer 4 may be configured such that a portion of its surface facing away from the substrate 1 is not covered by the first planarization layer 5, and the third wiring layer 6 extends along the surface of the first planarization layer 5 and contacts the surface of the second wiring layer 4 facing away from the substrate 1 to achieve electrical connection.

[0108] Specifically, in the embodiments of this application, the third wiring layer 6 is in contact with the side surface of the first planarization layer 5 facing away from the substrate 1.

[0109] The second planarization layer 7 can be located on the side of the third wiring layer 6 facing away from the substrate 1 to cover and protect the third wiring layer 6. Please refer to [link to relevant documentation]. Figure 5At this time, a second planarization layer 7 can be provided to cover at least a portion of the surface of the third wiring layer 6 on the side opposite to the substrate 1, and to be in contact with at least a portion of the surface of the third wiring layer 6 on the side opposite to the substrate 1.

[0110] Specifically, at least a portion of the orthographic projection of the third wiring layer 6 onto the substrate 1 lies within the outer contour of the orthographic projection of the second planarization layer 7 onto the substrate 1.

[0111] Alternatively, it can be arranged side by side with the third wiring layer 6 on the side surface of the first planarization layer 5 facing away from the substrate 1. This embodiment does not limit it.

[0112] In this embodiment, the first planarization layer 5 can provide certain protection to the side surface of the insulating layer 3 facing away from the substrate 1, so as to improve the situation in the subsequent process of the third wiring layer 6 where the surface of the insulating layer 3 located outside the non-target area is etched and thinned or damaged due to non-selective etching or over-etching, thereby reducing the possibility of display abnormalities in the display panel 10 due to the thinning of the insulating layer 3, and helping to improve the process performance and durability of the display panel 10, so as to extend the service life of the display panel 10.

[0113] Compared with related technologies, this solution can effectively improve the etching damage of the third wiring layer 6 to the insulating layer 3 in the display panel 10, so that the insulating layer 3 can have sufficient thickness, reduce the possibility of cracks in the insulating layer 3 due to stress, and further prevent moisture from entering through the cracks in the insulating layer 3, which helps to improve the processing technology and reliability of the display panel 10.

[0114] In the display panel 10 provided in the embodiments of this application, at least a portion of the second wiring layer 4 and the third wiring layer 6 are located in the non-display area NA, especially the lower border area NA1.

[0115] Of course, the non-display area NA also includes the upper border area NA2, the left border area NA3, and the right border area NA4. These areas, together with the lower border area NA1, constitute the non-display area NA surrounding the outer periphery of the display area AA. In some embodiments, it is possible that a portion of the first routing layer 2, the second routing layer 4, and the third routing layer 6 extends from the lower border area NA1 into the display area AA, or into other non-display areas NA. This embodiment does not limit this.

[0116] The display panel 10 also includes an inorganic encapsulation layer located on the side of the second planarization layer 7 facing away from the substrate 1. The inorganic encapsulation layer covers the non-display area NA and extends from the non-display area NA to the display area AA. The barrier 8 and the second planarization layer 7 are both located between the inorganic encapsulation layer and the substrate 1.

[0117] Specifically, the inorganic encapsulation layer includes a first inorganic encapsulation layer and a second inorganic encapsulation layer stacked together, both of which are prepared by chemical vapor deposition (CVD) process.

[0118] The display panel 10 also includes a touch film layer located on the side of the inorganic encapsulation layer facing away from the substrate 1, and a buffer layer located between the first wiring layer 2 and the substrate 1. The buffer layer includes at least one of organic and inorganic materials, which will not be described in detail here.

[0119] It is understood that the display panel 10 provided in this application embodiment can effectively protect at least a portion of the surface of the insulating layer 3 facing away from the substrate 1 without changing the manufacturing process of the display panel 10 by adjusting the distribution range of the first planarization layer 5. This reduces the possibility of the insulating layer 3 being damaged and thinned by non-selective etching after the first planarization layer 5 process, improves the reliability of the insulating layer 3, and to a certain extent improves the manufacturing process of the display panel 10, as well as improves the reliability and service life of the display panel 10.

[0120] Based on the same inventive concept, in a second aspect, embodiments of this application provide a method for manufacturing a display panel 10. Please refer to [link to relevant documentation]. Figure 6 .

[0121] The preparation method provided in this application embodiment is used to prepare the display panel 10 described above, and the specific preparation method includes:

[0122] Step S1: A first wiring layer 2 is prepared on one side of the substrate 1, and an insulating layer 3 is prepared on the same side of the substrate 1 after the first wiring layer 2 is prepared. At least a portion of the insulating layer 3 is located on the side of the first wiring layer 2 facing away from the substrate 1.

[0123] Step S2: A second wiring layer 4 is prepared on the side of the insulating layer 3 facing away from the substrate 1, and the second wiring layer 4 is electrically connected to the first wiring layer 2;

[0124] Step S3: Prepare a first planarization layer 5 on the side of the second wiring layer 4 facing away from the insulating layer 3. The first planarization layer 5 is in contact with a portion of the surface of the insulating layer 3 facing away from the substrate 1.

[0125] Step S4: Prepare a third wiring layer 6 on the side of the first planarization layer 5 opposite to the insulating layer 3. The third wiring layer 6 is electrically connected to the second wiring layer 4.

[0126] Step S5: Prepare a second planarization layer 7 on the side of the first planarization layer 5 facing away from the substrate 1. The orthographic projection of the second planarization layer 7 on the substrate 1 is located within the outer contour of the orthographic projection of the first planarization layer 5 on the substrate 1.

[0127] Since the first planarization layer 5 is in contact with a portion of the surface of the insulating layer 3 facing away from the substrate 1, it can provide a certain degree of protection for the surface of the insulating layer 3 facing away from the substrate 1. This effectively protects the insulating layer 3, reducing the area of ​​the insulating layer 3 that is etched and thinned during the etching process of the third wiring layer 6. This helps improve the reliability of the insulating layer 3, reducing the possibility of display abnormalities in the display panel 10 due to etch damage to the insulating layer 3. It also helps improve the process performance and reliability of the display panel 10 and extends its service life. In addition, by adjusting the orthographic projection of the second planarization layer 7 on the substrate 1 to be within the outer contour of the orthographic projection of the first planarization layer 5 on the substrate 1, stress generated at the end of the second planarization layer 7 will not directly act on the insulating layer 3, but will first act on the first planarization layer 5. This further reduces the damage of stress at the end of the second planarization layer 7 to the insulating layer 3, reducing the possibility of cracks appearing in the insulating layer 3 under stress and causing the first wiring layer 2 to be eroded and broken by moisture. This optimizes the manufacturing process of the display panel 10.

[0128] In step S1, at least a portion of the insulating layer 3 is located on the side of the first wiring layer 2 facing away from the substrate 1 and is in contact with the surface of the first wiring layer 2 facing away from the substrate 1. At this time, at least a portion of the first wiring layer 2 is located between the insulating layer 3 and the substrate 1.

[0129] In step S2, as mentioned above, a first via is provided on the insulating layer 3, and the second wiring layer 4 can be electrically connected to the first wiring layer 2 through the first via.

[0130] In some embodiments, step S2, the step of preparing a second wiring layer 4 on the side of the insulating layer 3 facing away from the substrate 1, includes:

[0131] Step S21: Prepare a second wiring material layer on the side of the insulating layer 3 facing away from the substrate 1;

[0132] Step S22: Etch and pattern the second wiring material layer to form the second wiring layer 4.

[0133] Specifically, the etching method for patterning is dry etching.

[0134] Dry etching, such as reactive ion etching and inductively coupled plasma etching, utilizes the interaction between ions and free radicals in plasma to achieve a highly directional etching process. Ions bombard the material surface perpendicularly under an electric field, exhibiting anisotropy, which allows for precise control of the etching direction, greatly reducing lateral etching and effectively avoiding side etching problems.

[0135] After the second wiring material layer is prepared by means of vapor deposition, the second wiring material layer can be etched by dry etching technology to obtain the second wiring layer 4 that meets the design requirements.

[0136] After the second wiring layer 4 is fabricated in step S2, it can contact a portion of the surface of the insulating layer 3 facing away from the substrate 1. Subsequently, step S3 is performed to fabricate the first planarization layer 5, which can simultaneously contact the surface of the insulating layer 3 facing away from the substrate 1 and the surface of the second wiring layer 4 facing away from the substrate 1. Furthermore, the first planarization layer 5 has a second via, through which the third wiring layer 6 fabricated in step S4 can be electrically connected to the second wiring layer 4.

[0137] In some embodiments, step S4, the step of preparing a third wiring layer 6 on the side of the first planarization layer 5 opposite to the insulating layer 3, includes:

[0138] Step S41: Prepare a third wiring material layer on the side of the first planarization layer 5 facing away from the substrate 1;

[0139] Step S42: Etch and pattern the third wiring material layer to form the third wiring layer 6.

[0140] Specifically, the etching method for patterning is dry etching.

[0141] After the third wiring material layer is prepared by means of vapor deposition, the third wiring material layer can be etched by dry etching technology to obtain the third wiring layer 6 that meets the design requirements.

[0142] After step S4 is completed, step S5 is performed, at which point the second planarization layer 7 covers at least a portion of the surface of the third wiring layer 6 on the side facing away from the substrate 1.

[0143] Specifically, the second planarization layer 7 is in contact with the side surface of the third wiring layer 6 facing away from the substrate 1, at which time at least part of the third wiring layer 6 is located between the first planarization layer 5 and the second planarization layer 7.

[0144] It is understood that the method for preparing the display panel 10 provided in this application embodiment can prepare the display panel 10 described above, thereby improving the processing technology of the display panel 10 and improving the reliability and service life of the prepared display panel 10.

[0145] Based on the same inventive concept, in a third aspect, embodiments of this application provide a display device 100, please refer to... Figure 7 The display device 100 includes the display panel 10 described in any of the preceding claims, or includes a display panel 10 prepared by the preparation method of the display panel 10 described in any of the preceding claims.

[0146] For details regarding the specific structure of the display panel 10, please refer to the specific description in the foregoing embodiments, which will not be repeated here.

[0147] The display device 100 provided in this embodiment can be a mobile phone, laptop, tablet computer, smartwatch, smart bracelet, navigator, monitor, personal digital assistant (PDA), or other products or components with display functions.

[0148] Since the display device 100 has the aforementioned display panel 10, the display device 100 has at least the beneficial effects of any one or more of the aforementioned display panels 10. The specific effects are as described above and will not be repeated here.

[0149] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel (10) includes: Substrate (1); The first wiring layer (2) is located on one side of the substrate (1); An insulating layer (3) is located at least partially on the side of the first wiring layer (2) facing away from the substrate (1); The second wiring layer (4) is at least partially located on the side of the insulating layer (3) facing away from the substrate (1), and the second wiring layer (4) is electrically connected to the first wiring layer (2); The first planarization layer (5) is at least partially located on the side of the second wiring layer (4) facing away from the substrate (1), and the first planarization layer (5) is in contact with a portion of the surface of the insulating layer (3) facing away from the substrate (1). The third wiring layer (6) is at least partially located on the side of the first planarization layer (5) facing away from the substrate (1), and the third wiring layer (6) is electrically connected to the second wiring layer (4). The second planarization layer (7) is at least partially located on the side of the first planarization layer (5) facing away from the substrate (1); Wherein, along the direction perpendicular to the plane where the substrate (1) is located, the orthographic projection of the second planarization layer (7) on the substrate (1) is located within the outer contour of the orthographic projection of the first planarization layer (5) on the substrate (1).

2. The display panel according to claim 1, characterized in that, The display panel (10) further includes a barrier (8), which is located on the side of the insulating layer (3) facing away from the substrate (1) and is arranged in a direction parallel to the plane of the substrate (1). The barrier (8) is spaced apart from the first planarization layer (5). Wherein, the first planarization layer (5) has a first gap with the retaining wall (8), and the second planarization layer (7) has a second gap with the retaining wall (8), wherein the first gap is smaller than the second gap; Preferably, the first spacing is greater than or equal to 30 μm.

3. The display panel according to claim 2, characterized in that, The display panel (10) includes a display area (AA) and a non-display area (NA). The barrier (8) is located in the non-display area (NA) and surrounds the display area (AA). The first planarization layer (5) and the second planarization layer (7) are both located on the side of the barrier (8) facing away from the display area (AA). Preferably, the non-display area (NA) includes a lower border area (NA1), and at least a portion of the first planarization layer (5) and the second planarization layer (7) are located in the lower border area (NA1); Preferably, at least a portion of the first wiring layer (2), the second wiring layer (4), and the third wiring layer (6) are located in the lower border area (NA1).

4. The display panel according to claim 2 or 3, characterized in that, The second planarization layer (7) has a first sidewall (701) at one end near the barrier wall (8), and the first sidewall (701) has an angle with the plane where the substrate (1) is located; Preferably, the included angle is a right angle, and the first sidewall (701) is perpendicular to the plane where the substrate (1) is located; or, the included angle is an acute angle, and along a direction parallel to the plane where the substrate (1) is located and pointing from the middle of the second planarization layer (7) to the barrier wall (8), the distance between the side surface of the first sidewall (701) facing away from the substrate (1) and the substrate (1) gradually decreases.

5. The display panel according to claim 1, characterized in that, The material of the first planarization layer (5) includes an organic material; and / or, the material of the second planarization layer (7) includes an organic material.

6. The display panel according to claim 1, characterized in that, In a direction perpendicular to the plane of the substrate (1), the orthographic projection of the first wiring layer (2) on the substrate (1) overlaps with the orthographic projection of the first planarization layer (5) on the substrate (1); Preferably, the first wiring layer (2) includes at least two parallel first wirings (21), and at least one of the first wirings (21) has a portion of its orthographic projection on the substrate (1) located within the orthographic projection of the first planarization layer (5) on the substrate (1); Preferably, at least one of the first traces (21) has a partial orthographic projection on the substrate (1) within the orthographic projection of the second planarization layer (7) on the substrate (1).

7. The display panel according to claim 1, characterized in that, At least a portion of the orthographic projection of the second wiring layer (4) onto the substrate (1) lies within the outer contour of the orthographic projection of the first planarization layer (5) onto the substrate (1); Preferably, the second planarization layer (7) covers at least a portion of the surface of the third wiring layer (6) on the side opposite to the substrate (1); Preferably, at least a portion of the orthographic projection of the third wiring layer (6) onto the substrate (1) lies within the outer contour of the orthographic projection of the second planarization layer (7) onto the substrate (1).

8. A method for manufacturing a display panel, characterized in that, include: A first wiring layer (2) is prepared on one side of a substrate (1), and an insulating layer (3) is prepared on the same side of the substrate (1) after the first wiring layer (2) is prepared. At least a portion of the insulating layer (3) is located on the side of the first wiring layer (2) facing away from the substrate (1). A second wiring layer (4) is prepared on the side of the insulating layer (3) facing away from the substrate (1), and the second wiring layer (4) is electrically connected to the first wiring layer (2); A first planarization layer (5) is prepared on the side of the second wiring layer (4) facing away from the insulating layer (3), and the first planarization layer (5) is in contact with a portion of the surface of the insulating layer (3) facing away from the substrate (1); A third wiring layer (6) is prepared on the side of the first planarization layer (5) facing away from the insulating layer (3), and the third wiring layer (6) is electrically connected to the second wiring layer (4); A second planarization layer (7) is prepared on the side of the first planarization layer (5) facing away from the substrate (1), and the orthographic projection of the second planarization layer (7) on the substrate (1) is located within the outer contour of the orthographic projection of the first planarization layer (5) on the substrate (1).

9. The method for manufacturing a display panel according to claim 8, characterized in that, The step of fabricating a second wiring layer (4) on the side of the insulating layer (3) facing away from the substrate (1) includes: A second wiring material layer is prepared on the side of the insulating layer (3) facing away from the substrate (1); The second trace material layer is etched and patterned to form the second trace layer (4); Preferably, the etching method for patterning is dry etching; And / or, the step of preparing a third wiring layer (6) on the side of the first planarization layer (5) opposite to the insulating layer (3) includes: A third wiring material layer is prepared on the side of the first planarization layer (5) facing away from the substrate (1); The third wiring material layer is etched and patterned to form the third wiring layer (6); Preferably, the etching method for patterning is dry etching; And / or, the second planarization layer (7) covers at least a portion of the surface of the third wiring layer (6) on the side opposite to the substrate (1); Preferably, the second planarization layer (7) is in contact with the side surface of the third wiring layer (6) facing away from the substrate (1).

10. A display device, characterized in that, The display panel (10) includes any one of claims 1-7, or the display panel (10) is prepared by the preparation method of the display panel (10) according to claim 8 or 9.

Images