Electronic device and method for manufacturing an electronic device

Abstract

This application relates to electronic devices and methods for manufacturing electronic devices. The electronic device may include a display module comprising a light-emitting element and a pixel-defining film including an opening. The light-emitting element may include a first electrode exposed through the opening, a scattering layer on the first electrode, an emitting layer on the scattering layer, and a second electrode on the emitting layer. The scattering layer may include a base portion and a plurality of hollow silica particles dispersed in the base portion, each including a first hollow silica particle and a second hollow silica particle. The first hollow silica particle may be disposed on a top surface of the scattering layer spaced apart from the first electrode and may protrude from the top surface of the scattering layer toward the emitting layer, and the second hollow silica particle may be disposed on the top surface of the scattering layer and may have an exposed inner surface.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0046538, filed on April 10, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some exemplary embodiments of this disclosure relate herein to electronic devices and / or methods of manufacturing thereof, including a scattering layer comprising hollow silica particles. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing in various ways. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation systems, and smart TVs. Display devices include display panels that generate images, and these display panels can be organic light-emitting display panels. Organic light-emitting display panels include so-called self-emitting light-emitting elements, which achieve display by causing the light-emitting material of the emitting layer to emit light through the recombination of holes and electrons injected into the emitting layer from a first electrode and a second electrode. Considering the environment in which electronic devices are used, research is underway to improve the display quality of electronic devices. Summary of the Invention

[0005] Some exemplary embodiments of this disclosure provide electronic devices that offer improved display quality.

[0006] Some exemplary embodiments of this disclosure provide methods for manufacturing electronic devices that ensure improved manufacturability.

[0007] An exemplary embodiment of the present invention provides an electronic device including a display module. The display module includes a light-emitting element and a pixel-defining film including an opening. The light-emitting element includes a first electrode exposed through the opening, a scattering layer on the first electrode, an emitting layer on the scattering layer, and a second electrode on the emitting layer. The scattering layer includes a base portion and a plurality of hollow silica particles dispersed in the base portion. The plurality of hollow silica particles includes a first hollow silica particle and a second hollow silica particle. The first hollow silica particle is on the top surface of the scattering layer and protrudes from the top surface of the scattering layer toward the emitting layer. The top surface of the scattering layer is spaced apart from the first electrode. The second hollow silica particle is on the top surface of the scattering layer and has an exposed inner surface.

[0008] In an exemplary embodiment, the second hollow silica particles may include a plurality of second hollow silica particles, and the total surface area based on the top surface of the scattering layer is 100%, and the sum of the surface areas of the plurality of second hollow silica particles may be about 0.05% or greater and about 20% or less.

[0009] In an exemplary embodiment, each of the plurality of hollow silica particles may have a size of about 50 nm to about 200 nm.

[0010] In an exemplary embodiment, the total weight of the plurality of hollow silica particles may be about 0.5 wt% or more and about 15 wt% or less, based on the total weight of the scattering layer.

[0011] In an exemplary embodiment, the scattering layer may be located within an opening in the pixel-defined film.

[0012] In an exemplary embodiment, the light-emitting element may further include a metal layer disposed between the scattering layer and the emitting layer. The metal layer may include at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn and Zn; two or more compounds selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn and Zn; a mixture of two or more selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn and Zn; or an oxide of any one of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn and Zn.

[0013] In an exemplary embodiment, the metal layer may be directly on the scattering layer.

[0014] In an exemplary embodiment, the metal layer may have a thickness of about 200 Å to about 500 Å.

[0015] In an exemplary embodiment, the metal layer may be located within an opening in the pixel-defining film.

[0016] In an exemplary embodiment, the plurality of hollow silica particles may further include a third hollow silica particle that does not protrude from the top surface of the scattering layer toward the emitting layer and does not have an exposed inner surface.

[0017] In an exemplary embodiment, the base portion may include organic materials.

[0018] In an exemplary embodiment, the electronic device may further include at least one of a processor, a power supply circuit, and a memory.

[0019] In an exemplary embodiment of the present invention, a method for manufacturing an electronic device includes: preparing a base layer; forming a first electrode on the base layer; forming a pixel defining film having an opening through which the first electrode is exposed; forming a scattering layer on the first electrode; forming an emission layer on the scattering layer; and forming a second electrode on the emission layer. The forming of the scattering layer includes: forming a preliminary scattering layer on the first electrode, the preliminary scattering layer including a preliminary base portion and a plurality of preliminary hollow silica particles dispersed in the preliminary base portion; and treating the preliminary scattering layer with plasma to form the scattering layer. The scattering layer includes a base portion formed by the preliminary base portion and the plurality of preliminary hollow silica particles, and a plurality of hollow silica particles, wherein the plurality of hollow silica particles include a first hollow silica particle and a second hollow silica particle. The first hollow silica particle is disposed on the top surface of the scattering layer and protrudes from the top surface of the scattering layer toward the emission layer, the top surface of the scattering layer being spaced apart from the first electrode. The second hollow silica particle is disposed on the top surface of the scattering layer and has an exposed inner surface.

[0020] In an exemplary embodiment, the plasma may include fluorine plasma or oxygen plasma.

[0021] In an exemplary embodiment, the initial base portion can be etched during plasma processing.

[0022] In an exemplary embodiment, the total weight of the plurality of hollow silica particles may be about 0.5 wt% or more and about 15 wt% or less, based on the total weight of the scattering layer.

[0023] In an exemplary embodiment, each of the plurality of hollow silica particles may have a size of about 50 nm to about 200 nm.

[0024] In an exemplary embodiment, the initial scattering layer can be formed by inkjet printing or photolithography.

[0025] In an exemplary embodiment, the method may further include: forming a metal layer on the scattering layer after forming the scattering layer and before forming the emitting layer, wherein the metal layer may include at least one selected from the group consisting of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn, and at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, Two or more compounds selected from the group consisting of W, In, Sn and Zn; mixtures of two or more compounds selected from the group consisting of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn and Zn; or oxides selected from any one of the group consisting of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn and Zn.

[0026] In an exemplary embodiment, the method may further include performing an ashing process on the metal layer prior to forming the emitter layer. Attached Figure Description

[0027] The accompanying drawings, included to provide a further understanding of the inventive concept, are incorporated in and constitute a part of this specification. The drawings illustrate some exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings: Figure 1 This is a block diagram of an electronic device according to an exemplary embodiment; Figure 2 This is a view of an electronic device according to various exemplary embodiments; Figure 3 This is a perspective view of an electronic device according to an exemplary embodiment of the concept of the present invention; Figure 4 This is an exploded perspective view of an electronic device according to an exemplary embodiment of the concept of the present invention; Figure 5 It is along Figure 4 A sectional view taken by line I-I'; Figure 6 This is a plan view illustrating a portion of an electronic device according to an exemplary embodiment; Figure 7A This is a cross-sectional view showing a portion of an electronic device according to an exemplary embodiment; Figure 7B This is a perspective view showing a portion of an electronic device according to an exemplary embodiment; Figure 7CThis is a cross-sectional view showing a portion of an electronic device according to an exemplary embodiment; Figure 8A This is a flowchart illustrating a method for manufacturing an electronic device according to an exemplary embodiment; Figure 8B This is a flowchart illustrating a method for manufacturing an electronic device according to an exemplary embodiment; Figure 9 This is a diagram schematically illustrating the operation of manufacturing an electronic device according to an exemplary embodiment; Figure 10 This is a diagram schematically illustrating the steps for manufacturing an electronic device according to an exemplary embodiment; Figure 11 This is a diagram schematically illustrating steps for manufacturing an electronic device according to an exemplary embodiment; Figure 12 This is a diagram schematically illustrating steps for manufacturing an electronic device according to an exemplary embodiment; Figure 13 This is a diagram schematically illustrating the steps for manufacturing an electronic device according to an exemplary embodiment; Figure 14A This is an image showing a pixel-defined film in an experimental example; Figure 14B This is an image showing a pixel-defined film in an experimental example; Figure 14C This is an image showing a pixel-defined film in an experimental example; and Figure 14D This is an image showing a pixel-defined film in an experimental example. Detailed Implementation

[0028] Because this disclosure can be implemented with different modifications, specific exemplary embodiments are shown in the accompanying drawings and described in the detailed description of the inventive concept. However, this is not intended to limit this disclosure to the specific exemplary embodiments, and it should be understood that this disclosure covers all modifications, equivalents, and substitutions within the spirit and technical scope of this disclosure.

[0029] In this specification, it will also be understood that when a component (or area, layer, part) is referred to as being "on" another component, "connected" to another component, or "attached" to another component, it may be directly mounted on or directly connected to / attached to another component, or there may be an intermediary third component.

[0030] The same reference numerals always denote the same elements. Furthermore, in the drawings, the thickness, scale, and dimensions of parts are exaggerated for clarity. The term "and / or" includes any and all combinations of one or more of the related parts.

[0031] Terms such as "first" and "second" may be used to describe various components, but these components should not be limited by these terms. These terms are used only for the purpose of distinguishing one component, part, region, layer, or section from another component, part, region, layer, or section. For example, without departing from the scope of the inventive concept, a first component, first part, first region, first layer, or first section may be referred to as a second component, second part, second region, second layer, or second section, and similarly, a second component, second part, second region, second layer, or second section may be referred to as a first component, first part, first region, first layer, or first section. The singular form also includes the plural form, unless the context clearly indicates otherwise.

[0032] In addition, terms such as "below," "under," "above," and "upper" are used to explain the relationships between the components shown in the accompanying drawings. These terms can be relative concepts and are described based on the directions presented in the drawings.

[0033] It will be understood that, when used in this specification, the terms "include" or "comprise" mean the presence of the stated features, integrals, steps, operations, elements, components or combinations thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components or combinations thereof.

[0034] As used herein, when used with a list of elements, expressions such as “one of…”, “one or more of…”, “any one of…”, “at least one of…”, “selected from at least one of…”, and “selected from two or more of…” modify the entire list of elements rather than individual elements within it. Thus, for example, “at least one of A, B, and C” means A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0035] Although the terms “same,” “equal,” or “identical” are used in the description of exemplary embodiments, it should be understood that some inaccuracies may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that an element or value is identical to another element within the expected range of manufacturing or operational tolerances (e.g., ±10%).

[0036] When the terms “about,” “substantially,” or “approximately” are used in conjunction with numerical values ​​in this specification, the relevant numerical values ​​are intended to be included within manufacturing or operational tolerances (e.g., ±10%). Furthermore, when the terms “about,” “substantially,” or “approximately” are used in conjunction with geometry, it means that precision of the geometry is not required, but rather that the degree of freedom of the shape is within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified to “about” or “substantially,” it will be understood that such numerical values ​​and shapes should be interpreted as including the numerical values ​​or shapes within manufacturing or operational tolerances (e.g., ±10%).

[0037] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. Furthermore, terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted as having an overly ideal or formal meaning unless explicitly specified.

[0038] In the following description, some exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0039] Figure 1 This is a block diagram of an electronic device according to an exemplary embodiment. The electronic device EA may include a display module DM. The electronic device EA may also include at least one of a processor PR, a memory MR, and a power module (or power supply circuit) PM. Reference Figure 1 An electronic device EA according to an exemplary embodiment may include a display module (or display) DM, a processor PR, a memory MR, and a power module PM.

[0040] The processor PR may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0041] The memory MR can store the data information required for the operation of the processor PR or the display module DM. When the processor PR executes the application program stored in the memory MR, image data signals and / or input control signals can be transmitted to the display module DM, and the display module DM can process the received signals to output image information through the display screen.

[0042] The power module PM may include a power supply module such as a power adapter or battery device, and a power conversion module configured to convert the power supplied by the power supply module to generate the power required to operate the electronic device EA.

[0043] At least one of the components of the electronic device EA described above may be included in a display device according to the exemplary embodiments described below. Furthermore, a portion of a discrete module functionally included in a single module may be included in the display device, while another portion may be disposed separately from the display device. For example, the display device may include a display module DM, and the processor PR, memory MR, and power module PM may be disposed as other devices within the electronic device EA, rather than within the display device.

[0044] Figure 2 These are schematic diagrams of electronic devices according to various exemplary embodiments. (Reference) Figure 2 Various electronic devices that apply the display device according to the exemplary embodiments may include image display electronic devices (such as smartphones EA_1a, tablet PCs EA_1b, laptop computers EA_1c, televisions (TVs) EA_1d, and desktop displays EA_1e), wearable electronic devices including display modules (such as smart glasses EA_2a, head-mounted displays EA_2b, and smartwatches EA_2c), and vehicle electronic devices including display modules EA_3 (such as CIDs (central information displays) and interior mirror displays disposed on a vehicle's cluster, center fascia, or dashboard).

[0045] Figure 3 This is a perspective view of an electronic device according to an exemplary embodiment of the concept of the present invention. Figure 3 The electronic device EA in the exemplary embodiments shown can be a device activated by an electrical signal. For example, the electronic device EA can be a tablet PC, personal computer, laptop computer, personal digital assistant, game console, portable electronic device, television, monitor, outdoor billboard, in-vehicle navigation system, or wearable device, but the exemplary embodiments are not limited thereto. Figure 3 The image shows an example of a tablet PC as an electronic device EA.

[0046] Electronic device EA can provide an image IM to a user via a display surface EA-IS. The display surface EA-IS can be parallel to the plane defined by a first directional axis DR1 and a second directional axis DR2. Electronic device EA can display the image IM on a third directional axis DR3. The image IM can include dynamic images and / or static images. Figure 3 An electronic device EA with a flat display surface EA-IS is shown, but exemplary embodiments are not limited thereto. For example, the electronic device EA may include a curved display surface or a three-dimensional display surface. A three-dimensional display surface may include multiple display areas indicating different orientations.

[0047] The directions indicated as the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 in this specification can be relative concepts and therefore can be changed to different directions. Furthermore, the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 can be described as a first direction to a third direction, and the same reference numerals can be used.

[0048] In this specification, the first direction axis DR1 and the second direction axis DR2 may be perpendicular to each other. The third direction axis DR3 may be a normal direction relative to the plane defined by the first direction DR1 and the second direction DR2. The thickness direction of the electronic device EA may be parallel to the third direction axis DR3. The thickness direction of the electronic device EA may be indicated by the same reference numeral "DR3" as the third direction axis. The front surface (or top surface) and the rear surface (or bottom surface) may be opposite each other on the third direction axis DR3, and the normal directions of the front surface (or top surface) and the rear surface (or bottom surface) may be parallel to the third direction axis DR3. The front surface (or top surface) may refer to the surface adjacent to the display surface EA-IS, and the rear surface (or bottom surface) may refer to the surface spaced apart from the display surface EA-IS. The upper side may refer to the direction approaching the display surface EA-IS, and the lower side may refer to the direction away from the display surface EA-IS.

[0049] In this specification, a cross-sectional surface refers to a surface parallel to the thickness direction DR3. A planar surface refers to a surface perpendicular to the thickness direction DR3 and parallel to the plane defined by the first directional axis DR1 and the second directional axis DR2.

[0050] In this specification, when one component overlaps with another component, it means that they overlap in a plan view (e.g., in a plan drawing). Furthermore, the overlap between one component and another is not limited to cases where they have the same surface area and the same shape, but may include cases where they have different surface areas and / or different shapes.

[0051] In this specification, when a component is directly mounted on / provided on another component, it means that a third component is not inserted between the two components. In other words, when a component is directly mounted on / provided on another component, it means that the two components are in contact with each other.

[0052] An electronic device (EA) can detect external inputs applied from the outside. External inputs can include various types of inputs provided from outside the electronic device (EA). For example, external inputs can include not only contact made through a part of a person's body (such as a user's hand), but also external inputs applied by approaching or being near the electronic device (EA) at a desired distance (or alternatively, a predetermined distance) (e.g., hovering). Furthermore, external inputs can take various forms, such as force, pressure, temperature, or light.

[0053] The display surface EA-IS can include a display area EA-DA and a non-display area EA-NDA. The electronic device EA can display an image IM through the display area EA-DA.

[0054] The display area EA-DA can be an area activated by an electrical signal. The display area EA-DA can be an area where an image IM is displayed and various types of external inputs can be sensed.

[0055] The display area EA-DA may include a plane defined by a first direction axis DR1 and a second direction axis DR2. Unlike the example shown, the display area EA-DA may include a curved surface that bends from at least one side of the plane defined by the first direction axis DR1 and the second direction axis DR2. For example, the display area EA-DA may also include four curved surfaces that bend from all four sides of the plane defined by the first direction axis DR1 and the second direction axis DR2, respectively.

[0056] The electronic device EA in an exemplary embodiment can be flexible. "Flexible" means having a bendable characteristic and can include any structure, from a fully foldable structure to one capable of bending at a level of several nanometers. For example, the electronic device EA can be a rigid device. In some exemplary embodiments, the electronic device EA can be a foldable device.

[0057] The non-display area EA-NDA can have a desired color (or, optionally, a predetermined color). The non-display area EA-NDA can be an area adjacent to the display area EA-DA. The non-display area EA-NDA can surround the display area EA-DA. Therefore, the shape of the display area EA-DA can be substantially defined by the non-display area EA-NDA. However, Figure 3 This is merely an illustrative example, and the non-display area EA-NDA may be configured to be adjacent only to one side of the display area EA-DA, or it may be omitted. The display area EA-DA may be provided in various shapes and is not limited to any one exemplary embodiment.

[0058] Figure 4 This is an exploded perspective view of an electronic device according to an exemplary embodiment of the concept of the present invention. (Reference) Figure 4The electronic device EA may include a display device DD. Additionally, the electronic device EA may also include a window component WM and a housing HAU.

[0059] A window component WM can be disposed on the display device DD. The window component WM can cover the entire outer side of the electronic device EA. The window component WM can include a transmissive area TA and a bezel area BZA. The front surface of the window component WM, including the transmissive area TA and the bezel area BZA, can correspond to the front surface of the electronic device EA. The transmissive area TA can correspond to... Figure 3 The electronic device EA shown has a display area EA-DA, and the border area BZA can correspond to... Figure 3 The non-display area EA-NDA of the electronic device EA shown.

[0060] The transmissive region TA can be an optically transparent region. The border region BZA can be a region whose light transmittance is relatively less than that of the transmissive region TA. The border region BZA can have a desired color (or, optionally, a predetermined color). The border region BZA can be configured to be adjacent to and surround the transmissive region TA. The border region BZA can define the shape of the transmissive region TA. However, exemplary embodiments are not limited to those shown, and the border region BZA can be configured to be adjacent only to one side of the transmissive region TA, or a portion of the border region BZA can be omitted.

[0061] The housing HAU may comprise a material with relatively high rigidity. For example, the housing HAU may comprise a frame and / or panel made of glass, plastic, or metal. Multiple frames and / or panels may be provided. The housing HAU provides the desired (or alternatively, a predetermined) housing space. The display device DD can be housed within this housing space and protected from external impacts.

[0062] The display device DD may include a display module DM and an optical layer PP disposed on the display module DM. The display module DM can be activated according to an electrical signal and can provide an image IM (see [link]). Figure 3 The display module DM can be activated to display the electronic device EA in the display area EA-DA (see...). Figure 3 The image IM is displayed in (see) Figure 3 The effective area DM-AA and the ineffective area DM-NAA can be defined in the display module DM.

[0063] The active region DM-AA can be a region activated by an electrical signal. Pixels (not shown) can be set within the active region DM-AA. Pixels may include transistors TR (see [link to relevant documentation]). Figure 7A ) and light-emitting elements (ED) (see Figure 7AThe inactive region DM-NAA can be a region positioned adjacent to at least one side of the active region DM-AA. Circuitry or wiring for driving the active region DM-AA can be provided within the inactive region DM-NAA.

[0064] The optical layer PP can be a layer that reduces reflectivity due to external light incident from the outside. Furthermore, the optical layer PP can transmit source light emitted from the display module DM or convert the wavelength of the source light. The optical layer PP can be disposed on the display module DM through a continuous process. The optical layer PP may include a polarizer or may include a color filter layer. For example, the optical layer PP may include at least one of a retarder, a polarizer, a polarizing film, and a polarizing filter. In some exemplary embodiments, the optical layer PP may include a plurality of color filters arranged in a desired pattern (or optionally, a predetermined pattern), and a black matrix adjacent to the color filters. Unlike what is shown, the optical layer PP may be omitted.

[0065] Figure 5 It is along Figure 4 A sectional view taken by line I-I'. Figure 5 It may be a cross-sectional view showing a display module DM according to an exemplary embodiment.

[0066] refer to Figure 5 The display module DM may include a display panel DP and an input sensing layer TP disposed on the display panel DP. The display panel DP may include a base layer BS, a circuit layer DP-CL disposed on the base layer BS, a display element layer DP-EL disposed on the circuit layer DP-CL, and a packaging layer TFE disposed on the display element layer DP-EL.

[0067] The display panel DP can be the configuration that actually generates the image. The display panel DP can be a light-emitting display panel. For example, the display panel DP can be an organic light-emitting display panel. In some exemplary embodiments, the display panel DP can be a quantum dot light-emitting display panel that includes quantum dot light-emitting elements. The display panel DP can emit source light.

[0068] The base layer BS can be a component that provides a base surface on which the circuit layer DP-CL is disposed. The base layer BS can be a rigid substrate or a flexible substrate that can withstand bending, folding, or rolling. The base layer BS can be a glass substrate, a metal substrate, or a polymer substrate. However, exemplary embodiments are not limited thereto, and the base layer BS can be an inorganic layer, an organic layer, or a composite material layer.

[0069] The DP-CL circuit layer can be disposed on the base layer BS. The DP-CL circuit layer may include insulating layers, semiconductor patterns, conductive patterns, and signal lines. After the insulating layer, semiconductor layer, and conductive layer are disposed on the base layer BS through coating, deposition, or other processes, the insulating layer, semiconductor layer, and conductive layer can be selectively patterned using multiple photolithography processes. Subsequently, semiconductor patterns, conductive patterns, and signal lines included in the DP-CL circuit layer can be provided.

[0070] The display element layer DP-EL can be disposed on the circuit layer DP-CL. The display element layer DP-EL may include the pixel defining film PDL, which will be described later (see [link to PDL]). Figure 7A ) and light-emitting elements (ED) (see Figure 7A In the display module DM, the light-emitting element ED (see...) Figure 7A It can emit source light. For example, the display element layer DP-EL can include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic hybrid light-emitting materials, quantum dots, or quantum rods. For example, the display element layer DP-EL can include micron-LEDs or nano-LEDs.

[0071] The TFE encapsulation layer protects the display element layer (DP-EL) from foreign matter such as moisture, oxygen, and / or dust particles. The TFE encapsulation layer may include at least one inorganic layer. The TFE encapsulation layer may include a structure in which inorganic layers, organic layers, and inorganic layers are sequentially stacked.

[0072] The input sensing layer TP can detect external input, convert the input into a desired input signal (or optionally, a predetermined input signal), and provide the input signal to the display panel DP. For example, the input sensing layer TP can be a touch sensing layer that detects touch. The input sensing layer TP can recognize direct touch from the user, indirect touch from the user, direct touch from an object, and / or indirect touch from an object.

[0073] The input sensing layer TP can detect at least one of the location of a touch and the intensity (pressure) of a touch applied from the outside. The input sensing layer TP can have various structures or be made of various materials, and is not limited to any one exemplary embodiment. For example, the input sensing layer TP can detect external input using a capacitive method. The display panel DP can receive input signals from the input sensing layer TP and can generate an image corresponding to the input signals.

[0074] Figure 6 This is an enlarged plan view showing a portion of the effective area according to an exemplary embodiment. Reference Figure 6 The effective area DM-AA can include a light-emitting area PXA and a light-blocking area NPXA. The light-blocking area NPXA can surround the light-emitting area PXA.

[0075] The emitting region PXA can be configured as multiple emitting regions that emit light in different wavelength ranges. The emitting region PXA may include a first emitting region PXA-B, a second emitting region PXA-G, and a third emitting region PXA-R. For example, the first emitting region PXA-B may emit blue light, the second emitting region PXA-G may emit green light, and the third emitting region PXA-R may emit red light. However, the exemplary implementation is not limited thereto, and the first emitting region PXA-B, the second emitting region PXA-G, and the third emitting region PXA-R may emit light of colors other than blue, green, and red.

[0076] In the emitting region PXA, the surface area of ​​the first emitting region PXA-B, which emits blue light, can be the largest, and the surface area of ​​the second emitting region PXA-G, which emits green light, can be the smallest. Here, surface area refers to the surface area of ​​a plane. However, this is only an example, and the surface areas of the first emitting region PXA-B, the second emitting region PXA-G, and the third emitting region PXA-R are not limited to this.

[0077] exist Figure 6 In the first row, the first luminous region PXA-B and the third luminous region PXA-R are arranged alternately along the second direction DR2, and the second luminous region PXA-G is arranged in the second row, spaced apart from the first luminous region PXA-B and the third luminous region PXA-R. However, this is only an example, and the arrangement of the first luminous region PXA-B, the second luminous region PXA-G, and the third luminous region PXA-R is not limited to this. Furthermore, the planar shapes of the first luminous region PXA-B, the second luminous region PXA-G, and the third luminous region PXA-R are not limited to those shown, and can be defined in different shapes.

[0078] The light-blocking region NPXA can be the region between adjacent light-emitting regions PXA-B, PXA-G, and PXA-R, and can correspond to the pixel-defined film PDL, which will be described later (see [link to PXA-B]). Figure 7A The light-emitting region PXA can correspond to the light-emitting element ED, which will be described later (see [link]). Figure 7A ).

[0079] Figure 7A This is a cross-sectional view specifically illustrating a display device DD according to an exemplary embodiment. Figure 7A It can also correspond to Figure 6 The diagram shows a cross-sectional view of the second emitting region PXA-G and the adjacent light-blocking region NPXA. In the following text, the description of the second emitting region PXA-G can be applied similarly. Figure 6 The first luminescent region PXA-B and the third luminescent region PXA-R are shown.

[0080] refer to Figure 7A The base layer BS may comprise a single-layer or multi-layer structure. For example, the base layer BS may comprise a first synthetic resin layer, multiple or a single inorganic layer, and a second synthetic resin layer disposed on the multiple or single inorganic layer. Each of the first and second synthetic resin layers may comprise a polyimide-based resin. Furthermore, each of the first and second synthetic resin layers may comprise at least one of the following: acrylic acid-based resin, methacrylic acid-based resin, polyisoprene-based resin, vinyl-based resin, epoxy-based resin, urethane-based resin, cellulose-based resin, siloxane-based resin, polyamide-based resin, and dinaphthalene-based resin. In this specification, "based on" resin means containing the "~~" functional group.

[0081] The display panel (DP) may include transistors (TR) and light-emitting elements (ED). The transistors (TR) and ED can be disposed on the base layer (BS). Although in Figure 7A Only one transistor TR is shown in the image, but the display panel DP can essentially include multiple transistors for driving the light-emitting element ED and at least one capacitor.

[0082] The circuit layer DP-CL may include an insulating layer, semiconductor patterns, conductive patterns, and signal lines. For example, the circuit layer DP-CL may include switching transistors and driving transistors for driving the light-emitting elements ED of the display element layer DP-EL.

[0083] The circuit layer DP-CL may include a shielding electrode BML, a transistor TR, a connection electrode CNE, and multiple insulating layers BFL and INS1 to INS6. The multiple insulating layers BFL and INS1 to INS6 may include a buffer layer BFL and first insulating layers INS1 to sixth insulating layers INS6. However, Figure 7A The stack-up structure of the DP-CL circuit layer shown is illustrative only, and the stack-up structure of the DP-CL circuit layer can vary depending on the configuration of the display panel DP or the manufacturing process of the DP-CL circuit layer.

[0084] A shielding electrode BML can be disposed on the base layer BS. The shielding electrode BML can overlap with the transistor TR. The shielding electrode BML protects the transistor TR by blocking light incident on it from the lower portion of the display panel DP. The shielding electrode BML may include a conductive material. When a voltage is applied to the shielding electrode BML, the threshold voltage of the transistor TR disposed on the shielding electrode BML can be maintained. However, exemplary embodiments are not limited thereto, and the shielding electrode BML can be a floating electrode. The shielding electrode BML may be omitted.

[0085] A buffer layer BFL can be disposed on the base layer BS to cover the shielding electrode BML. The buffer layer BFL may include an inorganic layer. The buffer layer BFL can enhance the adhesion between the semiconductor pattern or conductive pattern disposed on the buffer layer BFL and the base layer BS.

[0086] A transistor TR may include a source S1, a channel C1, a drain D1, and a gate G1. The source S1, channel C1, and drain D1 of the transistor TR may be provided from a semiconductor pattern. The semiconductor pattern of the transistor TR may include polycrystalline silicon, amorphous silicon, or metal oxide, and any material may be used without limitation if the semiconductor pattern has any semiconductor properties, and the material of the semiconductor pattern is not limited to any one of them.

[0087] Semiconductor patterns can include multiple regions, which are distinguished by their conductivity levels. In a semiconductor pattern, doped regions, either doped with a dopant or regions where the metal oxide is reduced, can have relatively high conductivity and can essentially serve as the source and drain electrodes of a transistor TR. Relatively heavily doped regions in a semiconductor pattern can correspond to the source S1 and drain D1 of a transistor TR. Undoped regions, relatively lightly doped regions, or regions where the metal oxide remains unreduced and the semiconductor pattern has relatively low conductivity can correspond to the channel C1 (or active region) of a transistor TR.

[0088] The first insulating layer INS1 can cover the semiconductor pattern of the transistor TR and can be disposed on the buffer layer BFL. The gate G1 of the transistor TR can be disposed on the first insulating layer INS1. In a plan view, the gate G1 can overlap with the channel C1 of the transistor TR. In the process of doping the semiconductor pattern of the transistor TR, the gate G1 can be used as a mask.

[0089] The second insulating layer INS2 can cover the gate G1 and can be disposed on the first insulating layer INS1. The third insulating layer INS3 can be disposed on the second insulating layer INS2.

[0090] The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 for electrically connecting the transistor TR and the light-emitting element ED. However, the configuration of the connection electrode CNE for electrically connecting the transistor TR and the light-emitting element ED is not limited thereto, and the first connection electrode CNE1 or the second connection electrode CNE2 may be omitted, or additional connection electrodes may be further included.

[0091] The first connecting electrode CNE1 can be disposed on the third insulating layer INS3. The first connecting electrode CNE1 can be connected to the drain electrode D1 through the first contact hole CH1 passing through the first insulating layer INS1 to the third insulating layer INS3. The fourth insulating layer INS4 can cover the first connecting electrode CNE1 and can be disposed on the third insulating layer INS3. The fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4.

[0092] The second connecting electrode CNE2 can be disposed on the fifth insulating layer INS5. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the second contact hole CH2 passing through the fourth insulating layer INS4 and the fifth insulating layer INS5. The sixth insulating layer INS6 can cover the second connecting electrode CNE2 and can be disposed on the fifth insulating layer INS5.

[0093] Each of the first insulating layer INS1 to the sixth insulating layer INS6 may include an inorganic layer or an organic layer. For example, the inorganic layer may include at least one of alumina, titanium dioxide, silicon dioxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and poly(p-phenylene dimethyl) resin.

[0094] The display element layer DP-EL may include a pixel defining film PDL and a light-emitting element ED. The pixel defining film PDL may be disposed on a sixth insulating layer INS6. The pixel defining film PDL may define an opening PX_OP that exposes a portion of the first electrode AE. The portion of the first electrode AE ​​exposed through the opening PX_OP may be defined as a second light-emitting region PXA-G. The area in which the pixel defining film PDL is disposed may correspond to a light-blocking region NPXA.

[0095] Pixel defining film (PDL) can be made of polymer resin. For example, PDL can include a polyacrylate-based resin or a polyimide-based resin. Furthermore, PDL can also include inorganic materials in addition to polymer resin. Pixel defining film PDL can be provided by including light-absorbing materials or by including black pigments or black dyes. Pixel defining film PDL including black pigments or black dyes can achieve a black pixel defining film. Carbon black can be used as the black pigment or black dye for forming the pixel defining film PDL, but exemplary embodiments are not limited to this.

[0096] Furthermore, the pixel-defining film (PDL) can be composed of or include inorganic materials. For example, the pixel-defining film (PDL) can be made of materials such as silicon nitride (SiN). x ), silicon dioxide (SiO) x) or silicon oxynitride (SiO) x N y It is composed of inorganic materials.

[0097] Light-emitting elements (EDs) allow for Lambertian reflection. Lambertian reflection refers to the phenomenon where the brightness remains constant regardless of the observer's viewing angle.

[0098] A light-emitting element (ED) may include a first electrode AE, a scattering layer STL disposed on the first electrode AE, an emitting layer EML disposed on the scattering layer STL, and a second electrode CE disposed on the emitting layer EML. The ED may also include a hole transport region HTR disposed between the scattering layer STL and the emitting layer EML, and an electron transport region ETR disposed between the emitting layer EML and the second electrode CE. As an example, the first electrode AE ​​of the ED can be connected to a second connecting electrode CNE2 via a third contact hole CH3 passing through the sixth insulating layer INS6, thereby connecting to the transistor TR.

[0099] The first electrode AE ​​can be made of a metallic material, a metallic alloy, or a conductive compound. The first electrode AE ​​can be an anode or a cathode. However, exemplary embodiments of the present invention are not limited thereto. Furthermore, the first electrode AE ​​can be a pixel electrode. The first electrode AE ​​can be a transmission electrode, a semi-transmission / semi-reflection electrode, or a reflection electrode. The first electrode AE ​​can include at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, and Zn (or can include at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, and Zn), a compound selected from two or more of these, a mixture selected from two or more of these, or an oxide of any one of these. The first electrode AE ​​can also include LiF or a mixture of LiF and at least one of the above materials.

[0100] When the first electrode AE ​​is a transmissive electrode, it may comprise a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). When the first electrode AE ​​is a transmissive / reflective electrode or a reflective electrode, it may comprise Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg) or a material having a multilayer structure such as LiF / Ca (a stacked structure of LiF and Ca) or LiF / Al (a stacked structure of LiF and Al). In some exemplary embodiments, the first electrode AE ​​may have a multilayer structure, comprising a reflective layer or a transmissive / reflective layer and a transparent conductive layer made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). For example, the first electrode AE ​​may have a three-layer structure of ITO / Ag / ITO, but is not limited thereto. Furthermore, the exemplary embodiments are not limited thereto, and the first electrode AE ​​may include the metallic materials described above, a combination of two or more metallic materials described above, or an oxide of the metallic materials described above. The first electrode AE ​​may have a thickness in the range of about 700 Å to about 10000 Å. For example, the thickness of the first electrode AE ​​may be in the range of about 1000 Å to about 3000 Å.

[0101] The scattering layer STL can be disposed in the opening PX_OP of the pixel-defining film PDL. The scattering layer STL can be in contact with the inner surface of the defining opening PX_OP of the pixel-defining film PDL. For example, in the thickness direction DR3, the scattering layer STL can have a thickness in the range of about 200 nm to about 1000 nm.

[0102] In one exemplary embodiment, the scattering layer STL may include a base portion BP and a plurality of hollow silica particles SP dispersed in the base portion BP. The base portion BP may be optically transparent. The base portion BP may serve as a medium in which the hollow silica particles SP are dispersed, and may be made of or comprise various resin compositions. The base portion BP may include organic materials. For example, the base portion BP may include acrylic resin. However, this is merely an example, and the base portion BP may be composed of any optically transparent organic material that allows for easy dispersion of the hollow silica particles SP.

[0103] Light incident on the scattering layer STL can be scattered by hollow silica particles SP. The hollow silica particles SP can be used as scattering elements. The hollow silica particles SP may include a first hollow silica particle PT1 and a second hollow silica particle PT2. The first hollow silica particle PT1 and the second hollow silica particle PT2 can be located at the top surface ST_UF of the scattering layer STL.

[0104] The scattering layer STL can be directly disposed on the first electrode AE. The scattering layer STL may include a top surface ST_UF and a bottom surface ST_DF. The top surface ST_UF and the bottom surface ST_DF may be integrally formed. The top surface ST_UF and the bottom surface ST_DF may face each other in the thickness direction DR3. The top surface ST_UF may be spaced apart from the first electrode AE. The bottom surface ST_DF may be disposed between the top surface ST_UF and the first electrode AE. The bottom surface ST_DF may be spaced apart from the emitter layer EML. The top surface ST_UF may be disposed between the bottom surface ST_DF and the emitter layer EML. The first hollow silica particle PT1 and the second hollow silica particle PT2 may not be located at the bottom surface ST_DF of the scattering layer STL.

[0105] Along the thickness direction DR3, the scattering layer STL can be divided into a first part, a second part, and a third part. The first part may include the top surface ST_UF of the scattering layer STL. The second part may include the bottom surface ST_DF of the scattering layer STL. The third part may be located between the first and second parts and may not include the top surface ST_UF or the bottom surface ST_DF. The first hollow silica particle PT1 and the second hollow silica particle PT2 may be present in the first part and may not be present in the second or third part. The third hollow silica particle PT3, which will be described later, may be present in at least one of the first to third parts.

[0106] Figure 7B This is a schematic perspective view of a scattering layer according to an exemplary embodiment. (Reference) Figure 7A and Figure 7BA first hollow silica particle PT1 can protrude from the top surface ST_UF of the scattering layer STL toward the emitter layer EML. In hollow silica particles SP, a hollow silica particle located at the top surface ST_UF of the scattering layer STL and protruding toward the emitter layer EML can be defined as the first hollow silica particle PT1. The first hollow silica particle PT1 can partially protrude toward the emitter layer EML. A portion of the first hollow silica particle PT1 can be located outside the top surface ST_UF of the scattering layer STL. A portion of the surface of the first hollow silica particle PT1 can be located outside the top surface ST_UF of the scattering layer STL. The portion of the first hollow silica particle PT1 protruding toward the emitter layer EML can be connected to components directly disposed on the scattering layer STL (e.g., hole transport region HTR or metal layer AML (see...)). Figure 7C A portion of the surface of the first hollow silica particle PT1 may come into contact with components directly disposed on the scattering layer STL (e.g., the hole transport region HTR or the metal layer AML (see...)). Figure 7C ))touch.

[0107] The second hollow silica particle PT2 may have an exposed inner surface due to partial fracture of the outer surface. In hollow silica particles SP, a hollow silica particle located at the top surface ST_UF of the scattering layer STL and having an exposed inner surface due to partial fracture of the outer surface can be defined as the second hollow silica particle PT2. This includes components directly disposed on the scattering layer STL (e.g., hole transport region HTR or metal layer AML (see...)). Figure 7C The material in the second hollow silica particle PT2 may be present on the exposed inner surface of the second hollow silica particle PT2. In some exemplary embodiments, the exposed inner surface of the second hollow silica particle PT2 may be empty.

[0108] The hollow silica particles SP may also include a third hollow silica particle PT3. The third hollow silica particle PT3 neither protrudes toward the emitter layer EML nor has an exposed inner surface. In the hollow silica particles SP, a hollow silica particle that does not protrude toward the emitter layer EML and does not have an exposed inner surface can be defined as a third hollow silica particle PT3. Multiple third hollow silica particles PT3 can be provided, and they can be dispersed in the scattering layer STL. A portion of the third hollow silica particle PT3 can be positioned adjacent to the top surface ST_UF of the scattering layer STL.

[0109] Multiple first hollow silica particles PT1 and second hollow silica particles PT2 can be provided. These particles can be irregularly located on the top surface ST_UF of the scattering layer STL. On the top surface ST_UF of the scattering layer STL, the first hollow silica particles PT1 and / or the second hollow silica particles PT2 can exist in one region, and they can be absent in another region. The roughness of the region containing the first hollow silica particles PT1 and / or the second hollow silica particles PT2 can differ from the roughness of the region where they are absent. Therefore, the top surface ST_UF of the scattering layer STL can have a non-uniform roughness. Furthermore, a third hollow silica particle PT3, positioned adjacent to the top surface ST_UF of the scattering layer STL, can be mixed with the first hollow silica particle PT1 and the second hollow silica particle PT2 to further enhance the non-uniform roughness of the scattering layer STL. The scattering layer STL including the top surface ST_UF with non-uniform roughness can reduce the reflection and diffraction of external light, enhance light extraction efficiency, and / or improve brightness variation according to viewing angle. Brightness variation according to viewing angle refers to the phenomenon that brightness changes depending on the position of the emitting surface being observed. In other words, it can represent a phenomenon where the brightness is lower when viewed from a side angle compared to when viewed directly from the front. The first hollow silica particle PT1, the second hollow silica particle PT2, and the third hollow silica particle PT3 can reduce (or minimize) the reflection and diffraction of external light, enhance light extraction efficiency, and / or improve brightness variation according to viewing angle. Therefore, an electronic device EA including the scattering layer STL according to an exemplary embodiment (see...) Figure 4 It can have improved display quality.

[0110] Multiple second hollow silica particles PT2 can be provided. The total surface area of ​​the top surface ST_UF based on the scattering layer STL is 100%, and the total surface area of ​​the second hollow silica particles PT2 can range from 0.05% to 20%. Surface area refers to the surface area of ​​a plane. When the sum of the surface areas of the second hollow silica particles PT2 is less than approximately 0.05% (the total surface area of ​​the top surface ST_UF based on the scattering layer STL is 100%), it is not easy to reduce (or minimize) the reflection and diffraction of external light. When the total surface area of ​​the top surface ST_UF based on the scattering layer STL is 100%, and the sum of the surface areas of the second hollow silica particles PT2 exceeds approximately 20%, the light extraction efficiency is not improved, and the durability of the scattering layer STL deteriorates. Conversely, in one exemplary embodiment, the total surface area of ​​the top surface ST_UF of the scattering layer STL is 100%, wherein the sum of the surface areas of the second hollow silica particles PT2 is about 0.05% to about 20%. The scattering layer STL can provide improved durability, can prevent or minimize the reflection and diffraction of external light, can improve light extraction efficiency, and / or can improve brightness variation according to viewing angle.

[0111] Refer again Figure 7A Each of the hollow silica particles SP can have a size ranging from about 50 nm to about 200 nm. The size of the hollow silica particle SP can represent the length of the hollow silica particle SP in a cross-sectional view (or plan view). The size can represent the diameter of the hollow silica particle SP. When the size of the hollow silica particle SP is less than about 50 nm, it is not easy to reduce (or minimize) the reflection and diffraction of external light. When the size of the hollow silica particle SP exceeds about 200 nm, the durability of the scattering layer STL may deteriorate, and it may therefore be difficult to provide such particles during the formation of the scattering layer STL, thereby reducing manufacturing efficiency. Conversely, in an exemplary embodiment, a scattering layer STL including hollow silica particle SP having a size ranging from about 50 nm to about 200 nm can be manufactured relatively easily and is able to reduce (or minimize) the reflection and diffraction of external light.

[0112] The total weight of the scattering layer STL is 100 wt%, and the total weight of the hollow silica particles SP can range from about 0.5 wt% to about 15 wt%. A scattering layer STL including hollow silica particles SP with a total weight ranging from about 0.5 wt% to about 15 wt% (based on a total weight of 100 wt% for the scattering layer STL) can exhibit improved durability, reduced (or minimized) reflection and diffraction of external light, enhanced light extraction efficiency, and / or improved brightness variation according to viewing angle.

[0113] The hole transport region (HTR) can be disposed on the scattering layer (STL) and the pixel-defined film (PDL). The HTR can be disposed as a common layer overlapping the second emitting region (PXA-G) and the light-blocking region (NPXA). The HTR can include at least one of a hole transport layer, a hole injection layer, and an electron blocking layer. The HTR can include known hole injection materials and / or known hole transport materials. For example, the HTR can have a thickness in the range of about 50 Å to about 15000 Å.

[0114] The emission layer EML can be disposed on the hole transport region HTR. The emission layer EML can be disposed in the region corresponding to the opening PX_OP. In some exemplary embodiments, the emission layer EML can be disposed as a common layer. The emission layer EML can include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, or quantum rods. The emission layer EML can emit light of any color, including red, green, and blue. For example, the emission layer EML overlapping the second light-emitting region PXA-G can emit green light.

[0115] For example, the emitter layer EML can have a thickness of about 100 Å to about 1000 Å, or about 100 Å to about 300 Å. The emitter layer EML can have a monolayer structure comprising a single material, a monolayer structure comprising different materials from each other, or a multilayer structure comprising multiple layers comprising different materials from each other.

[0116] The electron transport region (ETR) can be disposed on the emitter layer (EML) and the pixel-defining film (PDL). The ETR can be disposed as a common layer overlapping the second emitting region (PXA-G) and the light-blocking region (NPXA). The ETR can include at least one of an electron transport layer, an electron injection layer, and a hole blocking layer. The ETR can include known electron injection materials and / or known electron transport materials. For example, the ETR can have a thickness of about 1000 Å to about 1500 Å.

[0117] The second electrode CE can be disposed on the electron transport region ETR and the pixel defining film PDL. The second electrode CE can be disposed as a common layer overlapping the second light-emitting region PXA-G and the light-blocking region NPXA.

[0118] The second electrode CE can be a common electrode. The second electrode CE can be a cathode or an anode, but the exemplary embodiments are not limited thereto. For example, when the first electrode AE ​​is an anode, the second electrode CE can be a cathode, and when the first electrode AE ​​is a cathode, the second electrode CE can be an anode.

[0119] The second electrode CE can be a transmission electrode, a semi-transmission / semi-reflection electrode, or a reflection electrode. When the second electrode CE is a transmission electrode, the second electrode CE can be made of or include a metal oxide (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)).

[0120] When the second electrode CE is a semi-transmissive / semi-reflective electrode or a reflective electrode, the second electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, Yb, W, or compounds or mixtures thereof (e.g., AgMg, AgYb, or MgYb) or materials having a multilayer structure such as LiF / Ca or LiF / Al. In some exemplary embodiments, the second electrode CE may have a multilayer structure, including a reflective layer or a semi-transmissive / semi-reflective layer and a transparent conductive layer, said transparent conductive layer being made of or including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). For example, the second electrode CE may include the metallic materials described above, combinations of two or more of the metallic materials described above, or oxides of the metallic materials described above.

[0121] The encapsulation layer TFE can be disposed on the display element layer DP-EL. The encapsulation layer TFE can also be disposed on the second electrode CE to cover the light-emitting element ED. The encapsulation layer TFE protects the display element layer DP-EL from foreign matter such as moisture, oxygen, and / or dust particles. The encapsulation layer TFE may comprise multiple thin films.

[0122] The encapsulation layer TFE may include at least one inorganic film. For example, the encapsulation layer TFE may include multiple inorganic films disposed on the second electrode CE and an organic film disposed between the inorganic films. The inorganic film can protect the light-emitting element ED from moisture / oxygen, and the organic film can protect the light-emitting element ED from foreign matter such as dust particles.

[0123] The input sensing layer TP can be disposed on the display panel DP. For example, the input sensing layer TP can be directly disposed on the encapsulation layer TFE of the display panel DP. In some exemplary embodiments, an adhesive layer can be disposed between the input sensing layer TP and the display panel DP.

[0124] The input sensing layer TP may include a first sensing insulating layer IL1, a second sensing insulating layer IL2, and a third sensing insulating layer IL3. The input sensing layer TP may include at least one conductive layer disposed on the sensing insulating layers IL1 and IL2. The input sensing layer TP may include a first conductive layer CDL1 and a second conductive layer CDL2.

[0125] A first sensing insulating layer IL1 may be disposed on the encapsulation layer TFE. The first sensing insulating layer IL1 may include at least one inorganic insulating layer. The first sensing insulating layer IL1 may be in contact with the encapsulation layer TFE. Alternatively, the first sensing insulating layer IL1 may be omitted, in which case the first conductive layer CDL1 may be in contact with the encapsulation layer TFE.

[0126] A first conductive layer CDL1 may be disposed on a first sensing insulating layer IL1. The first conductive layer CDL1 may include a plurality of first conductive patterns. The plurality of first conductive patterns may be disposed on the first sensing insulating layer IL1. A second sensing insulating layer IL2 may be disposed on the first sensing insulating layer IL1 to cover at least a portion of the first conductive layer CDL1.

[0127] A second conductive layer CDL2 may be disposed on a second sensing insulating layer IL2. The second conductive layer CDL2 may include a plurality of second conductive patterns. The plurality of second conductive patterns may be disposed on the second sensing insulating layer IL2. Each of the plurality of second conductive patterns may be connected to a plurality of first conductive patterns through a contact hole defined in the second sensing insulating layer IL2.

[0128] Each of the plurality of first conductive patterns in the first conductive layer CDL1 and the plurality of second conductive patterns in the second conductive layer CDL2 may correspond to a light-blocking region NPXA. Each of the plurality of first conductive patterns in the first conductive layer CDL1 and the plurality of second conductive patterns in the second conductive layer CDL2 may be a grid pattern.

[0129] The third sensing insulating layer IL3 may be disposed on the second sensing insulating layer IL2 and may cover the second conductive layer CDL2. Each of the second sensing insulating layer IL2 and the third sensing insulating layer IL3 may include an inorganic insulating layer or an organic insulating layer.

[0130] Each of the first conductive layer CDL1 and the second conductive layer CDL2 may have a monolayer structure or a multilayer structure stacked along the third direction DR3. Conductive layers CDL1 and CDL2 (each having a monolayer structure) may include a conductive metal layer or a transparent conductive layer. The conductive metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). Furthermore, the transparent conductive layer may include conductive polymers such as poly(3,4-ethylenedioxythiophene (PEDOT)), metal nanowires, graphene, etc.

[0131] The multilayer conductive layers CDL1 and CDL2 may include conductive metal layers. The conductive metal layers may have a three-layer structure, such as titanium (Ti) / aluminum (Al) / titanium (Ti). The multilayer conductive layers CDL1 and CDL2 may include at least one conductive metal layer and at least one transparent conductive layer.

[0132] An optical layer PP can be disposed on the input sensing layer TP. The optical layer PP may include a patterned portion BM and a color filter CF. The patterned portion BM may define a sub-aperture B_OP. The color filter CF may be configured to fill the sub-aperture B_OP. In addition, the optical layer PP may also include an outer coating OC disposed on the patterned portion BM and the color filter CF.

[0133] The patterned portion BM may overlap with the light-blocking region NPXA, but may not overlap with the second emitting region PXA-G. The material constituting the patterned portion BM can be used without restriction, as long as it is a light-absorbing material. The patterned portion BM may be black and may include a black colorant. The black colorant may include black dyes and / or black pigments. The black colorant may include carbon black, metals such as chromium, or oxides thereof.

[0134] A color filter CF can be configured to correspond to an emissive layer EML. The color filter CF may include pigments or dyes. For example, a color filter CF corresponding to an emissive layer EML that emits green light may include green pigments or green dyes. A color filter CF corresponding to an emissive layer EML that emits green light can be a green color filter. An optical layer PP including a color filter CF containing pigments or dyes can improve the display quality of the display device DD. (See also: Display device DD) Figure 4 Electronic devices (EAs) can provide improved display quality.

[0135] The outer coating OC can cover the patterned portion BM and the color filter CF. The outer coating OC can include organic materials. The outer coating OC can be a planarization layer.

[0136] Figure 7CThis is a cross-sectional view illustrating another exemplary embodiment of a display device according to the concept of the present invention. Figure 7C The following description will not repeat the reference. Figures 1 to 7B The descriptions will overlap, and the main focus will be on the differences.

[0137] and Figure 7A Compared to the display device DD shown, Figure 7C The difference in the display device DD-a shown is that the light-emitting element ED-a also includes a metal layer AML. The light-emitting element ED-a may also include a metal layer AML disposed between the scattering layer STL and the emitting layer EML. More specifically, the metal layer AML may be disposed between the scattering layer STL and the hole transport region HTR.

[0138] The metal layer AML can be directly disposed on the scattering layer STL. The metal layer AML can be disposed within the opening PX_OP of the pixel-defining film PDL. The metal layer AML can be in contact with the inner surface of the opening PX_OP of the pixel-defining film PDL. The scattering layer STL can be directly disposed between the metal layer AML and the first electrode AE. The metal layer AML may not be in contact with the first electrode AE.

[0139] The metal layer AML may include at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, and Zn (e.g., including at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, and Zn), a compound selected from two or more of these, a mixture selected from two or more of these, or an oxide of any one of these. The metal layer AML may also include LiF or a mixture of LiF and at least one of the above materials. The metal layer AML can improve the driving characteristics of the light-emitting element ED-a.

[0140] The metal layer AML may include the same material as the first electrode AE. For example, the metal layer AML may include a transparent conductive film formed of or containing ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), or ITZO (indium tin zinc oxide). For example, the first electrode AE ​​may have a three-layer structure of ITO / Ag / ITO, and the metal layer AML may include ITO.

[0141] In the thickness direction DR3, the metal layer AML can have a thickness of approximately 200 Å to approximately 500 Å. A metal layer AML with a thickness of approximately 200 Å to approximately 500 Å can improve the driving characteristics of the light-emitting element ED-a without increasing the driving voltage or reducing the light extraction efficiency.

[0142] An electronic device according to an exemplary embodiment can be manufactured by a method for manufacturing an electronic device according to an exemplary embodiment. Figure 8A and Figure 8B This is a flowchart illustrating a method for manufacturing an electronic device according to an exemplary embodiment. Figures 9 to 12 This is a schematic diagram illustrating the operation of manufacturing an electronic device according to an exemplary embodiment. Below is a description of... Figures 8A to 12 The description will not repeat the reference. Figures 1 to 7C The descriptions will overlap, and the main focus will be on the differences.

[0143] refer to Figure 8A A method for manufacturing an electronic device according to an exemplary embodiment may include operations S100 of preparing a base layer, S200 of forming a first electrode on the base layer, S300 of forming a pixel defining film defining an opening exposing the first electrode, S400 of forming a scattering layer on the first electrode, S500 of forming an emission layer on the scattering layer, and S600 of forming a second electrode on the emission layer. (See reference...) Figure 8B The step S400 of forming the scattering layer may include the operation S410 of forming a preliminary scattering layer and the operation S420 of treating the preliminary scattering layer with plasma to form the scattering layer.

[0144] refer to Figure 9 A P-STL for forming a preliminary scattering layer can be provided on the first electrode AE ​​(see...). Figure 11 The composition COP. The preliminary scattering layer P-STL can be formed by inkjet printing, dispensing, or photolithography. The composition COP can be provided by inkjet printing, dispensing, or photolithography. In Figure 9 In this context, composition COP is shown as being supplied via nozzle NZ, but the equipment used for supplying composition COP is not limited to this.

[0145] Figure 10 yes Figure 9 A magnified view of region A' in the image. (Reference) Figure 10 The composition COP may include an organic solvent SV and a plurality of preliminary hollow silica particles P-SP dispersed in the organic solvent SV. The preliminary hollow silica particles P-SP may be combined with the third hollow silica particles PT3 described above (see [link to article]). Figure 7A The basic components are essentially the same. The initial foundational part, P-BP (see...) Figure 11 ) can be formed by organic solvent SV, and the basic part BP (see Figure 12 It can be formed from the initial base component P-BP. For example, the organic solvent SV can include an acrylic acid-based resin.

[0146] Based on a total COP of 100 wt% for the composition, the weight of the preliminary hollow silica particles P-SP can range from about 0.5 wt% to about 15 wt%. Each preliminary hollow silica particle P-SP can have a size of about 50 nm to about 200 nm. Preliminary hollow silica particles P-SP with a size of about 50 nm to about 200 nm can be readily provided by inkjet printing or photolithography.

[0147] Figure 11 The preliminary scattering layer P-STL shown can be formed by curing a composition COP provided on the first electrode AE. For example, heat or light can be provided when curing the composition COP. The preliminary scattering layer P-STL may include a preliminary base portion P-BP and preliminary hollow silica particles P-SP. The preliminary scattering layer P-STL can be treated with plasma LS, and a scattering layer STL can be formed (see [link to documentation]). Figure 12 In the operation of forming the scattering layer STL, either fluorine plasma or oxygen plasma can be provided. When performing plasma LS processing, either fluorine or oxygen gas can be provided as the plasma LS. For example, CF4 or NF3 can be provided as fluorine gas.

[0148] refer to Figure 11 and Figure 12 By treating the initial scattering layer P-STL with plasma LS, the basic BP can be formed from the initial basic P-BP (see...). Figure 12Hollow silica particles SP can be formed from preliminary hollow silica particles P-SP. First hollow silica particles PT1 and second hollow silica particles PT2 can be formed by plasma LS processing. In the plasma LS processing operation, the preliminary base portion P-BP can be etched. The first hollow silica particles PT1 and second hollow silica particles PT2 can be formed simultaneously with the etching of the preliminary base portion P-BP. When the preliminary base portion P-BP is etched, some of the preliminary hollow silica particles P-SP can protrude to form the first hollow silica particle PT1. Furthermore, in the plasma LS processing operation, some of the preliminary hollow silica particles P-SP may have fractured surfaces, and second hollow silica particles PT2 with exposed inner surfaces may be formed. The bonds between silicon and oxygen atoms constituting the hollow silica particles can be broken by fluorine gas (or oxygen), and second hollow silica particles PT2 with exposed inner surfaces can be formed. Therefore, a method for manufacturing an electronic device according to an exemplary embodiment (including the operation of plasma LS processing) can provide improved processability.

[0149] refer to Figure 13 A method for manufacturing an electronic device according to an exemplary embodiment may further include operations of forming a scattering layer STL and forming an emissive layer EML (see [link to embodiment]). Figure 7C The operations of forming a metal layer AML between operations of forming an emission layer EML (see [link to EML]). The metal layer AML may include at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, and Zn (e.g., including at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, and Zn), a compound selected from two or more of them, a mixture selected from two or more of them, or an oxide of any one of them. The metal layer AML may also include LiF or a mixture of LiF and at least one of the above materials. Figure 7C Before proceeding, an ashing process can be performed on the metal layer AML. This ashing process can correct the work function of the metal layer AML and improve the driving characteristics of the light-emitting element ED-a. For example, oxygen AH can be provided during the ashing process. When oxygen AH is provided, the oxygen content on the surface of the metal layer AML can increase. A relatively high oxygen content can exist on the surface of the metal layer AML.

[0150] Figures 14A to 14D These are pixel-defined images of an experimental example film after plasma treatment, captured using a scanning electron microscope (SEM). Figures 14A to 14D In the experimental example, the pixel-defining film includes hollow silicon particles.

[0151] exist Figure 14A and Figure 14B CF4 was provided during plasma processing in the experimental example. Figure 14C and Figure 14D NF3 is provided during plasma processing in experimental examples. Figure 14A and Figure 14C In an experimental example, plasma treatment was performed for 120 seconds using a power supply voltage of 0.5 kW and a bias voltage of 0 kW. Figure 14B and Figure 14D In an experimental example, plasma processing was performed for 60 seconds using a source voltage of 1 kW and a bias voltage of 0.4 kW.

[0152] refer to Figure 14A and Figure 14D The first hollow silica particle PT1, which protruded through plasma treatment, can be identified. (Reference) Figure 14B and Figure 14C The second hollow silica particle PT2, which has an exposed inner surface due to plasma treatment, can be identified. Therefore, it can be understood that when plasma is applied to a preliminary scattering layer comprising the preliminary hollow silica particles, protruding first hollow silica particles and second hollow silica particles with exposed inner surfaces can be formed.

[0153] When using ImageJ analysis program (an open-source image analysis program developed by the National Institutes of Health, NIH) for analysis Figure 14B and Figure 14C When creating the image, only the second hollow silica particles with exposed inner surfaces can be independently identified. The identification area is darkened so that the surface area of ​​the second hollow silica particles can be converted into a fractional percentage.

[0154] A method for manufacturing an electronic device according to an exemplary embodiment may include the operation of treating a preliminary scattering layer with plasma to form the scattering layer. First hollow silica particles and second hollow silica particles can be formed by plasma treatment. Therefore, the method for manufacturing an electronic device according to an exemplary embodiment can provide improved processability.

[0155] An electronic device according to an exemplary embodiment can be manufactured using methods for manufacturing electronic devices. The electronic device according to an exemplary embodiment may include a scattering layer disposed on a first electrode and comprising a first hollow silica particle and a second hollow silica particle. The first and second hollow silica particles may be located on the top surface of the scattering layer. The first hollow silica particle may protrude in a direction from the top surface of the scattering layer toward an emitting layer. The second hollow silica particle may have a fractured surface exposing its interior. The scattering layer comprising the first and second hollow silica particles can improve the reflection and / or diffraction of external light, enhance light extraction efficiency, and / or improve brightness variation according to viewing angle. The electronic device comprising the scattering layer can have improved display quality.

[0156] Because the electronic device according to an exemplary embodiment includes a first hollow silica particle and a second hollow silica particle, it can have improved display quality.

[0157] A method for manufacturing an electronic device according to an exemplary embodiment may include operations of forming a first hollow silica particle and a second hollow silica particle by plasma treatment, thereby providing improved processability.

[0158] Any functional block shown in the figure and described above can be implemented in processing circuitry, such as hardware (which includes logic circuitry), hardware / software combinations (such as a processor executing software), or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0159] Although some exemplary embodiments of the inventive concept have been described, it should be understood that the inventive concept is not limited to these exemplary embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the inventive concept claimed herein.

Claims

1. Electronic devices, including: The display module includes a light-emitting element and a pixel-defining film including openings. The light-emitting element includes: The first electrode is exposed through the opening. A scattering layer is located on the first electrode. The emitting layer, on the scattering layer, and The second electrode is located on the emission layer. The scattering layer includes: The basic part, and Multiple hollow silica particles are dispersed in the base portion, including first hollow silica particles and second hollow silica particles. The first hollow silica particle protrudes from the top surface of the scattering layer toward the emitting layer, and the top surface of the scattering layer is spaced apart from the first electrode. The second hollow silica particle is located on the top surface of the scattering layer and has an exposed inner surface.

2. The electronic device according to claim 1, wherein, The second hollow silica particle comprises a plurality of second hollow silica particles, and the total surface area based on the top surface of the scattering layer is 100%, and the sum of the surface areas of the plurality of second hollow silica particles is 0.05% or greater and 20% or less.

3. The electronic device according to claim 1, wherein, Each of the plurality of hollow silica particles has a size ranging from 50 nm to 200 nm.

4. The electronic device according to claim 1, wherein, Based on the total weight of the scattering layer, the total weight of the plurality of hollow silica particles is 0.5 wt% or greater and 15 wt% or less.

5. The electronic device according to claim 1, wherein, The scattering layer is located in the opening of the pixel-defining film.

6. The electronic device according to claim 1, wherein, The light-emitting element further includes a metal layer between the scattering layer and the emitting layer. The metal layer comprises at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn; two or more compounds selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, and Zn; a mixture of two or more selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn; or an oxide of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, or Zn.

7. The electronic device according to claim 6, wherein, The metal layer is directly on the scattering layer.

8. The electronic device according to claim 6, wherein, The metal layer has a thickness of 200 Å to 500 Å.

9. The electronic device according to claim 6, wherein, The metal layer is in the opening of the pixel-defining film.

10. The electronic device according to claim 1, further comprising at least one of a processor, a power supply circuit, and a memory.

11. A method for manufacturing an electronic device, comprising: Preparation of the base layer; A first electrode is formed on the base layer; A pixel-defining film with an opening is formed, through which the first electrode is exposed; A scattering layer is formed on the first electrode; An emission layer is formed on the scattering layer; as well as A second electrode is formed on the emitter layer. The formation of the scattering layer includes: A preliminary scattering layer is formed on the first electrode, the preliminary scattering layer comprising a preliminary base portion and a plurality of preliminary hollow silica particles dispersed in the preliminary base portion, and The preliminary scattering layer is formed by treating the preliminary scattering layer with plasma, the scattering layer comprising a preliminary base portion and a plurality of hollow silica particles respectively formed by the preliminary base portion and the plurality of preliminary hollow silica particles. The plurality of hollow silica particles include a first hollow silica particle and a second hollow silica particle. The first hollow silica particle is disposed on the top surface of the scattering layer and protrudes from the top surface of the scattering layer toward the emitting layer. The top surface of the scattering layer is spaced apart from the first electrode. The second hollow silica particle is disposed on the top surface of the scattering layer and has an exposed inner surface.

12. The method according to claim 11, wherein, The plasma includes fluorine plasma or oxygen plasma.

13. The method according to claim 11, wherein, The initial scattering layer is formed by inkjet printing or photolithography.

14. The method of claim 11, further comprising: After the scattering layer is formed and before the emitting layer is formed, a metal layer is formed on the scattering layer. The metal layer comprises at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn; a compound selected from two or more selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, and Zn; a mixture selected from two or more selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn; or an oxide of any one of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, and Zn.

15. The method of claim 14, further comprising: An ashing process is performed on the metal layer before the emission layer is formed.

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