Preparation method of flexible organic electronic chip and flexible organic electronic chip

Abstract

This invention discloses a method for fabricating a flexible organic electronic chip and the flexible organic electronic chip itself, belonging to the field of 3D chip technology. This invention achieves three-dimensional vertical integration of the device by pre-fabricating a polymer deposition layer on a glass substrate, then stacking multiple functional devices layer by layer, and finally peeling off the entire chip. This invention uses polymer materials as the dielectric and encapsulation layers of the device, compressing the interlayer spacing to 3μm, significantly improving the integration density; the multilayer device adopts a common gate and via interconnect structure, shortening the signal transmission distance. The fabricated flexible chip maintains a thousand-level on / off ratio under bending conditions, exhibiting stable electrical performance. The flexible substrate can adapt to multi-angle bending scenarios, effectively solving the problems of low two-dimensional integration density, poor three-dimensional interconnect technology, large interlayer spacing, and insufficient bending stability of traditional organic devices. It is suitable for flexible electronics fields such as wearables, bio-implants, and flexible sensors.

Description

Technical Field

[0001] This invention belongs to the field of 3D chip technology, specifically relating to a method for preparing a flexible organic electronic chip and the flexible organic electronic chip itself. Background Technology

[0002] Silicon-based 3D chips are widely used in the integrated circuit field due to their mature processes. However, the rigidity, brittleness, and inability to bend or deform silicon substrates severely limit their application in flexible electronics scenarios such as wearable electronic devices, bio-implantable devices, and flexible sensor arrays. Traditional organic electronic devices mostly adopt two-dimensional planar layouts, resulting in low integration density and the inability to achieve three-dimensional interconnects. At the same time, the existing interlayer interconnect via technology has low maturity, and mainstream laser drilling processes easily damage the functional layers of devices, leading to a significant decrease in via yield. Furthermore, traditional processes struggle to compress interlayer spacing, with conventional interlayer spacing generally exceeding 30μm, severely restricting the miniaturization and high-density integration of flexible organic electronic chips.

[0003] In summary, existing flexible organic electronic chips suffer from problems such as low integration density in two-dimensional layout, immature three-dimensional interconnection technology, damage to functional layers due to drilling, low yield of through-holes, large interlayer spacing, and poor stability under bending conditions. There is an urgent need for a three-dimensional fabrication scheme for flexible organic electronic chips that is simple in process, has high yield, high integration density, and stable performance. Summary of the Invention

[0004] Technical problems to be solved: In view of the above-mentioned technical problems, the present invention provides a method for fabricating a flexible organic electronic chip and a flexible organic electronic chip, which can effectively solve the technical problems of low two-dimensional layout integration density, immature three-dimensional interconnection process, easy damage to functional layers by laser drilling, low yield of through holes, large interlayer spacing, and poor bending stability of organic electronic devices in the prior art. It realizes high-density three-dimensional integration of devices, low-damage interlayer interconnection, and ultra-small interlayer spacing, while ensuring stable working performance of devices under bending conditions.

[0005] Technical solution: In a first aspect, the present invention provides a method for fabricating a flexible organic electronic chip, comprising the following steps: S1. Substrate pretreatment: A fluoropolymer (Cytop) is spin-coated onto the surface of a clean glass slide, and the spin-coated glass slide is then heated and cured. The polymer material is vaporized at high temperature using a polymer material coating equipment and uniformly deposited onto the surface of the glass slide to prepare a glass substrate with a polymer material deposition layer on the surface. S2. Multilayer device fabrication: At least one layer of functional device is fabricated sequentially from bottom to top on the upper surface of the deposition layer, and multilayer device integration is achieved by vertical stacking. S3. Device peeling and molding: The deposited layer is peeled off from the glass substrate at the end face. After peeling, the deposited layer with multiple functional devices constitutes a flexible organic electronic device.

[0006] Preferably, the polymer material is parylene, povidone, or polyvinylpyrrolidone, and the polymer material is a polymer material with insulation, flexibility, and chemical stability. Preferably, the first layer of devices, the second layer of devices, and the third layer of devices are fabricated sequentially from bottom to top along the end face of the deposition layer. Through the multi-layer device stacking structure in the vertical direction of the deposition layer, the device integration density per unit area is greatly improved without increasing the substrate footprint.

[0007] Furthermore, the fabrication method of the first layer device includes: spin-coating photoresist onto the surface of a glass sheet with a deposition layer, and pre-baking the spin-coated glass sheet with heat; patterning the glass sheet using photolithography, and immersing the exposed glass sheet in a developer and ultrapure water for cleaning; vaporizing gold (Au) material using a vapor deposition device and depositing it on the surface of the treated deposition layer to form a metal conductive layer; immersing and rinsing the glass sheet with acetone to remove residual photoresist on the surface, and shaping to obtain the device source electrode.

[0008] Furthermore, the fabrication method of the first layer device also includes: depositing a polymer material on the surface of the glass slide on which the active electrode is fabricated to form a device insulating layer; repeating the spin coating, pre-baking, photolithography, and development processes in the region corresponding to the source electrode; using a reactive ion etching machine to etch away the polymer insulating layer material in the exposed area; removing residual photoresist by immersion in acetone to isolate the conductive paths of the source and drain electrodes and avoid electrode cross-conduction; and again fabricating the drain electrode in the region corresponding to the insulating layer by a complete set of processes including spin coating, pre-baking, photolithography, development, evaporation, and photoresist removal.

[0009] Furthermore, the fabrication method of the first layer device also includes: preparing an organic semiconductor layer on the surface of a substrate integrating an active electrode, an insulating layer, and a drain electrode using a blade coating process; attaching a poly(p-dimethylsiloxane) (PDMS) protective layer to the electrode lead-out region of the organic semiconductor layer; and then depositing a polymer material layer to prepare the device dielectric layer.

[0010] Furthermore, the fabrication method of the first layer device also includes: fabricating a gate electrode on the surface of the dielectric layer by spin coating, pre-baking, photolithography, development, evaporation, and resist removal processes; and depositing a polymer material layer on the upper end face of the gate electrode to complete the overall encapsulation and protection of the first layer device.

[0011] Furthermore, the second layer device is stacked on the upper surface of the first layer device packaging layer. The second layer device is provided with an organic semiconductor layer, a polymer dielectric layer, and a gate electrode from bottom to top. Active electrodes and drain electrodes are symmetrically arranged on both sides of the organic semiconductor layer.

[0012] Furthermore, the fabrication method of the third-layer device includes: depositing a polymer material layer on the upper surface of the second-layer device as the dielectric layer of the third-layer device; forming interconnecting vias between the second-layer device and the third-layer device to construct an interlayer via interconnection structure; sequentially performing spin coating, pre-baking, photolithography, and development processes on the dielectric layer, and etching away the polymer material in the exposed area using a reactive ion etching machine; performing spin coating, pre-baking, photolithography, development, evaporation, and resist removal processes again to prepare the via interconnection metal structure; and finally repeating the fabrication process of the first-layer device to sequentially complete the fabrication of the source electrode, insulating layer, drain electrode, and organic semiconductor layer of the third-layer device.

[0013] Secondly, the present invention provides a flexible organic electronic chip, which is prepared by the preparation method described in the first aspect; the flexible organic electronic chip includes a flexible deposition layer, and a first layer device, a second layer device and a third layer device are stacked sequentially from bottom to top on the end face of the deposition layer; the second layer device and the third layer device adopt a common gate structure, and the two layers of devices are interconnected through metal vias, effectively shortening the connection distance between the interlayer devices; after the deposition layer is peeled off from the glass substrate, a flexible substrate is formed, so that the overall chip has excellent bending adaptability and can meet the flexible use requirements of multiple angles and multiple scenarios.

[0014] Beneficial effects: 1) The present invention adopts a vertical three-dimensional stacked structure, which breaks through the area limitation of traditional two-dimensional planar device integration, and greatly improves the device integration density under the same substrate area, realizing chip miniaturization and high-density integration; 2) This invention abandons the traditional laser drilling process and achieves interlayer interconnection of vias through photolithography, etching and polymer material deposition process, which effectively avoids damage to the functional layer of the device by laser processing, greatly improves the yield of via fabrication, simplifies the fabrication process and reduces production costs. 3) This invention uses high-molecular-weight parylene as the dielectric layer and encapsulation layer of each device, which can compress the interlayer spacing of the device to 3μm, which greatly improves the chip integration accuracy and compactness compared to the traditional interlayer spacing of more than 30μm. 4) This invention adopts a substrate pre-deposition polymer release layer process, which can realize the overall non-destructive release of multi-layer devices. The formed device uses polymer material as a flexible substrate, has excellent bending performance, and can be adapted to various multi-angle flexible application scenarios. 5) The flexible organic electronic chip prepared by this invention can still maintain a high switching ratio of three orders of magnitude under bending conditions. The device has stable electrical performance, strong resistance to bending interference, and its reliability is far superior to that of traditional flexible organic devices. Attached Figure Description

[0015] Figure 1 This is an overall structural diagram of the device according to an embodiment of the present invention; Figure 2The transfer characteristic curve of the top-level device in an embodiment of the present invention; In the figure, the numbers are: 100, deposition layer; 200, first layer device; 300, second layer device; 400, third layer device. Detailed Implementation

[0016] The present invention will be described in detail below with reference to specific embodiments: Unless otherwise specified, all raw materials used in the embodiments of this invention are commercially available conventional materials. The preferred polymer material is parylene, but polyvinyl ketone, polyvinylpyrrolidone, and other polymer materials with equivalent insulation, flexibility, and chemical stability can also be used.

[0017] Device performance testing methods: The performance testing of the device in this invention was performed using a Keithley 4200-SCS semiconductor parameter analyzer in conjunction with a probe station. The specific testing procedure is as follows: (1) Equipment calibration: Connect the equipment power supply, complete the connection and calibration of the semiconductor parameter analyzer and probe station, check the cleanliness and contact status of the probe head, adjust the test environment temperature and humidity to the standard range, and avoid electrical noise and vibration interference. (2) Sample pretreatment: Nitrogen gas is used to purge the sample surface to remove dust, oil and other impurities. The transistor sample to be tested is fixed on the probe stage to ensure that the electrode and probe are accurately aligned. The sample is fixed by vacuum adsorption to avoid displacement during the test. (3) Probe docking: The probe position is precisely adjusted by the microscope so that the probe corresponds to the source, drain and gate of the device respectively. The probe is slightly pressed down to ensure good electrical contact and avoid excessive pressure to avoid damaging the device; the gate is connected to the voltage source channel, the drain is connected to the current measurement channel, and the source is grounded. (4) Selection of device under test: Select the device under the curved surface as the test object to simulate the actual flexible use scenario; (5) Parameter setting and testing: Set the gate-source voltage VGS bias range to -10V to 5V, with a voltage step of 0.2V, and fix the drain-source voltage VDS at -10V. Test and collect the device IDS-VGS transfer curve, check for abnormal data jumps, and ensure test stability. (6) Data processing: The test data is stored in CSV format, and repeated tests are performed to ensure data consistency. The off-state current (pA level) and on-state current (nA level) are extracted, and the device switching ratio is calculated. (7) Equipment reset: After the test is completed, slowly lift the probe, take out the sample, record the test data, turn off the equipment and clean up the experimental environment. Example 1

[0018] A method for fabricating a flexible organic electronic chip, such as Figure 1As shown, it includes the following steps: (1) Spin-coat a fluoropolymer (fluoropolymer solution, Xiaoan Trading (Shanghai) Co., Ltd. CTL-809M) onto a clean glass slide (7.7cm×7.7cm) and heat it on a 50℃ heating plate for 10 minutes to complete the curing; use a polymer coating equipment to vaporize 12g of parylene at high temperature and deposit it evenly on the surface of the glass slide to form a polymer deposition layer 100, which facilitates the subsequent overall peeling of the device; (2) Photoresist was spin-coated on the surface of a glass slide with a deposition layer of 100 and pre-baked at 50°C for 30 min. After pattern exposure, the glass slide was placed in the developer and then immersed in ultrapure water for 8 s to clean it. A 15 nm thick gold (Au) layer was deposited using a vapor deposition device to form a metal conductive layer. The residual photoresist was removed by rinsing with acetone and the device source electrode was obtained. (3) 3g of parylene is deposited on the surface of the source electrode as an insulating layer; the insulating layer area is subjected to spin coating, pre-baking, photolithography and development; the insulating layer material in the exposed area is etched by reactive ion etching machine; the residual photoresist is removed with acetone to isolate the conduction path of the source and drain electrodes; the drain electrode is prepared again by a complete set of processes including spin coating, pre-baking, photolithography, development, evaporation and photoresist removal. (4) An organic semiconductor layer (C8 solution) is prepared on the surface of the electrode structure by a scraping process. The scraping speed is 200 μm / s, the scraper height is 300 μm and the tilt angle is 30°. 3 μL of C8 solution is transferred to complete the scraping. A PDMS protective layer is attached to the electrode lead-out area, and 3 g of parylene is deposited to prepare a dielectric layer. (5) A gate electrode is prepared on the surface of the dielectric layer by photolithography and vapor deposition, and finally 3g of parylene is deposited to complete the overall packaging of the first layer device 200. (6) Repeat the fabrication process of the first layer device 200 to fabricate the second layer device 300 and the third layer device 400 in sequence. The second layer device 300 and the third layer device 400 adopt a common gate structure. (7) 3g of parylene is deposited on the surface of the second layer device 300 as the dielectric layer of the third layer device 400; through-holes are processed by photolithography and etching, and metal material is deposited again to form through-hole interconnect structure; repeat the fabrication process of the first layer device 200 to complete the fabrication of the electrode and semiconductor layer structure of the third layer device 400. (8) Remove excess parylene material around the glass sheet, purge the surface with nitrogen, and peel the multilayer device and the deposition layer 100 together from the glass substrate to obtain a flexible organic electronic chip.

[0019] The fabricated top-layer device was placed in a probe station, and its transfer characteristic curves were tested using a semiconductor parameter analyzer. With a fixed source-drain voltage VDS = -10V, the gate voltage scan range was 5V to -10V, and a complete hole transport transfer curve was obtained. The results are as follows: Figure 2 As shown, the top-level device in this embodiment exhibits excellent performance, with a device on / off ratio exceeding 10. 3 Magnitude. Example 2

[0020] This embodiment is basically the same as that of embodiment 1, except that perfluorooctylsilane (FTS) is used to replace the fluoropolymer in step (1), and the rest of the preparation process and parameters are the same as those in embodiment 1, so as to obtain a flexible organic electronic chip. Example 3

[0021] This embodiment is basically the same as that of embodiment 1, except that the Au vapor deposition thickness in steps (2), (3), (5), (6) and (7) is adjusted from 15nm to 30nm. The rest of the preparation process and parameters are the same as those in embodiment 1, and a flexible organic electronic chip is obtained.

[0022] Comparative Example 1 This comparative example is basically the same as Example 1, except that the pre-baking process parameters of each step are adjusted to 80°C and 15min, replacing the original pre-baking parameters of 50°C and 30min, while the other process parameters remain unchanged, to obtain the comparative sample device.

[0023] The electrical performance of the organic electronic devices prepared in Examples 1-3 and Comparative Example 1 was tested, and the results are shown in Table 1 below: Table 1 Performance test results of the organic electronic devices prepared in Examples 1-3 , As shown in Table 1, the device in Example 1 has the optimal on / off ratio, reaching 7.4659 × 10⁻⁶. 3 The device exhibits excellent electrical performance and stable switching characteristics. Replacing the substrate pretreatment material and adjusting the metal layer thickness will slightly affect the device performance, but a high on / off ratio can still be maintained. In contrast, after adjusting the pre-baking temperature and time in Comparative Example 1, the device on / off ratio dropped significantly. This is because high-temperature short-time baking will damage the organic semiconductor layer structure and severely degrade the device's electrical performance, proving that the 50°C, 30min pre-baking process of this invention is the optimal process parameter.

[0024] This invention relates to a flexible organic electronic chip using a polymeric parylene deposition layer as a flexible substrate. Three functional devices are vertically stacked on the substrate. The second and third layers of devices adopt a common gate structure and are interconnected through metal vias, significantly shortening the signal transmission distance between layers and reducing parasitic resistance and signal delay. Compared to traditional two-dimensional planar organic devices, this invention employs a 3D vertical stacking architecture, which can achieve several times the device density on the same substrate area, enabling integrated sensing, driving, signal processing, and storage functions.

[0025] Meanwhile, parylene materials possess excellent insulation, flexibility, and chemical stability. They can be used as ultra-thin dielectric and encapsulation layers to achieve an ultra-small 3μm interlayer spacing, and as flexible support substrates to ensure the structural and electrical performance stability of devices under multi-angle bending conditions. They are perfectly suited for various flexible electronic applications such as wearable devices, bio-implantable devices, and flexible sensor arrays.

[0026] It should be noted that the present invention preferably uses a three-layer device stacking structure. In practical applications, one or more device layers can be stacked as needed. The more layers there are, the higher the device integration density and the wider the applicable scenarios.

[0027] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a flexible organic electronic chip, characterized in that, Includes the following steps: S1. A fluoropolymer is spin-coated onto the surface of a clean glass slide, and the spin-coated glass slide is then heated and cured. The polymer material is vaporized at high temperature using a polymer material coating equipment and uniformly deposited onto the surface of the glass slide to prepare a glass substrate with a polymer material deposition layer on the surface. S2. At least one layer of functional device is fabricated sequentially from bottom to top on the upper surface of the deposition layer; S3. The deposited layer is peeled off from the glass substrate at the end face. After peeling, the deposited layer with multiple functional devices constitutes a flexible organic electronic device.

2. The preparation method according to claim 1, characterized in that: The polymer material is parylene, povidone, or polyvinylpyrrolidone.

3. The preparation method according to claim 1, characterized in that: The first, second, and third layers of devices are fabricated sequentially from bottom to top along the end face of the deposition layer. Through the multi-layer device stacking structure in the vertical direction of the deposition layer, the device integration density per unit area is significantly improved without increasing the substrate footprint.

4. The preparation method according to claim 3, characterized in that, The fabrication method of the first layer device includes: spin-coating photoresist onto the surface of a glass slide with a deposition layer, and pre-baking the spin-coated glass slide with heat; patterning the glass slide using photolithography, and immersing the exposed glass slide in developer and ultrapure water for cleaning; vaporizing gold material using evaporation equipment and depositing it on the surface of the treated deposition layer to form a metal conductive layer; immersing and rinsing the glass slide with acetone to remove residual photoresist on the surface, and shaping to obtain the device source electrode.

5. The preparation method according to claim 4, characterized in that, The fabrication method of the first layer device further includes: depositing a polymer material on the surface of the glass slide on which the active electrode is prepared to form a device insulating layer; repeating the spin coating, pre-baking, photolithography, and development processes in the region corresponding to the source electrode; using a reactive ion etching machine to etch away the polymer insulating layer material in the exposed area; removing residual photoresist by immersion in acetone to isolate the conductive paths of the source and drain electrodes and avoid electrode cross-conduction; and again fabricating the drain electrode in the region corresponding to the insulating layer by a complete set of processes including spin coating, pre-baking, photolithography, development, evaporation, and photoresist removal.

6. The preparation method according to claim 5, characterized in that, The fabrication method of the first layer device further includes: preparing an organic semiconductor layer on the surface of a substrate integrating an active electrode, an insulating layer, and a drain electrode using a blade coating process; attaching a polydimethylsiloxane protective layer to the electrode lead-out region of the organic semiconductor layer; and then depositing a polymer material layer to prepare the device dielectric layer.

7. The preparation method according to claim 6, characterized in that, The fabrication method of the first layer device further includes: fabricating a gate electrode on the surface of the dielectric layer by spin coating, pre-baking, photolithography, development, evaporation, and resist removal processes; and depositing a polymer material layer on the upper end face of the gate electrode to complete the overall encapsulation and protection of the first layer device.

8. The preparation method according to claim 3, characterized in that, The second layer device is stacked on the upper surface of the first layer device packaging layer. The second layer device is provided with an organic semiconductor layer, a polymer dielectric layer and a gate electrode from bottom to top. Active electrodes and drain electrodes are symmetrically arranged on both sides of the organic semiconductor layer.

9. The preparation method according to claim 3, characterized in that, The fabrication method of the third-layer device includes: depositing a polymer material layer on the upper surface of the second-layer device as the dielectric layer of the third-layer device; forming interconnecting vias between the second-layer device and the third-layer device to construct an interlayer via interconnection structure; sequentially performing spin coating, pre-baking, photolithography, and development processes on the dielectric layer, and etching away the polymer material in the exposed areas using a reactive ion etching machine; performing spin coating, pre-baking, photolithography, development, evaporation, and resist removal processes again to prepare the via interconnection metal structure; and finally repeating the fabrication process of the first-layer device to sequentially complete the fabrication of the source electrode, insulating layer, drain electrode, and organic semiconductor layer of the third-layer device.

10. A flexible organic electronic chip, characterized in that, The flexible organic electronic chip is prepared by the preparation method described in claim 3; the flexible organic electronic chip includes a flexible deposition layer, and a first layer device, a second layer device and a third layer device are stacked sequentially from bottom to top on the end face of the deposition layer; the second layer device and the third layer device adopt a common gate structure, and the two layers of devices are interconnected through metal vias.

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