A hybrid integration method of superconducting nanowire single-photon detector

Abstract

This invention discloses a hybrid integration method for superconducting nanowire single-photon detectors (SNSPDs), relating to the field of superconducting single-photon detection technology. The method includes: performing joint simulation design based on the target operating wavelength, incident light direction, and optical cavity material properties of the SNSPD to determine device and optical structure parameters; separating the superconducting nanowire device chip and the combined optical structure; flip-bonding qualified superconducting nanowire devices and the combined optical structure to form a stacked structure; encapsulating and completing electrical connections and optical path assembly. This invention avoids damage to the superconducting thin film caused by repeatedly applying high-temperature or strong etching processes to the selected superconducting nanowire devices through joint simulation design of the SNSPD device structure and optical cavity structure; and then separately fabricating the superconducting nanowire device and optical structure. This helps maintain excellent intrinsic single-photon detection performance and improves device fabrication compatibility and yield.

Description

Technical Field

[0001] This invention belongs to the field of superconducting single-photon detection technology, specifically relating to a hybrid integration method for superconducting nanowire single-photon detectors. Background Technology

[0002] Superconducting nanowire single-photon detectors (SNSPDs) possess characteristics such as high detection efficiency, low dark count rate, and low timing jitter, and have been widely used in quantum communication, deep space exploration, bioimaging, weak light detection, and integrated quantum optics. The system detection efficiency of SNSPDs depends not only on the superconducting thin film and nanowire structure but also strongly on the enhancement and absorption of the incident light by the local electric field at the nanowire location. Therefore, it is necessary to improve the nanowire absorption rate through optical cavities, mirrors, antireflective layers, microcavities, or other complex optical structures.

[0003] Currently, most mainstream fabrication methods for high-efficiency SNSPDs employ monolithic integrated stacking processes. This involves sequentially depositing and patterning superconducting nanowires, electrodes, and multilayer optical structures on the same wafer substrate. For example, integrating multilayer optical cavity structures on a single silicon wafer can improve the overall performance of the SNSPD; or ion irradiation combined with multilayer optical cavity stacking can optimize the device's detection efficiency. While this type of monolithic integration can improve light absorption efficiency to some extent, it suffers from fundamental process and architectural defects, severely limiting device yield, stability, and scalability.

[0004] First, the core superconducting film of SNSPD is only a few nanometers thick, making the nanowire structure extremely fragile. After the nanowires are fabricated, subsequent complex processes such as high-temperature deposition, etching, stripping, and cleaning can easily damage the edge morphology of the NbN superconducting film and nanowires, leading to critical current degradation, increased microscopic defects, and a significant increase in the probability of device failure.

[0005] Secondly, the optical cavity multilayer film system involves repeated deposition and patterning of multiple materials and thicknesses, all superimposed on the already formed superconducting device structure. The process tolerance is extremely low, making it difficult to support large-area arrays and mass production, and the overall device yield is severely limited.

[0006] Furthermore, traditional monolithic integration processes cannot identify high-performance qualified chips in advance. They can only uniformly stack optical cavity processes on all devices. The inability to pre-screen devices leads to a large waste of process resources on inferior devices, resulting in high manufacturing costs and high process redundancy.

[0007] Furthermore, the monolithic layer-by-layer integrated architecture has limited compatibility with optical cavity material systems, film thickness systems, structural morphology, and optical path incident methods, making it difficult to achieve rapid customization and adaptation for the differentiated needs of different operating bands and different quantum optical systems, resulting in weak device versatility.

[0008] In summary, existing monolithic stacking processes suffer from numerous technical bottlenecks, including easy device damage, low yield, poor screening capabilities, weak versatility, and insufficient stability of heterogeneous connections. There is an urgent need for a hybrid SNSPD integration solution that can protect shaped superconducting devices, support pre-screening, and be compatible with various complex optical cavity junctions. Summary of the Invention

[0009] The purpose of this invention is to propose a hybrid integration method for superconducting nanowire single-photon detectors. This method involves first jointly simulating and designing the SNSPD device structure and optical cavity structure; then separately fabricating the superconducting nanowire device and optical structure, and performing electrical screening after device fabrication; finally, stacking the screened devices with the optical structure using PDMS transfer stamping and flip-chip bonding. This avoids the need for multiple high-temperature or strong etching processes to be applied to the screened superconducting nanowire device, reducing damage to the superconducting thin film from subsequent processes.

[0010] To achieve the above objectives, the present invention proposes the following technical solution:

[0011] A hybrid integration method for superconducting nanowire single-photon detectors includes: designing the overall layout of the single-photon detector based on the target operating wavelength, light incident direction, and optical cavity material properties; establishing an electromagnetic simulation model and performing optical absorption simulation with the light absorption rate of the superconducting nanowire as the optimization target to iteratively determine the device structure parameters and optical structure parameters; fabricating superconducting nanowire device chips on a large area based on the device structure parameters, and screening qualified superconducting nanowire devices through performance testing; fabricating a combined optical structure based on the optical structure parameters; picking up qualified superconducting nanowire devices and flip-bonding them with the combined optical structure to form a stacked structure, and then encapsulating and completing electrical connections and optical path assembly.

[0012] Furthermore, in the flip-chip bonding stage, indium pillars are used as the fixed interconnect structure.

[0013] Furthermore, the device structural parameters include: the effective detection area of ​​the SNSPD, the thickness of the thin film, the thickness of the electrode, and the routing, width, and duty cycle of the nanowires.

[0014] Furthermore, based on the aforementioned device structural parameters, a superconducting nanowire device chip is fabricated over a large area, including:

[0015] Substrate pretreatment and deposition of a superconducting thin film of known thickness on the substrate: Electrode patterns are defined on the surface of the superconducting thin film, and after development, an electrode layer of known thickness is deposited by magnetron sputtering, followed by a lift-off process to form device electrodes; Nanowire patterns are defined, and after development, reactive ion etching is performed, and after resist removal, a superconducting nanowire device chip is obtained.

[0016] Furthermore, the combined optical structure includes: a master plate serving as a substrate for supporting the optical cavity and a reflector chip serving as a complex optical structure. The master plate is used for alignment and bonding with the superconducting nanowire device; the reflector chip is used to form a weak resonant structure in the vertical direction together with the superconducting nanowire and the optical cavity, so that the incident light forms an enhanced light field at the location of the nanowire.

[0017] The optical structural parameters include: the structure and thickness of the optical cavity, and the material and thickness of the reflector.

[0018] Furthermore, the reflector chip and the master plate are fabricated separately; the flip bonding of the superconducting nanowire device with the combined optical structure includes: completing the alignment and bonding of the master plate and the superconducting nanowire device through a flip-chip alignment and bonding system, and then aligning and bonding the reflector chip with the master plate or the superconducting nanowire device.

[0019] Furthermore, the master template also includes: alignment marks and bonding regions with indium pillars; the preparation process of the master template includes:

[0020] The substrate is pretreated, and master electrodes, alignment marks and bonding pads are defined on the substrate. After development, the electrode layer is deposited by magnetron sputtering and then stripped to form a metal pattern. The optical cavity pattern is defined on the receiving side of the superconducting nanowire device, and a SiO2 optical cavity layer of known thickness is deposited.

[0021] Indium patterns are defined in the bonding region, and then indium pillars of a predetermined thickness are prepared and peeled off.

[0022] After preparation, a protective adhesive is coated on the surface of the master template and cut into small pieces of a preset size for flip-chip alignment with a single superconducting nanowire device.

[0023] Furthermore, the alignment and bonding of the master plate and the superconducting nanowire device via the flip-chip alignment welding system includes:

[0024] Using PDMS stamping, a single screened superconducting nanowire device is picked up from a released superconducting nanowire device chip and transferred to a temporary carrier;

[0025] The superconducting nanowire device on the temporary carrier is placed into the flip-chip alignment and welding system to align the effective detection area of ​​the superconducting nanowire single-photon detector with the optical cavity area on the mother plate, and to align the electrodes of the superconducting nanowire device with the indium pillars on the mother plate.

[0026] A stable metal connection is formed by performing flip bonding for a preset duration at a preset temperature and pressure.

[0027] Furthermore, when the light incident direction is through the substrate of the master plate into the stacked structure, the master plate also includes an anti-reflection layer disposed on the incident side;

[0028] The optical structural parameters also include: the material and thickness of the anti-reflective layer;

[0029] The preparation process of the master template also includes: depositing an anti-reflective layer of known thickness on the incident side.

[0030] Furthermore, when the reflector chip is disposed on one side of the master plate, the reflector chip and the master plate are fabricated on the same substrate as part of the master plate's optical structure.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0032] (1) This invention separates and independently prepares superconducting nanowire devices and optical cavity structures, and then achieves vertical stacking integration through high-precision transfer and low-temperature flip bonding. This completely changes the traditional process mode of single-wafer layer-by-layer stacking, avoiding the high-temperature deposition, multiple etching, peeling, cleaning and other strong damage processes required by the optical cavity for superconducting films and nanowire structures. This fundamentally avoids the degradation of the morphology of superconducting films and nanowires, effectively stabilizes the critical current of the device, reduces dark count, and maintains excellent intrinsic performance of single-photon detection. At the same time, the device preparation, optical structure preparation and stacking are separated into independent but precisely aligned modules, which is compatible with mature micro-nano processes such as electron beam exposure, laser direct writing, magnetron sputtering, PECVD, electron beam evaporation, reactive ion etching and flip bonding, improving the compatibility and yield of device processing. In addition, by separating the device and the master, the number of superconducting detectors can be increased on the same size superconducting film, improving the production efficiency of the detector and reducing the manufacturing cost.

[0033] (2) The present invention completes the screening of the electrical performance of superconducting nanowire devices before flip bonding, and only carries out the subsequent optical cavity integration and bonding process for superconducting nanowire devices with qualified performance, avoiding the ineffective process investment of traditional processes for failed and degraded devices, and greatly improving the resource utilization rate and the yield of large-area array fabrication.

[0034] (3) The separation preparation and three-dimensional stacking architecture proposed in this invention can be extended to novel micro-nano optical structures such as DBR multilayer cavity, metal-dielectric composite cavity, photonic crystal, and metasurface. The film thickness, material system and layer structure can be flexibly adjusted according to different working wavelengths such as ultraviolet, visible light and communication bands, which greatly improves the design freedom and band adaptability of optical cavity and adapts to the needs of high-precision single photon detection in multiple scenarios and multiple bands. Attached Figure Description

[0035] Figure 1 This is a flowchart of a hybrid integration method for a superconducting nanowire single-photon detector provided in an embodiment of the present invention;

[0036] Figure 2 This is a simulation of the three-layer composite structure with a wavelength of 1550nm in this embodiment of the invention, and its simulated light absorption rate curve.

[0037] Figure 3 This is a simulation of the three-layer composite structure with a wavelength of 1064nm in this embodiment of the invention, and its simulated light absorption rate curve.

[0038] Figure 4 This is a schematic diagram of a superconducting nanowire device chip fabricated over a large area in an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of the master template structure in an embodiment of the present invention, wherein a is a master template without a reflector and b is a master template with a reflector.

[0040] Figure 6 This is a schematic diagram of the transfer process of the superconducting nanowire device in an embodiment of the present invention, wherein a is the device after being hollowed out, b is the PDMS stamp picking device, and c is a single device after transfer. Detailed Implementation

[0041] To better understand this invention, the following description, in conjunction with the accompanying drawings of the embodiments of this invention, will provide further details, but these descriptions are not intended to limit the scope of the invention. Various modifications and improvements made to the technical solutions of this invention by those skilled in the art without departing from the inventive concept should fall within the protection scope of this invention.

[0042] This embodiment discloses a hybrid integration method for superconducting nanowire single-photon detectors. The core idea is as follows: First, the superconducting nanowire device structure and optical structure are jointly simulated and designed. The optimal layout design, as well as the device structure parameters and optical structure parameters, are determined by observing the light absorption rate. Then, the superconducting nanowire device and the combined optical structure are fabricated separately based on the device structure parameters and optical structure parameters. After the device is fabricated, an electrical screening is performed. Finally, the screened superconducting nanowire device is stacked with the combined optical structure using PDMS transfer stamping and flip-chip alignment bonding, and then packaged into a superconducting nanowire single-photon detector.

[0043] refer to Figure 1 The hybrid integration method for superconducting nanowire single-photon detectors includes the following steps:

[0044] Step 1: Co-simulation design to obtain device structural parameters and optical structure and parameters.

[0045] Specifically, the co-simulation design includes two parts: overall layout design and optical absorption simulation. First, the overall layout of the single-photon detector is designed based on the target operating wavelength, light incident direction, and optical cavity material properties of the superconducting nanowire single-photon detector. Then, by establishing an electromagnetic simulation model, optical absorption simulation is performed with the light absorption rate of the superconducting nanowire as the optimization target, and the device structural parameters and optical structural parameters are determined iteratively.

[0046] In one embodiment, the overall layout design is performed in LayoutEditor software to determine the effective detection area of ​​the SNSPD, the optical structure composition, the device structure composition, the thickness of the Au electrode, the thickness of the thin film, the alignment marks and bonding areas, and the routing, width and duty cycle of the nanowires.

[0047] Optical absorption simulation was performed in COMSOL software to determine the incident side structure, optical cavity thickness, anti-reflective layer material and thickness, as well as the position, material and thickness of the reflector.

[0048] Specifically, in COMSOL, the photon absorption process of SNSPD is equivalent to a plane wave incident on a periodic nanowire grating structure.

[0049] Since nanowires are periodic in the transverse direction, a periodic unit is selected to establish a two-dimensional model. Periodic boundary conditions or Floquet periodic boundary conditions are set on both sides of the periodic unit, and ports, scattering boundaries or matching layers are set in the incident direction.

[0050] Plane waves are incident perpendicularly from the silicon substrate side or a specified incident side. The local electric field distribution is calculated for different nanowire thicknesses, linewidths, periods, fill factors, and dielectric layer thicknesses.

[0051] It should be noted that in the simulation program of this embodiment, based on Calculate the light absorptivity, i.e.:

[0052] ;

[0053] In the formula, This represents the time-averaged resistance dissipation in the nanowire. Indicates the period of the nanowire. Indicates the thickness of the nanowire. Represents the time-averaged incident Poynting power density, where:

[0054] ;

[0055] for Typical nanowires with a value of 4-7 nm Its value is given by Ohm's law:

[0056] ;

[0057] In other implementations, the light absorption rate can also be calculated from the standing wave ratio.

[0058] Figure 2 The optimal three-layer stacked structure designed for a wavelength of 1550 nm is demonstrated. The optical structure includes a master substrate supporting a simple optical cavity and a gold mirror serving as a complex optical structure. The master substrate is fabricated by growing 264 nm SiO2 on a silicon substrate. Since the incident light enters from the bottom of the master substrate, a 207 nm silicon nitride layer is placed on the incident side as an anti-reflection layer. The superconducting nanowire device is fabricated by growing 7 nm NbN on the 264 nm SiO2 substrate, and the gold mirror is placed on one side of the device.

[0059] like Figure 2 As shown in the simulation curve, at a working wavelength of 1550nm, Figure 2 The superimposed structure shown enables the optical cavity to achieve a light absorption rate of 99.99%.

[0060] Figure 3 This demonstrates the optimal three-layer stacked structure designed at a wavelength of 1064nm, and... Figure 2 The difference is that the master is prepared by growing 185nm SiO2 on an Al2O3 substrate, with a 142nm silicon nitride layer on its incident side as an anti-reflection layer; the gold mirror is placed on one side of the device and is prepared by generating 100nm Au on a 290nm SiO2 dielectric spacer layer.

[0061] like Figure 3 As shown in the simulation curve, at a working wavelength of 1064nm, Figure 3 The superimposed structure shown enables the optical cavity to achieve a light absorption rate of 94.8%.

[0062] It should be noted that the number of layers can be adjusted. In addition to the three-layer structure of device-master-gold mirror, it can also be expanded into a two-layer or multi-layer flip-chip structure depending on the complexity of the optical cavity.

[0063] In other implementations, other layout drawing software and optical simulation software can also be used for layout design and optical simulation.

[0064] Step 2: Separate and prepare the superconducting nanowire device, the master template, and the mirror.

[0065] On the one hand, superconducting nanowire device chips are fabricated on a large area based on device structure parameters, and qualified superconducting nanowire devices are screened through performance testing. This specifically includes the following steps:

[0066] Step 211: Substrate Pretreatment

[0067] Specifically, a four-inch double-sided polished silicon substrate with a thermally oxidized SiO2 layer is cut into 2cm×2cm wafers; after dicing, the wafers are ultrasonically cleaned in acetone, ethanol and deionized water in sequence, and then dried with nitrogen.

[0068] Step 212: Preparation of NbN thin films

[0069] Specifically, a NbN superconducting thin film of about 7 nm was deposited on the substrate using magnetron sputtering.

[0070] It should be noted that the NbN thickness can be adjusted in the range of approximately 5-10 nm depending on the performance of the target device, and the thin film composition and crystal state can be optimized between amorphous, polycrystalline, or near-polycrystalline structures depending on the process conditions.

[0071] Step 213: Fabrication of Au electrode for device

[0072] Specifically, Au electrode patterns are defined on the surface of an NbN thin film by laser direct writing, followed by magnetron sputtering deposition of 100 nm Au after development, and then device electrodes are formed by a lift-off process.

[0073] Step 214: Preparation of SNSPD Nanowires

[0074] Specifically, high-precision nanowire patterns are defined by electron beam exposure, NbN is etched by reactive ion etching after development, and SNSPD nanowire devices are obtained after resist removal.

[0075] Step 215: Large-area fabrication and screening of superconducting nanowire device arrays

[0076] like Figure 4 As shown, approximately 1800 superconducting nanowire devices were fabricated on a 2cm×2cm chip through layout optimization. After fabrication, the device chips were placed on a probe station or a low-temperature testing system, and devices that met the requirements for critical current, switching characteristics, dark count, or response performance were screened through automated testing procedures.

[0077] Step 216: Device Hollowing / Release

[0078] Specifically, the screened device areas are re-coated and the cut-out pattern is defined by laser direct writing. First, BOE solution is used to remove SiO2 from the exposed areas, and then reactive ion etching or other silicon etching processes are used to remove Si from the designated areas to obtain a locally released device that can be picked up by the PDMS stamp.

[0079] On the other hand, the master template provided in this embodiment is an optical cavity carrier substrate independent of the device chip and the gold reflector chip, used to provide the optical cavity layer, alignment marks, bonding pads and indium pillars, and to receive the selected SNSPD devices in subsequent flip bonding.

[0080] When the light incident direction is through the substrate of the master plate into the stacked structure, the master plate also includes an anti-reflection layer disposed on the incident side;

[0081] Specifically, this embodiment uses indium pillars as the fixed interconnect structure in the flip-chip bonding stage. Indium metal has excellent low-temperature toughness, perfectly adapting to deep cryogenic operating environments of 2K~4K. It can buffer thermal mismatch stress between the device and the substrate, avoiding problems such as interface cracking, electrode detachment, and structural warping during cryogenic thermal cycling. In addition, indium pillars can achieve large-area tight bonding through plastic deformation, forming an Au-In metallurgical alloy interface with gold electrodes. This balances low contact resistance, high mechanical stability, and high-precision support, effectively reducing interface contact resistance and parasitic thermal effects. It avoids interface slippage, delamination, and parameter drift caused by cryogenic thermal cycling and encapsulation stress, significantly improving the low-temperature operating stability and long-term reliability of the device. Compared with conventional pure gold bonding and solder bonding, it is more suitable for the cryogenic precision integration requirements of superconducting devices.

[0082] It should be noted that the bonding material and bonding method can be adjusted. In this embodiment, Au-In metal bonding is preferred, but In, AuSn, InSn, Au-Au hot-press bonding, micro-bump bonding or other bonding structures that can provide stable electrical / mechanical connections can also be selected according to the process and low-temperature compatibility.

[0083] In one embodiment, the process of preparing the master based on optical structural parameters includes:

[0084] Step 221: Cut the double-sided polished silicon substrate into 2cm×2cm pieces and clean them;

[0085] Step 222: Define the master Au electrode, alignment mark and bonding pad by laser direct writing. After development, remove the SiO2 in the specified area on the back as needed, and then use magnetron sputtering to deposit Au and peel it off to form a metal pattern.

[0086] Step 223: Prepare a 207 nm SiN antireflection layer on the incident side using plasma-enhanced chemical vapor deposition;

[0087] Step 224: Define the optical cavity pattern on the receiving side of the device by laser direct writing, and form a 250-265nm SiO2 optical cavity layer by electron beam evaporation or magnetron sputtering, and then remove excess material.

[0088] It should be noted that the method of optical structure fabrication can be adjusted, and different optical structures can be fabricated using electron beam evaporation, thermal evaporation, magnetron sputtering, spin coating, transfer printing, dry etching, wet etching, or stripping processes.

[0089] Step 225: Define the In pattern in the bonding area by laser direct writing, form 200nm In bumps by vacuum evaporation and then peel them off.

[0090] Step 226: After preparation, a protective adhesive can be applied to the surface of the master plate and cut into small pieces of 4mm×4mm for subsequent flip-chip alignment with individual SNSPD devices.

[0091] In this embodiment, the gold reflector chip is fabricated separately from the master substrate. Its function is to be located on the opposite side of the SNSPD nanowire after the stacking and assembly, and together with the lower optical cavity and anti-reflection layer, form the target optical cavity, so that the incident light is enhanced at the NbN nanowire position.

[0092] Specifically, the gold reflector chip is fabricated on a separate silicon or silicon dioxide substrate. The process includes: first, substrate cleaning and patterning; then, SiO2 or other dielectric spacer layers are prepared according to the simulation design results; next, 100nm Au is deposited as the reflector layer; non-target areas are hollowed out or thinned through BOE and silicon etching processes, and indium pillars are prepared to form a reflector structure that is easy to flip-chip.

[0093] In other embodiments, the gold mirror can be fabricated on the same substrate as the master template, as part of the master template's optical structure.

[0094] Figure 5 The diagram shows the master template structure in two cases. In case a, the master template does not include the reflector and contains four indium pillars (top, bottom, left, and right). When soldering components, the top and bottom indium pillars are used, and when soldering the reflector, the left and right indium pillars are used. In case b, the master template includes the reflector and contains only the top and bottom indium pillars, which are used when soldering components.

[0095] It is important to note that whether the gold mirror is part of the master substrate can be selected based on the device's focusing method and optical cavity design. When the device uses a specific incident direction and requires integration of the reflective structure on the master substrate side, the gold mirror can be fabricated on the same substrate as the master substrate, serving as part of the master substrate's optical structure. However, when the reflective structure needs to be optimized, transferred, and bonded separately, the gold mirror can be fabricated independently of the master substrate and then aligned and bonded to the device or master substrate structure during the stacking stage.

[0096] The separation and fabrication method provided in this embodiment improves the compatibility of the three-dimensional hybrid integration process with different light-gathering schemes and complex optical cavity structures.

[0097] Step 3: Pick up qualified superconducting nanowire devices and flip-bond them with combined optical structures to form a stacked structure, then encapsulate and complete the electrical connection and optical path assembly.

[0098] This embodiment provides a three-dimensional stacked assembly process based on two-step flip-chip bonding. After the independent fabrication and device screening of the SNSPD device chip, optical cavity master, and gold mirror chip are completed, the decoupled integration of the superconducting device and the multilayer optical cavity structure is achieved through non-destructive device transfer, high-precision alignment, and Au-In metal bonding. This avoids the secondary process damage to the superconducting nanowires caused by the traditional monolithic stacking process, and finally forms an optical cavity enhanced SNSPD device with stable structure, accurate light field matching, and high performance consistency.

[0099] First, the pre-processed device chips are picked up and temporarily transferred as single devices without damage.

[0100] In one embodiment, a flexible PDMS transfer stamp is used to precisely contact a single qualified SNSPD device, and the micro-adhesion of PDMS is used to complete the non-destructive pickup. The picked-up superconducting device is then precisely attached to the surface of a temporary carrier made of heat-release adhesive material to achieve temporary fixation and orientation regularization of the device.

[0101] Figure 6 A schematic diagram of the device transfer process is shown, where a is the device after being hollowed out, b is the device picked up by the PDMS stamp, and c is a single device after transfer.

[0102] This transfer method can completely avoid mechanical extrusion, pulling and impact, fully protecting the ultrathin NbN superconducting film and the meandering nanowire structure, and avoiding morphological damage and performance degradation of the device before assembly.

[0103] Secondly, the first high-precision flip bonding of the SNSPD device and the optical cavity master plate was completed.

[0104] In one embodiment, the temporary carrier carrying the SNSPD device is placed into a high-precision flip-chip alignment and welding system. Alignment and calibration are completed by relying on the micron-level alignment marks preset on the master plate and the device. On the one hand, this ensures that the effective photosensitive detection area of ​​the SNSPD is precisely coincident with the central area of ​​the optical cavity layer of the master plate. On the other hand, it ensures that the Au electrode pattern of the device corresponds one-to-one with the In indium pillars on the surface of the master plate and is precisely aligned.

[0105] After alignment, flip bonding is completed under preset bonding temperature, bonding pressure and holding time conditions, so that Au metal and In metal undergo an alloying reaction to form a dense and stable metal metallurgical connection.

[0106] In one embodiment, the indium pillar welding process includes a staged heating process: holding at 150°C for 1 min and then at 220°C for 2 min, to promote stable contact between the indium pillar and the metal electrode. This metal connection not only provides an electrical path but also serves to fix the device and support its three-dimensional structure.

[0107] After indium pillar flip-chip bonding is completed, further optical alignment is required. This step is used to confirm the positional relationship between the effective detection area of ​​the SNSPD and the incident light spot, the central region of the optical cavity, and the subsequent mirror structure. Microscopic observation or optical testing can determine whether the light spot accurately falls within the effective area of ​​the device. Good alignment accuracy is crucial for ensuring high system detection efficiency, because the absorption efficiency of the SNSPD depends not only on the performance of the nanowire itself but also on the degree of spatial overlap between the incident light field and the nanowire absorption area.

[0108] Compared to traditional weak connection methods such as van der Waals bonding and Au-Au contact, the Au-In metal hard connection formed in this embodiment has multiple functions: it can realize low-resistance electrical conduction between the device electrodes and the motherboard circuit, ensuring the stability of low-temperature electrical transmission; it can also provide high-strength mechanical fixation, firmly locking the relative position of the device and the motherboard; at the same time, it relies on the bonding alignment accuracy to maintain the posture of the optical structure, effectively preventing interface slippage, misalignment and interlayer peeling problems, and greatly improving the assembly consistency and structural reliability of the stacked structure.

[0109] Next, the second flip-chip bonding of the gold reflector chip was completed, constructing a complete optical resonant stack structure.

[0110] In one embodiment, after the first bonding is completed and the device and the master form a stable composite structure, the independently prepared gold reflector chip and the aforementioned composite structure are sent back into the flip-chip bonding system for a second precise alignment and flip-chip bonding.

[0111] Through secondary stacking assembly, a complete stacked structure is formed from top to bottom, consisting of an incident-side SiN anti-reflection layer, a master optical cavity dielectric layer, an NbN superconducting nanowire detection layer, a dielectric spacer layer, and a gold reflector.

[0112] Finally, the post-processing and reliability verification of the entire device were completed.

[0113] In one embodiment, after the lamination bonding is completed, the device can be subjected to routine cleaning, visual inspection, and electrical screening. Due to the high bonding strength and excellent interface stability of Au-In metallurgical bonding interface, the laminated device can withstand routine cleaning processes, low-temperature cooling and thermal cycling, and subsequent packaging stress without failure issues such as contact resistance drift, interface delamination, or structural misalignment. The long-term operational stability and batch consistency of the device are significantly better than traditional monolithic integration and thin-film bonding solutions.

[0114] The stacked optical cavity enhanced SNSPD device is then installed into a dedicated low-temperature compatible package, and connected via wire bonding and PCB adapter board to achieve stable electrical lead-out of the device electrodes, ensuring stable signal transmission and uniform contact resistance under low-temperature conditions.

[0115] Optical coupling methods can be flexibly configured according to the operating band and application scenario, including direct fiber coupling, self-aligned fiber ferrule coupling, and focusing lens incident coupling.

[0116] During assembly, the optical path is strictly ensured to be incident in the forward direction, so that the photon to be measured enters the anti-reflection layer and the optical cavity dielectric layer perpendicularly from the preset incident side. After being enhanced by multiple reflections in the resonant cavity, it is accurately absorbed by the NbN superconducting nanowire in the middle layer. This ensures that after assembly, the NbN superconducting nanowire is accurately located at the peak position of the standing wave optical field of the optical cavity, maximizing the local optical field intensity and significantly improving the absorption efficiency of the superconducting nanowire for incident photons, thereby greatly enhancing the detection efficiency of the device.

[0117] Furthermore, after packaging and optical path assembly, the device is placed in a cryogenic cooling environment to conduct systematic performance testing and index characterization. The key parameters such as device system detection efficiency, dark count rate, time jitter, critical current characteristics, and response uniformity are tested and calibrated to complete the full set of device performance verification and screening, and obtain a cavity-enhanced superconducting nanowire single-photon detector with high stability and high consistency.

[0118] This embodiment adopts a decoupled assembly approach of "device pre-screening - independent optical structure fabrication - non-destructive transfer - two-step flip-chip metallurgical bonding", which completely avoids the drawbacks of traditional processes that involve adding damaging processes such as high temperature, etching, and peeling to the formed superconducting device. It has significant technical advantages in protecting the intrinsic properties of superconducting devices, improving fabrication yield, expanding the degree of freedom in optical structure design, and enhancing the low-temperature reliability of devices.

[0119] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered by the present invention.

Claims

1. A hybrid integration method for superconducting nanowire single-photon detectors, characterized in that, include: Based on the target operating wavelength, light incident direction, and optical cavity material properties of the superconducting nanowire single-photon detector, the overall layout design of the single-photon detector is carried out. By establishing an electromagnetic simulation model, optical absorption simulation is performed with the light absorption rate of the superconducting nanowire as the optimization target, and the device structure parameters and optical structure parameters are determined iteratively. Based on the aforementioned device structure parameters, superconducting nanowire device chips were fabricated over a large area, and qualified superconducting nanowire devices were screened through performance testing. A combined optical structure is fabricated based on the aforementioned optical structure parameters; The qualified superconducting nanowire devices are picked up and flip-bonded with the combined optical structure to form a stacked structure, which is then packaged and the electrical connection and optical path assembly are completed.

2. The hybrid integration method for superconducting nanowire single-photon detectors according to claim 1, characterized in that, In the flip-chip bonding stage, indium pillars are used as the fixed interconnect structure.

3. The hybrid integration method for superconducting nanowire single-photon detectors according to claim 1, characterized in that, The device structural parameters include: the effective detection area of ​​the SNSPD, the thickness of the thin film, the thickness of the electrode, and the routing, width, and duty cycle of the nanowires.

4. The hybrid integration method for superconducting nanowire single-photon detectors according to claim 3, characterized in that, The large-area fabrication of superconducting nanowire device chips based on the device structure parameters includes: Substrate pretreatment, followed by deposition of a superconducting thin film of known thickness on the substrate: Electrode patterns are defined on the surface of the superconducting thin film. After development, an electrode layer of known thickness is deposited by magnetron sputtering, and then the device electrodes are formed by a lift-off process. The nanowire pattern is defined, and after development, reactive ion etching is performed. After resist removal, the superconducting nanowire device chip is obtained.

5. The hybrid integration method for superconducting nanowire single-photon detectors according to claim 1, characterized in that, The combined optical structure includes: It serves as a master template for the optical cavity support substrate, used for alignment and bonding with superconducting nanowire devices; As a complex optical structure, the reflector chip is used together with the superconducting nanowire and optical cavity to form a weak resonant structure in the vertical direction, so that the incident light forms an enhanced optical field at the location of the nanowire. The optical structural parameters include: the structure and thickness of the optical cavity, and the material and thickness of the reflector.

6. The hybrid integration method for superconducting nanowire single-photon detectors according to claim 5, characterized in that, The reflector chip and the master plate are manufactured separately; The flip-chip bonding of the superconducting nanowire device to the combined optical structure includes: completing the alignment and bonding of the master plate and the superconducting nanowire device through a flip-chip alignment and bonding system, and then aligning and bonding the mirror chip to the master plate or the superconducting nanowire device.

7. The hybrid integration method for superconducting nanowire single-photon detectors according to claim 6, characterized in that, The master plate also includes: alignment marks and bonding areas with indium pillars; The preparation process of the master plate includes: The substrate is pretreated, and master electrodes, alignment marks and bonding pads are defined on the substrate. After development, the electrode layer is deposited by magnetron sputtering and then stripped to form a metal pattern. The optical cavity pattern is defined on the receiving side of the superconducting nanowire device, and a SiO2 optical cavity layer of known thickness is deposited. Indium patterns are defined in the bonding region, and then indium pillars of a predetermined thickness are prepared and peeled off. After preparation, a protective adhesive is coated on the surface of the master template and cut into small pieces of a preset size for flip-chip alignment with a single superconducting nanowire device.

8. The hybrid integration method for superconducting nanowire single-photon detectors according to claim 7, characterized in that, The alignment and bonding of the master plate and the superconducting nanowire device via a flip-chip alignment welding system includes: Using PDMS stamping, a single screened superconducting nanowire device is picked up from a released superconducting nanowire device chip and transferred to a temporary carrier; The superconducting nanowire device on the temporary carrier is placed into the flip-chip alignment and welding system to align the effective detection area of ​​the superconducting nanowire single-photon detector with the optical cavity area on the mother plate, and to align the electrodes of the superconducting nanowire device with the indium pillars on the mother plate. A stable metal connection is formed by performing flip bonding for a preset duration at a preset temperature and pressure.

9. The hybrid integration method for superconducting nanowire single-photon detectors according to claim 7, characterized in that, When the light incident direction is through the substrate of the master plate into the stacked structure, the master plate also includes an anti-reflection layer disposed on the incident side; The optical structural parameters also include: the material and thickness of the anti-reflective layer; The preparation process of the master template also includes: depositing an anti-reflective layer of known thickness on the incident side.

10. The hybrid integration method for superconducting nanowire single-photon detectors according to claim 5, characterized in that, When the reflector chip is placed on one side of the master plate, the reflector chip and the master plate are fabricated on the same substrate as part of the master plate's optical structure.

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