Nonvolatile memory cell array based on silicon nanowire ion regulation effect and preparation method thereof

Abstract

This invention discloses a non-volatile memory cell array based on the ion modulation effect of silicon nanowires and its fabrication method. The array includes a substrate, multiple independent memory cells disposed on the substrate, and an external selection circuit for independent addressing of each cell. Each memory cell constitutes an independent bit, and the cells are electrically isolated from each other through a dielectric isolation structure. The structures are identical and independent. Each memory cell comprises: a pair of source / drain electrodes, a bundle of doped silicon nanowires, a solid ion-conducting layer, and an ion reservoir (top electrode). This invention solves the problems of insufficient readout current, sensitivity to single-wire defects, large resistance fluctuations, and the difficulty in reversibly applying the ion-silicon reaction process to non-volatile memory in existing silicon-based nanowire memory cells.

Description

Technical Field

[0001] This invention relates to the fields of non-volatile memory, resistive switching memory devices, silicon-based micro / nanoelectronic devices and ion control devices, and particularly to a non-volatile memory and its fabrication method that utilizes silicon nanowires as ion-responsive conductive channels, achieves non-volatile resistive state control through reversible migration of ions between the reservoir, solid electrolyte and silicon nanowires, and forms an array of multiple completely independent memory cells. Background Technology

[0002] With the development of IoT, wearable electronics, flexible electronics, and edge computing chips, the demand for low-power, high-reliability, and flexibly integrateable non-volatile memory is becoming increasingly urgent. Traditional flash memory faces miniaturization limits and operating voltage bottlenecks; while resistive random access memory (RRAM) and phase-change memory (PCM) have the potential for miniaturization, they suffer from problems such as large resistance fluctuations, low read current, and insufficient compatibility with silicon processes.

[0003] Silicon, as the most mature semiconductor material, possesses inherent advantages in micro / nano fabrication processes and CMOS back-end integration. Fabricating silicon into nanowire structures significantly shortens ion diffusion distances and reserves volume expansion buffer space between nanowire bundles, providing a structural basis for novel non-volatile storage mechanisms based on silicon. Specifically, doped silicon nanowires offer two key structural advantages: first, their size (within 100 nm in diameter) significantly shortens ion diffusion distances, improving ion modulation efficiency; second, the nanowire structure provides buffer space for volume changes during ion insertion, accommodating significant volume expansion and avoiding cracking and pulverization problems common in bulk silicon or coarse nanowires. Furthermore, the in-plane oriented alignment of silicon nanowires facilitates the direct formation of source / drain electrode connection structures, a crucial foundation for achieving high reliability, high consistency, and flexible compatibility.

[0004] However, despite the aforementioned advantageous structural features of silicon nanowires, existing silicon nanowire-based or non-volatile memory technologies have failed to fully utilize these advantages, and can be mainly categorized into three types: The first type consists of single-strand silicon nanowire field-effect transistors or single-strand resistive switching memory cells. This type of scheme utilizes a single nanowire as the channel or resistive switching medium, and achieves state switching through gate voltage or voltage pulses. However, the diameter of a single nanowire is extremely small (typically less than 100 nm), resulting in a very small absolute current value, requiring highly sensitive readout circuitry. At the same time, single nanowires are extremely sensitive to surface defects, interface states, and process fluctuations, leading to discrete resistance distribution between cells, limited yield, and difficulty in constructing large-scale uniform arrays.

[0005] The second category is resistive switching memory based on thin-film or bulk silicon. This type of solution achieves resistive switching through metal-insulator-metal (MIM) structures or silicon-based conductive filaments. The technology is relatively mature, but the resistive switching region is random, and the position of the conductive filaments is uncontrollable, resulting in poor device cycling consistency and a wide resistive state distribution. Furthermore, thin-film silicon lacks the geometric advantages of nanowire structures for ion transport and stress relief, making it difficult to achieve compatibility with flexible substrates.

[0006] The third category consists of battery electrodes or energy storage devices based on the reaction between silicon and ions. This type of solution utilizes the alloying reaction between silicon and ions (such as lithium ions) to achieve high-capacity energy storage, but its design goal is energy storage rather than information storage. Under deep reaction conditions, silicon materials undergo enormous volume expansion (>300%), leading to structural pulverization, interface instability, and cycle degradation. Furthermore, existing solutions do not transform the ion insertion / extraction process into two precisely distinguishable stable resistive states, nor do they solve core memory problems such as cell addressing, array integration, and non-volatile readout.

[0007] In summary, the main drawbacks of existing solutions are: the current of a single nanowire is too small and fluctuates drastically; the consistency of resistive switching in thin films is poor; and while ion storage solutions possess resistive switching potential, they lack reversible design, independent unit architecture, and effective integration of the geometric advantages of silicon nanowires. Therefore, there is an urgent need for a non-volatile memory structure that can utilize multiple silicon nanowires connected in parallel to increase current, achieve stable resistive switching through reversible ion migration, and form an array of completely independent units to meet the practical requirements of high reliability, high consistency, and flexible integration. Summary of the Invention

[0008] This invention proposes a non-volatile memory cell array based on the ion modulation effect of silicon nanowires and its preparation method, aiming to solve the problems of insufficient readout current, sensitivity to single wire defects, large resistance fluctuations, and the difficulty in reversibly applying the ion-silicon reaction process to non-volatile storage in existing silicon-based nanowire memory cells.

[0009] Specifically, the present invention needs to solve the following technical problems: (1) How to use doped silicon nanowires to form conductive channels, read current in a single memory cell, and reduce resistance fluctuations caused by defects in a single nanowire; (2) How to use doped silicon nanowires (with a diameter of 1 nm to 100 nm, preferably 2 nm to 50 nm, more preferably 6 nm to 30 nm) to alleviate volume expansion stress during ion insertion / extraction and achieve reversible, non-destructive resistance state switching; (3) How to ensure that each storage unit has an independent ion reservoir and solid electrolyte coverage, so as to ensure that the units do not interfere with each other and achieve stable "0" and "1" resistance state maintenance; (4) How to integrate multiple completely independent memory cells on the same substrate to form an array, with each cell having an independent electrode lead-out, and realize cell addressing, independent writing and reading control through an external selection circuit, thereby forming a high-reliability memory array that can be integrated on a large scale. (5) How to make the memory compatible with flexible substrates and low-temperature back-end processes so that it can be used in flexible electronics and three-dimensional integration scenarios.

[0010] The specific plan is as follows: On one hand, this invention provides a non-volatile memory cell array based on the ion modulation effect of silicon nanowires, including a substrate, a plurality of independent memory cells disposed on the substrate, and an external selection circuit for independent addressing of each cell; each memory cell constitutes an independent bit, and the cells are electrically isolated from each other through a dielectric isolation structure, with identical structures and mutual independence; the memory cell comprises: A pair of source / drain electrodes (S / D) are disposed on the substrate surface and arranged at intervals along a first direction, serving as the source (S) and drain (D) respectively. The source and drain electrodes are independently led out and serve as the bottom electrodes of each memory cell for external connection. A silicon-doped nanowire bundle is composed of n silicon-doped nanowires connected in parallel. The silicon-doped nanowires are arranged in parallel along the channel direction between the source and the drain, and their two ends are electrically connected to the source and the drain, respectively. The silicon-doped nanowires serve as the active host for ion insertion and extraction. A solid ion-conducting layer covers the active region between the surface of the doped silicon nanowires and the source / drain electrodes, and at least partially enters the gap between adjacent nanowires, providing a continuous transport channel for ions. An ion reservoir, positioned above the solid-state ion-conducting layer, covers the active region of the doped silicon nanowire bundle corresponding to the memory cell. It serves as both the ion supply and receiving layer and also acts as the independent top electrode for that memory cell. The ion reservoir of each memory cell is independently led out, serving as the top electrode connection point for that cell, and is not connected to the ion reservoirs of other cells. Alternatively, an alternative architecture with symmetrical electrodes at both ends and gate-controlled ion migration can be used.

[0011] Furthermore, the source and drain electrodes are made of titanium, chromium, nickel, titanium nitride, tungsten, or composite layers thereof (e.g., Ti / TiN bilayer structure), with a thickness of 10 nm to 50 nm; the electrode material is compatible with the ion reservoir material to avoid electrochemical corrosion or alloying reactions under operating voltage.

[0012] Further, n is an integer from 1 to 100, preferably from 4 to 50, more preferably from 6 to 20; the diameter of the doped silicon nanowire is from 1 nm to 100 nm, preferably from 6 nm to 30 nm; the length is from 1 μm to 10 μm; multiple nanowires together form a conductive channel for a storage cell, rather than each nanowire storing information separately; the doped silicon nanowire is grown and transferred to the substrate using IPSLS (in-plane solid-liquid-solid) technology, or grown in situ directly in a patterned guide structure on the substrate, and then annealed (200–400°C, nitrogen atmosphere) to form a stable crystalline structure.

[0013] Furthermore, the doped silicon nanowires serve as the active host for ion insertion / extraction; in the initial state (unactivated state), the nanowire bundle is crystalline doped silicon (c-Si), with doping including p-type doping (such as indium, boron) or n-type doping (such as phosphorus, arsenic), and the doping concentration ranges from 10. 16 cm -3 Up to 10 19 cm -3 The selection is adjusted based on the initial resistivity required by the device, the target resistance-state contrast, and the interface characteristics of the solid electrolyte system; p-type indium doping is preferred, with a concentration of 10%. 17 cm -3 Up to 3×10 17 cm -3 This concentration range ensures that the initial resistivity is 10. -1 Up to 10 1 The concentration is on the order of Ω·cm, which avoids exceeding the Mott transition critical concentration due to heavy doping (the Mott transition critical concentration for indium doping is lower than that for boron doping, which is approximately 3.5 × 10⁻⁶). 18 cm -3 This results in metallic conductivity and loss of high-resistivity contrast, while avoiding an excessively wide space charge layer at the semiconductor / electrolyte interface due to light doping, which leads to lithium ion localization at the edges and difficulty in uniform embedding. Controllable doping concentration is achieved by adjusting at least one of the following process parameters: the atomic ratio of dopant elements in the catalyst, the dopant flow rate ratio in the growth source gas, the growth temperature, and the annealing conditions.

[0014] Furthermore, the solid-state ion-conducting layer isolates the silicon nanowires from the ion reservoir above, and is selected from oxide solid electrolytes, sulfide solid electrolytes, oxynitride solid electrolytes, polymer solid electrolytes or their composite structures, with a thickness of 50 nm to 200 nm.

[0015] Furthermore, the dielectric isolation structure is a dielectric isolation layer or an insulating trench, which is disposed between adjacent storage cells to completely electrically isolate the ion reservoir, solid ion conduction layer and active region of doped silicon nanowire bundle of each cell, thereby preventing ion crosstalk and electrical crosstalk between cells.

[0016] Furthermore, the memory cell also includes a gate electrode disposed above the solid-state ion-conducting layer and isolated from the ion-conducting layer by a gate insulating layer, used for electric field-controlled ion migration. Multiple memory cells are arranged in a one-dimensional or two-dimensional array on the same substrate, each cell having an independent top electrode (ion reservoir lead-out) and bottom electrode (source drain electrode lead-out). Voltages are applied to the top and bottom electrodes of each memory cell through external selection circuits (such as multiplexers, switch arrays, independent pads, or probe arrays) to achieve independent writing, erasing, and reading of the cells. Since each cell is completely independent and isolated from each other, applying an operating voltage to one cell will not affect the state of other cells.

[0017] Furthermore, the operation mode of the storage unit is as follows: when writing "1" (low resistance state), a first polar voltage is applied to the top electrode of the selected unit, and ions are injected into the crystalline silicon nanowires through the solid ion conduction layer to form an amorphous ion-silicon alloy phase, and the resistance drops to the low resistance state; when erasing "0" (high resistance state), a reverse voltage is applied, ions are extracted and returned to the ion reservoir, the nanowire bundle is restored to amorphous silicon, and the resistance rises back to the high resistance state; when reading, a read voltage far below the write threshold is applied, and the resistance state is determined by detecting the current, and the read process is non-destructive.

[0018] On the other hand, the present invention provides a method for fabricating a non-volatile memory cell array based on the ion modulation effect of silicon nanowires, comprising the following steps: S1 provides a clean substrate: Si wafers, PI or other suitable substrates are provided; S2, Preparation of doped silicon nanowires: In each memory cell region, a bundle of doped silicon nanowires consisting of n doped silicon nanowires connected in parallel is formed, where n is an integer from 1 to 100. S3, forming source and drain electrodes: and patterning source and drain electrodes arranged at intervals along a first direction in each memory cell region, wherein the spacing between the source and drain electrodes defines the nanowire channel length, and an isolation region is reserved between each memory cell region; the source and drain electrodes are obtained by photolithography and electron beam evaporation; S4, Deposit a solid-state ion-conducting layer: Deposit a solid-state ion-conducting film on the substrate on which the doped silicon nanowire bundles have been formed, such that the solid-state ion-conducting layer continuously covers the surface of the doped silicon nanowire bundles in each memory cell region, fills the gaps between adjacent nanowires, and covers the active region between the source and the drain; the solid-state ion-conducting layer is obtained by atomic layer deposition; S5, Forming an ion reservoir: An ion supply layer is deposited above the solid ion conduction layer and patterned by photolithography and etching to form an independent ion reservoir above each memory cell. The ion reservoirs of each memory cell are completely disconnected from each other, and each ion reservoir is independently led out as the top electrode connection terminal of the memory cell. The ion reservoir can also be obtained by atomic layer deposition. S6, Source and drain electrode lead-out: The source and drain of each memory cell are led out independently to form the bottom electrode external connection terminal; S7, forming a dielectric isolation structure: a dielectric isolation structure is formed between adjacent memory cells to completely electrically isolate the ion reservoir, solid ion conduction layer and active region of doped silicon nanowire bundles of each memory cell.

[0019] Further, in step S1, a silicon wafer, glass, ceramic, metal foil, or a flexible polyimide substrate is provided as a substrate. Multiple isolated memory cell regions are formed on the substrate surface using photolithography, etching, or nanoimprint lithography, and source / drain electrodes (S / D) are patterned within each cell region. The source / drain electrodes are arranged along a first direction, and their spacing defines the length of the nanowire channel. Isolation regions are reserved between each cell region for subsequent formation of a dielectric isolation structure.

[0020] Furthermore, in step S2, nanowire bundles are prepared and arranged using one of the following two process routes: Route A (IPSLS in-situ growth, preferred route): Ordered silicon nanowires are directly grown in-situ on a patterned guiding structure (such as steps, trenches, or catalytic site arrays) of the target substrate using IPSLS (In-Plane Solid-Liquid-Solid) technology. First, growth channels of the SiNWs are photolithographically patterned, followed by ICP etching. After channel formation, a second photolithography is performed to pattern the metal catalyst channels, then the metal catalyst is thermally evaporated, stripped, and then subjected to long-wire operation in PECVD. After H2 plasma treatment and a-Si film deposition in PECVD, the growth diameter is 1 nm to 100 nm (preferably 2 nm to 50 nm, more preferably 6 nm to 30 nm), and the indium doping concentration is controllable, preferably 10 nm. 17 cm -3 Up to 3×10 17 cm -3The length of the nanowires is controlled between 1 μm and 10 μm. The controllable doping concentration is achieved by adjusting at least one parameter among the following: the atomic ratio of indium to silicon in the catalyst, the indium dopant flow rate ratio in the growth source gas, the growth temperature (within the range of 300-400°C), and the annealing conditions (250-350°C, 30-60 minutes). The doping concentration of different memory cells in the same array can be regionally controlled by differentiating the composition or size of the catalyst particles. After growth, crystallization is achieved by annealing at 250–350°C for 30–60 minutes. By controlling the growth temperature, time, and catalyst particle size, the number, diameter, and length of nanowires in each cell are kept consistent. This route allows the nanowires to be grown directly on the target substrate without transfer, which is the preferred embodiment of this invention.

[0021] Route B (VLS Growth Substrate + Transfer Assembly): Silicon nanowires are fabricated over a large area on a dedicated growth substrate (e.g., SiO2 / Si) using VLS (gas-liquid-solid) technology. The nanowires are transferred to the source / drain electrodes of the target memory cell via dry transfer (e.g., PDMS stamp pick-and-print) or wet transfer (e.g., solution dispersion followed by dielectrophoresis-assisted assembly). Through dielectrophoretic force field or microchannel self-assembly, n nanowires (n = 2 to 100) are overlapped parallel to each other along the source / drain direction to form a nanowire bundle. The spacing between nanowires within the same cell is 20 nm to 100 nm. Local annealing (200-300°C) or metal reinforcement is applied to the contact area between the nanowires and the source / drain electrodes to reduce contact resistance. This route is suitable for substrates where direct IPSLS growth is not possible or for scenarios requiring heterogeneous integration.

[0022] Further, in step S3, a solid ion-conducting thin film is deposited on the substrate where the nanowire bundle has been formed, so that it continuously covers the surface of the nanowire bundle, fills the gaps between the nanowires, and covers the active region between the source and drain electrodes within each memory cell region. The deposition method can be magnetron sputtering, chemical vapor deposition, atomic layer deposition, or pulsed laser deposition. After deposition, low-temperature annealing can improve the interface density.

[0023] Furthermore, in step S4, an ion supply layer is deposited above the solid-state ion conduction layer and patterned by photolithography and etching, so that an independent ion reservoir region is retained above each memory cell, and the ion reservoirs of each cell are completely disconnected. Each ion reservoir is independently led out as the top electrode connection terminal of that cell.

[0024] The ion reservoir in this invention is not limited to a metallic lithium layer; pre-lithiation compounds can also be used as the ion supply layer and top electrode functional layer. Specifically, LiCoO2, LiFePO4, LiMn2O4, and Li X WO3, Li XLithium-containing materials such as MoO3 are deposited on top of a solid ion-conducting layer to form an ion reservoir. During the writing process, under the influence of an applied electric field, the Li in the reservoir... + Migrating through the solid-state ion-conducting layer into the interior of the doped silicon nanowires, it undergoes a lithiation reaction with silicon to form Li. X The Si phase brings the device into a low-resistivity state; during the erase process, a reverse voltage is applied to drive the Li phase. + From Li X The lithium nanowires are extracted from the silicon and returned to the reservoir, restoring them to a delithiated state and a high-resistivity state. Compared to metallic lithium reservoirs, lithium-containing compound reservoirs offer better environmental stability and process compatibility, effectively reducing air sensitivity and interfacial side reactions, and improving device cycle life and packaging reliability. While maintaining the same working mechanism, the reversible control of the conductivity state of doped silicon nanowires can still be achieved using the aforementioned lithium-containing compound reservoir; therefore, it is an equivalent implementation of the technical solution of this invention.

[0025] Furthermore, in step S5, the source and drain electrodes of each memory cell are independently led out to form bottom electrodes for external connection. The source and drain electrodes can be made of the same or different conductive materials as the source and drain electrodes, and external electrical connections are achieved through metal interconnects or probe contacts.

[0026] Further, in step S6, a dielectric isolation layer (such as SiO2, Si3N4, or a polymer insulating layer) is deposited or an insulating trench is etched between adjacent memory cells to completely electrically isolate the ion reservoir, solid-state ion conduction layer, and nanowire active region of each cell. Packaging, external interconnection, and post-processing are then performed as needed to improve device environmental stability and operational safety. For Li + / Na + The system and the encapsulation layer must have water and oxygen barrier properties (such as Al2O3 atomic layer deposition thin film or metal / polymer composite encapsulation).

[0027] In the above preparation method, the number, diameter, length, and spacing of nanowires in the nanowire bundle can be adjusted by IPSLS growth parameters, catalytic site design, and transfer process; the thickness of the ion reservoir and solid ion conduction layer can be precisely controlled by deposition time. Therefore, the initial resistance, ion embedding depth, and resistivity contrast of each storage cell can be pre-set at the layout level, thereby improving the consistency between different cells in the array.

[0028] The beneficial effects of this invention are as follows: 1. Multiple nanowires connected in parallel form a conductive channel, significantly improving readout current and reducing defect fluctuations. This invention connects multiple doped silicon nanowires in parallel into a storage cell, utilizing the collective effect of the bundle structure to improve the readout current to a practical level; at the same time, local defects or breaks in a single nanowire only reduce the number of parallel branches, without causing the entire cell to fail, significantly reducing resistance fluctuations and improving the identification of storage status.

[0029] 2. The nanowire geometry mitigates volume expansion, enabling reversible ion insertion / extraction. A diameter of 1 nm to 100 nm (preferably about 6 nm) allows silicon nanowires to effectively release stress through radial expansion during ion insertion, avoiding the cracking and pulverization problems common in bulk silicon or coarse nanowires. The gaps between nanowire bundles further provide expansion buffer space, enabling reversible cycling of the ion insertion / extraction process, thereby achieving stable non-volatile resistance state switching.

[0030] 3. A clear resistive state contrasts between amorphous silicon and the ion-alloyed state, and the amorphous state improves structural stability during cycling. After the first cycle, the device stabilizes in the lithiated amorphous silicon (a-Si, high-resistivity state, 10) state. 3 -10 5 Ω·cm) and amorphous ion-silicon alloy phase (a-Li X Si, low-resistivity state 10 -4 -10 -3 The resistivity can reversibly switch between Ω·cm. Amorphous silicon exhibits high resistivity due to its high defect state density and low carrier mobility; amorphous alloy phases possess metallic transport characteristics, resulting in a significant reduction in resistivity. There is a sufficiently large contrast between the two resistive states (10 Ω·cm). 6 -10 9 This facilitates high-speed, low-error-rate readout. Furthermore, the reversible phase transitions between amorphous states are more isotropic, avoiding stress concentration and fracture problems caused by the anisotropic expansion of crystalline silicon, thus significantly improving cycle life.

[0031]

[0032] 4. Completely independent cell structure completely eliminates inter-cell crosstalk. Each memory cell has an independent ion reservoir, a solid-state ion conduction layer, and independent source / drain electrodes. Cells are completely isolated from each other by a dielectric isolation layer. Ion migration is strictly confined within the cell, eliminating the sneak path problem found in cross-arrays and the interference of electric or ion fields between adjacent cells. This significantly improves the array's reliability, long-term retention characteristics, and operational stability.

[0033] 5. Independent electrode leads simplify addressing circuitry and testing. Since each cell has independent top and bottom electrodes, there is no need to design complex shared word line / bit line networks and selector (1T1R) structures. Each cell can be read and written independently via external multiplexers, switch arrays, or probe cards, significantly reducing the design difficulty and process complexity of the array's peripheral circuitry. This is particularly suitable for prototype verification, research testing, and high-reliability small-to-medium-scale storage applications.

[0034] 6. Compatible with flexible substrates and low-temperature processes, expanding application scenarios. The fabrication process of this invention does not involve high-temperature wafer processes and is compatible with flexible substrates such as PI, PET, and PEN, making it suitable for wearable electronics, flexible storage, and irregular curved surface integration scenarios.

[0035] 7. Doped silicon nanowires are the key structural basis for realizing this invention. The small diameter of the silicon nanowires significantly shortens the ion diffusion distance and improves ion control efficiency; the nanowire bundle structure provides a buffer space for volume changes during ion insertion; and the in-plane arrangement facilitates the direct formation of source / drain electrode connection structures. Therefore, doped silicon nanowires are the key structural basis for achieving the high reliability, high consistency, and flexible compatibility of this invention.

[0036] 8. Controllable doping concentration synergistically optimizes the Mott transition and space charge layer effect, ensuring device switchability and ion transport uniformity. This invention designs the doping concentration of silicon nanowires to be controllable, ranging from 10⁻⁶. 16 cm -3 Up to 10 19 cm -3 (Preferably p-type indium doping, concentration of 10) 17 cm -3 Up to 3×10 17 cm -3 The controllable concentration is adjusted based on the initial resistivity required by the device, the target resistance-to-state contrast, and the interfacial characteristics of the solid electrolyte system. This range has been optimized through a combination of electrochemistry and semiconductor physics: it is lower than the Mott insulator-to-metal transition critical concentration of indium-doped silicon (the ionization energy of indium is approximately 156 meV, and its Mott transition critical concentration is lower than that of boron-doped silicon, approximately 3 × 10⁻⁶ mV). 18 cm -3 This ensures that the initial crystalline silicon retains its semiconductor transport properties, with an initial resistivity of 10. -1 Up to 10 1 The resistance is on the order of Ω·cm, thus exhibiting a distinctly high resistance in the unlithiated state (based on the "0" state); simultaneously, it is significantly higher than the intrinsic carrier concentration, suppressing excessive broadening of the space charge layer at the semiconductor / solid electrolyte interface, preventing lithium ions from being localized at the nanowire edges due to the interface barrier, and ensuring that Li⁺ can uniformly and efficiently enter the nanowire bulk phase. For ultrafine nanowires with diameters ranging from 6 nm to 30 nm, 1017 cm -3 The doping at this level corresponds to a space charge layer thickness comparable to the nanowire diameter, which facilitates uniform lithium-ion embedding across the cross-section. Furthermore, after the first cycle, the device operates in both amorphous silicon (a-Si) and amorphous lithium-silicon alloy (a-Li) configurations. X Between Si), the doped atoms in a-Si are activated and deactivated due to lattice disorder, further consolidating the stability of the high-resistivity state. This makes the optimized design of the doping concentration play a key role in both the initial and cyclic states. The controllable doping concentration is achieved by adjusting at least one process parameter among the following: the proportion of doped elements in the catalyst, the dopant flow rate ratio in the growth source gas, the growth temperature, and the annealing conditions. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the device of the present invention.

[0038] Figure 2 This is a schematic diagram of high and low resistance states.

[0039] Figure 3 This is a structural diagram of the present invention. Detailed Implementation

[0040] The present invention will be further described below with reference to embodiments. It should be understood that the following embodiments are only used to explain the technical concept of the present invention, and include but are not limited to the scope of protection of the present invention. Any equivalent substitutions or conventional modifications made based on the concept of the present invention regarding the substrate material, the number of nanowires, the type of nanowire doping, the type of solid-state ion conduction layer, the ion reservoir material, the electrode layout, or the array interconnection method should be considered to fall within the scope of protection of the present invention.

[0041] like Figure 1-3 As shown, the present invention provides a non-volatile memory cell array based on the ion modulation effect of silicon nanowires, including a substrate, a plurality of independent memory cells disposed on the substrate, and an external selection circuit for independent addressing of each cell; each memory cell constitutes an independent bit, and the cells are electrically isolated from each other through a dielectric isolation structure, and the structures are completely identical and independent of each other.

[0042] Example 1: Memory Cell Layout Design and Source / Drain Electrode Fabrication A silicon wafer, glass sheet, or flexible polyimide substrate is provided as the substrate. A dielectric layer (such as SiO2 or a polymer planarization layer) is deposited or transferred on the substrate surface, and multiple isolated memory cell regions (e.g., eight cells A, B, C, D, E, F, G, and H) are formed through photolithography and etching processes. Source (S) and drain (D) regions are spaced apart along the x-direction within each memory cell region. A Ti / TiN composite metal layer (bottom Ti 20 nm, top TiN 100 nm) or a Cr / Au composite layer (bottom Cr 10 nm, top Au 100 nm) is deposited in the source and drain electrode regions, with a total thickness of 50 nm to 200 nm, forming strip-shaped source and drain electrodes. The channel length between the source and drain electrodes is defined as 100 nm to 2 μm, and silicon nanowires will be arranged within this region. The spacing between each cell is 5 μm to 50 μm for subsequent formation of the dielectric isolation structure.

[0043] Example 2: Preparation and Alignment of Controllably Doped p-Type Silicon Nanowires An in-situ growth approach was adopted: On the target substrate, an array of catalytic sites was defined using electron beam lithography, with n (n=6-20) indium-based catalytic particles (approximately 20 nm in diameter, spaced 50 nm apart) deposited in each unit region. Indium-doped p-type silicon nanowires with a diameter of approximately 6 nm and a length of approximately 2 μm were grown in situ using IPSLS technology at low temperatures (300-350°C) with indium as both a catalyst and dopant source. The indium doping concentration was controlled to approximately 10⁻⁶ by adjusting the atomic ratio of indium to silicon in the catalyst and the growth temperature. 17 cm -3 Up to 3×10 17 cm -3 After growth, the nanowires were annealed at 300°C for 30 minutes to achieve crystallization. By controlling the density of the catalytic particles and the growth time, the number, diameter, and length of the nanowires within each unit were kept consistent. After growth, the nanowires were arranged parallel to each other along the source and drain directions, with their ends overlapping the source and drain electrodes, respectively, forming a nanowire bundle.

[0044] Example 3: Formation of solid electrolyte and independent ion reservoir (using Li) + (Taking the system as an example) On a substrate with pre-formed nanowire bundles, a LiPON (lithium phosphorus oxynitride) thin film with a thickness of 20 nm to 50 nm is deposited as a solid-state ion-conducting layer via radio frequency magnetron sputtering. The LiPON layer continuously covers the surface of the nanowire bundles within each memory cell region, filling the gaps between the nanowires and completely encapsulating the nanowire bundles while forming a stable interface with the source and drain electrode surfaces. Above the LiPON layer, a lithium metal layer with a thickness of 50 nm to 200 nm is deposited as an ion reservoir via vacuum thermal evaporation or electron beam evaporation. The lithium layer is patterned using photolithography and reactive ion etching, ensuring that each memory cell (AH) has an independent rectangular lithium reservoir, and that the lithium reservoirs in each cell are completely disconnected and not interconnected. Each lithium reservoir is led out via an independent metal lead or pad, serving as the independent top electrode for that cell.

[0045] The source and drain electrodes of each memory cell are independently led out to form the bottom electrode connection terminals. Dielectric isolation layers (such as SiO2 or Si3N4) are deposited or insulating trenches are etched between adjacent memory cells to completely electrically isolate the lithium reservoir, LiPON layer, and nanowire active region of each cell. Finally, an Al2O3 encapsulation layer (50 nm thick, atomic layer deposition) is deposited to block water and oxygen.

[0046] Example 4: Array Addressing and Read / Write Operation Modes (using Li) + (Taking the system as an example) A positive voltage pulse (100 ns to 10 μs width) of +2 V to +5 V is applied to the top electrode of the lithium reservoir in the selected cell (e.g., cell A), while one of its source and drain electrodes is grounded or applied a low potential. Lithium ions are injected from the lithium reservoir into the underlying nanowire bundle via LiPON under the influence of the electric field. During the initial initialization process, the crystalline silicon nanowires undergo an irreversible amorphization transformation. Subsequent device operation is based on amorphous silicon (a-Si) and amorphous lithium-silicon alloy (a-Li). x Reversible switching between crystalline doped p-type Si nanowires and amorphous Li. X In the Si alloy, the resistance of unit A drops to a low-resistivity state (LRS, e.g., 100 Ω to 1 kΩ). Subsequently, a negative voltage pulse of -2 V to -5 V is applied, causing lithium ions to migrate from Li... X The nanowires are extracted from Si and returned to the lithium reservoir, transforming into amorphous silicon (a-Si), and the resistance rises back to a high-resistivity state (HRS, e.g., 100 kΩ to 1 MΩ). At this point, unit A completes its initialization and enters a reversible functional state. (Based on resistivity difference 10...) 6 -10 9 Based on the nanowire bundle geometry parameters, the measured device-level resistive contrast ratio is 10. 3 -10 5 .

[0047] Subsequent writing of "1" (lithiation): A positive voltage pulse of +2 V to +5 V is applied to the top electrode of the lithium reservoir of the selected cell (e.g., cell A) that has been initialized, and lithium ions are injected into the amorphous silicon nanowire to form amorphous Li. x In the Si alloy, the resistance of cell A drops to a low resistance state (LRS). At this time, cell BH remains in its original state because no voltage is applied.

[0048] Subsequent "0" erasure (de-lithiation): A negative voltage pulse of -2 V to -5 V is applied to the top electrode of the lithium reservoir in the selected cell (e.g., cell A), with its source and drain electrodes either floating or grounded. Lithium ions migrate from amorphous Li x The nanowires are extracted from Si and returned to the lithium reservoir, restoring the nanowire bundle to amorphous silicon (a-Si), and the resistance of unit A rises back to the high-resistivity state (HRS). Unit BH remains unaffected.

[0049] Readout: A readout voltage of +0.1 V to +0.5 V (far below the write threshold) is applied between the lithium reservoir and the source / drain electrodes of the selected cell (e.g., cell A), and the current flowing through the nanowire bundle is detected. If the current is greater than a preset threshold (e.g., >50 μA), it is determined as "1" (amorphous Li). x If the current is less than the threshold (e.g., << 10 μA), it is determined to be "0" (amorphous silicon a-Si state). The readout process does not change the resistance state of cell A, nor does it affect other cells.

[0050] Example 5: Sodium ions (Na) + Extended implementation of the system In the above Li + Based on the main embodiment, the technical platform of the present invention can be extended to Na + The system can be realized by replacing the solid ion-conducting layer with a sodium ion-conducting thin film such as NASICON or β-Al2O3, and replacing the ion reservoir with a sodium metal layer. + The storage unit. Na + Like silicon, it can also form amorphous Na. X The Si alloy phase has an insertion / extraction mechanism similar to that of Li. + Similar systems: Na + Amorphous Na formed by embedding amorphous silicon (a-Si) nanowire bundles X Si alloy phase (LRS), Na + After extraction, it reverts to amorphous silicon (a-Si) (HRS). + The systems are similar, but solid electrolyte materials and ion reservoir materials differ. Due to Na... + Ionic radius greater than Li + The volume expansion during the embedding process is relatively large, therefore the buffer design of the gaps between the nanowires is more critical. The ions described in this invention are not limited to Li.+ and Na + It can also be used for K + Mg 2+ Zn 2+ Al 3+ Metal ions that can reversibly insert and extract under the action of an electric field.

[0051] Example 6: Extended implementation of this structure – two-sided symmetrical gated structure (no independent ion reservoir required) While maintaining the same principles of lithium-ion insertion and extraction, this invention further proposes an alternative architecture based on symmetrical electrodes at both ends and gate-controlled ion migration (corresponding to...). Figure 1 (The top lithium storage is removed). This architecture does not require a separate top electrode for the ion reservoir as a lithium source. Instead, it uses symmetrical source and drain electrodes in conjunction with a lithium-containing solid electrolyte layer covering the nanowire bundle. The gate electric field drives the reversible insertion / extraction of lithium ions in the electrolyte, achieving non-volatile resistance state control equivalent to the vertical stacked structure described above. The specific implementation steps are as follows: Step 1: Fabrication of substrate and symmetrical source / drain electrodes A silicon wafer or a flexible polyimide (PI) substrate is provided as the substrate. A SiO2 dielectric layer (200 nm thick) is deposited on the substrate surface, or multiple isolated memory cell regions are formed by photolithography. Within each cell region, a symmetrical source / drain electrode pair (S / D) is deposited by electron beam evaporation. The source and drain electrodes are made of the same material and have the same thickness, exhibiting interchangeable symmetry, and are selected from Ti / TiN composite layers (bottom Ti 20 nm, top TiN 1 nm, top Au 100 nm), with a total thickness of 50 nm to 200 nm. The source and drain electrodes are arranged at intervals along the channel direction, and the channel length is defined as 100 nm to 2 μm. The source and drain electrodes simultaneously serve as the electric field application terminals during writing / erasing and the current detection terminals during reading.

[0052] Step 2: Preparation and Alignment of Doped Silicon Nanowire Bundles Doped silicon nanowire bundles are fabricated and arranged between the source and drain electrodes using either Route A (IPSLS in-situ growth) or Route B (VLS transfer assembly). Taking Route A as an example: a catalytic site array is defined by electron beam lithography, and n (n=6-20) indium-based catalytic particles (approximately 20 nm in diameter and 50 nm spacing) are deposited in each unit region. Indium-doped p-type silicon nanowires with a diameter of approximately 6 nm and a length of approximately 2 μm are grown in situ using IPSLS at a low temperature (300-350°C), with a doping concentration of approximately 10⁻⁶. 17 cm -3 Up to 3×10 17 cm -3After growth, the nanowires were annealed at 300°C for 30 minutes to achieve crystallization. The nanowires were arranged parallel to each other along the source and drain directions, with their ends overlapping the source and drain electrodes respectively, forming parallel conductive channels. The contact area between the nanowires and the source and drain electrodes was locally annealed (200-300°C) to reduce the contact resistance.

[0053] Step 3: Deposition of lithium-containing solid-state ion electrolyte On a substrate with pre-formed nanowire bundles, a LiPON (lithium phosphorus oxynitride) thin film with a thickness of 20 nm to 50 nm is deposited as a solid-state ion-conducting layer via radio frequency magnetron sputtering. The LiPON layer continuously covers the surface of the nanowire bundles within each memory cell region, filling the gaps between the nanowires and covering the active region between the source and drain electrodes. Crucially, in this embodiment, the LiPON itself contains stoichiometric or excess migratable lithium ions, serving as both an ion transport channel and a lithium-ion supply source, eliminating the need for additional deposition of a metallic lithium layer or a lithium-containing compound reservoir as a separate top electrode.

[0054] Step 4: Gate Electrode Fabrication A gate insulating layer (such as Al₂O₃ or HfO₂, with a thickness of 5 nm to 20 nm) is prepared above the LiPON layer by atomic layer deposition (ALD). Then, gate electrode material (TiN, ITO, or heavily doped polysilicon), with a thickness of 50 nm to 200 nm, is deposited by sputtering or electron beam evaporation. The gate electrode is then lithographically and etched to cover the nanowire channel region and aligned with the source / drain electrodes, forming a top-gate structure. The gate electrode is led out via independent metal leads, serving as the gate control terminal for this unit. Alternatively, the gate electrode can be fabricated below the substrate (back gate) or beside the source / drain electrodes (side gate), achieving electric field coupling with the nanowire bundle through a solid-state ion-conducting layer.

[0055] Step 5: Dielectric isolation and packaging SiO2 or Si3N4 dielectric isolation layers (100 nm to 500 nm thick) are deposited between adjacent memory cells, or insulating trenches are etched to completely electrically isolate the gate electrode, LiPON layer, and nanowire active region of each cell. Finally, an Al2O3 encapsulation layer (50 nm thick, atomic layer deposition) is deposited to block water and oxygen.

[0056] This embodiment has the following features: (1) The independent top electrode of the lithium metal or lithium-containing compound reservoir is eliminated, and LiPON itself serves as the ion supply source, reducing the types of materials and photolithography etching steps; (2) The source and drain electrodes are completely symmetrical and interchangeable, reducing the complexity of circuit design and process alignment requirements; (3) The gate voltage drive separates the ion migration and current readout functions, enabling resistance state switching at lower source and drain voltages, reducing power consumption and supporting multi-level resistance state control.

Claims

1. A non-volatile memory cell array based on the ion modulation effect of silicon nanowires, characterized in that, It includes a substrate, multiple independent memory cells disposed on the substrate, and external selection circuitry for independent addressing of each cell; each memory cell constitutes an independent bit, and the cells are electrically isolated from each other through a dielectric isolation structure, with identical structures and mutual independence; the memory cell comprises: A pair of source and drain electrodes are disposed on the substrate surface and arranged at intervals along a first direction, serving as the source and drain electrodes respectively. The source and drain electrodes are independently led out and serve as the bottom electrodes of each memory cell for external connection. A silicon-doped nanowire bundle is composed of n silicon-doped nanowires connected in parallel. The silicon-doped nanowires are arranged in parallel along the channel direction between the source and the drain, and their two ends are electrically connected to the source and the drain, respectively. The silicon-doped nanowires serve as the active host for ion insertion and extraction. A solid ion-conducting layer covers the active region between the surface of the doped silicon nanowires and the source / drain electrodes, and at least partially enters the gap between adjacent nanowires, providing a continuous transport channel for ions. An ion reservoir is disposed above a solid ion conduction layer, covering the active region of the doped silicon nanowire bundle corresponding to the memory cell. It serves as both a source and receiver of ions and an independent top electrode for the memory cell. The ion reservoir of each memory cell is independently led out as the top electrode of the cell and is not connected to the ion reservoirs of other cells. Alternatively, an alternative architecture with symmetrical electrodes at both ends and gate-controlled ion migration can be used.

2. The non-volatile memory cell array based on silicon nanowire ion modulation effect according to claim 1, characterized in that, The source and drain electrodes are made of titanium, chromium, nickel, titanium nitride, tungsten or a composite layer thereof, with a thickness of 10 nm to 50 nm; the electrode material is compatible with the ion reservoir material.

3. The non-volatile memory cell array based on the ion modulation effect of silicon nanowires according to claim 1, characterized in that, n is an integer from 1 to 100, preferably from 4 to 50, and more preferably from 6 to 20; the diameter of the doped silicon nanowire is from 1 nm to 100 nm, preferably from 6 nm to 30 nm; the length is from 1 μm to 10 μm; multiple nanowires together constitute a conductive channel of a memory cell; the doped silicon nanowire is grown and transferred to the substrate by IPSLS technology, or grown in situ directly in a patterned guide structure on the substrate, and then annealed to form a stable crystalline structure.

4. The non-volatile memory cell array based on silicon nanowire ion modulation effect according to claim 1, characterized in that, The doped silicon nanowires serve as the active host for ion insertion / extraction; in the initial state, the nanowire bundle is crystalline doped silicon, with doping including p-type or n-type doping, and the doping concentration ranging from 10. 16 cm -3 Up to 10 19 cm -3 The selection is adjusted based on the initial resistivity required by the device, the target resistance-state contrast, and the interface characteristics of the solid electrolyte system; p-type indium doping is preferred, with a concentration of 10%. 17 cm -3 Up to 3×10 17 cm -3 The controllable doping concentration is achieved by adjusting at least one of the following process parameters: the atomic ratio of dopants in the catalyst, the dopant flow rate in the growth source gas, the growth temperature, and the annealing conditions.

5. The non-volatile memory cell array based on the ion modulation effect of silicon nanowires according to claim 1, characterized in that, The solid ion-conducting layer isolates the silicon nanowires from the ion reservoir above. It is selected from oxide solid electrolytes, sulfide solid electrolytes, oxynitride solid electrolytes, polymer solid electrolytes or their composite structures, and has a thickness of 50 nm to 200 nm.

6. The non-volatile memory cell array based on the silicon nanowire ion modulation effect according to claim 1, characterized in that, The dielectric isolation structure is a dielectric isolation layer or an insulating trench, which is disposed between adjacent storage cells to completely electrically isolate the ion reservoir, solid ion conduction layer and active region of doped silicon nanowire bundle in each cell.

7. The non-volatile memory cell array based on the ion modulation effect of silicon nanowires according to claim 1, characterized in that, The memory cell also includes a gate electrode disposed above the solid ion conduction layer and isolated from the ion conduction layer by a gate insulating layer, used for electric field-controlled ion migration; multiple memory cells are arranged on the same substrate in a one-dimensional or two-dimensional array, each cell having an independent top electrode and bottom electrode; voltages are applied to the top electrode and bottom electrode of each memory cell by an external selection circuit to realize independent writing, erasing and reading of the cell.

8. The non-volatile memory cell array based on the silicon nanowire ion modulation effect according to claim 1, characterized in that, The operation mode of the storage unit is as follows: when writing "1", a first polar voltage is applied to the top electrode of the selected unit, and ions are injected into the crystalline silicon nanowire through the solid ion conduction layer to form an amorphous ion-silicon alloy phase, and the resistance drops to a low resistance state; when erasing "0", a reverse voltage is applied, the ions are extracted and returned to the ion reservoir, the nanowire bundle is restored to amorphous silicon, and the resistance rises back to a high resistance state; when reading, a read voltage far below the write threshold is applied, and the resistance state is determined by detecting the current, and the read process is non-destructive.

9. A method for fabricating a non-volatile memory cell array based on the ion modulation effect of silicon nanowires, used to fabricate the non-volatile memory cell array of claim 1, characterized in that, Includes the following steps: S1 provides a clean substrate: Si wafers, PI or other suitable substrates are provided; S2, Preparation of doped silicon nanowires: In each memory cell region, a bundle of doped silicon nanowires consisting of n doped silicon nanowires connected in parallel is formed, where n is an integer from 1 to 100. S3, Fabrication of source and drain electrodes: and patterning source and drain electrodes arranged at intervals along a first direction in each memory cell region, wherein the spacing between the source and drain electrodes defines the nanowire channel length, and an isolation region is reserved between each memory cell region; the source and drain electrodes are obtained by photolithography and electron beam evaporation; S4, Deposit a solid-state ion conduction layer: Deposit a solid-state ion conduction film on the substrate on which the doped silicon nanowire bundle has been formed, such that the solid-state ion conduction layer continuously covers the surface of the doped silicon nanowire bundle in each memory cell region, fills the gaps between adjacent nanowires, and covers the active region between the source and the drain. The solid-state ion-conducting layer is obtained through atomic layer deposition. S5, Forming an ion reservoir: An ion supply layer is deposited above the solid ion conduction layer and patterned by photolithography and etching to form an independent ion reservoir above each memory cell. The ion reservoirs of each memory cell are completely disconnected from each other, and each ion reservoir is independently led out as the top electrode connection terminal of the memory cell. The ion reservoir can also be obtained by atomic layer deposition. S6, Source and drain electrode lead-out: The source and drain of each memory cell are led out independently to form the bottom electrode external connection terminal; S7, forming a dielectric isolation structure: a dielectric isolation structure is formed between adjacent memory cells to completely electrically isolate the ion reservoir, solid ion conduction layer and active region of doped silicon nanowire bundles of each memory cell.

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