A process integration method for improving polysilicon etch loading effect

Abstract

This invention relates to the field of semiconductor manufacturing technology, and particularly to a process integration method for improving the etching load effect in polysilicon. The method includes: forming a first mask pattern on a layer to be etched, defining a functional pattern and a sacrificial pattern located in a sparse region of the pattern to reduce pattern density differences; etching the layer to be etched, simultaneously forming functional and sacrificial elements; forming a second mask layer covering the functional elements and exposing the sacrificial elements; and using the second mask layer as a mask, employing an isotropic etching process with high selectivity for the sacrificial elements to remove them. This invention effectively improves etching uniformity and device morphology accuracy by introducing sacrificial patterns. Simultaneously, by combining a protective mask with selective isotropic etching, it achieves non-destructive and clean removal of the sacrificial patterns, resulting in high process integration, compatibility with standard semiconductor processes, and significantly improved device electrical performance and reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a process integration method for improving the etching load effect of polysilicon. Background Technology

[0002] In semiconductor manufacturing, etching is widely used to transfer patterns from a photomask to the layer to be etched on the wafer surface. However, the loading effect is a common problem affecting etching uniformity. It refers to the phenomenon where, during etching, differences in pattern density across different areas of the wafer surface lead to significantly different etching rates and morphologies. Typically, in sparsely patterned areas, the etching gas or etchant has more thorough contact with the material surface, and reaction products diffuse faster, resulting in a higher etching rate than in densely patterned areas. This can easily cause over-etching, uncontrolled sidewall morphology, and increased etching deviations, ultimately affecting the electrical performance of devices and product yield.

[0003] To mitigate the loading effect, the industry commonly employs the method of adding non-functional sacrificial patterns (also known as dummy patterns) to sparse regions to increase local pattern density, making them closer to dense regions. However, in certain semiconductor device manufacturing processes, such as the fabrication of heterojunction bipolar transistors, due to limitations in device structure or electrical performance, these sacrificial patterns cannot be retained on the final structure after etching. Existing removal methods are prone to damaging the formed functional patterns, thus limiting the applicability of this method. Summary of the Invention

[0004] In a first aspect, the present invention provides a process integration method for improving the etching load effect of polysilicon, the specific method being as follows: Form the layer to be etched on the substrate; A first mask pattern is formed on the layer to be etched. The first mask pattern defines a functional pattern and a sacrifice pattern located at least in the sparse pattern region. The sacrifice pattern is set such that the difference in pattern density between the sparse pattern region and the dense pattern region is reduced. Using the first mask pattern as a mask, the layer to be etched is etched to simultaneously form functional elements and sacrificial elements; A second mask layer is formed on the substrate, the second mask layer covering the functional element and having an opening that exposes the sacrificial element; Using the second mask layer as a mask, the sacrificial element is removed by an isotropic etching process; Remove the second mask layer.

[0005] In one possible implementation, prior to removing the sacrificial element using an isotropic etching process, the method further includes: Using the second mask layer as a mask, the isolation layer covering the sacrificial element is removed to expose the sacrificial element.

[0006] In one possible implementation, the isolation layer is removed using a wet etching process.

[0007] In one possible implementation, the isotropic etching process has an etching selectivity ratio of more than 10:1 for the layer to be etched relative to the underlying dielectric layer.

[0008] In one possible implementation, the opening size of the second mask layer is smaller than the size of the sacrificial element to cover lithographic alignment misalignment.

[0009] In one possible implementation, the layer to be etched is any one or a combination of a polysilicon layer, a metal layer, or a dielectric layer.

[0010] In one possible implementation, the first mask pattern and / or the second mask layer is a photoresist layer or a hard mask layer.

[0011] In one possible implementation, the addition of the sacrifice graphics makes the difference in graphics density between the sparse and dense regions of the graphics less than a target value.

[0012] In one possible implementation, the method is used for etching processes in integrated circuit manufacturing or microelectromechanical system manufacturing.

[0013] Secondly, this application provides a method for manufacturing a semiconductor device, including the method described above.

[0014] Due to the adoption of the above technical solutions, this application has the following beneficial effects: 1. Effectively improves etching uniformity and precisely controls component morphology: This invention introduces sacrificial patterns in sparse areas, making the pattern density across the entire wafer surface more uniform, fundamentally suppressing the loading effect caused by uneven reactant diffusion rates and plasma distribution. Thus, in a single etching process, both functional and sacrificial components can obtain vertical and uniform sidewall profiles, avoiding defects such as over-etching, trapezoidal or concave sidewalls that are prone to occur in sparse areas in traditional processes, significantly improving the uniformity of critical dimensions and the accuracy of etching morphology.

[0015] 2. Achieving non-destructive and clean removal of sacrificial patterns while protecting functional components: This invention creatively introduces a removal strategy of "secondary masking + isotropic etching". The second mask layer completely covers and protects the functional components, exposing only the sacrificial components to be removed; then, utilizing the high etching selectivity of the sacrificial component material relative to the underlying dielectric layer, isotropic etching technology (such as chemical dry etching) can thoroughly and cleanly "hollow out" and remove the sacrificial components without damaging the underlying dielectric layer and lateral functional components. Compared with traditional wet or anisotropic dry removal methods, this solves the problems of adhesion and collapse caused by wet methods, and sidewall residue or substrate damage caused by anisotropic dry methods.

[0016] 3. High process integration, compatible with standard semiconductor processes, and wide applicability: The overall process of this invention—coating, photolithography, etching, and resist removal—are all standard processes in semiconductor manufacturing. It requires no extreme or non-standard equipment or materials, making it easy to integrate and promote directly on existing production lines. As described in several embodiments, this method is not only applicable to the etching of polycrystalline silicon materials but can also be extended to other layers to be etched, such as metal layers and dielectric layers; it is not only applicable to logic circuits and heterojunction bipolar transistors but also to the manufacturing of microelectromechanical systems (MEMS) devices, exhibiting strong universality and portability.

[0017] 4. Wide process window and low manufacturing cost: By defining the mask opening size to be smaller than the size of the sacrificial element, a sufficient tolerance window is provided for lithographic alignment deviations (overlay accuracy offsets), reducing reliance on high-end lithography equipment and the risk of defects. Furthermore, since no additional chemical mechanical polishing or complex multilayer hard mask alignment techniques are required, overall manufacturing costs are effectively controlled.

[0018] 5. Improved Device Electrical Performance and Reliability: By eliminating component morphology differences and etching damage caused by load effects, the resulting functional components exhibit highly consistent electrical characteristics. In transistor manufacturing, this translates to improved uniformity of key parameters such as threshold voltage and saturation current; in microelectromechanical systems (MEMS) manufacturing, it means better consistency and predictability of the mechanical properties of microstructures, thereby fundamentally improving device performance, yield, and long-term operational reliability. Attached Figure Description

[0019] To more clearly illustrate the technical solution of the present invention and facilitate a further understanding of its technical effects, features, and objectives, the present invention will be described in detail below with reference to the accompanying drawings. The drawings constitute an essential part of the specification and are used together with Embodiment 1 of the present invention to illustrate the technical solution of the present invention, but do not constitute a limitation on the present invention.

[0020] The same reference numerals in the attached diagrams represent the same parts, specifically: Figure 1 This is a schematic diagram of the structure after step 1 of Example 1.

[0021] Figure 2 This is a schematic diagram of the structure after step 3 of Example 1.

[0022] Figure 3 This is a schematic diagram of the structure after step 5 of Example 1.

[0023] Figure 4 This is a schematic diagram of the overall process of Example 1.

[0024] in: 1. Substrate; 2. Polysilicon layer; 3. Silicon oxide layer; 4. First photoresist layer; 5. Sacrificial polysilicon pattern; 6. Functional polysilicon pattern; 7. Second photoresist layer; 8. Opening. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be described in detail below with reference to several embodiments. It should be noted that these embodiments are merely some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0026] In the description of this invention, "substrate" can be a semiconductor substrate such as silicon, germanium, silicon-germanium, silicon-on-insulator, or silicon-on-sapphire, or a substrate on which various thin films or device structures are formed. "Layer to be etched" can be any one of polycrystalline silicon layer, amorphous silicon layer, metal layer (such as aluminum, tungsten, copper, etc.), dielectric layer (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) or a stack thereof.

[0027] In the description of this invention, "sacrifice graphics" refers to non-functional graphics added to balance graphics density and which will eventually be removed from the substrate. Example 1

[0028] This embodiment provides a process integration method using polysilicon as the etchable layer, such as... Figure 4 As shown, the specific steps are as follows: Step 1: Provide a substrate 1, on which a polysilicon layer 2 and a silicon oxide layer 3 are sequentially formed. A first photoresist layer 4 is coated on the polysilicon layer 2 as a first mask pattern. Through photolithography, a functional polysilicon pattern and a sacrificial polysilicon pattern 5 located in the sparse region of the pattern are defined. The addition of the sacrificial polysilicon pattern 5 ensures that the pattern density difference between the sparse and dense regions is less than 10%. Figure 1 As shown.

[0029] Step 2: Using the first photoresist layer 4 as a mask, dry etching is performed on the polysilicon layer 2 to simultaneously form the functional polysilicon pattern 6 and the sacrificial polysilicon pattern 5 (pseudo-polysilicon pattern). After etching, the first photoresist layer 4 is removed.

[0030] Step 3: A second photoresist layer 7 is coated on the substrate 1, and a second mask layer is formed by photolithography. This second mask layer covers the functional polysilicon pattern 6 and forms an opening 8 above the sacrificial polysilicon pattern 5. The size of the opening 8 is smaller than the width of the sacrificial element to tolerate alignment deviations in the photolithography process. Figure 2 As shown.

[0031] Step 4: Using the second photoresist layer 7 as a mask, first use dilute hydrofluoric acid (wet method) to remove the silicon oxide isolation layer on top of the sacrificial polysilicon pattern 5 to expose the polysilicon surface.

[0032] Step 5: With the second photoresist layer 7 in place, use an isotropic chemical dry etching process with high selectivity for polysilicon to completely etch away the exposed sacrificial polysilicon pattern 5, such as... Figure 3 As shown, this chemical dry etching method has an etching selectivity ratio of more than 10:1 for polysilicon relative to the underlying silicon oxide, thereby avoiding significant loss of the underlying silicon oxide layer 3.

[0033] Step 6: Remove the second photoresist layer 7 to obtain a structure that retains only the functional polysilicon pattern 6. Example 2

[0034] This embodiment is basically the same as Embodiment 1, except that: if the top of the sacrificial element is not covered by an isolation layer after the first etching, or if it has been removed in the previous process, then step 4 in Embodiment 1 can be omitted. That is, after forming the second mask layer and opening a window to expose the sacrificial element, the exposed sacrificial element can be directly etched by the isotropic etching process. Example 3

[0035] This embodiment is basically the same as Embodiment 1, except for the method of removing the isolation layer. In this embodiment, the isolation layer on top of the sacrificial device is silicon nitride. After forming the second mask layer, a dry etching process with a high selectivity for silicon nitride over polysilicon is used to create windows in the isolation layer, replacing wet etching. Subsequently, the same chemical dry etching is performed to remove the sacrificial polysilicon pattern 5. Example 4

[0036] This embodiment is essentially the same as Embodiment 1, except for the material of the second mask layer. In this embodiment, the second mask layer is not photoresist, but a silicon nitride hard mask layer deposited using a chemical vapor deposition process. Subsequently, openings 8 for exposing sacrificial elements are formed on the hard mask layer using photolithography and etching processes. This hard mask scheme provides higher etching resistance during subsequent isotropic etching. After completion, the hard mask layer is removed by wet etching. Example 5

[0037] This embodiment is basically the same as Embodiment 1, except for the application field. The method in this embodiment is used for the fabrication of microelectromechanical systems (MEMS) devices. The layer to be etched is a polycrystalline silicon structure layer, and the functional pattern is a micromechanical structure (such as a cantilever beam, diaphragm, etc.). By introducing a sacrificial pattern, the loading effect of deep etching is improved, and the sacrificial pattern is cleanly removed using the method of this invention, thereby obtaining a high-precision, residue-free micromechanical structure.

[0038] In summary, the present invention provides a process integration method for improving etching loading effects. By combining the introduction of sacrificial patterns with subsequent highly selective, isotropic etching, it achieves non-destructive and clean removal of sacrificial patterns while improving loading effects. This method can be widely applied in various material systems and device manufacturing processes. The above embodiments have described this in detail, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this invention should be included within the scope of protection of this invention.

Claims

1. A process integration method for improving the etching load effect of polysilicon, characterized in that, The specific method is as follows: Form the layer to be etched on the substrate; A first mask pattern is formed on the layer to be etched. The first mask pattern defines a functional pattern and a sacrifice pattern located at least in the sparse pattern region. The sacrifice pattern is set such that the difference in pattern density between the sparse pattern region and the dense pattern region is reduced. Using the first mask pattern as a mask, the layer to be etched is etched to simultaneously form functional elements and sacrificial elements; A second mask layer is formed on the substrate, the second mask layer covering the functional element and having an opening that exposes the sacrificial element; Using the second mask layer as a mask, the sacrificial element is removed by an isotropic etching process; Remove the second mask layer.

2. The process integration method for improving polysilicon etching load effect as described in claim 1, characterized in that, Before removing the sacrificial element using an isotropic etching process, the process further includes: Using the second mask layer as a mask, the isolation layer covering the sacrificial element is removed to expose the sacrificial element.

3. The process integration method for improving polysilicon etching load effect as described in claim 2, characterized in that, The isolation layer is removed using a wet etching process.

4. The process integration method for improving polysilicon etching load effect as described in claim 1, characterized in that, The isotropic etching process has an etching selectivity ratio of more than 10:1 for the layer to be etched relative to the underlying dielectric layer.

5. The process integration method for improving polysilicon etching load effect as described in claim 1, characterized in that, The opening size of the second mask layer is smaller than the size of the sacrificial element to cover lithographic alignment deviations.

6. The process integration method for improving polysilicon etching load effect as described in claim 1, characterized in that, The layer to be etched is any one or a combination of a polysilicon layer, a metal layer, or a dielectric layer.

7. The process integration method for improving polysilicon etching load effect as described in claim 1, characterized in that, The first mask pattern and / or the second mask layer are photoresist layers or hard mask layers.

8. The process integration method for improving polysilicon etching load effect as described in claim 1, characterized in that, The addition of the sacrificial graphic makes the difference in graphic density between the sparse and dense regions of the graphic less than the target value.

9. The process integration method for improving polysilicon etching load effect as described in claim 1, characterized in that, This method is used for etching processes in integrated circuit manufacturing or microelectromechanical system manufacturing.

10. A method for manufacturing a semiconductor device, characterized in that, The method included in any one of claims 1 to 9.

Images