Heating power control for semiconductor structure processing

Abstract

Methods, apparatus, and systems for controlling the amount of power used by various heating sources during semiconductor structure processing are disclosed. The disclosed methods / apparatus / systems perform, for example, heating a semiconductor structure disposed on a substrate within a reactor chamber of an epitaxial reactor system using a first heating source, heating the substrate using a second heating source, and controlling at least one of a first power of the first heating source or a second power of the second heating source based on stored data.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor structure processing methods and systems, and specifically to the field of device and integrated circuit manufacturing. More specifically, this disclosure generally relates to controlling the power of a heating source during semiconductor structure processing. Background Technology

[0002] With advancements in semiconductor technology, precise temperature control during semiconductor manufacturing processes is becoming increasingly important. For example, complementary metal-oxide-semiconductor (CMOS) integration schemes can utilize advanced integration techniques involving device stacking, buried power rails, the creation of high-k / metal gates, and the creation of source / drain contact layers. For instance, the formation of source / drain layers relies on a deposition process with high dielectric selectivity, typically applying a very narrow temperature distribution "selectivity window" across the wafer being processed. Ideally, the temperature across the entire wafer should be extremely uniform, typically on the order of 500 degrees Celsius. However, achieving temperature uniformity is challenging.

[0003] Typically, semiconductor wafers are placed on a pedestal within a reactor chamber. Both the wafer and the pedestal are then heated to a target temperature. Typically, a lamp above the wafer illuminates the top of the wafer, and another lamp below the pedestal illuminates the bottom of the pedestal. Thus, the wafer is directly heated by radiation from above, while the bottom of the wafer receives heat from the heated pedestal. Ideally, the top and bottom of the wafer would be heated to equal temperatures at equal rates. However, in practice, this is not easily achieved. In reality, the radiation field from the lamps is not perfectly uniform, the pedestal may not distribute heat evenly to all parts of the wafer resting on it, and the gases flowing through the reaction chamber can transfer heat from one location within the chamber to another.

[0004] To address some of these issues, the pedestal is typically rotated, thus rotating the semiconductor wafer along with it, in an attempt to average out any non-uniformities within the chamber. This can help create a more uniform temperature distribution within the semiconductor wafer, and consequently, a more uniform layer on the wafer. While rotation can produce non-uniformities that are sometimes radially symmetrical, it is still possible to experience radially asymmetrical non-uniformities in temperature (and therefore layer thickness and mass). Radial symmetry refers to symmetry about a central point. For example, for a circular shape with radial symmetry, dividing the circle into appropriately sized wedges extending from the center (like slicing a pie) will result in each wedge having the same value of that property; each wedge will have the same distribution of that property. Examples of radially symmetrical objects include idealized starfish and many types of flowers. Other techniques for reducing temperature non-uniformity include defining individually adjustable temperature zones and adjusting the gas flow within the reaction chamber. However, these techniques still do not adequately address certain types of temperature non-uniformity, such as radially asymmetrical temperature non-uniformity.

[0005] Any discussion set forth in this section (including discussions of problems and solutions) is included in this disclosure for the purpose of providing background information and should not be construed as an admission that any or all of the discussions were known at the time of making this invention or otherwise constitute prior art. Summary of the Invention

[0006] This invention provides a simplified overview of some concepts, which will be described in further detail below. This invention is not intended to require the identification of key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0007] Various embodiments of this disclosure relate to processing a semiconductor structure, such as a semiconductor wafer, by using top / bottom heating power to heat at least the semiconductor structure and a substrate on which the semiconductor structure is disposed, wherein the top / bottom heating power is selected to potentially increase the uniformity of layer growth on the semiconductor structure.

[0008] According to an example of this disclosure, a reactor system, such as an epitaxial reactor system, is disclosed, comprising a reactor chamber, a gas delivery system, a first heating source, and a second heating source. The reactor chamber may include at least one receiving region configured to receive a base. The gas delivery system may be configured to deliver a precursor gas within the reactor chamber. The first heating source may be configured to heat a semiconductor structure disposed on the base, and the second heating source may be configured to heat the base. The epitaxial reactor system may further include one or more processors and a memory storing instructions, which, when executed by the one or more processors, cause the epitaxial reactor system to store data related to heating power delivery and control at least one of a first power of the first heating source or a second power of the second heating source based on the data.

[0009] According to examples of this disclosure, a method is disclosed that includes: heating a semiconductor structure disposed on a base within a reactor chamber of an epitaxial reactor system using a first heating source; heating the base using a second heating source; and controlling at least one of a first power of the first heating source or a second power of the second heating source based on stored data.

[0010] According to an example of this disclosure, a non-transitory computer-readable medium storing instructions and data is disclosed. When executed, the instructions can configure an epitaxial reactor system to cause a first heating source to heat a semiconductor structure disposed on a base within the reactor chamber of the epitaxial reactor system; to cause a second heating source to heat the base; and to control at least one of a first power of the first heating source or a second power of the second heating source based on the data.

[0011] For the purpose of summarizing the invention and its advantages relative to the prior art, certain objects and advantages of the invention have been described above. It should be understood, of course, that not all of these objects or advantages may necessarily be achieved according to any particular embodiment of the invention. Therefore, for example, those skilled in the art will recognize that the invention may be embodied or implemented in a manner that achieves or optimizes one or more advantages taught or suggested herein, without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0012] All these embodiments are intended to fall within the scope of the invention disclosed herein. Those skilled in the art will readily appreciate these and other embodiments from the following detailed description of certain embodiments with reference to the accompanying drawings; however, the invention is not limited to any particular embodiment disclosed. Attached Figure Description

[0013] To facilitate identification of any particular element or action being discussed, one or more of the most significant digits in the reference numerals refer to the drawing number in which the element was first introduced.

[0014] Embodiments of this disclosure can be more fully understood when considered in conjunction with the following illustrative drawings, and by referring to the detailed description and claims.

[0015] Figure 1 This is a schematic diagram of an example semiconductor device manufacturing system according to one or more embodiments of the present invention.

[0016] Figure 2 This is to illustrate other details according to one or more embodiments of the present invention. Figure 1 A schematic diagram of an example semiconductor device manufacturing system.

[0017] Figure 3 This is a top view of an example base for holding multiple semiconductor structures according to one or more embodiments of the present disclosure.

[0018] Figure 4 According to one or more embodiments of this disclosure Figure 2 A schematic diagram of the system's controller.

[0019] Figure 5 This is a flowchart of one or more embodiments of the present disclosure for controlling heating power during semiconductor structure processing.

[0020] Figure 6 This is another flowchart for controlling heating power during semiconductor structure processing according to one or more embodiments of the present disclosure.

[0021] Figure 7 This illustrates one or more embodiments according to the present disclosure. Figure 6 A flowchart detailing the example implementation of the steps.

[0022] It should be understood that the elements in the accompanying drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements to aid in understanding the embodiments shown in this disclosure. Detailed Implementation

[0023] The following description of exemplary embodiments of the methods and compositions is merely illustrative and for purposes of explanation only. The following description is not intended to limit the scope of this disclosure or the claims. Furthermore, the description of multiple embodiments having indicated features or steps is not intended to exclude other embodiments having additional features or steps or other embodiments including different combinations of said features or steps.

[0024] As used herein, the term "substrate" can refer to any one or more underlying materials that can be used to form or on which devices, circuits, or films can be formed according to the methods of embodiments of this disclosure. A substrate may comprise a bulk material, such as silicon (e.g., single-crystal silicon), other group IV materials (e.g., germanium), or other semiconductor materials (e.g., group II-VI or III-V semiconductor materials), and may comprise one or more layers overlying or underlying the bulk material. A substrate may include various topologies, such as gaps, including spaces between recesses, lines, trenches, or raised portions (e.g., fins) formed within or on at least a portion of the layers of the substrate. By way of example, a substrate may comprise a bulk semiconductor material and an insulating or dielectric material layer covering at least a portion of the bulk semiconductor material. Furthermore, the term "substrate" can refer to any one or more underlying materials that can be used or on which devices, circuits, or films can be formed. A "substrate" can be continuous or discontinuous; rigid or flexible; solid or porous. A "substrate" can be in any form, such as powder, plate, or workpiece. Plate-type substrates can include wafers of various shapes and sizes. The substrate can be made of materials such as silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, and silicon carbide. The continuous substrate can extend beyond the boundary of the processing chamber where the deposition process occurs and can move through the processing chamber, allowing the process to continue until the end of the substrate is reached. The continuous substrate can be supplied from a continuous substrate supply system that allows the continuous substrate to be manufactured and output in any suitable form. Non-limiting examples of continuous substrates may include sheets, nonwoven films, rolls, foils, fiber webs, flexible materials, bundles of continuous filaments or fibers (i.e., ceramic fibers or polymer fibers). The continuous substrate may also include a carrier or sheet on which a non-continuous substrate is mounted.

[0025] As used herein, the term "layer" can refer to any continuous or discontinuous structure and material. For example, a layer can include two-dimensional materials, three-dimensional materials, nanoparticles, or even partial or complete molecular layers or partial or complete atomic layers or atomic and / or molecular clusters. A layer can include a material or layer with pinholes, which can be at least partially continuous.

[0026] In this disclosure, any two numbers of a variable may constitute a feasible range of the variable, and any range indicated may include or exclude endpoints. Furthermore, any value of the indicated variable (whether or not it is indicated by “about”) may refer to an exact value or an approximate value and includes equivalents, and in some embodiments may refer to an average, median, representative value, multi-value, etc. Additionally, in this disclosure, the terms “comprising,” “consisting of,” and “having” may, in some embodiments, independently mean “generally or broadly comprising,” “including,” “substantially consisting of,” or “consisting of.” The meaning of any definition in this disclosure does not necessarily exclude the common and customary meaning in some embodiments. In some cases, percentages indicated herein may be relative or absolute percentages.

[0027] Numerous exemplary materials are provided throughout the embodiments of this disclosure. It should be noted that the chemical formulas given for each exemplary material should not be construed as limiting, and the non-limiting exemplary materials given should not be limited by the given exemplary stoichiometry.

[0028] In this specification, it will be understood that the terms "on" or "above" may be used to describe relative positional relationships. Another element, film, or layer may be directly on the mentioned layer, or another layer (intermediate layer) or element may be inserted between them, or a layer may be disposed on the mentioned layer but not completely cover the surface of the mentioned layer. Therefore, unless the term "directly" is used alone, the terms "on" or "above" will be interpreted as relative concepts. Similarly, it will be understood that the terms "below," "under," or "beneath" will be interpreted as relative concepts.

[0029] Now turn to the attached image. Figure 1 This is a schematic diagram of system 100, which includes one or more reaction chambers 102 and a gas delivery system. The gas delivery system includes a first precursor gas source 104, a second precursor gas source 105, a reactant gas source 106, a purge gas source 108, and an exhaust device 110. System 100 may also include a controller 112. System 100 may include, for example, an epitaxial reactor system.

[0030] One or more reaction chambers 102 may each include any suitable reaction chamber, such as an ALD or CVD reaction chamber.

[0031] The first precursor gas source 104 may include a container containing one or more precursors as described herein—either alone or mixed with one or more carrier gases. Each of the one or more carrier gases may be any kind of gas. For example, each of the one or more carrier gases may be a reactive gas or a rare gas. For example, each of the one or more carrier gases may be a gas such as H2, N2, or a rare gas. The second precursor gas source 105 may include a container containing one or more reactants as described herein (either alone or mixed with one or more carrier gases).

[0032] The purge gas source 108 may include a container containing one or more gases (e.g., rare gases or other purge gases). Although the gas delivery system of system 100 is shown as having four gas sources 104-108, system 100 may include any suitable number of gas sources. Gas sources 104-108 may be physically connected to one or more reactor chambers 102 via gas lines 114-118, each of which may include a flow controller, valve, heater, etc. Exhaust device 110 may include a vacuum system comprising one or more vacuum pumps for adjusting the pressure within one or more reactor chambers 102.

[0033] The controller 112 may include electronic circuitry, an FPGA, an ASIC, a processor, memory storing computer-executable instructions (such as software or firmware), data, and / or other components (configured to selectively operate valves, manifolds, heaters, pumps, and other components included in system 100).

[0034] Other configurations of system 100 are possible, including different numbers and types of precursor and reactant sources, as well as purge gas sources. Furthermore, it should be understood that numerous arrangements of valves, conduits, precursor sources, and purge gas sources exist that can be used to achieve the objective of selectively supplying gas to one or more reactor chambers 102. Because... Figure 1 This is a schematic diagram of the system. For the sake of simplicity, many components have been omitted from the accompanying drawings; such components may include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and / or bypasses.

[0035] During operation of reactor system 100, a substrate, such as a semiconductor wafer (not shown), may be transferred from, for example, a substrate processing system to one or more reactor chambers 102. Once the substrate has been transferred to one or more reactor chambers 102, one or more gases (e.g., precursors, reactants, carrier gases, and / or purge gases) from gas sources 104-108 are introduced into reactor chamber 102.

[0036] refer to Figure 2The reactor chamber 102 may include a retainer for the base 202, which may be configured to rotate about an axis 203 powered by an electric motor. The base 202 may be configured to support a semiconductor wafer 204 or other semiconductor structure thereon, such that the semiconductor wafer 204 rotates together with the base. The reactor chamber 102 may also include a plurality of heating sources for heating the base 202 and the semiconductor wafer 204. For example, a heating source 207 may be positioned above the semiconductor wafer 204 and configured to directly or indirectly supply heat to the semiconductor wafer 204, and another heating source 208 may be positioned below the base 202 and configured to directly or indirectly supply heat to the base 202. A controller 112 may control how much power is supplied to each heating source. The reactor chamber 102 may also include a plurality of temperature sensors. For example, at least one temperature sensor 209 may be configured to directly or indirectly measure the temperature of at least a portion of the semiconductor wafer 204, and at least one temperature sensor 210 may be configured to directly or indirectly measure the temperature of at least a portion of the base 202. Multiple temperature sensors can be configured to measure multiple different portions of the semiconductor wafer 204 and the substrate 202. For example, temperature sensor 210 can remotely measure the temperature of a specific portion of the substrate 210 (e.g., an annular region of the substrate 210), and another temperature sensor 211 can be directly embedded in or otherwise attached to the substrate 211 to measure the local temperature at the location of temperature sensor 211. Each temperature sensor can provide a signal, such as data, to the controller 112.

[0037] Figure 3 A top view of a semiconductor wafer 204 resting on a base 202 is shown. Although both structures are shown as having a circular shape, this is only for example, and each structure 202, 204 can be any desired shape.

[0038] The heating sources can be used to simultaneously heat the semiconductor wafer 204 and the substrate 202. The heating target can be both the top side (away from the substrate 202) and the bottom side (facing the substrate 202) of the semiconductor wafer 204. To achieve this, the top side of the semiconductor wafer 204 can be heated remotely using radiant heat, and the bottom side of the semiconductor wafer 204 can be heated conductively from the heated substrate 202. Each of the heating sources 207 and 208 may include one or more heating devices, such as one or more lamps (e.g., infrared lamps), one or more resistance heaters, and / or one or more induction heaters. Each of the heating sources 207 and 208 may have a power adjustable by the controller 112. For example, the controller 112 can control the heating source 207 to provide a first power amount (e.g., the power of the heat generated by the heating source 207) and can control the heating source 208 to provide a second power amount (e.g., the power of the heat generated by the heating source 208). The controller 112 can control the power of the heating sources 207, 208 by, for example, controlling how much electrical power is supplied to each of the heating sources 207, 208 and / or sending signals to the heating sources 207, 208 to indicate or otherwise control the amount of heat to be generated.

[0039] Rotation of the pedestal 202 and the semiconductor wafer 204 within the reaction chamber 102 can help average any different conditions (e.g., temperature, gas flow, and / or heating) that may exist at different locations throughout the reaction chamber 102 during semiconductor wafer 204 processing. For example, different amounts of heating and / or gas flow experienced by different points on the top surface of the semiconductor wafer 204 can affect one or more properties of the semiconductor wafer 204, such as the thickness of the layer grown on top of the semiconductor wafer 204. While rotation can average the conditions in the reaction chamber to some extent for any given point on the semiconductor wafer 204, in practice, rotation may not necessarily resolve all the inconsistent conditions experienced by the semiconductor wafer 204 during processing. Such rotation may result in a semiconductor wafer 204 with one or more radially asymmetric properties (e.g., layer thickness). For example, layer thickness may be affected by the growth rate, which may be affected by the heat applied during processing. Because rotation of the semiconductor wafer 204 during processing can still result in the semiconductor wafer 204 having radially asymmetric properties, one or more environmental conditions experienced by a given point of the semiconductor wafer 204 may be “fixed” despite its rotation.

[0040] For example, the material density and / or thickness of the base 202 itself may be inconsistent, so different parts of the base 202 may conduct heat from the bottom of the base 202 to the top of the base 202 (towards the semiconductor wafer 204) at different rates. This inconsistency may cause the semiconductor wafer 204 to be heated by different amounts at different locations. Because the base 202 can rotate at the same rotational speed as the semiconductor wafer 204, this inconsistency in the base 202 can be "fixed" in position relative to the semiconductor wafer 204 despite rotation. In other words, this inconsistency in the base 202 will rotate with the base 202, and therefore any temperature changes caused by variations in the base 202 itself will not be expected to be averaged out due to rotation.

[0041] While it might require more effort to produce a more uniform substrate, this is likely impractical due to the increased costs. Furthermore, even if substrates with minimal variations in thickness and material could be produced, they typically incorporate wafer lifting pins used to carefully place and remove semiconductor wafers from the substrate. These lifting pins, or at least the interface between them and the substrate body, inherently introduce some variability in the thermal conductivity of the substrate near the lifting pins. In fact, lower thermal conductivity has been observed in regions of the substrate near the lifting pins. Therefore, substantially reducing radial asymmetry through improvements in substrate manufacturing techniques is probably impractical.

[0042] It has been further observed that the relative heat applied to the substrate 202 and the semiconductor wafer 204 may also affect the radial asymmetry of the semiconductor wafer 204. For heat applied by a bottom heating source (e.g., heating source 208) providing heat to the bottom surface of the substrate, the temperature of the wafer surface affected by this bottom heat is influenced by upward heat transfer from the bottom of the substrate. If there is a substrate region with lower thermal conductivity, the wafer surface above that region may be cooler due to the applied upward heat, resulting in a locally slower growth rate. For heat applied by a top heating source (e.g., heating source 207) providing heat to the top of the semiconductor wafer, the temperature of the wafer surface is influenced by downward heat transfer to the bottom of the substrate. In this case, the temperature of the wafer surface above a region of lower thermal conductivity in the substrate may be hotter due to the downward applied heat, resulting in a locally faster growth rate. Therefore, there may be a ratio of top-down heat to bottom-up heat that can produce better results by balancing the slow growth effects and fast growth effects occurring in the semiconductor wafer in low heat transfer regions (or other variable regions) of the substrate. In other words, refer to again Figure 2The uniformity of the processed semiconductor wafer 204 can be improved by adjusting the ratio of the power applied by the top heating source 207 to the power applied by the bottom heating source 208. The specific ratio used may depend on a variety of factors, such as the specific processing formulation used (including temperature, gas, pressure, rotation speed, and time), the nature of the substrate 202, the nature of the semiconductor wafer 204, and / or the type of layer formed on the semiconductor wafer 204 during processing.

[0043] refer to Figure 4 The controller 112 of system 100 may include, for example, one or more processors 401 and memory 402. Memory 402 may store computer-executable instructions 410 and / or data 411. When executed by one or more processors 401, the computer-executable instructions 410 may cause system 100 (e.g., under the control of controller 112) to perform any of the functions and operations described herein, including but not limited to those described herein. Figure 5 , 6 The steps and functions are illustrated in Figure 7. For example, controller 112 can be operated to introduce precursor and purge gases from corresponding gas sources 104-108. Controller 112 can control the timing of the gas sequence, the temperature of one or more reaction chambers 102 and / or the substrate therein, the pressure within reaction chamber 102, the power of heating sources 207, 208, and / or various other operations to provide proper operation of system 100. Controller 112 can electrically and / or pneumatically control valves to control the inflow and outflow of precursor, reactant, and purge gases into one or more reactor chambers 102. Physical control of these characteristics of system 100 can be performed via one or more control interfaces 404, which can be connected to various other parts of system 100 via one or more electrical and / or pneumatic lines.

[0044] The controller 112 of system 100 may also include one or more communication interfaces 403. The communication interfaces may provide, for example, a user interface to receive user input and / or provide information to the user and / or another device. For example, one or more communication interfaces 403 may include a keyboard, mouse, display, speaker, universal serial bus (USB) interface, serial bus interface, another type of wired communication interface, and / or wireless communication interface.

[0045] As described above, the ratio of top power to bottom power (which can be the ratio of top power to bottom power, or bottom power to top power) can affect the symmetry of the resulting semiconductor wafer structure. Experiments conducted by the inventors show that the inhomogeneity (NU) of the example semiconductor wafer is affected by the ratio of top heating lamp power (TL) to bottom heating lamp power (BL). Although heating lamps were used in these experiments, similar results can be expected for any type of heating source. NU measurements with varying TL / BL ratios were performed on sample annular strips (“circumferential samples”) with different inner radii surrounding the semiconductor wafer. The results show that a minimum NU value can be found for each circumferential sample. Under the experimental conditions of this experiment, the minimum value corresponds to a TL / BL ratio in the range of about 2 to about 3. Therefore, for this particular example, using a TL / BL ratio in the range of about 2 to about 3 is expected to result in a lower NU for the semiconductor wafer, at least within the sample annular strip, and potentially extending throughout the entire semiconductor wafer. In other words, such a TL / BL ratio can result in an improved radial symmetry for the processed semiconductor wafer. This is just one example involving a specific set of conditions, such as a specific semiconductor wafer, a specific substrate, and a specific processing formulation. It can be expected that the optimal TL / BL ratio for the minimum NU will vary under different conditions, but similar methods can be applied to identify the optimal ratio.

[0046] Figure 5 This is an example flowchart illustrating steps that can be performed to control the power of one or more heating sources during semiconductor wafer processing. Figure 5 The steps can be performed and / or controlled by, for example, controller 112. For example, controller 112 can execute instructions, such as instruction 410 stored in memory 402. In step 501, controller 112 can obtain previously stored data, such as data 411 in memory 402. Stored data 411 may have been provided from user input or from another device to one or more communication interfaces 403 and stored in memory 402. Stored data 411 may represent information related to the power of the top heating source 207 and / or the bottom heating source 208. For example, stored data 411 may indicate or otherwise be used to determine a target relationship (e.g., ratio) between the power of the top heating source 207 and the power of the bottom heating source 208. The target relationship is the power of the top heating source 207 (P... T ) and bottom heating source 208 power (P B In the case of a ratio of ), such a ratio can be similar to the TL / BL ratio discussed above. T / P B Ratio, or P B / P TRatio. In other examples, the target relationship can be a range of target ratios. For example, the range of target ratios could be a specific target ratio plus or minus a predetermined error. Alternatively or concurrently, the stored data 411 can indicate P. B and / or P T The value, for example, is expressed in watts or kilowatts. Alternatively, the stored data 411 may indicate the power factor F. For example, the stored data 411 may indicate P. T The values ​​of P and F, where P B It can be identified as P B =F×P T Alternatively, the stored data 411 can instruct P. B The values ​​of P and F, where P T It can be identified as P T =F×P B As another example, the stored data 411 may include a lookup table with any of the aforementioned power-related information, and index values ​​pointing to desired portions of the lookup table. Any stored data may have been provided from user input or from another device to one or more communication interfaces 403 and stored in memory 402.

[0047] In steps 502 and 503, controller 112 can cause the first heating source (e.g., top heating source 207) to use a determined power P. T This generates heat and can further enable a second heating source (e.g., bottom heating source 208) to use a defined power P. B Heat is generated. Steps 502 and 503 can be performed in parallel (e.g., simultaneously). The first heat source can be a semiconductor structure, such as semiconductor wafer 204, to generate heat, and the second heat source can be a base, such as base 202, to generate heat.

[0048] Figure 6 This is another example flowchart illustrating steps that can be performed to control the power of one or more heating sources during semiconductor wafer processing. Figure 6 The steps can be performed and / or controlled by, for example, controller 112. For example, controller 112 can execute instructions, such as instruction 410 stored in memory 402. In step 601, the first heating source (e.g., top heating source 207) can use power P. T Heat is generated to provide heat to the semiconductor structure (e.g., semiconductor wafer 204). In step 602, a second heating source (e.g., bottom heating source 208) can use power P. B Heat is generated to provide heat to the base (e.g., base 202). P T and P B The initial value can be determined based on stored data (such as data 411). Data 411 can indicate, for example, P.T and P B The actual values, ratios between these values, or some other relationship between these values. Data 411 may also indicate one or more target temperatures, such as a target first temperature associated with the semiconductor structure and / or a target second temperature associated with the substrate. As another example, data 411 may indicate a target relationship between the first and second temperatures, such as a target ratio of temperatures, an indication that temperatures are equal to each other, an indication that temperatures are within a target temperature range, a target difference between temperatures, and / or an indication that each temperature will fall into a target temperature range.

[0049] Steps 601 and 602 can be performed in parallel (e.g., simultaneously). In step 603, while applying the heat from steps 601 and 602, one or more first sensors can be used to measure a first temperature associated with the semiconductor structure. The one or more first sensors may include, for example, temperature sensor 209. In step 604, while applying the heat from steps 601 and 602, one or more second sensors can be used to measure a second temperature associated with the base. The one or more second sensors may include, for example, temperature sensor 210 and / or temperature sensor 211. Steps 601 and 602 can be performed in parallel (e.g., simultaneously).

[0050] In step 605, it can be determined whether P needs to be adjusted. T and / or P B The value is used to maintain a target relationship between the temperature and / or power of the heating source. This determination can be based on a measured first temperature, a measured second temperature, and P. T The current value of P B The current value and / or stored data. For example, in step 605, it can be determined whether the first temperature and the second temperature satisfy a target relationship between the first temperature and the second temperature (indicated by the stored data). For example, it can be determined whether the first temperature and the second temperature are substantially equal or within a predetermined target range for each other. If so, then P T and P B The value of P can remain unchanged. If not, then P can be adjusted. T The value and / or P B The value of P. Adjustment can be, for example, to make the first and second temperatures equal to each other or within a predetermined range. If adjustment is made, then P... T and / or P B The adjustments and / or new values ​​can be stored as data 411, for example, by updating, supplementing, or replacing some or all of the existing data 411. The process can then return to steps 601 and 602 to use P. T and P B The current value of P continues to be heated, as described above. T and PB The current value may have been adjusted.

[0051] Figure 7 An example of how step 605 can be implemented is shown. In this example, step 605 may include steps 701-706. As described above, performing steps 603 and 604 results in the measurement of the first and second temperatures. Figure 7 For the purpose of this study, the first temperature associated with the semiconductor structure (e.g., a semiconductor wafer) will be referred to as T. W And the second temperature associated with the base will be referred to as T. S In step 701, it can be determined whether a temperature imbalance exists between the first temperature and the second temperature. Determining the existence of a temperature imbalance can be useful, for example, when it is desirable for the temperatures of the semiconductor wafer and substrate to be approximately equal, at least within a small margin of error. Equalized temperatures can lead to more uniform growth of layers on the semiconductor wafer. One or more criteria can be used to determine whether a temperature imbalance exists. For example, if T... W and T S Not equal, or if T W and T S If the difference between them is greater than a predetermined threshold, then a temperature imbalance can be determined. On the other hand, if T W and T S Equal, or if T W and T S If the difference between the measured temperatures is less than a predetermined threshold, then it can be determined that there is no temperature imbalance. As another example, the criterion may include a target temperature range or a target ratio of the measured temperatures. These are just some examples of criteria that can be used to determine the presence of a temperature imbalance; one or more other criteria may be used.

[0052] If it is determined in step 701 that there is no temperature imbalance, the process can proceed to step 705, which returns the process to... Figure 6 Steps 601 and 602. However, if a temperature imbalance is determined in step 701, the process can proceed to step 702. In step 702, the nature of the imbalance can be determined. For example, T can be determined. W and T S Which one is greater than or less than the other? For example, it can be determined that T W Is it greater than T? S Or T S Is it greater than T? W Mathematically equivalent, T can be determined. S Is it less than T? W Or T W Is it less than T? S .

[0053] For example, if T is determined W Less than T S (or T) S Greater than T W This means that the measurement temperature of the semiconductor wafer is lower than the measurement temperature of the substrate. In this case, it may be necessary to raise the temperature of the semiconductor wafer, lower the temperature of the substrate, or both. In this case, the process can move to step 703, where the bottom power P can be reduced. B (This will lower the temperature of the base) and can increase the top power P T (This will raise the temperature of the semiconductor wafer), or both can be done.

[0054] On the other hand, if T is determined W Greater than T S (or T) S Less than T W This means that the measurement temperature of the semiconductor wafer is higher than the measurement temperature of the substrate. In this case, it may be necessary to lower the temperature of the semiconductor wafer, raise the temperature of the substrate, or both. In this case, the process can instead be moved from step 702 to step 704, where the bottom power P can be increased. B (This will raise the temperature of the base), which can reduce the top power P T (This will lower the temperature of the semiconductor wafer), or both can be done.

[0055] After adjustments are made in step 703 or 704, the process can move to step 706, where P can be... B and / or P T Any adjustment values ​​are recorded, for example, in memory 402. These adjustment values ​​can supplement or replace previously stored power value data. The process can then proceed to step 705, which allows the process to return to steps 601 and 602 for further temperature measurements. Therefore, the process can be repeated... Figure 6 and Figure 7 The process involves repeated temperature measurements and power adjustments via feedback control to equalize the temperature until the semiconductor processing recipe (or its desired portion) is complete.

[0056] once Figure 6 and Figure 7 Once the process is complete, memory 402 can thus store P, which indicates the temperature at which the semiconductor structure and substrate achieve relative equilibrium (or near-similarity). B and P T The final adjusted value data. This data can be used as initial conditions during future processing of the semiconductor structure. For example, P B and P TThe final adjusted value can be used as initial condition data for steps 501, 601, and / or 602. In this way, Figure 6 and Figure 7 This process can be used not only for the actual processing of semiconductor wafers and other semiconductor structures, but also for determining the bottom power P of a given semiconductor structure processing recipe. B and top power P T The setpoint. For example, the expected equilibrium (or near-equilibrium) bottom and top power can lead to... Figure 7 The TL / BL ratio is at or near the minimum NU.

[0057] For the purpose of summarizing the invention and its advantages relative to the prior art, certain objects and advantages of the invention have been described above. It should be understood, of course, that not all of these objects or advantages may necessarily be achieved according to any particular embodiment of the invention. Therefore, for example, those skilled in the art will recognize that the invention may be embodied or implemented in a manner that achieves or optimizes one or more advantages taught or suggested herein, without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0058] All these embodiments are intended to fall within the scope of the invention disclosed herein. Those skilled in the art will readily appreciate these and other embodiments from the following detailed description of certain embodiments with reference to the accompanying drawings; however, the invention is not limited to any particular embodiment disclosed.

Claims

1. An epitaxial reactor system, comprising: A reactor chamber, comprising at least one receiving area configured as a receiving base; A gas delivery system configured to deliver precursor gas within a reactor chamber; The first heating source is configured to heat a semiconductor structure disposed on a base; The second heating source is configured as a heating base; One or more processors; as well as A memory that stores instructions, which, when executed by one or more processors, enable the epitaxial reactor system: Store data related to heating power delivery; as well as Based on data control, at least one of the first power of the first heating source or the second power of the second heating source is controlled.

2. The epitaxial reactor system of claim 1, further comprising a user interface configured to receive user input, wherein, The data is based on user input.

3. The epitaxial reactor system according to claim 1, wherein, The instructions, when executed by the one or more processors, further enable the epitaxial reactor system: Based on the data, a target relationship between the first power and the second power is determined; and Controlling at least one of the first power or the second power by adjusting at least one of the first power or the second power to maintain the target relationship.

4. The epitaxial reactor system according to claim 3, wherein, The target relationship includes at least one of the following: The target ratio or target ratio range of the first power and the second power; or The target difference or target difference range between the first power and the second power.

5. The epitaxial reactor system according to claim 1, further comprising: A first sensor is configured to measure a first temperature associated with the semiconductor structure; as well as A second sensor is configured to measure a second temperature related to the semiconductor structure. Wherein, the instructions, when executed by the one or more processors, cause the epitaxial reactor system to: Based on the data, a target relationship between the first temperature and the second temperature is determined; and At least one of the first power or the second power is controlled by adjusting at least one of the first power or the second power to maintain the target relationship.

6. The epitaxial reactor system according to claim 5, wherein, The target relationship includes at least one of the following: The target ratio or target ratio range between the first temperature and the second temperature; or The target difference or target difference range between the first temperature and the second temperature.

7. The epitaxial reactor system of claim 1 further includes a user interface configured to display indications based on the data.

8. The epitaxial reactor system of claim 1 further includes a vacuum system configured to adjust the pressure inside the reactor chamber.

9. A method comprising: The semiconductor structure on the base disposed within the reactor chamber of the epitaxial reactor system is heated using a first heating source. The base is heated using a second heating source; as well as Based on the stored data, control at least one of the first power of the first heating source or the second power of the second heating source.

10. The method of claim 9, further comprising receiving user input, wherein, The data is based on user input.

11. The method of claim 9, further comprising: Based on the data, a target relationship between the first power and the second power is determined; as well as Controlling at least one of the first power or the second power includes adjusting at least one of the first power or the second power to maintain the target relationship.

12. The method according to claim 11, wherein, The target relationship includes at least one of the following: The target ratio or target ratio range of the first power and the second power; or The target difference or target difference range between the first power and the second power.

13. The method of claim 9, further comprising: Measure a first temperature associated with the semiconductor structure; Measure the second temperature related to the semiconductor structure; as well as Based on the data, a target relationship between the first temperature and the second temperature is determined. Controlling at least one of the first power or the second power includes adjusting at least one of the first power or the second power to maintain the target relationship.

14. The method according to claim 13, wherein, The target relationship includes at least one of the following: The target ratio or target ratio range between the first temperature and the second temperature; or The target difference or target difference range between the first temperature and the second temperature.

15. The method of claim 9, further comprising displaying an indication based on the data.

16. The method of claim 9, further comprising adjusting the pressure inside the reactor chamber.

17. A non-transitory computer-readable medium for storing instructions and data, wherein, When executed, the instruction configures the epitaxial reactor system as follows: The first heating source heats the semiconductor structure on the base located inside the reactor chamber of the epitaxial reactor system; The second heating source heats the base; and Based on data control, at least one of the first power of the first heating source or the second power of the second heating source is controlled.

18. The non-transitory computer-readable medium according to claim 17, wherein, When the instruction is executed, it further configures the epitaxial reactor system as follows: Based on the data, a target relationship between the first power and the second power is determined; and Controlling at least one of the first power or the second power by adjusting at least one of the first power or the second power to maintain the target relationship.

19. The non-transitory computer-readable medium according to claim 18, wherein, The target relationship includes at least one of the following: The target ratio or target ratio range of the first power and the second power; or The target difference or target difference range between the first power and the second power.

20. The non-transitory computer-readable medium according to claim 17, wherein, When the instruction is executed, it further configures the epitaxial reactor system as follows: Measure a first temperature associated with the semiconductor structure; Measure the second temperature related to the semiconductor structure; Based on the data, determine the target relationship between the first temperature and the second temperature; as well as At least one of the first power or the second power is controlled by adjusting at least one of the first power or the second power to maintain the target relationship.

Images