Semiconductor device and its divisibility monitoring method

Abstract

This disclosure relates to semiconductor devices and methods for monitoring the slittleability of the same. One semiconductor device includes: a substrate comprising a chip region and a guard ring region located outside and adjacent to the chip region; a transfer test pad disposed across the guard ring region and a scribe line region continuously positioned with respect to the guard ring region; a cell test pad disposed within the guard ring region and positioned on the transfer test pad; and a scribe line test pad disposed within the scribe line region and positioned on the transfer test pad.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0047866, filed on April 14, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a semiconductor device and a method for monitoring the divisibility of the same. Background Technology

[0003] Due to characteristics such as miniaturization, versatility, and / or low manufacturing costs, semiconductor chips have become a focus of attention as crucial components in the electronics industry. As the electronics industry advances, semiconductor chips have become increasingly highly integrated. With this increased integration, the size of each chip gradually decreases, and the number of semiconductor chips formed on an individual wafer increases.

[0004] After connecting ferry wafers and unit wafers, semiconductor chips are divided into individual semiconductor chips through a dicing process. As semiconductor chips become more highly integrated, it becomes increasingly difficult to visually inspect the straightness of the diced surfaces of the individual semiconductor chips. Summary of the Invention

[0005] The advantages of the embodiments disclosed herein are not limited to those mentioned herein, and other advantages not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] This disclosure provides a semiconductor device and a method for monitoring the divisibility of a wafer by confirming the straightness of the division when dividing it into individual chips.

[0007] This disclosure provides a semiconductor device comprising: a substrate including a chip region and a guard ring region located outside and adjacent to the chip region; a transfer test pad disposed across the guard ring region and a scribe line region continuously positioned with respect to the guard ring region; a first unit test pad disposed in the guard ring region and positioned on the transfer test pad; and a scribe line test pad disposed in the scribe line region and positioned on the transfer test pad.

[0008] This disclosure provides a semiconductor device comprising: a substrate including a chip region, a guard ring region located outside and adjacent to the chip region, and a scribe line region positioned adjacent to the guard ring region; a cell test pad disposed across the guard ring region and the scribe line region; and a transfer test pad disposed within the guard ring region and positioned below the cell test pad.

[0009] This disclosure provides a method for monitoring the slicability of a semiconductor device, the semiconductor device comprising: a cell test pad disposed in a guard ring region; a scribe test pad disposed in a scribe region continuously positioned with respect to the guard ring region; and a transfer test pad connected to the cell test pad and the scribe test pad, the method comprising applying a voltage to the scribe test pad; and measuring the current flowing between the cell test pad and the scribe test pad to determine the straightness of the scribe.

[0010] According to embodiments of this disclosure, it may be possible to provide a semiconductor device and a method for monitoring the divisibility of a wafer by confirming the straightness of the division when dividing a wafer into individual chips.

[0011] The advantages of the embodiments disclosed herein are not limited to those mentioned above, and those skilled in the art will clearly understand from the description of the claims other advantages not mentioned. Attached Figure Description

[0012] The embodiments of this disclosure will be more fully understood from the following detailed description and accompanying drawings, which are provided for illustrative purposes only and do not limit the scope of this disclosure.

[0013] Figure 1 This is a view showing the planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 2 It shows along Figure 1 A view of the cross-sectional structure taken by line A-A'.

[0015] Figure 3 This is a view showing another planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 4 It shows along Figure 3 A view of the cross-sectional structure taken by line B-B'.

[0017] Figure 5 This is a view showing another planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 6 It shows along Figure 5 A view of the cross-sectional structure taken by line C-C'.

[0019] Figure 7 It shows along Figure 5 A view of another cross-sectional structure taken by line C-C'.

[0020] Figure 8 This is a view showing another planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 9 It shows along Figure 8 A view of the cross-sectional structure cut by line D-D'.

[0022] Figures 10 to 16 This is a view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 17 and Figure 18 This is a view showing the cross-sectional structure of a semiconductor device after it has been segmented.

[0024] Figure 19 This is a view illustrating a method for monitoring the separability of a semiconductor device according to an embodiment of this disclosure. Detailed Implementation

[0025] In the following, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In assigning reference numerals to components in each drawing, the same component may be assigned the same reference numerals even if shown in different drawings. Details of known technology or function may be omitted if they are considered to obscure the subject matter of the present disclosure. As used herein, terms such as “comprising,” “having,” or “consisting of” relating to components may allow the inclusion of additional components, unless terms such as “only” are explicitly used. Furthermore, singular expressions such as “a,” “an,” and “the” are intended to include their plural forms unless the context clearly indicates otherwise.

[0026] Labels such as “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used to describe the components of this disclosure. These labels are intended only to distinguish one component from another and are not intended to limit the nature, order, sequence, or number of the components.

[0027] Regarding the description of the positional relationship between components, when two or more components are described as "connected," "coupled," or "linked," it should be understood that they can be directly "connected," "coupled," or "linked," or they can have an intermediary component. Furthermore, the intermediary component can be included in one or more of the two or more components that are "connected," "coupled," or "linked" to each other.

[0028] When terms such as “after,” “next,” “following,” or “before” are used to describe the temporal or sequential relationship between components, operating methods, or manufacturing methods, they may also include non-continuous cases unless explicitly stated by terms such as “immediately” or “directly.”

[0029] When a component is associated with a value or its corresponding information (e.g., level), such a value or information can be interpreted as including tolerances due to a variety of factors (e.g., process variation, internal or external shocks or noise), even without an explicit separate description.

[0030] In the following, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0031] In the accompanying drawings, the areas indicated by reference numerals beginning with "1" and the areas indicated by reference numerals beginning with "2" can each constitute different semiconductor devices. The description of one semiconductor device also applies to the same configuration of another semiconductor device.

[0032] Figure 1 This is a plan view illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken by line A-A'.

[0033] refer to Figure 1 and Figure 2 The semiconductor device may include a substrate 200, a first insulating layer 201 on the substrate 200, a second insulating layer 202 on the first insulating layer 201, and a third insulating layer 203 on the second insulating layer 202. The substrate 200, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 may be stacked along a third direction VD. The substrate 200, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 may each have a flat top surface and a flat bottom surface extending parallel to a plane defined by a first direction FD and a second direction SD. The third direction VD may be perpendicular to the plane defined by the first direction FD and the second direction SD. The third direction may also be referred to herein as the perpendicular direction. The semiconductor device may further include a first transition test pad 101, a first cell test pad 234, a first scribe test pad 238, a first internal guard ring wiring structure 240, a first external guard ring wiring structure 250, a first scribe wiring structure 260, a first internal transition lower contact 211, a first internal transition lower conductive layer 215, a first internal transition upper contact 219, a first internal transition upper conductive layer 223, a first transition protection bonding contact 227, a first transition protection bonding pad 231, a first external transition lower contact 212, a first external transition lower conductive layer 216, a first external transition upper contact 220, a first external transition upper conductive layer 224, and a first transition test contact 228.

[0034] The substrate 200 may include a first chip region CR1, a first guard ring region GRR1, and a first scriber region SLR1. The first chip region CR1 may be a region where memory cells are disposed and peripheral circuitry for transmitting various signals and voltages to the memory cells. The first guard ring region GRR1 may surround the first chip region CR1, and the first scriber region SLR1 may surround the first guard ring region GRR1. The first guard ring region GRR1 may include a first inner guard ring region IGRR1 and a first outer guard ring region OGRR1. Compared to the first outer guard ring region OGRR1, which may be located adjacent to the first scriber region SLR1, the first inner guard ring region IGRR1 may be a region located adjacent to the first chip region CR1.

[0035] Substrate 200 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Substrate 200 may also include a III-V compound semiconductor substrate, such as a gallium arsenide (GaAs) substrate. Substrate 200 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof. Other semiconductor materials may also be used.

[0036] A first insulating layer 201, a second insulating layer 202, and a third insulating layer 203 are disposed on a substrate 200 in the order described, wherein the first insulating layer 201 is disposed on the substrate 200. Although shown as a single layer, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 are not limited thereto and may be a multilayer structure. The first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 may each comprise silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a high-k dielectric material, or a combination thereof.

[0037] The first internal protection ring region IGRR1 may include a first internal protection ring IGR1, and the first external protection ring region OGRR1 may include a first external protection ring OGR1. Similarly, the second internal protection ring region IGRR2 may include a second internal protection ring IGR2, and the second external protection ring region OGRR2 may include a second external protection ring OGR2.

[0038] In the first internal protection ring region IGRR1, the first internal transition lower contact 211, the first internal transition lower conductive layer 215, the first internal transition upper contact 219, the first internal transition upper conductive layer 223, the first transition protection bonding contact 227, and the first transition protection bonding pad 231 can be disposed within the first insulating layer 201. The substrate 200, the first internal transition lower contact 211, the first internal transition lower conductive layer 215, the first internal transition upper contact 219, the first internal transition upper conductive layer 223, the first transition protection bonding contact 227, and the first transition protection bonding pad 231 can be sequentially arranged in contact with each other. The first internal transition lower contact 211, the first internal transition lower conductive layer 215, the first internal transition upper contact 219, the first internal transition upper conductive layer 223, the first transition protection bonding contact 227, and the first transition protection bonding pad 231 may include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The top surface of the first transition protection bonding pad 231 may be coplanar or substantially coplanar with the interface between the first insulating layer 201 and the second insulating layer 202.

[0039] In the second inner protective ring region IGRR2, the second inner transition lower contact 214, the second inner transition lower conductive layer 218, the second inner transition upper contact 222, the second inner transition upper conductive layer 226, the second transition protection bonding contact 230, and the second transition protection bonding pad 232 can be disposed within the first insulating layer 201. The substrate 200, the second inner transition lower contact 214, the second inner transition lower conductive layer 218, the second inner transition upper contact 222, the second inner transition upper conductive layer 226, the second transition protection bonding contact 230, and the second transition protection bonding pad 232 can be sequentially arranged in contact with each other. The second internal transition lower contact 214, the second internal transition lower conductive layer 218, the second internal transition upper contact 222, the second internal transition upper conductive layer 226, the second transition protection bonding contact 230, and the second transition protection bonding pad 232 may include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The top surface of the second transition protection bonding pad 232 may be coplanar or substantially coplanar with the interface between the first insulating layer 201 and the second insulating layer 202.

[0040] The first internal transition lower contact 211, the first internal transition lower conductive layer 215, the first internal transition upper contact 219, the first internal transition upper conductive layer 223, the first transition protection bonding contact 227, and the first transition protection bonding pad 231 can be continuously arranged along the boundary between the first chip region CR1 and the first protection ring region GRR1.

[0041] In the first outer protective ring region OGRR1, the first outer transition lower contact 212, the first outer transition lower conductive layer 216, the first outer transition upper contact 220, the first outer transition upper conductive layer 224, the first transition test contact 228, and the first transition test pad 101 can be disposed within the first insulating layer 201. The substrate 200, the first outer transition lower contact 212, the first outer transition lower conductive layer 216, the first outer transition upper contact 220, the first outer transition upper conductive layer 224, the first transition test contact 228, and the first transition test pad 101 can be in sequential contact and disposed within the first insulating layer 201. The top surface of the first transition test pad 101 can be formed into a plane substantially the same as the top surface of the first transition protection bonding pad 231. The first external switch lower contact 212, the first external switch lower conductive layer 216, the first external switch upper contact 220, the first external switch upper conductive layer 224, the first switch test contact 228, and the first switch test pad 101 may include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0042] In the second outer protective ring region OGRR2, the second outer transition lower contact 213, the second outer transition lower conductive layer 217, the second outer transition upper contact 221, the second outer transition upper conductive layer 225, the second transition test contact 229, and the second transition test pad 102 can be disposed within the first insulating layer 201. The substrate 200, the second outer transition lower contact 213, the second outer transition lower conductive layer 217, the second outer transition upper contact 221, the second outer transition upper conductive layer 225, the second transition test contact 229, and the second transition test pad 102 can be in sequential contact and disposed within the first insulating layer 201. The top surface of the second transition test pad 102 can be formed into a plane substantially the same as the top surface of the second transition protection bonding pad 232. The second external switch lower contact 213, the second external switch lower conductive layer 217, the second external switch upper contact 221, the second external switch upper conductive layer 225, the second switch test contact 229, and the second switch test pad 102 may include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0043] The bottom surface of the first unit test pad 234 can contact the top surface of the first switch test pad 101. The width of the first unit test pad 234 in the second direction SD can be narrower than the width of the first switch test pad 101 in the second direction SD.

[0044] The first external transition lower contact 212, the first external transition lower conductive layer 216, the first external transition upper contact 220, the first external transition upper conductive layer 224, the first transition test contact 228, and the first transition test pad 101 can be continuously arranged along the boundary between the first chip region CR1 and the first guard ring region GRR1.

[0045] In the first guard ring region GRR1, the first cell protection bonding pad 233, the first inner guard ring wiring structure 240, the first cell test pad 234, and the first outer guard ring wiring structure 250 can be disposed within the second insulating layer 202 and the third insulating layer 203. The first inner guard ring wiring structure 240 can contact the top surface of the first cell protection bonding pad 233. The first outer guard ring wiring structure 250 can contact the top surface of the first cell test pad 234. The first cell protection bonding pad 233, the first cell test pad 234, the first outer guard ring wiring structure 250, and the first inner guard ring wiring structure 240 can include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0046] The first internal protection ring wiring structure 240 may include a lower contact 244 of the first internal unit, a lower conductive layer 243 of the first internal unit, an intermediate contact 242 of the first internal unit, an intermediate conductive layer 241 of the first internal unit, an upper contact 245 of the first internal unit, and an upper conductive layer 246 of the first internal unit. The first external protection ring wiring structure 250 may include a lower contact 254 of the first external unit, a lower conductive layer 253 of the first external unit, an intermediate contact 252 of the first external unit, an intermediate conductive layer 251 of the first external unit, an upper contact 255 of the first external unit, and an upper conductive layer 256 of the first external unit.

[0047] In the second guard ring region GRR2, the second unit protection bonding pad 237, the second inner guard ring wiring structure 290, the second unit test pad 236, and the second outer guard ring wiring structure 280 can be disposed within the second insulating layer 202 and the third insulating layer 203. The second inner guard ring wiring structure 290 can contact the top surface of the second unit protection bonding pad 237. The second outer guard ring wiring structure 280 can contact the top surface of the second unit test pad 236. The second unit protection bonding pad 237, the second unit test pad 236, the second outer guard ring wiring structure 280, and the second inner guard ring wiring structure 290 can include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0048] The second internal protection ring wiring structure 290 may include a lower contact 294 of the second internal unit, a lower conductive layer 293 of the second internal unit, an intermediate contact 292 of the second internal unit, an intermediate conductive layer 291 of the second internal unit, an upper contact 295 of the second internal unit, and an upper conductive layer 296 of the second internal unit. The second external protection ring wiring structure 280 may include a lower contact 284 of the second external unit, a lower conductive layer 283 of the second external unit, an intermediate contact 282 of the second external unit, an intermediate conductive layer 281 of the second external unit, an upper contact 285 of the second external unit, and an upper conductive layer 286 of the second external unit.

[0049] The first internal protection ring IGR1 and the first external protection ring OGR1 can be connected through the internal protection ring wiring structure 240 and the external protection ring wiring structure 250.

[0050] The first unit protection bonding pad 233, the first internal protection ring wiring structure 240, the first unit test pad 234, and the first external protection ring wiring structure 250 can be continuously arranged along the boundary between the first chip region CR1 and the first protection ring region GRR1.

[0051] According to embodiments of this disclosure, the first inner protection ring IGR1 and the first outer protection ring OGR1 can be continuously arranged in a linear form around the first chip region CR1, thereby protecting the semiconductor from moisture penetration and the like.

[0052] The lower conductive layer 243 of the first inner unit and the lower contact 254 of the first outer unit can be in contact. The intermediate conductive layer 241 of the first inner unit and the intermediate conductive layer 251 of the first outer unit can be in contact. The upper conductive layer 246 of the first inner unit and the upper conductive layer 256 of the first outer unit can be in contact.

[0053] In the first scribe zone SLR1, a first transition test pad 101, a first scribe test pad 238, and a first scribe wiring structure 260 can be provided. The first scribe wiring structure 260 may include a first scribe lower contact 264, a first scribe lower conductive layer 263, a first scribe middle contact 262, a first scribe middle conductive layer 261, a first scribe upper contact 265, and a first scribe upper conductive layer 266. The first transition test pad 101, the first scribe test pad 238, and the first scribe wiring structure 260 may include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0054] In the second scribe zone SLR2, a second transition test pad 102, a second scribe test pad 235, and a second scribe routing structure 270 can be provided. The second scribe routing structure 270 may include a second scribe lower contact 274, a second scribe lower conductive layer 273, a second scribe intermediate contact 272, a second scribe intermediate conductive layer 271, a second scribe upper contact 275, and a second scribe upper conductive layer 276. The second scribe routing structure 270 can be positioned above the second scribe test pad 235. The second transition test pad 102, the second scribe test pad 235, and the second scribe routing structure 270 may include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0055] The bottom surface of the first scribing test pad 238 can contact the top surface of the first swiveling test pad 101. The width of the first scribing test pad in the second direction SD can be narrower than the width of the first swiveling test pad 101 in the second direction SD. The first scribing test pad 238 can be spaced apart from the first cell test pad 234.

[0056] The first scribing routing structure 260 may have a structure that is physically separate from the first outer guard ring routing structure 250. The first scribing routing structure 260 may be electrically connected to the first outer guard ring routing structure 250 via the first transition test pad 101.

[0057] The widths of the first lane marking area SLR1 and the second lane marking area SLR2 in the second direction SD can be 40µm or greater and 60µm or less.

[0058] The top surfaces of the conductive layer 246 on the first inner unit, the conductive layer 256 on the first outer unit, and the conductive layer 266 on the first scribbled surface can form the same or substantially the same plane.

[0059] The first transition test pad 101 can be set across the first outer guard ring area OGRR1 and the first scribe area SLR1.

[0060] The first transition test pad 101, the first scribe test pad 238, and the first scribe wiring structure 260 can be continuously set along the boundary between the first chip area CR1 and the first guard ring area GRR1.

[0061] Figure 3 Another planar structure of a semiconductor device according to an embodiment of this disclosure is shown. Figure 4 It shows Figure 3 A cross-sectional view of the B-B' section.

[0062] refer to Figure 3 and Figure 4In the first stencil area SLR1, a first dummy pad 300 may be disposed within a first insulating layer 201 and a second insulating layer 202. The first dummy pad 300 may include a first transition dummy pad 301 and a first unit dummy pad 302 respectively disposed in the first and second insulating layers. The first transition dummy pad 301 and the first unit dummy pad 302 may contact each other at an interface that is coplanar or substantially coplanar with the interface between the first insulating layer 201 and the second insulating layer 202. The first transition dummy pad 301 and the first unit dummy pad 302 may include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0063] In the second scribing area SLR2, a second dummy pad 310 may be disposed within the first insulating layer 201 and the second insulating layer 202. The second dummy pad 310 may include a second transition dummy pad 311 and a second unit dummy pad 312. The second transition dummy pad 311 and the second unit dummy pad 312 may contact each other at an interface that is coplanar or substantially coplanar with the interface between the first insulating layer 201 and the second insulating layer 202. The second transition dummy pad 311 and the second unit dummy pad 312 may include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0064] The first unit dummy pad 302 can be set apart from the first swipe test pad 238. The first transition dummy pad 301 can be set apart from the first transition test pad 101.

[0065] The top surface of the first dummy pad 301 can be formed to be substantially the same as the top surface of the first dummy test pad 101. The bottom surface of the first unit dummy pad 302 can be formed to be the same as or substantially the same as the bottom surface of the first unit test pad 234.

[0066] The top surface of the first dummy pad 301 and the bottom surface of the first unit dummy pad 302 can be in contact. The width of the first dummy pad 301 in the second direction SD can be the same as the width of the first unit dummy pad 302 in the second direction SD.

[0067] The first ferry dummy pad 301 and the first unit dummy pad 302 can be discontinuously set along the boundary between the first chip region CR1 and the first guard ring region GRR1. (See reference) Figure 3The first dummy pad 301 and the first unit dummy pad 302 (collectively referred to as 300) can be discontinuously arranged parallel to one side or the entire side of the boundary between the first chip region CR1 and the first guard ring region GRR1. The second dummy pad 310 (311, 312) can be discontinuously arranged parallel to one side or the entire side of the boundary between the second chip region CR2 and the second guard ring region GRR2.

[0068] The first transition dummy pad 301 can be configured to be further away from the first chip region CR1 than the first transition test pad 101. The first cell dummy pad 302 can be configured to be further away from the first guard ring region GRR1 than the first scribe test pad 238. The first transition dummy pad 301 and the first cell dummy pad 302 can completely overlap each other along the third direction VD. In this configuration, "complete overlap" means that the first transition dummy pad 301 and the first cell dummy pad 302 are aligned such that their entire surface areas coincide with each other along the third direction (VD), and no part of one of the first transition dummy pad 301 and the first cell dummy pad 302 extends beyond the boundary of the other.

[0069] Figure 5 Another planar structure of a semiconductor device according to an embodiment of this disclosure is shown. Figure 6 It shows Figure 5 A cross-sectional view of the C-C' section.

[0070] refer to Figure 5 and Figure 6 The first unit test pad 501 can be disposed within the second insulating layer 202. The first unit test pad 501 can be disposed across the first outer guard ring region OGRR1 and the first scribe zone SLR1. The first unit test pad 501 can extend along the second direction SD partially inside the first outer guard ring region OGRR1 and also inside the first scribe zone SLR1.

[0071] The second cell test pad 502 can be disposed within the second insulating layer 202. The second cell test pad 502 can be disposed across the second outer guard ring region OGRR2 and the second scribe zone SLR2. The second cell test pad 502 can extend along the second direction SD partially inside the second outer guard ring region OGRR2 and also inside the second scribe zone SLR2.

[0072] In the first outer guard ring region OGRR1, a first transition test pad 601 can be disposed within the first insulating layer 201. The top surface of the first transition test pad 601 can contact the bottom surface of the first unit test pad 501. The top surface of the first transition test pad 601 can contact the bottom surface of the first unit test pad 501 at a level that is coplanar or substantially coplanar with the interface between the first insulating layer 201 and the second insulating layer 202. The width of the first transition test pad 601 in the second direction SD can be narrower than the width of the first unit test pad 501 in the second direction SD. Figure 6 As shown, the edge of the first transition test pad 601, located within the first outer protection ring area OGRR1, can be aligned with the edge of the first unit test pad 501 on the third direction VD.

[0073] In the second outer guard ring region OGRR2, a second transition test pad 602 can be disposed within the first insulating layer 201. The top surface of the second transition test pad 602 can contact the bottom surface of the second unit test pad 502. The width of the second transition test pad 602 in the second direction SD can be narrower than the width of the second unit test pad 502 in the second direction SD. The top surface of the second transition test pad 602 can contact the bottom surface of the second unit test pad 501 at a level that is coplanar or substantially coplanar with the interface between the first insulating layer 201 and the second insulating layer 202. The width of the second transition test pad 602 in the second direction SD can be narrower than the width of the second unit test pad 502 in the second direction SD. Figure 6 As shown, the edge of the second swoop test pad 602, located within the second outer protection ring area OGRR2, can be aligned with the edge of the second unit test pad 502 on the third direction VD.

[0074] As another example (not shown), the first transition test pad 601 may be set across the first outer guard ring region OGRR1 and the first scribe region SLR1. Furthermore, in another example (not shown), the second transition test pad 602 may be set across the second outer guard ring region OGRR2 and the second scribe region SLR2.

[0075] The first transition test pad 601 and the first unit test pad 501 may include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0076] Figure 7 An embodiment according to this disclosure is shown. Figure 5 Another cross section of the C-C' portion.

[0077] refer to Figure 5 and Figure 7In the first scribe zone SLR1, the first scribe test pad 701 can be set within the first insulating layer 201.

[0078] In the second scribe zone SLR2, the second scribe test pad 702 can be set within the first insulating layer 201.

[0079] The top surface of the first scribing test pad 701 can contact the bottom surface of the first unit test pad 501. The width of the first scribing test pad 701 in the second direction SD can be narrower than the width of the first unit test pad 501 in the second direction SD. The top surface of the first scribing test pad 701 can form a plane that is substantially the same as the top surface of the first swiveling test pad 601. The first scribing test pad 701 can have a structure that is physically separate from the first swiveling test pad 601.

[0080] The first swipe test pad 701 may include a conductive material, such as, for example, a metal, a metal oxide, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof.

[0081] Figure 8 Another planar structure of a semiconductor device according to an embodiment of this disclosure is shown. Figure 9 It shows Figure 8 A cross-sectional view of the D-D' section.

[0082] refer to Figure 8 and Figure 9 The first dummy pad 800 can be located in the first trace area SLR1. The first dummy pad 800 may include a first transition dummy pad 801 and a first unit dummy pad 802. The first transition dummy pad 801 and the first unit dummy pad 802 may include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The first transition dummy pad 801 and the first unit dummy pad 802 may completely overlap each other along the third direction VD.

[0083] In the second dummy area SLR2, a second dummy pad 860 may be provided. The second dummy pad 860 may include a second transition dummy pad 861 and a second unit dummy pad 862. The second transition dummy pad 861 and the second unit dummy pad 862 may include conductive materials, such as, for example, metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The second transition dummy pad 861 and the second unit dummy pad 862 may completely overlap each other along the third direction VD.

[0084] The first unit dummy pad 802 can be set apart from the first unit test pad 501. The first transition dummy pad 801 can be set apart from the first transition test pad 601.

[0085] The top surface of the first dummy pad 801 can form a plane that is substantially the same as the top surface of the first dummy test pad 601. The bottom surface of the first unit dummy pad 802 can form a plane that is substantially the same as the bottom surface of the unit test pad 501.

[0086] The top surface of the first dummy pad 801 and the bottom surface of the first unit dummy pad 802 can be in contact. The width of the first dummy pad 801 in the second direction SD and the width of the first unit dummy pad 802 in the second direction SD can be the same.

[0087] refer to Figure 8 The first dummy pad 801 and the first unit dummy pad 802 (collectively referred to as the first dummy pad 800) can be discontinuously arranged along the boundary between the first chip region CR1 and the first guard ring region GRR1. The first dummy pad 801 and the first unit dummy pad 802 can be discontinuously arranged on one side or the entire side of the boundary between the first chip region CR1 and the first guard ring region GRR1.

[0088] The first unit dummy pad 802 can be set to be further away from the first chip region CR1 than the unit test pad 501. The first transition dummy pad 801 can be set to be further away from the first guard ring region GRR1 than the first scribe test pad 238.

[0089] Figures 10 to 16 A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0090] refer to Figure 10 A first internal shunting lower contact 211 and a first external shunting lower contact 212 are formed on the substrate 200. A first internal shunting lower conductive layer 215 is formed on the first internal shunting lower contact 211, and a first external shunting lower conductive layer 216 is formed on the first external shunting lower contact 212. A first internal shunting upper contact 219 is formed on the first internal shunting lower conductive layer 215, and a first external shunting upper contact 220 is formed on the first external shunting lower conductive layer 216. A first internal shunting upper conductive layer 223 is formed on the first internal shunting upper contact 219, and a first external shunting upper conductive layer 224 is formed on the first external shunting upper contact 220.

[0091] refer to Figure 11A first transition protection bonding contact 227 may be formed on a first inner transition conductive layer 223, and a first transition test contact 228 may be formed on a first outer transition conductive layer 224. A first transition protection bonding pad 231 may be formed on the first transition protection bonding contact 227, and a first transition test pad 101 may be formed on the first transition test contact 228. The first transition test pad 101 may be formed across a first guard ring region GRR1 and a first scribe region SLR1. In one embodiment, a first transition dummy pad 301 may be formed in the first scribe region SLR1.

[0092] refer to Figure 12 A first internal unit intermediate conductive layer 241, a first external unit intermediate conductive layer 251, and a first scribe line intermediate conductive layer 261 can be formed on the unit wafer substrate 1200. A first internal unit intermediate contact 242 can be formed on the first internal unit intermediate conductive layer 241, a first external unit intermediate contact 252 can be formed on the first external unit intermediate conductive layer 251, and a first scribe line intermediate contact 262 can be formed on the first scribe line intermediate conductive layer 261. A first internal unit lower conductive layer 243 can be formed on the first internal unit intermediate contact 242, a first external unit lower contact 254 can be formed on the first external unit intermediate contact 252, and a first scribe line lower conductive layer 263 can be formed on the first scribe line intermediate contact 262.

[0093] refer to Figure 13 The first internal cell lower contact 244 can be formed on the first internal cell lower conductive layer 243, the first external cell lower contact 254 can be formed on the first external cell lower conductive layer 253, and the first scribe line lower contact 264 can be formed on the first scribe line lower conductive layer 263. The first cell protection bonding pad 233 can be formed on the first internal cell lower contact 244, the first cell test pad 234 can be formed on the first external cell lower contact 254, and the scribe line test pad can be formed on the first scribe line lower contact 264. In one embodiment, the first cell dummy pad 302 can be formed in the first scribe line region SLR1.

[0094] refer to Figure 14 , Figure 11 semiconductor devices and Figure 13 Semiconductor devices can be bonded together. Figure 13The semiconductor devices can be bonded in a flipped state. In this case, the first cell protection bonding pad 233 can contact the first transition protection bonding pad 231. The first cell test pad 234 and the scribe test pad can contact the first transition test pad 101. In one embodiment, the first cell dummy pad 302 and the first transition dummy pad 301 can contact each other.

[0095] refer to Figure 15 The unit wafer substrate 1200 can be removed. The process for removing the unit wafer substrate 1200 may include, for example, a wet etching process.

[0096] refer to Figure 16 The first internal unit contact 245 can be formed on the first internal unit intermediate conductive layer 241, the first external unit contact 255 can be formed on the first external unit intermediate conductive layer 251, and the first scribe line contact 265 can be formed on the first scribe line intermediate conductive layer 261. The first internal unit conductive layer 246 can be formed on the first internal unit contact 245, the first external unit conductive layer 256 can be formed on the first external unit contact 255, and the first scribe line conductive layer 266 can be formed on the first scribe line contact 265.

[0097] According to embodiments of this disclosure, since the first transition test pad 101 or the first cell test pad 501 is configured across the first outer guard ring region OGRR1 and the first scribe region SLR1, it is possible to electrically determine whether the straightness of the diced surface of the diced semiconductor chip is acceptable.

[0098] Figure 17 and Figure 18 This is a diagram showing the cut surface structure of a semiconductor device according to embodiments of the present disclosure.

[0099] refer to Figure 17 Semiconductor devices can be partitioned along the boundary surface between the first partition region SLR1 of a semiconductor device and the second partition region SLR2 of an adjacent semiconductor device.

[0100] As an example, a ground voltage can be applied to the first cell test pad 234, and any voltage can be applied to the first swipe test pad 238. In this case, if as... Figure 17 By dividing the area as shown, it can be confirmed that current flows between the first unit test pad 234 and the first scribe test pad 238, thereby indicating that the straightness of the division is acceptable.

[0101] refer to Figure 18Semiconductor devices can be delimited along a portion of the boundary surface between a first scribe region SLR1 of one semiconductor device and a second scribe region SLR2 of an adjacent semiconductor device (including a portion of the interface between the first insulating layer 201 and the second insulating layer 202). As an example, delamination may occur at the interface between the first swipe test pad 101 and the first scribe test pad 238.

[0102] As an example, a ground voltage can be applied to the first cell test pad 234, and any voltage can be applied to the first swipe test pad 238. In this case, if as... Figure 18 If the division occurs as shown, there will be no current flow between the first unit test pad 234 and the first scribe test pad 238, thus indicating that the division lacks straightness.

[0103] Figure 19 A method for monitoring the separability of a semiconductor device according to an embodiment of this disclosure is illustrated. Hereinafter, by referring to... Figure 2 The semiconductor device described is used as an example to illustrate the method.

[0104] First, a voltage is applied to the first scribe test pad 238 within the semiconductor device (S1910). The conductive layer 256 on the first external cell can be grounded, and any voltage can be applied to the conductive layer 266 on the first scribe by contacting the probe.

[0105] Then, the current flowing between the first cell test pad 234 and the first scribe test pad 238 is measured to determine the straightness of the scribe (S1920). The presence or absence of the current can be checked by contacting the probes with the conductive layer 256 on the first outer cell and the conductive layer 266 on the first scribe, respectively.

[0106] If as Figure 17 If the division occurs as shown, current will flow between the first cell test pad 234 and the first scribe test pad 238, thus indicating that the straightness of the division is acceptable. If as shown... Figure 18 If the division occurs as shown, there will be no current flow between the first unit test pad 234 and the first scribe test pad 238, thus indicating that the division lacks straightness.

[0107] Traditionally, the straightness of the scribe lines in semiconductor chips is inspected visually. However, according to embodiments of this disclosure, the straightness of the scribe lines is determined by measuring the current flowing between the first cell test pad 234 and the first scribe test pad 238, thereby allowing for efficient determination of scribe line straightness or scribe defects.

[0108] The foregoing description provides illustrative embodiments of this disclosure. Therefore, those skilled in the art to which this disclosure pertains can make various modifications and variations to the embodiments without departing from the essential characteristics of this disclosure. Furthermore, the embodiments disclosed herein are not intended to limit the scope of this disclosure, but rather to describe it. Therefore, the scope of this disclosure should not be limited by the embodiments and their many variations, and additional embodiments can be readily conceived by those skilled in the art. Moreover, embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A substrate comprising a chip region and a guard ring region outside and adjacent to the chip region; A test pad is provided across the guard ring region and the scribe line region, wherein the scribe line region is continuously positioned with respect to the guard ring region. Unit test pads, which are disposed within the guard ring region and positioned on the transition test pads; and The scribe test pad is set in the scribe area and positioned on the swipe test pad.

2. The semiconductor device according to claim 1, wherein, The width of the scribing test pad is narrower than the width of the swiveling test pad.

3. The semiconductor device according to claim 1, wherein, The unit test pads are spaced apart from the scribe test pads.

4. The semiconductor device according to claim 1, wherein, The bottom surface of the unit test pad and the bottom surface of the scribe test pad are in contact with the top surface of the swiveling test pad.

5. The semiconductor device according to claim 1, wherein, The unit test pads are positioned along the boundary between the chip region and the guard ring region.

6. The semiconductor device according to claim 1, further comprising: An external guard ring wiring structure is disposed on the unit test pad; and A scribe line structure is provided on the scribe test pad. in, The scribing structure and the external protective ring structure are physically separate.

7. The semiconductor device according to claim 6, in, The external protective ring wiring structure and the scribbled wiring structure include a conductive layer, and The first conductive layer in the conductive layer of the outer protective ring wiring structure that is furthest from the unit test pad is positioned on the same layer as the second conductive layer in the conductive layer of the scribe wiring structure that is furthest from the scribe test pad.

8. The semiconductor device according to claim 6, wherein, The external protection ring wiring structure and the scribbled wiring structure are electrically connected through the swiveling test pad.

9. The semiconductor device according to claim 6, further comprising: An inner protective ring is disposed within the protective ring area; as well as An outer protective ring is disposed within the protective ring area and is further away from the chip area than the inner protective ring. The external protection ring includes at least a portion of the swiveling test pad, the unit test pad, and the external protection ring wiring structure.

10. The semiconductor device of claim 9, wherein, The internal protective ring includes: A ferry protection bonding pad is disposed in the protection ring area, adjacent to the chip area, and positioned on the same layer as the ferry test pad; Unit protection bond pads, which are disposed on the transition protection bond pads; and An internal protection ring wiring structure is provided on the cell protection bonding pad.

11. The semiconductor device according to claim 10, wherein, The inner protection ring and the outer protection ring are connected through the wiring structure of the outer protection ring and the wiring structure of the inner protection ring.

12. The semiconductor device according to claim 1, further comprising: A dummy pad is used for ferrying, which is set in the scribing area and spaced apart from the ferrying test pad. as well as The unit dummy pad is set on the ferry dummy pad.

13. The semiconductor device according to claim 12, wherein, The top surface of the ferry dummy pad and the top surface of the ferry test pad are located on the same plane.

14. The semiconductor device according to claim 12, wherein, The ferry dummy pads and the unit dummy pads are discontinuously arranged along the boundary between the chip area and the guard ring area.

15. The semiconductor device according to claim 12, wherein, The width of the top surface of the ferry dummy pad is the same as the width of the bottom surface of the unit dummy pad.

16. The semiconductor device according to claim 12, wherein, The scribing test pads are positioned closer to the guard ring area than the cell dummy pads.

17. A semiconductor device, comprising: The substrate includes a chip region, a guard ring region located outside the chip region and adjacent to the chip region, and a scribe line region located adjacent to the guard ring region; Unit test pads, which are positioned across the guard ring region and the scribe line region; and The transfer test pad is located within the protection ring area and below the unit test pad.

18. The semiconductor device of claim 17, further comprising a scribe test pad disposed in the scribe area and positioned below the cell test pad.

19. The semiconductor device of claim 17, further comprising: The unit dummy pad is set in the scribe area and spaced apart from the unit test pad; as well as The dummy pad is positioned below the dummy pad of the unit.

20. A method for monitoring the separability of a semiconductor device, the semiconductor device comprising: Unit test pads are located within the guard ring area; A scribe test pad is set in a scribe area, which is continuously positioned with the guard ring area; as well as A transfer test pad, which is connected to the unit test pad and the scribe test pad, the method includes: Apply voltage to the scribe test pads; and The current flowing between the unit test pad and the scribe test pad is measured to determine the straightness of the scribe.

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