A wafer regeneration edge chamfering process method

Abstract

This application belongs to the field of semiconductor manufacturing, specifically relating to an edge chamfering process method in wafer remanufacturing. Addressing the problems of poor angle control precision and unstable surface quality in existing wafer remanufacturing processes, this invention provides an optimized edge chamfering process method. This method includes precise grinding and polishing of the remanufactured wafer edges, optimizing the edge profile by controlling the chamfer angle and surface roughness. By employing the above technical solution, this application achieves high-precision edge processing of remanufactured wafers, significantly improving edge quality consistency, reducing particle contamination and stress concentration problems in subsequent processes, and effectively improving the reliability and yield of remanufactured wafers.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing, and specifically relates to an edge chamfering process method in wafer regeneration. Background Technology

[0002] As the core foundation of modern information technology, the semiconductor industry has experienced rapid growth in recent years. Wafers, as an irreplaceable core substrate material in semiconductor chip manufacturing, have become crucial links in the semiconductor industry chain in terms of utilization and production cost control. In actual production, due to the requirements of equipment stability and the high price of positive wafers, equipment typically requires the use of dummy wafers and monitor wafers for testing and verification. To effectively reduce the cost of semiconductor production consumables and improve resource utilization, wafer regeneration technology has emerged. This technology involves professionally regenerating test wafers to meet the quality standards for secondary production. However, the standard chamfered structure of virgin wafers inevitably suffers from defects such as wear, edge chipping, microcracks, scratches, and oxidation damage after undergoing a process, cleaning, and manual handling. If the edge areas of the regenerated wafer are not effectively treated during the regeneration process, these micro-defects will continue to spread and worsen in subsequent high-temperature processes, leading to a series of serious problems such as wafer cracking, particle detachment, and uneven film adhesion, directly affecting the performance and lifespan of the regenerated wafer. Therefore, it is necessary to thoroughly remove the damaged layer at the edge of the regenerated wafer through a professional chamfering process and reconstruct a chamfer structure that meets the standards.

[0003] Among the various processes involved in wafer regeneration, the edge chamfering process is a key technological step that determines the quality of the regenerated wafer. The core objective of this process is to precisely remove the damaged layer at the wafer edge while simultaneously reconstructing a standardized chamfer geometry. This ensures that the regenerated wafer possesses good edge integrity and structural stability, thereby meeting the stringent requirements of advanced semiconductor manufacturing processes for substrate materials. The chamfering process not only needs to safely remove the damaged layer but also requires a balance across multiple dimensions, including processing accuracy, material utilization, and control of residual edge stress. This places extremely high technical demands on the design and implementation of the process method.

[0004] Existing technologies already include solutions for wafer edge treatment. Patent CN111761419B employs an end-face etching method to immerse and etch the wafer, followed by grinding the wafer edges with a silicone carbide tape to remove the damaged layer. However, this technology has significant shortcomings: the tape grinding method cannot reconstruct the standard chamfer structure of the wafer edge, making it difficult to restore the standard chamfer dimensions; this process primarily targets edge damage repair, failing to differentiate between the degree of damage at the wafer edge, and cannot provide differentiated and precise treatment for different damage types; the grinding stress generated during tape grinding may increase residual stress at the wafer edge, affecting the long-term stability of the regenerated wafer. Another patent, CN108666203B, removes organic matter from the wafer edge through edge ashing, then removes silicon-based residues, metal residues, and other impurity particles through etching, while simultaneously using masking to avoid damage to the entire wafer. However, this technical solution also has significant drawbacks: the method mainly targets the improvement of wafer edge morphology and impurity removal, and is not specifically designed for the chamfering process of regenerated wafers, thus failing to effectively reconstruct the standard chamfer structure; the etching method used to remove material makes it difficult to precisely control the consistency of chamfer dimensions, failing to meet the stringent requirements of high-end semiconductor wafers for chamfer size accuracy; the method does not fully consider the layered removal requirements of the edge damage layer of regenerated wafers, failing to completely remove deep microcracks and hidden damage layers, resulting in poor chamfer size consistency of the regenerated wafer. The aforementioned existing technical solutions indicate that current wafer edge processing technologies are mainly geared towards original wafer manufacturing or general edge repair scenarios, failing to fully consider the special technical needs of wafer regeneration scenarios. They suffer from common problems such as a lack of differentiated processing capabilities, inability to completely remove deep damage, difficulty in ensuring chamfer size consistency, and insufficient control of residual edge stress, making it difficult to meet the urgent needs of high-end semiconductor wafers for high-precision, high-stability regeneration processing. Therefore, a differentiated, high-precision, and high-stability edge chamfering process method specifically for wafer regeneration is urgently needed. Summary of the Invention

[0005] The purpose of this invention is to provide an edge chamfering process method in wafer regeneration, which can effectively solve the problems in the background art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] An edge chamfering process for wafer regeneration includes the following specific steps:

[0008] Step 1: Wafer pretreatment: Select the wafer to be recycled, and use an appearance inspection device to inspect the edge of the wafer for chipping, scratches, microcracks, and the depth of residual damage layer, and classify the edge damage level. Then, perform ultrasonic spray cleaning and nitrogen drying on the wafer to remove dust, particles, and organic residual impurities from the wafer surface and edges.

[0009] Preferably, in step 1, the edge damage level is divided into three levels: mild damage, moderate damage, and severe damage. Mild damage is defined as an edge damage layer depth of less than 5 μm, with only minor scratches and no chipping or cracks. Moderate damage is defined as an edge damage layer depth of ≥5 μm and <15 μm, with a small amount of shallow chipping and micro-cracks. Severe damage is defined as an edge damage layer depth of ≥15 μm, with obvious chipping, deep cracks, and residual cutting marks.

[0010] Preferably, in step 1, the ultrasonic spray cleaning uses ultrapure water ultrasonic cleaning with a frequency of 40 to 60 kHz and a temperature of 25 to 35°C for 3 to 5 minutes, combined with high-pressure spray rinsing with a spray pressure of 0.2 to 0.3 MPa. After cleaning, high-purity nitrogen is used for constant temperature drying at a temperature of 30 to 40°C.

[0011] Step 2: Wafer positioning and clamping: Place the dried wafer in the precision chamfering station and fix it horizontally using vacuum adsorption. Use a vision alignment system to calibrate the coaxiality between the wafer center and the chamfering wheel, and control the coaxiality error within ±0.02mm.

[0012] Preferably, in step 2, the vision alignment system uses a high-precision industrial camera and image processing algorithm to determine the wafer center position through edge detection and center fitting algorithm, and calculates the coaxiality deviation value according to the calibration position of the chamfering grinding wheel. The motion control system adjusts the wafer position to control the coaxiality error within ±0.02mm.

[0013] Step 3: Segmented Differentiated Chamfering Grinding: A mapping database covering various wafer specifications and edge damage levels is pre-established. This database stores gradient grinding parameter templates corresponding to each damage level, wafer material, and size. Based on the edge damage level and basic wafer information defined in Step 1, the matching parameter template is retrieved from the mapping database. According to the preset gradient grinding parameters in the template, two-stage chamfering processing, rough grinding and fine grinding, is performed to remove all damaged layers from the wafer edge. For wafers with severe damage levels, an additional grinding process is added between rough grinding and fine grinding. The grinding parameters are also pre-stored in the mapping database and retrieved from it, forming a three-stage processing of rough grinding, grinding, and fine grinding.

[0014] Preferably, in step 3, the rough grinding process uses a diamond grinding wheel with a grit size of 800 to 1200 mesh, a rough grinding feed speed of 0.5 to 1.2 mm / s, a grinding wheel speed of 3000 to 4500 r / min, and a single-sided grinding allowance of 3 to 18 μm, to quickly remove large-area damage layers at the wafer edge; the fine grinding process uses a diamond grinding wheel with a grit size of 2000 to 3000 mesh, a fine grinding feed speed of 0.2 to 0.5 mm / s, a grinding wheel speed of 4500 to 6000 r / min, and a single-sided fine grinding allowance of 1 to 3 μm, to correct the chamfer contour accuracy and eliminate micro-scratches from the rough grinding.

[0015] Preferably, lightly damaged wafers are only subjected to fine grinding, without the need for a rough grinding step; moderately damaged wafers are subjected to rough grinding and fine grinding in sequence; and severely damaged wafers have an extended rough grinding time and an additional grinding step before fine grinding.

[0016] Preferably, in step 3, a special grinding coolant is continuously sprayed during the chamfering process. The grinding coolant is composed of alumina abrasive, grinding aid, and ultrapure water, wherein the abrasive accounts for 15% to 35% by mass, the grinding aid accounts for 1.9% to 3.3% by mass, and the remainder is ultrapure water. The spray flow rate is 5 to 8 L / min, and the coolant temperature is constant at 22 to 26°C.

[0017] Step 4: Fine edge polishing: The edges of the ground wafer are subjected to flexible polishing to eliminate residual grinding marks and microscopic defects, and to optimize the surface finish of the chamfered surfaces.

[0018] Preferably, in step 4, the flexible polishing uses a non-woven polishing wheel in conjunction with a silica polishing slurry, with a polishing wheel speed of 2000 to 3000 r / min and a polishing time of 2 to 4 minutes. After polishing, the roughness of the wafer edge chamfer surface is ≤0.02μm.

[0019] Step 5: Stress relief treatment: Place the polished wafer in a constant temperature and dust-free environment for constant temperature treatment to release the residual stress generated by the grinding process at the wafer edge.

[0020] Preferably, the isothermal aging treatment in step 5 is at a temperature of 45 to 55°C, lasts for 15 to 25 minutes, and is conducted in a Class 100 cleanroom environment to ensure that the wafer edge is not contaminated by external particles during stress release.

[0021] Step 6 Cleaning and Finishing: The entire wafer is cleaned and dried using ultrapure water circulation, and the edge chamfering process of wafer regeneration is completed.

[0022] Preferably, the cleaning process in step 6 uses a mixture of dilute hydrofluoric acid and ultrapure water, with a dilute hydrofluoric acid mass concentration of 0.5% to 2% and an immersion time of 30 to 60 seconds, to remove the micro-oxidation layer at the edge and improve the corrosion resistance and structural stability of the wafer edge.

[0023] Preferably, after processing, the wafer chamfer angle is 25 to 35 degrees, the chamfer width uniformity error is ≤ ±0.03mm, and there are no defects such as chipping, cracks, or scratches on the edges, which meets the standards for secondary processing of regenerated wafers.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. Strong ability to handle differentiation

[0026] This invention adds an edge damage detection and grading process to match differentiated grinding parameters for wafers with light, medium and heavy damage, thereby achieving precise processing. This effectively avoids material waste caused by over-processing and defect residue caused by under-processing, and significantly improves the processing accuracy and material utilization of regenerated wafers.

[0027] 2. High chamfer quality stability

[0028] This invention employs a three-stage gradient processing technique consisting of coarse grinding, fine grinding, and polishing. This process progressively removes the damaged layer, corrects the chamfer profile, and optimizes surface finish, completely eliminating microscopic defects at the edges and reconstructing a standard chamfer structure. After processing, the wafer exhibits a chamfer angle of 25 to 35 degrees, a chamfer width uniformity error ≤ ±0.03 mm, and an edge roughness ≤ 0.02 μm, meeting the stringent requirements for chamfer dimensional accuracy in high-end semiconductor wafers.

[0029] 3. Effective control of residual stress

[0030] This invention effectively releases residual stress generated during wafer edge grinding through constant temperature stress relief treatment. At the same time, it uses a special constant temperature grinding coolant to keep the coolant temperature constant at 22 to 26°C, which effectively reduces the wafer temperature rise during grinding, avoids thermal damage and stress generation, optimizes edge structure stability, and improves the reliability of regenerated wafers in subsequent high-temperature processes.

[0031] 4. Good edge integrity

[0032] This invention uses a mixture of dilute hydrofluoric acid and ultrapure water to clean the wafer edges, removing the microscopic oxide layer and improving the corrosion resistance and structural stability of the wafer edges. After regeneration, the wafer edges are free of defects such as chipping, cracks, and scratches, and the edge integrity and structural stability are significantly improved, providing quality assurance for the secondary processing of regenerated wafers. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the overall technical solution architecture of the wafer regeneration edge chamfering process proposed in this invention;

[0034] Figure 2 This is a schematic diagram of the core principle framework of adaptive control of edge chamfer parameters in this invention;

[0035] Figure 3 This is a schematic diagram of the main processing stages of the wafer edge chamfering process in this invention. Detailed Implementation

[0036] Example 1

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0038] This invention provides an edge chamfering process for wafer regeneration, comprising six core steps: wafer pretreatment, wafer positioning and clamping, segmented differentiated chamfering grinding, edge fine polishing, stress relief treatment, and cleaning. The following provides a detailed technical description of each step.

[0039] In step 1, the wafer preprocessing stage, the wafer to be recycled is first selected as the processing object. After being used in a single process, the edge area of ​​the wafer to be recycled usually has varying degrees of damage, including defects such as edge chipping, scratches, microcracks, and residual damage layers. The presence of these defects directly affects the performance and reliability of the recycled wafer in the secondary process. Therefore, before formal processing, the damage state of the wafer edge must be comprehensively evaluated using precise inspection methods.

[0040] The specific inspection process is completed using visual inspection equipment, which integrates an optical imaging system, a high-resolution image acquisition module, and a defect recognition algorithm module. The optical imaging system employs a dual illumination method using a coaxial light source and a ring light source, enabling clear visualization of the microscopic morphological features of the wafer edge region. The high-resolution image acquisition module achieves a pixel resolution of 0.5μm, capable of identifying various defects larger than 1μm in size at the wafer edge. The defect recognition algorithm module is built upon a deep learning convolutional neural network and, after training with a large number of wafer edge defect samples, can automatically classify and identify various defect types such as edge chipping, scratches, microcracks, and residual cutting marks. The defect identification algorithm module is built on an improved deep learning convolutional neural network. Its training process is as follows: First, a large number of original image samples of wafer edge regions are collected, covering four main defect types: chipping, scratches, microcracks, and residual cutting marks, as well as defect-free normal edge images. Each category has at least 5000 samples, and the samples come from wafers of different specifications and process stages to ensure sample diversity and representativeness. Second, professional inspection personnel perform pixel-level annotation of the defect areas in each sample image, generating corresponding defect category labels and location labels, forming standardized training and validation datasets, with the two datasets in an 8:2 ratio. The network is divided into sections. Then, a ResNet-50 deep residual network pre-trained on the ImageNet large-scale image dataset is used as the backbone feature extraction network, retaining its shallow general feature extraction capabilities. The deep classification layers are modified using transfer learning specifically for wafer edge defects. This involves replacing the original fully connected classification layers with new fully connected layers adapted for four-class classification tasks (edge ​​chipping, scratches, microcracks, and residual cutting marks). The entire network is then fine-tuned end-to-end using a labeled training dataset. During training, the cross-entropy loss function is used as the optimization objective, combined with the Adam optimizer and cosine annealing learning rate scheduling strategy. The initial learning rate is set to 1×10⁻⁶. -4 The training iterations (epochs) were set to 200, and the batch size was set to 32 images. During training, the model was evaluated on the validation dataset after each epoch. Training was terminated early when the validation accuracy no longer improved for 10 consecutive epochs to prevent overfitting. Finally, the model with the highest validation accuracy was selected as the final defect recognition model. This model achieved an accuracy of over 98% for the four types of defects and a false positive rate of less than 0.5% for defect-free edges.

[0041] During the inspection process, the visual inspection equipment performs a 360-degree full-circle scan of the wafer edge to acquire complete morphological image data of the wafer edge. The scanning resolution is set to acquire no less than 1000 sampling points per mm to ensure the completeness and accuracy of defect detection. Based on the inspection results, the system calculates the damage layer depth distribution data of each region of the wafer edge and classifies the edge damage level accordingly.

[0042] The edge damage levels are classified into three grades: Slightly damaged wafers have an edge damage layer depth of less than 5 μm, characterized by only minor scratches and no chipping or cracking; moderately damaged wafers have an edge damage layer depth ≥5 μm and <15 μm, characterized by a small amount of shallow chipping and microcracks; and severely damaged wafers have an edge damage layer depth ≥15 μm, characterized by significant chipping, deep cracks, and residual cutting marks. This precise classification of edge damage levels provides a scientific basis for matching subsequent differentiated grinding parameters.

[0043] After damage level detection, the wafer undergoes comprehensive ultrasonic spray cleaning. The ultrasonic spray cleaning system consists of core components such as an ultrasonic generator, spray head array, circulating filtration system, and temperature control system. The ultrasonic generator outputs ultrasonic vibration signals with a frequency range of 40kHz to 60kHz, creating a uniform cavitation effect field within the cleaning tank. Ultrapure water is used as the cleaning solution, with the water temperature constantly controlled between 25℃ and 35℃. This temperature range ensures optimal cavitation cleaning efficiency. Multiple spray head arrays are installed within the cleaning tank, with the spray pressure set to a high-pressure rinsing mode of 0.2MPa to 0.3MPa to ensure the cleaning solution effectively washes away various contaminants on the wafer surface and edge areas.

[0044] The cleaning process lasts 3 to 5 minutes, during which ultrasonic cavitation and high-pressure spraying work synergistically. Ultrasonic cavitation generates microscopic explosive shock waves on the wafer surface, effectively removing adhering microparticles and organic residues; high-pressure spraying flushes the removed contaminants off the wafer surface, preventing secondary adhesion. After cleaning, the wafer is dried at a constant temperature using high-purity nitrogen. The drying temperature is set between 30°C and 40°C, a range that allows for rapid evaporation of moisture from the wafer surface while avoiding thermal stress caused by excessive heat. The high-purity nitrogen reaches a purity of 99.999% or higher, ensuring that no new contaminants are introduced during the drying process.

[0045] After the above cleaning and drying process, dust, particles, and organic residues on the wafer surface and edges are thoroughly removed, providing a clean processing environment for subsequent precision chamfering.

[0046] In step 2, the wafer positioning and clamping stage, the dried wafer is transferred to the precision chamfering processing station. The precision chamfering processing station is located within a cleanroom, with an environmental cleanliness level meeting Class 100 standards, where the concentration of airborne particles is controlled to no more than 100 particles with a diameter of 0.5 μm per cubic foot. The station platform is supported by high-precision air bearings and a linear motor drive system, achieving sub-μm positioning accuracy.

[0047] The wafers are secured at the workstation using a vacuum adsorption method. The workstation platform surface is equipped with an array of vacuum adsorption holes. The layout of these holes has been precisely calculated and optimized to ensure uniform stress on the wafer under vacuum, preventing warping or deformation. The vacuum adsorption system uses an oil-free dry vacuum pump to provide the negative pressure source, achieving a vacuum level below -90 kPa. After the wafer is placed on the workstation platform, the adsorption holes and the back of the wafer form a sealed cavity. Once the vacuum pump is activated, the wafer is firmly adsorbed and fixed. This vacuum adsorption method avoids stress concentration and mechanical damage at the wafer edges that can occur with mechanical clamping.

[0048] After the wafer is fixed by adsorption, the coaxiality between the wafer center and the chamfering grinding wheel is calibrated using a vision alignment system. The vision alignment system consists of a high-precision industrial camera, a telecentric optical lens, an image processing workstation, and a motion control system. The image processing workstation has a built-in edge detection and center-fitting algorithm module. The specific implementation details of this module are as follows: First, the image preprocessing unit performs a series of preprocessing operations on the wafer edge image acquired by the high-precision industrial camera, including grayscale correction to compensate for illumination inhomogeneity, anisotropic filtering to preserve edge details and suppress sensor noise, and adaptive contrast enhancement to highlight the grayscale difference between the wafer edge and the background. Second, based on the preprocessed image, the sub-pixel edge extraction unit uses an interpolation-based sub-pixel edge localization technique—specifically, a quadratic curve fitting method. This involves first obtaining the pixel-level edge position using the Canny operator, and then performing a three-point quadratic interpolation fitting on the gradient magnitude along the normal direction of the pixel-level edge to solve for the precise position corresponding to the maximum gradient magnitude, thereby improving the edge localization accuracy to the sub-pixel level. Subsequently, the robust circle fitting unit employs a weighted least squares circle fitting algorithm on the sub-pixel edge point set. This algorithm assigns different weights to each edge point based on its local gradient magnitude and edge continuity confidence, and gradually reduces the influence of outlier noise points through iterative reweighted least squares (IRLS), ultimately outputting high-precision wafer center coordinates. The motion control system drives a linear motor to fine-tune the position based on the calculated coaxiality deviation value, controlling the coaxiality error between the wafer center and the grinding wheel center within ±0.02mm. The position coordinates of the chamfering grinding wheel are precisely calibrated using a high-precision laser displacement sensor with a measurement accuracy of 0.1μm, accurately acquiring the radial position information of the grinding wheel and providing benchmark data for coaxiality deviation calculation. Precise control of coaxiality accuracy is a crucial prerequisite for ensuring the uniformity of chamfering dimensions.

[0049] In step 3, the segmented differentiated chamfering grinding stage, a mapping database covering various wafer specifications and edge damage levels is pre-established. This database stores gradient grinding parameter templates corresponding to each damage level, wafer material, and size. The construction logic of this mapping database is as follows: First, for wafers of different specifications (including 6-inch, 8-inch, and 12-inch) and different materials (including monocrystalline silicon, polycrystalline silicon, and silicon carbide), combined with their typical edge damage levels (mild, moderate, and severe), multiple sets of process condition categories are formed, with each category corresponding to a database record. Second, for each category, a physical simulation model of the wafer edge chamfering grinding process is established using finite element simulation software (such as ANSYS or ABAQUS). The model inputs intrinsic mechanical parameters of the wafer material, such as Young's modulus, Poisson's ratio, and fracture toughness, as well as tool parameters such as abrasive grain size and bond type of the diamond grinding wheel. The simulation simulates the material removal process, stress distribution, and temperature field of the wafer edge under different combinations of grinding parameters (wheel speed, feed rate, and grinding depth). The optimal grinding parameter combination for each process condition category is determined using a multi-objective optimization algorithm (such as the NSGA-II genetic algorithm) with the constraints of preventing edge micro-cracks and thermal damage, and the objective functions of achieving optimal chamfer geometric accuracy and surface quality. Then, the parameter combinations obtained from the simulation optimization are used as initial values ​​for small-batch verification experiments on an actual wafer reprocessing line. At least 30 wafers are processed for each process condition category. Based on the chamfer angle, chamfer width uniformity, edge roughness, and surface defect detection results after actual processing, the simulation parameters are corrected and fine-tuned, with the correction range not exceeding ±10% of the simulation values. Finally, the parameter combinations that pass the experimental verification are solidified into standard parameter templates, which are stored in a mapping database using wafer specifications, material, and damage level as composite indexes. With the continuous accumulation of process data, this database has dynamic update capabilities; newly verified superior process parameters can be periodically added to the database, continuously enriching its coverage. In actual processing, the matching processing parameter template is automatically retrieved from the mapping database based on the edge damage level defined in step 1 and the current wafer material and size information. The template pre-sets key parameters for each stage of rough grinding and fine grinding, including wheel grit size, wheel speed, feed rate, single-sided grinding amount, and processing time. Based on the parameters set in the template, two stages of chamfering are performed sequentially: rough grinding and fine grinding, to completely remove all damaged layers from the wafer edge.

[0050] Rough grinding uses diamond wheels as the grinding tool. The abrasive of the diamond wheel is made of synthetic high-temperature, high-pressure diamond particles, combined with a bronze-based metal binder and prepared through a hot-pressing sintering process. The grit size of the grinding wheel is selected from 800 mesh to 1200 mesh, as diamond wheels in this grit range have appropriate grinding efficiency and surface quality balance. The outer diameter and thickness of the grinding wheel are customized according to the wafer size and chamfering requirements, with a typical configuration of 150 mm outer diameter and 15 mm thickness.

[0051] During rough grinding, the grinding wheel speed is set to 3000 rpm to 4500 rpm, a range that ensures the diamond abrasive grains maintain optimal cutting performance. The rough grinding feed rate is set to 0.5 mm / s to 1.2 mm / s, with the selection of feed rate taking into account both grinding efficiency and machining quality requirements. The rough grinding depth per edge of the wafer is set to 3 μm to 18 μm, a range that allows for rapid removal of large areas of damage layers at the wafer edges, including chipping, deep scratches, and macroscopic cracks. The primary function of rough grinding is to efficiently remove the damaged layer, providing a uniform machining allowance for finish grinding.

[0052] Fine grinding employs finer diamond grinding wheels, with a grit size of 2000 to 3000 mesh. The finer grit results in better surface finish and dimensional accuracy. During fine grinding, the wheel speed is set to 4500 to 6000 rpm, an increase compared to rough grinding, to accommodate the cutting characteristics of the finer abrasive. The fine grinding feed rate is set to 0.2 mm / s to 0.5 mm / s, a decrease compared to rough grinding, to ensure precision and surface quality. The fine grinding allowance on each edge of the wafer is set to 1 μm to 3 μm. This allowance is sufficient to correct micro-undulations and contour errors left by rough grinding, eliminate micro-scratches generated during rough grinding, and reconstruct a standard chamfer profile.

[0053] Different grinding strategies are employed for wafers with different damage levels. For wafers with mild damage (edge ​​damage layer depth less than 5μm), due to the minor damage, only fine grinding is required to completely remove the damaged layer, eliminating the need for rough grinding. This maximizes the usable area of ​​the wafer and improves material utilization. For wafers with moderate damage (edge ​​damage layer depth ≥5μm and <15μm), two stages of processing are required: rough grinding to remove the main damaged areas, and fine grinding for precise positioning and surface treatment. For wafers with severe damage (edge ​​damage layer depth ≥15μm), due to the severity of the damage, the rough grinding time needs to be extended, and a supplementary grinding process is added between rough and fine grinding. The grinding parameters for the supplementary grinding process (including wheel grit size, rotation speed, feed rate, and single-sided removal amount) are also retrieved from the mapping database and configured in conjunction with the rough grinding parameters to ensure that all damaged layers are completely removed before fine grinding is performed.

[0054] For slightly damaged wafers, after retrieving the parameter template, the system automatically compares the amount of material removed on one side of the fine grinding in the template with the actual depth of the damaged layer detected on the wafer. If the amount of material removed is less than the depth of damage, the system automatically adjusts the fine grinding allowance to a value that is not lower than the depth of damage, or prompts the operator to confirm the adjustment to ensure that the damaged layer is completely removed.

[0055] During the chamfering process, a dedicated grinding coolant is continuously sprayed to reduce the temperature of the grinding area, remove grinding debris, and lubricate the grinding interface. The grinding coolant is a compound of alumina abrasive, grinding aids, and ultrapure water, with the following mass ratio: alumina abrasive 15% to 35%, grinding aids 1.9% to 3.3%, and the remainder ultrapure water. The alumina abrasive, as an auxiliary grinding medium, enhances the grinding effect and improves processing efficiency. The grinding aids contain surfactants, lubricants, rust inhibitors, and other components, which improve the wettability, lubricity, and stability of the coolant. The spray flow rate of the grinding coolant is set to 5 L / min to 8 L / min, and the coolant temperature is constantly controlled between 22°C and 26°C via a heat exchanger. The effective use of the constant-temperature coolant continuously removes heat during the grinding process, keeping the temperature rise at the wafer edge within acceptable limits and preventing thermal damage and stress.

[0056] After chamfering, the wafer edge forms a standard chamfer structure, with the chamfer angle controlled between 25° and 35°, and the chamfer width uniformity error controlled within ±0.03mm. These chamfering parameters take into account the wafer's mechanical strength, photolithography compatibility, and the convenience of subsequent processes.

[0057] In step 4, the edge fine polishing stage, the edge of the ground wafer is subjected to flexible polishing treatment to completely eliminate grinding residue and micro-uneven defects, and optimize the smoothness of the chamfered surface.

[0058] The flexible polishing system uses a non-woven polishing wheel as the polishing tool. The base of the non-woven polishing wheel is made of high-density polyester fiber formed by needle punching, which has soft and conformable properties and can form a good fit with the edge of the wafer. The surface of the non-woven wheel is loaded with silica polishing slurry. The silica abrasive particles in the polishing slurry have a particle size in the range of 10nm to 50nm, which belongs to nanoscale ultrafine abrasives.

[0059] During polishing, the polishing wheel speed is set to 2000 rpm to 3000 rpm. The rotation direction of the polishing wheel is coordinated with the rotation direction of the wafer to form a harmonious relative motion trajectory, ensuring the uniformity of the polishing effect. The polishing time is set to 2 to 4 minutes, with the specific time fine-tuned according to the actual condition of the wafer edge. During polishing, the polishing slurry supply system continuously sprays silica polishing slurry onto the polishing area. Precise control of the polishing slurry flow rate and spray position is crucial to ensuring the uniformity of polishing quality.

[0060] The main mechanism of flexible polishing is to gradually remove micro-cutting marks and surface undulations left from the grinding stage through the micro-cutting action of nano-sized abrasive grains combined with the abrasive retention and stress buffering function of the soft substrate of the non-woven wheel. After polishing, the roughness Ra of the wafer edge chamfer can be reduced to below 0.02μm, achieving a mirror-like finish. This significant improvement in edge smoothness not only improves the appearance quality of the wafer edge but, more importantly, eliminates the source of micro-defects, enhancing the reliability of the wafer in subsequent high-temperature processes.

[0061] In step 5, the stress relief treatment stage, the polished wafer is placed in a constant temperature and dust-free environment for constant temperature treatment to release the residual stress generated at the wafer edge during the grinding and polishing process.

[0062] The stress relief treatment system consists of a constant temperature and humidity control chamber, an air circulation and filtration system, a temperature sensor array, and a data acquisition and control system. The volume of the constant temperature and humidity control chamber is designed according to the wafer batch processing volume, and the chamber walls are constructed with high thermal insulation materials to reduce the impact of ambient temperature fluctuations on the processing effect. The air cleanliness level inside the chamber is maintained at Class 100 to ensure that the wafer edges are not contaminated by external particles during stress relief.

[0063] The isothermal treatment temperature was set between 45°C and 55°C. This temperature range was chosen based on the following technical considerations: firstly, this temperature accelerates the recovery process of dislocation movement within the wafer edge material, promoting the relaxation and release of residual stress; secondly, this temperature is far below the softening temperature of the wafer material, and will not negatively affect the wafer's crystal structure and mechanical properties. The treatment duration was set between 15 and 25 minutes, ensuring that heat energy is fully transferred to the wafer edge region, achieving sufficient stress relief.

[0064] A temperature sensor array is distributed across multiple locations within the cabin to monitor the uniformity of temperature distribution in real time. Based on sensor feedback, the data acquisition and control system automatically adjusts the heating power and air circulation rate to keep cabin temperature fluctuations within ±1℃. The air circulation and filtration system operates continuously to ensure even distribution of hot air within the cabin, preventing uneven stress release caused by localized temperature differences.

[0065] After stress relief treatment, residual stress at the wafer edge is effectively released, significantly improving the structural stability of the wafer edge. This ensures that the regenerated wafer maintains dimensional stability in subsequent high-temperature processes (such as diffusion, oxidation, annealing, etc.), avoiding wafer warping or edge crack propagation problems caused by residual stress release.

[0066] In step 6, the wafer is cleaned and dried using ultrapure water circulation, completing the entire process of wafer regeneration edge chamfering.

[0067] The cleaning process uses a mixture of dilute hydrofluoric acid and ultrapure water as the cleaning medium. The concentration of dilute hydrofluoric acid ranges from 0.5% to 2% (mass concentration), which effectively removes the microscopic oxide layer formed at the wafer edges during grinding and polishing without causing excessive corrosion to the wafer substrate. The cleaning method is immersion, with an immersion time set to 30 to 60 seconds. During immersion, the dilute hydrofluoric acid reacts chemically with the silicon oxide layer on the wafer edge surface to generate soluble fluorosilicates, thereby achieving precise removal of the oxide layer.

[0068] After chemical cleaning, a multi-stage ultrapure water rinse is performed to thoroughly remove residual hydrofluoric acid and reaction products. The rinsing process employs a combination of overflow rinsing and spray rinsing to ensure that all areas of the wafer surface are thoroughly cleaned. The resistivity of the ultrapure water is maintained above 18.2 MΩ·cm, and the dissolved oxygen and particulate content in the water are controlled at sub-ppb levels.

[0069] After cleaning, the wafers are rapidly dried using high-purity nitrogen. The drying process is conducted in a Class 100 cleanroom environment to prevent the introduction of new particulate contamination. Once drying is complete, the wafer edge chamfering process is finished.

[0070] After processing, the wafer chamfer angle is 25° to 35°, the chamfer width uniformity error is less than or equal to ±0.03mm, and there are no defects such as chipping, cracks, or scratches on the edges. The technical indicators of the regenerated wafer meet the stringent requirements for secondary processes of high-end semiconductor wafers.

[0071] The technical solution of the present invention will be further explained below with reference to specific application examples. Suppose that a batch of 200mm (8-inch) silicon wafers needs to be regenerated after completing one semiconductor manufacturing process. During use, the edge areas of this batch of wafers have suffered varying degrees of damage, requiring repair and regeneration through the edge chamfering process of the present invention.

[0072] First, the batch of wafers underwent preprocessing as described in step 1. Edge defects were detected on each wafer using visual inspection equipment to obtain edge damage data for each wafer. Based on the inspection results, the batch of wafers was classified into different damage levels: approximately 30% of the wafers were lightly damaged, with a damage depth between 3μm and 5μm; approximately 50% of the wafers were moderately damaged, with a damage depth between 8μm and 12μm; and approximately 20% of the wafers were severely damaged, with a damage depth between 16μm and 22μm.

[0073] Based on the damage level classification results, the system retrieves the corresponding parameter templates from a pre-established mapping database. For lightly damaged wafers, the template is set to directly proceed to the fine grinding process; for moderately damaged wafers, the template is set to a two-stage process of rough grinding followed by fine grinding; for heavily damaged wafers, the template is set to a three-stage process of rough grinding, supplementary grinding, and fine grinding. The processing parameters for each type of wafer strictly adhere to the parameter ranges in the aforementioned technical solution and are automatically configured to the processing equipment by the template.

[0074] Taking a severely damaged wafer as an example, the depth of the edge damage layer was measured to be 20 μm. First, the wafer underwent rough grinding using a 1000-mesh diamond wheel at a rotation speed of 4000 rpm, a feed rate of 0.8 mm / s, and a single-sided grinding depth of 15 μm. After rough grinding, a finishing grinding process was performed using the same parameters, with a single-sided finishing grinding depth of 5 μm. After finishing grinding, a finish grinding process was performed using a 2500-mesh diamond wheel at a rotation speed of 5500 rpm, a feed rate of 0.35 mm / s, and a single-sided finish grinding allowance of 2 μm. During the grinding process, a dedicated grinding coolant was continuously sprayed, and the coolant temperature was kept constant at 24℃.

[0075] After grinding, a flexible polishing process was performed at a polishing wheel speed of 2500 r / min for 3 minutes, resulting in an edge roughness of 0.015 μm. Following this, a constant-temperature stress relief treatment was conducted at 50℃ for 20 minutes. After stress relief, chemical cleaning was performed by immersion in 1% dilute hydrofluoric acid for 45 seconds, followed by ultrapure water circulation cleaning and nitrogen drying.

[0076] After processing, the wafer underwent quality inspection. The results showed that the chamfer angle was 30.5°, within the target range of 25° to 35°; the chamfer width uniformity error was ±0.018mm, meeting the accuracy requirement of ±0.03mm; the edge roughness was 0.015μm, better than the target value of 0.02μm; and there were no chipping, cracks, or scratches on the edges. After remanufacturing, the wafer's performance indicators met the standards for new wafers and it can be reused on the semiconductor manufacturing production line.

[0077] Example 2

[0078] To further illustrate the applicability and flexibility of the technical solution of this invention, the regeneration process of a 12-inch (300mm) silicon wafer is used as an example. This size of wafer is widely used in the field of high-end semiconductor manufacturing, and the precision requirements for its edge chamfering are even more stringent.

[0079] In the preprocessing stage (Step 1), the chamfering of 12-inch silicon wafers requires the use of higher-resolution visual inspection equipment for edge defect detection. This equipment needs a pixel resolution of at least 0.3 μm to meet the defect detection accuracy requirements of larger wafers. The inspection scan density is set to 1500 sampling points per mm to ensure comprehensive coverage of the wafer edge area.

[0080] In step 2, the wafer positioning and clamping stage, the positioning accuracy requirements are higher due to the larger wafer size. The vacuum adsorption system needs to achieve a vacuum level of -95kPa or higher to ensure stable adsorption of large wafers under high rotational speed conditions. The coaxiality control accuracy of the vision alignment system needs to be better than ±0.015mm, and the image processing algorithm of the vision system needs to be optimized and calibrated for the geometric features of 300mm wafers.

[0081] In the segmented differentiated chamfering grinding stage of step 3, the rough grinding of the 12-inch wafer uses diamond grinding wheels with a larger outer diameter, typically 200 mm. The grinding wheel speed can be increased to 5000 rpm to 6000 rpm to meet the efficiency requirements of larger machining sizes. The finish grinding uses ultrafine diamond grinding wheels with a grit size of 3000 mesh to ensure precise control of edge contour accuracy.

[0082] As a preferred embodiment, the edge chamfering parameters of the 12-inch wafer need to be more strictly controlled. The chamfering angle range is set to 28° to 32°, which can balance the edge exposure uniformity and mechanical strength requirements of the wafer in the photolithography process. The chamfering width uniformity error is controlled within ±0.02mm to meet the accuracy requirements of advanced processes.

[0083] Taking a moderately damaged 12-inch silicon wafer as an example, assuming the edge damage layer depth is 10μm, the processing flow is as follows: First, rough grinding is performed using a 1000-grit diamond wheel at a rotation speed of 5000 rpm, a feed rate of 0.6 mm / s, and a single-sided grinding depth of 7μm. After rough grinding, fine grinding is performed using a 3000-grit diamond wheel at a rotation speed of 5800 rpm, a feed rate of 0.25 mm / s, and a single-sided fine grinding allowance of 2μm. The parameter settings for subsequent polishing, stress relief, and chemical cleaning processes are consistent with those in Example 1.

[0084] The inspection results after processing showed that the chamfer angle was 30.2°, the chamfer width uniformity error was ±0.012mm, and the edge roughness was 0.012μm, all of which reached excellent levels. This example proves that the technical solution of the present invention can well meet the needs of reprocessing large-size wafers.

[0085] Example 3

[0086] This embodiment uses the regeneration process of a 6-inch (150mm) silicon wafer as an example. This size of wafer is mainly used in discrete devices, power semiconductors, sensors, and other fields. The requirements for its edge chamfering are different from those for 12-inch logic chip wafers, with a greater emphasis on processing efficiency and cost control.

[0087] In the pre-processing stage of edge chamfering for 6-inch wafers, the pixel resolution of the inspection equipment can be set to the 0.8μm level, meeting defect detection requirements while reducing equipment costs. The inspection scan density is set to 800 sampling points per mm, improving inspection efficiency while ensuring inspection integrity.

[0088] During the positioning and clamping stage, the configuration of the vacuum adsorption system can be simplified appropriately; a vacuum level of -85 kPa is sufficient to meet the stable fixing requirements of 6-inch wafers. The coaxiality control accuracy of the vision alignment system is set to ±0.025 mm, which matches the processing accuracy requirements of wafers of this size.

[0089] In the segmented differentiated chamfering grinding stage, rough grinding of 6-inch wafers can use diamond wheels with an outer diameter of 120mm, and the wheel speed can be set to 3500 rpm to 4500 rpm. Fine grinding uses diamond wheels with a grit size of 2000 to 2500 mesh, and the wheel speed can be set to 4500 rpm to 5500 rpm. Considering the material characteristics of 6-inch wafers, the optimization of grinding parameters must comprehensively consider both processing efficiency and edge quality requirements.

[0090] The chamfer angle of a 6-inch wafer can be set from 25° to 35°, and the chamfer width uniformity error can be controlled within ±0.03mm to meet the requirements. In the processing of slightly damaged wafers, the process can be further simplified, and fine grinding can be directly used, eliminating the rough grinding step, effectively improving processing efficiency and reducing grinding costs.

[0091] Taking a slightly damaged 6-inch silicon wafer as an example, assuming the edge damage layer depth is 4μm, due to the minor damage, it is directly subjected to fine grinding using a 2500-mesh diamond wheel at a speed of 5000 rpm and a feed rate of 0.4 mm / s. The single-sided fine grinding allowance is set to 5μm to ensure complete coverage of the 4μm damage layer depth. After fine grinding, a flexible polishing treatment is performed for 2 minutes. The subsequent stress relief treatment temperature is set at 48℃ for 15 minutes. Chemical cleaning involves immersion in dilute hydrofluoric acid for 30 seconds.

[0092] The inspection results after processing showed that the chamfer angle was 28.5°, the chamfer width uniformity error was ±0.022mm, and the edge roughness was 0.018μm. After regeneration, the wafer meets the requirements for discrete device manufacturing and can be reused on the production line. This example demonstrates that the technical solution of this invention has good adaptability and can achieve optimized processing results by adjusting parameters to meet the wafer regeneration needs of different sizes and application scenarios.

[0093] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. An edge chamfering process method in wafer regeneration, comprising the following steps: Step 1: Wafer pretreatment. Edge damage status is detected on the wafer to be regenerated. Based on the detection results, the edge damage level is classified. The wafer is then subjected to ultrasonic spray cleaning and drying. Step 2: Wafer positioning and clamping. The wafer is transferred to a precision chamfering station. Vacuum adsorption is used to fix the wafer on the station platform. A vision alignment system is used to calibrate the coaxiality between the wafer center and the chamfering wheel. Step 3: Segmented differentiated chamfering grinding. A mapping database covering various wafer specifications and edge damage levels is pre-established. This database stores gradient grinding parameter templates corresponding to each damage level, wafer material, and size. Based on the edge damage level and basic wafer information obtained in Step 1, matching parameter templates are retrieved from the mapping database. The wafer is subjected to two-stage chamfering processes: rough grinding and fine grinding, based on preset parameters in the template, to remove the damaged layer at the wafer edge. For wafers with severe damage, a supplementary grinding process is added between rough grinding and fine grinding. The supplementary grinding parameters are also stored in the mapping database, forming a three-stage processing of rough grinding, supplementary grinding, and fine grinding. Step 4: Fine edge polishing. The edges of the ground wafer are subjected to flexible polishing to eliminate residual grinding marks and microscopic unevenness defects. Step 5: Stress relief treatment. The polished wafer is placed in a constant temperature and dust-free environment for constant temperature treatment to release the residual stress generated at the wafer edge during the grinding and polishing process. Step 6: Cleaning and finishing. The entire wafer is chemically cleaned and dried to complete the wafer regeneration edge chamfering process.

2. The edge chamfering process method in wafer regeneration as described in claim 1, characterized in that, After the chamfering process is completed, the chamfering angle of the wafer edge is 25° to 35°, and the chamfer width uniformity error is ≤ ±0.03mm.

3. The edge chamfering process method in wafer regeneration as described in claim 1, characterized in that, The edge damage detection is performed using an appearance inspection device, which integrates an optical imaging system, a high-resolution image acquisition module, and a defect recognition algorithm module. The optical imaging system uses a dual illumination method with a coaxial light source and a ring light source. The pixel resolution of the high-resolution image acquisition module reaches a level of 0.5μm or higher. The defect recognition algorithm module is built based on an improved deep learning convolutional neural network. After transfer learning and fine-tuning training on positive and negative samples of wafer edge defect features, it can automatically classify and identify various defect types such as edge chipping, scratches, microcracks, and residual cutting marks on the wafer edge, with an accuracy rate exceeding a preset threshold.

4. The edge chamfering process method in wafer regeneration as described in claim 1, characterized in that, The edge damage levels are classified into three grades: Slightly damaged wafers have an edge damage layer depth of less than 5 μm, characterized by only minor scratches and no chipping or cracking; moderately damaged wafers have an edge damage layer depth greater than or equal to 5 μm and less than 15 μm, characterized by a small amount of shallow chipping and microcracks; and severely damaged wafers have an edge damage layer depth greater than or equal to 15 μm. The defects are characterized by obvious chipping, deep cracks and residual cutting marks.

5. The edge chamfering process method in wafer regeneration as described in claim 1, characterized in that, The wafer positioning and clamping are carried out in an ultra-clean working chamber with an environmental cleanliness level of 100. The wafer is fixed on the workstation platform by vacuum adsorption, and the vacuum adsorption system is provided with a negative pressure source by an oil-free dry vacuum pump. The vision alignment system consists of a high-precision industrial camera, a telecentric optical lens, an image processing workstation, and a motion control system. The image processing workstation has a built-in edge detection and circle center fitting algorithm module, which includes an image preprocessing unit, a sub-pixel edge extraction unit, and a robust circle center fitting unit. The image preprocessing unit performs grayscale correction, anisotropic filtering denoising, and contrast adaptive enhancement on the acquired wafer edge images to eliminate the influence of uneven lighting and sensor noise. The subpixel edge extraction unit employs subpixel edge localization technology based on interpolation. By calculating the gradient magnitude and direction, it performs quadratic curve fitting based on the pixel-level edge detection results, improving the edge localization accuracy to the subpixel level. The robust circle center fitting unit uses a weighted least squares circle fitting algorithm, assigning different weight coefficients to the extracted edge point set and eliminating outlier noise points through iterative calculation, ultimately outputting high-precision wafer center coordinates. The motion control system drives a linear motor to perform fine-tuning of the position based on the calculated coaxiality deviation value, keeping the coaxiality error within the allowable range.

6. The edge chamfering process method in wafer regeneration as described in claim 1, characterized in that, The rough grinding process uses a diamond grinding wheel as the grinding tool. The abrasive of the diamond grinding wheel is made of artificial high-temperature and high-pressure diamond particles, combined with a bronze-based metal binder and prepared by hot pressing and sintering. The grinding wheel grit size for rough grinding is 800 to 1200 mesh, the grinding wheel speed is set to 3000 rpm to 4500 rpm, the feed rate is set to 0.5 mm / s to 1.2 mm / s, and the rough grinding allowance for each edge of the wafer is set to 3 μm to 18 μm. The fine grinding process uses a diamond grinding wheel with a finer grit size. The grinding wheel grit size for fine grinding is 2000 to 3000 mesh, the grinding wheel speed is set to 4500 rpm to 6000 rpm, the feed rate is set to 0.2 mm / s to 0.5 mm / s, and the fine grinding allowance for each edge of the wafer is set to 1 μm to 3 μm.

7. The edge chamfering process method in wafer regeneration as described in claim 5, characterized in that, The grinding coolant is composed of alumina abrasive, grinding aid, and ultrapure water. The alumina abrasive serves as an auxiliary grinding medium, and the grinding aid contains surfactants, lubricants, and rust inhibitors. The temperature of the grinding coolant is constantly controlled by a heat exchanger, and the spray flow rate of the grinding coolant is adjusted according to the processing conditions.

8. The edge chamfering process method in wafer regeneration as described in claim 1, characterized in that, The flexible polishing process uses a non-woven polishing wheel as the polishing tool. The base of the non-woven polishing wheel is made of high-density polyester fiber through a needle punching process, which has the characteristics of being soft and conformable. The surface of the non-woven wheel is loaded with silica polishing slurry. The silica abrasive particles in the polishing slurry have a particle size in the nanometer range. During the polishing process, the speed of the polishing wheel and the direction of wafer rotation are coordinated to form a coordinated relative motion trajectory. After the polishing process, the roughness of the chamfered surface of the wafer edge is reduced to below the preset value.

9. The edge chamfering process method in wafer regeneration as described in claim 1, characterized in that, The stress relief treatment is carried out in a constant temperature and humidity control chamber, which consists of a chamber wall, an air circulation and filtration system, a temperature sensor array, and a data acquisition and control system. The chamber wall is constructed with a high thermal insulation material, and the air cleanliness level inside the chamber is maintained at Class 100. The air circulation and filtration system operates continuously to ensure uniform distribution of hot air inside the chamber. The temperature sensor array is distributed in multiple locations inside the chamber to monitor the uniformity of temperature distribution in real time. The data acquisition and control system automatically adjusts the heating power and air circulation rate based on the sensor feedback data.

10. The edge chamfering process method in wafer regeneration as described in claim 1, characterized in that, Differentiated grinding strategies are adopted based on the edge damage level: For wafers with mild damage, due to the minor damage, only fine grinding is required to completely remove the damaged layer, eliminating the need for rough grinding. Furthermore, the preset single-sided removal amount in fine grinding must be greater than or equal to the actual damaged layer depth detected by the wafer to ensure complete removal while maximizing the preservation of the wafer's usable area. For wafers with moderate damage, two stages of processing are required: rough grinding to remove the main damaged areas, and fine grinding for precise positioning and surface treatment. For wafers with severe damage, due to the severity of the damage, the rough grinding time needs to be extended, and a supplementary grinding process is added between rough and fine grinding. The supplementary grinding parameters are also retrieved from the mapping database and work in conjunction with the rough grinding parameters to ensure that all damaged layers are completely removed before fine grinding. After chamfering, the wafer edges form a standard chamfer structure, with the chamfer angle range and chamfer width uniformity error controlled within a preset range.

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