Semiconductor structure and method of manufacturing the same

Abstract

The method includes providing a structure. The structure includes: an active region including a source / drain region and a channel region; and a gate structure located above the channel region. The source / drain region includes a first layer adjacent to a sidewall of the channel region and a second layer distal to the sidewall. The active region extends longitudinally along a first direction, and the gate structure extends longitudinally along a second direction. The method further includes depositing a low-k dielectric layer and a dielectric layer below the active region, patterning the dielectric layer and the low-k dielectric layer to form an initial trench therein, performing an etching process to extend the initial trench to form a trench exposing the source / drain region, and forming back-side source / drain contacts in the trench. In the initial trench, the exposed sidewalls of the low-k dielectric layer are laterally recessed from the exposed sidewalls of the dielectric layer. Embodiments of this disclosure also relate to semiconductor structures and methods of fabricating the same.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs.

[0003] This scaling down also increases the complexity of handling and manufacturing ICs, and advancements in IC handling and manufacturing are needed to achieve these progresses. For example, as device size shrinks, packaging contacts and reducing their resistance become challenging. Therefore, while existing structures and methods are generally sufficient for their intended purposes, they are not entirely satisfactory in every aspect. Summary of the Invention

[0004] One embodiment of this application provides a method for manufacturing a semiconductor structure, comprising: providing a structure including: a substrate; a channel region disposed above the substrate; a source / drain structure disposed above the substrate and connected to the channel region, wherein the source / drain structure includes a first layer adjacent to the sidewall of the channel region and a second layer away from the sidewall of the channel region; a contact etch stop layer (CESL) located above the source / drain structure; an interlayer dielectric (ILD) layer located above the contact etch stop layer; and a metal gate structure disposed above the channel region. The method further includes: flipping the structure; depositing a first dielectric layer over the substrate; depositing a second dielectric layer over the first dielectric layer; performing a first etching process to form a trench in the first dielectric layer and the second dielectric layer; performing a second etching process to extend the trench through the substrate and into the source / drain structure; and forming a contact member in the trench, wherein, in a cross-sectional view, a first interface between the first dielectric layer and the contact member has a first angle with a vertical line, and a second interface between the substrate and the contact member has a second angle with the vertical line, wherein the first angle is greater than the second angle.

[0005] Another embodiment of this application provides a method for manufacturing a semiconductor structure, comprising: providing a structure including an active region and a gate structure, the active region including a source / drain region and a channel region, the gate structure disposed above the channel region, wherein the source / drain region includes a first layer adjacent to the sidewall of the channel region and a second layer away from the sidewall of the channel region, wherein, in a top view, the active region extends longitudinally along a first direction, and the gate structure extends longitudinally along a second direction different from the first direction; depositing a low-k dielectric layer below the active region; depositing a dielectric layer below the low-k dielectric layer; patterning the dielectric layer and the low-k dielectric layer from the back side of the structure to form an initial trench in the dielectric layer and the low-k dielectric layer; performing an etching process to extend the initial trench to form a trench exposing the source / drain region; and forming a back-side source / drain contact in the trench, wherein, in the initial trench, the exposed sidewall of the low-k dielectric layer is laterally recessed from the exposed sidewall of the dielectric layer.

[0006] An embodiment of this application provides a semiconductor structure comprising: a substrate; a channel region disposed above the substrate; a source / drain component disposed above the substrate and connected to the channel region; a metal gate structure disposed above the channel region; a contact etch stop layer (CESL) disposed above the source / drain component; an interlayer dielectric (ILD) layer disposed above the contact etch stop layer; a first contact component extending through the interlayer dielectric layer to be electrically coupled to the source / drain component; a dielectric layer disposed below the substrate; and a second contact component extending through the dielectric layer and the substrate, and electrically connected to the source / drain component, wherein the second contact component includes a first portion embedded in the substrate and a second portion embedded in the dielectric layer, wherein the first portion has a first sidewall having a first slope, and the second portion has a second sidewall having a second slope less than the first slope. Attached Figure Description

[0007] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart of a method for manufacturing a semiconductor structure according to various aspects of this disclosure is shown.

[0009] Figure 2The following are shown in relation to various aspects of this disclosure. Figure 1 Partial top view of exemplary structures at various manufacturing stages associated with the method.

[0010] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 11 , Figure 12 , Figure 13A , Figure 13B , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17 , Figure 18A , Figure 18B , Figure 19 and Figure 20 The following are shown in relation to various aspects of this disclosure. Figure 1 Partial cross-sectional views of exemplary structures at various manufacturing stages associated with the method. Detailed Implementation

[0011] The following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components such that the first and second components are not in direct contact.

[0012] Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Additionally, in the following disclosure, a component formed on, connected to, and / or coupled to another component may include embodiments where the components are formed in direct contact, and may also include embodiments where additional components may be formed between the components so that the components are not in direct contact. Furthermore, for the convenience of describing the relationship between one component and another, spatially relative terms are used, such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.). Spatially relative terms are intended to cover different orientations of devices including components. Also, when numerical values ​​or ranges of values ​​are described using terms such as “about,” “approximately,” etc., these terms are intended to cover values ​​within a reasonable range, taking into account the variations inherent during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics associated with that value, the value or range of values ​​covers a reasonable range including the described value, such as within + / - 10% of the described value. For instance, a material layer with a thickness of “about 5 nm” can cover dimensions ranging from 4.25 nm to 5.75 nm, where a manufacturing tolerance of + / - 15% is known to those skilled in the art to be associated with the deposited material layer. Other ranges known to those skilled in the art are possible and may depend on the process.

[0013] As integrated circuit (IC) technology advances to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or portion thereof disposed above more than one side of the channel region. FinFETs and gate-all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. A FinFET has a raised channel enclosed by a gate on more than one side (e.g., the gate encloses the top and sidewalls of a “fin” of semiconductor material extending from the substrate). A gate-all-around (GAA) transistor has a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also provides alternative names for GAA transistors, such as nanosheet transistors or nanowire transistors.

[0014] Traditionally, source / drain and gate contacts of transistors on a substrate connect the source / drain components of the transistor to an interconnect structure above the front side of the substrate. As IC device dimensions shrink, the close proximity of the source / drain and gate contacts can reduce the process window used to form these contacts and potentially increase parasitic capacitance between them. Moving some contacts and power lines to the back side of the structure is a solution to alleviate contact congestion. However, as IC device dimensions shrink, reducing the resistance of these back-side routing components becomes challenging. Therefore, while existing structures and methods are generally sufficient for their intended purposes, they are not entirely satisfactory in every respect.

[0015] This disclosure generally relates to semiconductor structures and methods of fabricating semiconductor structures. More specifically, this disclosure relates to forming semiconductor structures with source / drain contacts having widened heads. In some embodiments, the methods disclosed herein include providing a structure including a substrate, a transistor over the substrate, and front-side contacts and interconnect structures over the transistor. The method also includes flipping the structure, depositing a first dielectric layer over the substrate, depositing a second dielectric layer over the first dielectric layer, and patterning the first and second dielectric layers to form a trench that overlaps with the source / drain components of the transistor in a top view. The first and second dielectric layers may have different compositions and different etch rates in the patterning process, such that the first dielectric layer is etched laterally more than the second dielectric layer in the patterning process. The method also includes performing an etching process to extend the trench through the substrate and expose the source / drain components, forming contacts in the trench, and performing a planarization process to remove portions of the contacts in the second and second dielectric layers, thereby forming back-side source / drain contacts with widened heads in the first dielectric layer. Widening the head reduces the resistance of the source / drain contacts on the back side, thereby increasing the current and velocity of the structure. Therefore, the overall performance of the structure can be improved.

[0016] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. The following is in conjunction with... Figures 2 to 20 Description method 100. Figure 2 It shows according to Figure 1 A partial top view of structure 200 at different manufacturing stages of an embodiment of method 100. Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 12 , Figure 15 and Figure 19 It shows according to Figure 1Along different manufacturing stages of embodiments of method 100 Figure 2 A partial cross-sectional view of structure 200 with line A-A' in the figure. Figure 4 , Figure 6 , Figure 8 , Figure 11 , Figure 14 , Figure 17 and Figure 20 It shows according to Figure 1 Along different manufacturing stages of embodiments of method 100 Figure 2 A partial cross-sectional view of structure 200 with line B-B' in the figure. Figures 10A to 10B , Figures 13A to 13B , Figures 16A to 16B and Figures 18A to 18B They are Figure 9 , Figure 12 , Figure 15 and Figure 17 An enlarged view of a portion of structure 200. Method 100 is merely an example and is not intended to limit this disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some of the described steps may be replaced, eliminated, or rearranged for additional embodiments of method 100. For simplicity, not all steps are described in detail herein. Because structure 200 will be fabricated as a semiconductor structure, structure 200 may be referred to herein as semiconductor structure 200 or semiconductor device 200, depending on the context. To avoid ambiguity, Figures 2 to 20 The X, Y, and Z directions are perpendicular to each other and are used consistently throughout this disclosure. In this disclosure, unless otherwise specified, the same reference numerals denote the same parts. That is, the material properties of the various numbered elements described in association with a method or drawing, and their comparisons, should be applied to the same numbered elements described in association with different methods or different drawings.

[0017] refer to Figures 1 to 4 Method 100 includes a frame 102 in which structure 200 is formed or provided. (See reference) Figure 2Structure 200 includes a plurality of active regions 212 longitudinally oriented along the X direction and one or more gate stacks 240 longitudinally oriented along the Y direction. The active regions for a transistor refer to the source region, drain region, and channel region below the gate structure of the transistor. The gate stack 240 is disposed above the active regions 212. A transistor is formed at the intersection of the active regions 212 and the gate stack 240. In some embodiments, the active regions 212 include elongated nanostructures (also referred to as channel members or channel layers) vertically stacked in a channel region 212C (described below) defined in and above a semiconductor substrate 204 (described below) of the active regions 212. The semiconductor substrate 204 protrudes upward from a substrate 202 (described below). In some embodiments, portions of the active regions 212 not covered by the gate stack 240 serve as source / drain regions 212SD (described below). Source / drain components are formed in a source / drain region 212SD defined in the active region 212 and above the semiconductor substrate 204. The source / drain components are adjacent to two opposite ends of the nanostructure.

[0018] refer to Figure 3 and Figure 4 Structure 200 includes a substrate 202 on its back side. In some embodiments, substrate 202 is a bulk silicon substrate (i.e., including bulk single-crystal silicon). In various embodiments, substrate 202 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In alternative embodiments, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In embodiments, substrate 202 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions may be formed in or on substrate 202. Depending on design requirements, the doped regions may be doped with n-type dopants (such as phosphorus or arsenic) and / or p-type dopants (such as boron). The doped region can be formed directly on the substrate 202 in the form of a p-well structure, an n-well structure, a double-well structure, or using a bump structure. The doped region can be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0019] In an embodiment, structure 200 includes an active region 212 located above substrate 202. Each active region 212 includes a semiconductor substrate 204 protruding from substrate 202 and a stack of nanostructures 208 vertically stacked and suspended above semiconductor substrate 204. Semiconductor substrate 204 may have the same composition as substrate 202. In an embodiment, semiconductor substrate 204 includes silicon, silicon-germanium, germanium, or other suitable semiconductors and may be doped with n-type or p-type dopants. The active regions 212 can be patterned by any suitable method. For example, the active regions 212 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as masking elements for patterning the active regions 212. For example, the masking elements can be used to etch grooves in a semiconductor layer above or within substrate 202, leaving the active regions 212 on substrate 202. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etching process can employ oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasmas and / or combinations thereof. For example, a wet etching process may include etching with dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH); or other suitable wet etchants. Many other embodiments of the method for forming the active region 212 may be suitable.

[0020] Nanostructure 208 in the stack connects the two source / drain structures 214 and serves as the channel layer for the GAA transistor. Therefore, nanostructure 208 can also be referred to as channel layer 208. Nanostructure 208 may include a semiconductor material suitable for the transistor channel, such as silicon, silicon germanium, or other semiconductor materials. In various embodiments, nanostructure 208 may be in the shape of a rod, strip, sheet, or other shape. In embodiments, nanostructure 208 is initially part of a stack of semiconductor layers comprising alternating layers of nanostructure 208 and other sacrificial semiconductor layers. The sacrificial semiconductor layers and nanostructure 208 comprise different material compositions (such as different semiconductor materials, different atomic percentages of components, and / or different weight percentages of components) to achieve etch selectivity. During the gate replacement process forming gate stack 240, the sacrificial semiconductor layers are selectively removed, leaving nanostructure 208 suspended above semiconductor substrate 204. It should be noted that in the illustrated embodiment, three (3) nanostructures 208 are stacked vertically; this is for illustrative purposes only and is not intended to limit the specific references in the claims. It is understood that any number of nanostructures can be formed depending on the device performance requirements. In some embodiments, the number of vertically stacked nanostructures 208 is between 2 and 10.

[0021] In this embodiment, the structure 200 also includes isolation components 218 formed around each active region 212 (such as...). Figure 4 As shown), to isolate two adjacent active regions 212. The isolation component 218 may also be referred to as a shallow trench isolation (STI) component and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof and / or other suitable materials.

[0022] In some embodiments, structure 200 includes a fin-cut structure 220 located above substrate 202 (e.g., Figure 3(As shown). The fin-cut structure 220 separates an active region 212 from another active region 212 aligned with the first active region 212 along the X direction. In the depicted embodiment, the fin-cut structure 220 contacts the channel layer 208. The fin-cut structure 220 can be formed using various different processes. In an example process, fin-cut trenches are formed along the Y direction to segment one or more active regions 212, followed by processes such as depositing dielectric material and performing chemical mechanical polishing (CMP). In some embodiments, each fin-cut structure 220 includes multiple dielectric layers. The fin-cut structure 220 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbide, oxides formed from TEOS, PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, degel, aerogel, amorphous fluorinated carbon, parylene, BCB, polyimide, other low-k dielectric materials, or combinations thereof.

[0023] In some embodiments, structure 200 includes source / drain structures 214 formed in and / or above the source / drain regions of active region 212, each source / drain structure 214 disposed adjacent to gate stack 240. Depending on the context, source / drain structures 214 may individually or collectively refer to a source or a drain. Source / drain structures 214 may be p-type source / drain structures 214P or n-type source / drain structures 214N. Source / drain structures 214 can be formed by any suitable technique, such as an etching process followed by one or more epitaxial growth processes. In one example, one or more etching processes are performed to remove portions of active region 212 to form source / drain trenches (not shown) in source / drain regions 212SD. Cleaning processes may be performed to clean the source / drain trenches with a hydrofluoric acid (HF) solution or other suitable solutions.

[0024] In some embodiments, the source / drain structure 214 includes an interposer layer (e.g., 214-1 and / or 214-2) located at the bottom of the source / drain trench, and source / drain components (also referred to as epitaxial source / drain components) located above the interposer layer and connected to the adjacent channel layer 208. The interposer layer may include a separator layer 214-1, a bottom layer 214-2, or both. The formation of the interposer layer is optional, and the interposer layer may not be present in the final structure. The separator layer 214-1 may include the same or different semiconductor material as the substrate 202 and may be formed by an epitaxial growth process. In some embodiments, the separator layer 214-1 is dopant-free, for example, no intentional doping is performed during the epitaxial growth process. The separator layer 214-1 may have a thickness of about 1 nm to about 30 nm (e.g., along the Z direction). The bottom layer 214-2 may be formed above the separator layer 214-1 or in the semiconductor substrate 204 (when the separator layer 214-1 is not formed). The bottom layer 214-2 may have a thickness of about 1 nm to about 5 nm (e.g., along the Z direction). In some embodiments, the bottom layer 214-2 is formed of an oxygen-free dielectric material, such as a nitride (e.g., silicon nitride). The bottom layer 214-2 may be formed by any suitable method, such as depositing a silicon nitride-containing chlorine layer in the source / drain region 212SD, and etching back (e.g., by a dry etching process) excess portions of the silicon nitride-containing chlorine layer. In some other embodiments, the bottom layer 214-2 includes a semiconductor layer (e.g., Si) doped with a dopant (e.g., boron). In such embodiments, the bottom layer 214-2 may be formed by an epitaxial growth process. The epitaxial source / drain components above the interposer may include multiple epitaxial layers, such as a first layer 214-3 on the sidewall of the channel layer 208 and a second layer 214-4 located above the first layer 214-3 and spaced apart from the sidewall of the channel layer 208. One or more epitaxial growth processes are performed to grow the epitaxial layers (e.g., 214-3 and 214-4). Each source / drain structure 214 may be adapted to form a p-type device or optionally an n-type device. The p-type source / drain structure 214P of a p-type transistor may include one or more epitaxial layers (e.g., 214-3 and 214-4) of silicon-germanium (epi-SiGe) doped with p-type dopants (such as boron, germanium, indium, and / or other p-type dopants). The n-type source / drain structure 214N of an n-type transistor may include one or more epitaxial layers (e.g., 214-3 and 214-4) of silicon (epi-Si) or silicon-carbon (epi-SiC) doped with n-type dopants (such as arsenic, phosphorus, and / or other n-type dopants). The dopant concentrations in the one or more epitaxial layers may be different. For example, the dopant concentration in the second layer 214-4 may be higher than the dopant concentration in the first layer 214-3.

[0025] In some embodiments, structure 200 further includes an internal spacer 216 disposed between the source / drain structure 214 and adjacent gate stack 240. In some embodiments, the internal spacer 216 comprises a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride). In some embodiments, the internal spacer 216 comprises a low-k dielectric material, such as those described herein. The internal spacer 216 can be formed by deposition and etching processes. For example, after etching the source / drain trenches and before forming the source / drain structure 214, an etching process can be used to partially recess the sacrificial semiconductor layer between adjacent channel layers 208 to form a gap perpendicularly located between adjacent channel layers 208. Then, one or more dielectric materials (e.g., using CVD or ALD) are deposited to fill the gap. Another etching process is performed to remove the dielectric material outside the gap, thereby forming the internal spacer 216.

[0026] In some embodiments, structure 200 includes a gate stack 240 located between two source / drain structures 214, the gate stack 240 being disposed over and enclosing each channel layer 208. Reference Figure 3 The gate stack 240 may include an interface layer 222 formed on the surface of the channel layer 208 adjacent to the gate stack 240, a high-k dielectric layer 224 formed above the interface layer 222, and a gate electrode layer formed above the high-k dielectric layer 224. The interface layer 222 may include silicon dioxide, silicon oxynitride, or other suitable materials. The interface layer 222 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer 224 may include high-k dielectric materials such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials with a high dielectric constant, for example, greater than that of silicon oxide (k≈3.9). The high-k dielectric layer 224 can be formed by ALD, CVD, metal-organic CVD (MOCVD), PVD, thermal oxidation, and / or other suitable methods. In some embodiments, the gate electrode layer includes a work function layer 226 as an n-type or p-type work function layer and a metal filler layer 228 located above the work function layer 226. For example, the n-type work function layer may include a metal with a sufficiently low effective work function, and the p-type work function layer may include a metal with a sufficiently large effective work function. For example, the n-type work function layer may include Ta, titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum oxide (TiAlO), TiAlN, or combinations thereof. For example, the p-type work function layer may include TiN, TaN, WN, or combinations thereof. In some embodiments, work function layer 226 may include a multilayer structure, such as a first work function layer and a second work function layer (not shown). For example, the first work function layer may include metals such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof, and the second work function layer may include metals such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. In embodiments, the metal filler layer 228 includes aluminum, tungsten, cobalt, copper, and / or other suitable materials. In some embodiments, the metal filler layer 228 disposed above the p-type work function layer (also referred to as metal filler layer 228p) is a p-type metal filler layer. In some embodiments, the metal filler layer 228 (also referred to as metal filler layer 228n) disposed above the n-type function layer is an n-type metal filler layer. In some other embodiments, metal filler layers 228p and 228n are made of the same material. The gate electrode layer can be formed by CVD, PVD, plating and / or other suitable processes. Because the gate stack 240 includes a high-k dielectric layer and a metal layer, it is also referred to as a high-k metal gate.

[0027] In some embodiments, the gate stack 240 is formed after fabricating other components of structure 200 (e.g., source / drain structure 214). This process, commonly referred to as a gate replacement process, includes forming a dummy gate structure (not shown) as a placeholder for the gate stack 240, forming the source / drain structure 214, forming a first-level contact etch stop layer (CESL) and a first-level interlayer dielectric (ILD) layer (described below) over the source / drain structure 214, planarizing structure 200, for example, to expose the top surface of the dummy gate structure, removing the dummy gate structure to form a trench exposing the channel region 212C of the active region 212, removing the sacrificial semiconductor layer for channel release, and forming the gate stack 240 in the trench and around the channel layer 208 to complete the gate replacement process. In some embodiments, the gate stack 240 is partially recessed, and a dielectric capping layer may be formed on the recessed gate stack 240.

[0028] In an embodiment, structure 200 further includes a gate spacer 232 disposed on the sidewall of gate stack 240. Gate spacer 232 may include a dielectric material, such as an oxygen-containing material (e.g., silicon oxide, silicon carbide, aluminum oxide, aluminum oxynitride, hafnium oxide, titanium oxide, aluminum zirconium oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, silicon carbonitride, etc.), a nitrogen-containing material (e.g., tantalum carbonitride, silicon nitride (SiN), zirconium nitride, silicon carbonitride, etc.), a silicon-containing material (e.g., hafnium silicide, silicon, zirconium silicide, etc.), other suitable materials, or combinations thereof. As shown, gate spacer 232 may be a single-layer or multi-layer structure. It should be noted that the composition of gate spacer 232 differs from the composition of the surrounding dielectric components (e.g., CESL and ILD layers), allowing for etch selectivity between gate spacer 232 and the surrounding dielectric components during subsequent etching processes. In an embodiment, gate spacer 232 comprises SiN. The gate spacer 232 can be formed by first depositing a blanket layer of spacer material over structure 200, and then performing an anisotropic etching process to remove part of the spacer material to form the gate spacer 232. For example... Figure 4 As shown, after the source / drain recess is formed, a portion of the gate spacer 232 can remain in the source / drain region 212SD.

[0029] In some embodiments, structure 200 includes a first-level CESL 234 disposed above source / drain structure 214 and a first-level ILD layer 236 disposed above the first-level CESL 234. The first-level CESL 234 may include silicon nitride, silicon oxynitride, silicon nitride having oxygen or carbon elements, other suitable materials, or combinations thereof, and may be formed by CVD, PVD, ALD, other suitable methods, or combinations thereof. The first-level ILD layer 236 may include dielectric materials such as tetraethyl orthosilicate (TEOS), silicon oxide, low-k dielectric materials, doped silicon oxide (such as borosilicate glass (BPSG), phosphosilicate glass (PSG), FSG, boron-doped silicate glass (BSG)), other suitable dielectric materials, or combinations thereof. The first-level ILD layer 236 may include a multilayer structure having multiple dielectric materials and may be formed by deposition processes such as, for example, CVD, flowable CVD (FCVD), spin-on glass (SOG), other suitable methods, or combinations thereof. The first ILD layer 236 can be deposited after the deposition of the first CESL 234.

[0030] In some embodiments, structure 200 further includes a second-level CESL 238 disposed above the first-level ILD layer 236, the fin-cut structure 220, the gate stack 240, and the gate spacer 232. In some embodiments, structure 200 further includes a second-level ILD layer 242 formed above the second-level CESL 238. The second-level CESL 238 may include components similar to the first-level CESL 234 and may be formed using methods similar to those used for the first-level CESL 234. The second-level ILD layer 242 may include components similar to the first-level ILD layer 236 and may be formed using methods similar to those used for the first-level ILD layer 236.

[0031] In some embodiments, structure 200 further includes a front source / drain contact 244 located above and electrically connected to the source / drain structure 214. The front source / drain contact 244 may extend through the first-level CESL 234, the first-level ILD layer 236, the second-level CESL 238, and the second-level ILD layer 242. In some embodiments, structure 200 further includes a silicide component 246 located between the front source / drain contact 244 and the corresponding source / drain structure 214. The silicide component 246 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In an embodiment, the front source / drain contact 244 includes a conductive barrier layer and a metal filler layer above the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal filler layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted from the front source / drain contact 244. The front source / drain contact 244 may connect multiple source / drain structures 214 and is referred to in some cases as a long contact. As shown in the figure, the structure 200 may also include a dielectric pad 252 located on the sidewall of the front source / drain contact 244 and a dielectric component 254 located below the front source / drain contact 244.

[0032] In some embodiments, structure 200 further includes a dielectric structure 250. The dielectric structure 250 may be disposed above the second-level ILD layer 242, the front source / drain contact 244, and the dielectric pad 252. In some embodiments, the dielectric structure 250 includes multiple dielectric layers (e.g., 264-0, 264-1, 263-2, 264-2) and multiple CESLs (e.g., 262-0, 262-1, 262-2). CESLs may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable materials; and may be formed by CVD, PVD, ALD, or other suitable methods. The dielectric layer may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide (such as borosilicate glass (BPSG), fluoride-doped silicon glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The dielectric layer can be formed by PECVD (plasma-enhanced CVD), FCVD (flowable CVD), or other suitable methods.

[0033] In some embodiments, structure 200 further includes a source / drain via 260. The source / drain via 260 may be embedded in the dielectric structure 250 and connect the front source / drain contact 244 to the metal line above it (described below). The source / drain via 260 may comprise a material similar to the front source / drain contact 244 and may be formed similarly to the front source / drain contact 244.

[0034] In some embodiments, structure 200 further includes conductive components embedded in dielectric structure 250. The conductive components and dielectric structure 250 may be collectively referred to as a multilayer interconnect structure (MLI). Conductive components may include metal lines, metal vias, etc. Conductive components may include conductive materials, such as metals or metal alloys. The conductive components electrically connect various devices and / or components of structure 200 (e.g., source / drain structure 214, gate stack 240) such that the various devices and / or components can operate according to the design requirements of structure 200. MLI may include one or more interconnect layers. In the depicted embodiments, MLI includes a metal zero interconnect layer (M0 level) (e.g., a layer including metal line 266) and a metal one interconnect layer (M1 level) (e.g., a layer including metal line 268). In embodiments, the M0 metal line is electrically connected to the M1 metal line. Although not shown, MLI may also include additional metal interconnect layers. Each of the M0 level, M1 level, ... and Mx levels may be referred to as a metal level, where x is an integer. Metal lines formed at the M0 level may be referred to as M0 metal lines. Similarly, vias or metal lines formed at the M1, ..., and Mx levels can be referred to as M1 metal lines, ..., and Mx metal lines, respectively. This disclosure contemplates that the MLI has more or fewer interconnect layers and / or levels; for example, the total number N of the N interconnect layers (levels) of the MLI is an integer from 1 to 10. As described above, each level of the MLI includes conductive components (e.g., metal lines, metal vias) disposed in one or more dielectric layers and CESL. In some embodiments, conductive components are simultaneously formed at the same level of the MLI (such as the M0 level). In some embodiments, conductive components located at the same level of the MLI have top surfaces that are substantially flat to each other and / or bottom surfaces that are substantially flat to each other.

[0035] refer to Figure 1 and Figures 5 to 6 Method 100 includes a frame 104 in which the structure 200 is flipped. A carrier substrate (not shown) may be bonded and / or attached to the front side FS of the structure 200 and flipped together with the structure 200 such that the back side BS of the structure 200 faces upward and the front side FS of the structure 200 faces downward.

[0036] Still referencing Figure 1 and Figures 5 to 6Method 100 includes block 106, wherein structure 200 is thinned from the back side BS. A thinning process can be performed to reduce the thickness of substrate 202 (e.g., along the Z direction) to a range of about 10 nm to about 50 nm. The thinning process is applied to the back side BS of structure 200. In some embodiments, after the thinning process, an extension of substrate 202 (i.e., semiconductor substrate 204) is retained. The thinning process can be a polishing process, a planarization process (e.g., CMP), an etching process, other suitable processes, or a combination thereof. In some embodiments, the thinning process stops upon reaching isolation member 218. In some embodiments, the thinning process can reduce the thickness of isolation member 218 (e.g., along the Z direction). The thickness of isolation member 218 can be about 5 nm to about 50 nm.

[0037] Still referencing Figure 1 and Figures 5 to 6 Method 100 includes block 108, wherein a first dielectric layer 270 is deposited over the back side BS of structure 200, and a second dielectric layer 272 is deposited over the first dielectric layer 270.

[0038] The first dielectric layer 270 may include a low-k dielectric material. The first dielectric layer 270 may include SiN, SiCN, SiC, or combinations thereof. In some embodiments, the first dielectric layer 270 includes about 40% to about 50% silicon, about 15% to about 40% carbon, and about 20% to about 45% nitrogen. In some embodiments, the first dielectric layer 270 and the fin-cut structure 220 have different compositions. In some other embodiments, the first dielectric layer 270 includes the same composition as the fin-cut structure 220 and may be incorporated with the fin-cut structure 220. Forming the first dielectric layer 270 may include making a low-k dielectric material... x H y Si z A gas containing ammonia (NH3) flows above structure 200, where x is about 1 to about 6, y is about 6 to about 20, and z is about 1 to about 3. In some embodiments, the gas includes C3H 10Si (trimethylsilane) and NH3. Forming the first dielectric layer 270 may include deposition processes such as, for example, chemical vapor deposition (CVD), flowable CVD (FCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-coated glass (SOG), other suitable methods, or combinations thereof. The first dielectric layer 270 may have a thickness of about 1 nm to about 30 nm along the Z direction, optionally about 1 nm to about 15 nm. In some embodiments, the first dielectric layer 270 has a dielectric constant of less than about 6, optionally about 3 to about 6, optionally about 3 to about 5. In some embodiments, the first dielectric layer 270 has a reduced breakdown voltage. By having the first dielectric layer, leakage between the back-side source / drain contacts (described) and nearby components can be avoided or reduced.

[0039] The second dielectric layer 272 may include a dielectric material. The second dielectric layer 272 may include oxides, nitrides, carbides, or combinations thereof. Examples of dielectric materials may include silicon oxide, SiCO, SiN, SiCN, and aluminum oxide (e.g., Al2O3). In some embodiments, the second dielectric layer 272 includes an oxide (e.g., silicon oxide). The second dielectric layer 272 and the first dielectric layer 270 may have different compositions. The second dielectric layer 272 may have a smaller dielectric constant than the first dielectric layer 270. The second dielectric layer 272 may have a greater thickness along the Z-direction than the first dielectric layer 270. The second dielectric layer 272 may have a thickness along the Z-direction of about 10 nm to about 100 nm. The second dielectric layer 272 may be formed using suitable deposition processes, such as those described above for forming the first dielectric layer 270.

[0040] Still referencing Figure 1 and Figures 5 to 6 Method 100 includes block 110, wherein a hard mask 275 is formed over a second dielectric layer 272. The hard mask 275 may include hard mask layers 274 and 276. Hard mask layer 274 is disposed on the second dielectric layer 272, and hard mask layer 276 is disposed on hard mask layer 274. The thickness of hard mask layer 276 may be less than the thickness of hard mask layer 274. Hard mask layers 274 and 276 may be formed by CVD, ALD, other suitable processes, or combinations thereof. Hard mask layers 274 and 276 may be formed by the same type of deposition process or different types of deposition processes. The composition of hard mask layer 274 may differ from the composition of hard mask layer 276. In some embodiments, each of hard mask layers 274 and 276 includes silicon, oxygen, nitrogen, carbon, or combinations thereof. For example, hard mask layer 274 may be an organic layer (e.g., an organic photoresist layer comprising C, H and O), and hard mask layer 276 may be an organic silicon layer (e.g., comprising C, H, O and Si).

[0041] refer to Figure 1 and Figures 7 to 8 Method 100 includes block 112, in which a hard mask 275, a second dielectric layer 272, and a first dielectric layer 270 are patterned to form a trench 280. The trench 280 exposes a semiconductor substrate 204 that overlaps with a source / drain structure 214 in a top view. Operations at block 112 may include forming a patterned photoresist layer 278 over the hard mask 275, and using the patterned photoresist layer 278 as an etch mask to etch the hard mask 275, the second dielectric layer 272, and the first dielectric layer 270.

[0042] Patterning can include photolithography and etching processes 279. In an example process, a photoresist layer can be blanket-deposited over structure 200, including over a hard mask 275. The photoresist layer is then exposed to radiation passing through or reflected from the mask, baked in a post-baking process, and developed in a developer solution to form a patterned photoresist layer 278, such as... Figures 7 to 8 As shown. In this illustrated embodiment, the patterned photoresist layer 278 has an opening directly located on the selected source / drain structure 214. Then, using the patterned photoresist layer 278 as an etching mask, an etching process 279 is performed to etch the hard mask 275, the second dielectric layer 272, and the first dielectric layer 270. The etching process 279 may include an isotropic etching process and / or anisotropic etching process. In some embodiments, the etching process 279 is an anisotropic etching process. The etching process 279 may include a dry etching process. A dry etching process may include using argon (Ar), oxygen (O2), nitrogen (N2), hydrogen (H2), C m H n F p Plasma of (m being about 1 to about 6, n being about 1 to about 5, and p being about 1 to about 8) or combinations thereof. During or after etching process 279, the patterned photoresist layer 278 and hard mask 275 may be selectively removed. After the operation at frame 112 is completed, the semiconductor substrate 204 may be exposed in trench 280.

[0043] In etching process 279, the first dielectric layer 270 may have a first etching rate, and the second dielectric layer 272 may have a second etching rate. The first etching rate may be greater than the second etching rate. For example, the ratio of the first etching rate to the second etching rate may be from about 4 to about 10. In etching process 279, the first dielectric layer 270 may be etched laterally more than the second dielectric layer 272. In some embodiments, after etching process 279 is completed, the sidewalls of the first dielectric layer 270 in the trench 280 are laterally recessed from the sidewalls of the second dielectric layer 272 in the trench 280. Figure 7As shown, the trench 280 may have a first width W1 in the first dielectric layer 270 and a second width W2 in the second dielectric layer 272. W1 and W2 are along the X direction, and W1 is greater than W2. W2 may be approximately 10 nm to approximately 20 nm. Figure 8 As shown, trench 280 may have a third width W3 in the first dielectric layer 270 and a fourth width W4 in the second dielectric layer 272. W3 and W4 are along the Y direction, and W3 is greater than W4. W4 may be from about 20 nm to about 80 nm. The difference between W1 and W2 and the difference between W3 and W4 can be adjusted by adjusting the operating conditions (e.g., duration, etchant composition). For example, by increasing the duration of the etching process 279, the difference between W1 and W2 and the difference between W3 and W4 increases.

[0044] Still referencing Figure 1 and Figures 7 to 8 Method 100 includes block 114, wherein a cleaning process is performed to clean the surfaces of structure 200, including surfaces in trench 280. In some embodiments, the cleaning process includes wet cleaning. In some examples, wet cleaning includes using a mixture of deionized water, ammonium hydroxide and hydrogen peroxide, a mixture of deionized water, hydrochloric acid and hydrogen peroxide, SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for oxide removal. In some examples, the temperature of wet cleaning is above 100°C.

[0045] refer to Figure 1 and Figures 9 to 11 Method 100 includes block 116, wherein an etching process 281 is performed on semiconductor substrate 204 to extend trench 280 to expose an epitaxial layer (e.g., second layer 214-4) of source / drain structure 214. Figure 10A yes Figure 9 Enlarged view of groove 280 in part C of structure 200. Figure 10B This is an optional view of groove 280 in part C. Figure 10A and Figure 10B For simplicity, components outside trench 280 (e.g., semiconductor substrate 204, source / drain structure 214, first dielectric layer 270, and second dielectric layer 272) are not explicitly depicted. Dashed lines indicate the hierarchy of the boundaries of these components.

[0046] refer to Figure 9 and Figure 11 In some embodiments, after etching process 281 is completed, trench 280 extends through semiconductor substrate 204 and interposer (including separator layer 214-1 and bottom layer 214-2) and exposes the epitaxial layer of source / drain structure 214. A portion of semiconductor substrate 204 and at least a portion of interposer are etched.

[0047] Etching process 281 may use the second dielectric layer 272 as an etching mask. Etching process 281 may include, for example, transferring a pattern in the second dielectric layer 272 to a component (e.g., the semiconductor substrate 204) beneath it by removing portions of the semiconductor substrate 204 exposed by trench 280. Etching process 281 may also include removing the interposer layer exposed by trench 280 after removing portions of the semiconductor substrate 204. Etching process 281 may include isotropic and / or anisotropic etching processes. In some embodiments, etching process 281 includes anisotropic etching processes. In some embodiments, etching process 281 may be a dry etching process using oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof. In some embodiments, the semiconductor substrate 204 and the interposer are removed in a multi-step process, such as a first etching process (selectively removing the semiconductor substrate 204 without etching (or ignoring) the interposer), a second etching process (selectively removing the separator layer 214-1 without etching (or ignoring) the bottom layer 214-2), and a third etching process (selectively removing the bottom layer 214-2). In some embodiments, different etchants and / or etching parameters may be used in different etching processes of the multi-step process.

[0048] In some other embodiments (e.g., when the underlying layer 214-2 comprises a dielectric material), after etching process 281, trench 280 may extend through semiconductor substrate 204 and separator layer 214-1 to expose underlying layer 214-2. In such embodiments, portions of semiconductor substrate 204 and at least a portion of separator layer 214-1 are etched. In such embodiments, etching process 281 may selectively remove semiconductor substrate 204 and separator layer 214-1, leaving underlying layer 214-2 substantially unetched. For example, etching process 281 etches semiconductor substrate 204 and / or separator layer 214-1 without etching (or negligibly) the second dielectric layer 272 and / or underlying layer 214-2. The etchant of etching process 281 may etch semiconductor material (e.g., semiconductor substrate 204 and separator layer 214-1) at a higher rate than that of dielectric material (e.g., second dielectric layer 272 and underlying layer 214-2). The bottom layer 214-2 can be used as an etch stop layer, and etching of the semiconductor substrate 204 and / or the separator layer 214-1 can be stopped upon reaching the bottom layer 214-2. The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. The bottom layer 214-2 can be removed in a subsequent process (described below).

[0049] In some embodiments, etching process 281 laterally etches the first dielectric layer 270, such that the sidewalls of the first dielectric layer 270 in the trench 280 are more laterally recessed than the sidewalls of the second dielectric layer 272 in the trench 280. For example, refer to Figure 9 The trench 280 has a width W1' in the first dielectric layer 270 and a second width W2 in the second dielectric layer 272. W1' is greater than W1 along the X direction, and the difference between W1' and W2 is greater than the difference between W1 and W2. (Reference) Figure 11 The trench 280 may have a width W3' in the first dielectric layer 270 and a fourth width W4 in the second dielectric layer 272. W3' is along the Y direction, W3' is greater than W3, and the difference between W3' and W4 is greater than the difference between W3 and W4. W1 to W4 are as described above. Figures 7 to 8 As described in [the text].

[0050] In some embodiments, reference Figure 10A The contour of trench 280 has a stepped change between the sidewalls 270s of the first dielectric layer 270 and the sidewalls 204s of the underlying semiconductor substrate 204, and also has a stepped change between the sidewalls 272s of the second dielectric layer 272 and the sidewalls 270s of the underlying first dielectric layer 270. During etching process 281, the top edge of the second dielectric layer 272 can be rounded. Optionally, refer to... Figure 10B The sidewalls 270s of the first dielectric layer 270 intersect with the sidewalls 204s of the underlying semiconductor substrate 204. In some embodiments, the slope of the sidewalls 270s is less than the slope of the sidewalls 204s. For example, the sidewalls 270s and the virtual vertical line 282 have a first angle D1 of about 10 degrees (°) to about 20 degrees. The sidewalls 204s and the virtual vertical line 282 may have a second angle D2 of about 0 to about 10 degrees. D1 may be greater than D2. Figure 10B In the depicted embodiments, the contour of the trench 280 has a stepped change between the sidewalls 272s of the second dielectric layer 272 and the sidewalls 270s of the first dielectric layer 270 below it. In some embodiments, the slope of the sidewalls 270s is less than the slope of the sidewalls 272s. Figures 10A to 10B The outline of groove 280 in the XZ plane is shown; it can be understood that the shape of groove 280 in the YZ plane can be similar. For example, as... Figure 11 An enlarged view of the groove 280 in part E of structure 200 shown can be similar to Figures 10A to 10B Except that angle D2 can be approximately 0 to approximately 5°.

[0051] In some embodiments, after etching process 281, an ashing process and a subsequent cleaning process may be performed to remove residues from etching process 281 and clean exposed surfaces in trench 280. The ashing process may use oxygen or hydrogen, and the cleaning process may be similar to that described above at box 114. In some embodiments, the cleaning process may apply a hot SPM solution (a mixture of sulfuric acid and hydrogen peroxide), for example at a temperature above 100°C.

[0052] refer to Figure 1 and Figures 12 to 14 Method 100 includes a frame 118, wherein a back-side contact member 285 is formed in a groove 280. Figure 13A yes Figure 12 An enlarged view of the back contact component 285 in part C of structure 200. Figure 13B This is an optional view of the back-side contact component 285 in part C. Figure 13A and Figure 13B Corresponding to respectively by Figure 10A and Figure 10B The embodiment produced by the structure in the example. Forming the back-side contact component 285 may include depositing a dielectric pad 284 in a trench 280, etching through the bottom portion of the dielectric pad 284, forming a silicide component 286 on the epitaxial layer of the source / drain structure 214, and forming a metal filler 288 in the trench 280 and above the dielectric pad 284 and the silicide component 286.

[0053] The dielectric pad 284 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the dielectric pad 284 includes silicon nitride. The dielectric pad 284 may have a thickness of about 1 nm to about 10 nm. For example, the dielectric pad 284 may be formed by conformally blanket-depositing a dielectric material layer over the back side of structure 200 using a process such as CVD, SACVD, ALD, PVD, or other suitable processes. In the illustrated embodiment, the deposition of the dielectric material layer is followed by an etch-back (e.g., anisotropic) process to remove the dielectric material layer from the horizontal surface of trench 280. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or combinations thereof. In some embodiments, the etch-back process includes a directional etching process. In an embodiment, after the etch-back process, the surface of the epitaxial layer (e.g., the second layer 214-4) of the source / drain structure 214 is exposed. A dielectric material layer may be retained as a dielectric pad 284 on the sidewalls of the semiconductor substrate 204, the interposer of the source / drain structure 214, the first dielectric layer 270, and the second dielectric layer 272. The dielectric pad 284 provides electrical isolation between the metal filler 288 and surrounding components (e.g., the semiconductor substrate 204). In some embodiments, the deposited dielectric material layer is first processed to change its composition. In this case, the processed portion of the dielectric material layer is retained during an etch-back process to form the dielectric pad 284, and the unprocessed portion is removed by the etch-back process. In a further embodiment, the dielectric pad 284 comprises silicon oxide, and the processing includes ion implantation using suitable ions (such as nitrogen ions) to introduce nitrogen into the bottom portion of the dielectric material layer. Subsequently, the processed portion of the dielectric material layer is selectively removed by an etch-back process using a suitable etchant (such as phosphorous acid). In embodiments where the underlying layer 214-2 is substantially not etched during etching process 281, the underlying layer 214-2 can be removed in the etch-back process to expose the epitaxial layer of the source / drain structure 214.

[0054] After forming the dielectric pad 284, a silicide component 286 may be formed. Forming the silicide component 286 may include depositing one or more metals into the trench 280 using CVD, PVD, ALD, or other suitable methods; performing an annealing process on the structure 200 to allow the one or more metals to react with the exposed epitaxial layer of the source / drain structure 214 to produce the silicide component 286; and removing unreacted portions of the one or more metals, leaving the silicide component 286 in the trench 280. In such an embodiment, the silicide component 286 is formed on the exposed surface of the epitaxial layer of the source / drain structure 214, but not on the exposed sidewall surface of the dielectric pad 284. In the depicted embodiment, the silicide component 286 is formed in the bottom of the trench 280. The silicide component 286 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), combinations thereof, or other suitable compounds. In some embodiments, the silicide component 286 comprises TiSi. The silicide component 286 is formed between the epitaxial layer of the source / drain structure 214 and the metal filler 288 to further reduce contact resistance.

[0055] Metal filler 288 may be disposed above dielectric pad 284 and silicide component 286, and laterally surrounded by dielectric pad 284. Metal filler 288 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, metal filler 288 includes W. Figures 12 to 14 The diagram shows the structure 200 after planarization. A silicide component 286, a dielectric pad 284, and a metal filler 288 together form a back contact component 285. The back contact component 285 substantially follows the contour of the trench 280. The back contact component 285 is electrically connected to the epitaxial layer of the source / drain structure 214.

[0056] refer to Figure 13AThe sidewall of one side of the metal filler 288 has portions 288s-1, 288s-2, and 288s-3. In some embodiments, portions 288s-1 and 288s-2 intersect, and there is no step change between them. The slope of portion 288s-2 may be less than the slope of portion 288s-1. In some embodiments, there is a step change between portions 288s-2 and 288s-3. The outer sidewall of the dielectric pad 284 follows as... Figure 10A The outline of groove 280 is shown, and it has a stepped change. (Reference) Figure 13B Parts 288s-1 and 288s-2 intersect, and there is no step change between them. In some embodiments, there is a step change between parts 288s-2 and 288s-3. The slope of part 288s-2 may be less than the slope of part 288s-1 and less than the slope of part 288s-3. Figures 13A to 13B The back-side contact member 285 in the XZ plane is shown; it can be understood that the back-side contact member 285 in the YZ plane can be similar. For example, as... Figure 14 An enlarged view of the back contact component 285 in part E of structure 200 shown can be compared with... Figures 13A to 13B similar.

[0057] refer to Figure 1 and Figures 15 to 18B Method 100 includes block 120, wherein a planarization process is performed to remove a portion of the back-side contact 285 in the second dielectric layer 272. In some embodiments, the planarization process also removes a top portion of the first dielectric layer 270 and a portion of the back-side contact 285 therein. This can remove, for example... Figures 12 to 14 The portion shown is a horizontally oriented dielectric pad 284 at the interface of the first dielectric layer 270 and the second dielectric layer 272. The remaining portion of the back-side contact 285 may be referred to as the back-side source / drain contact 285'. The remaining portion of the first dielectric layer 270 may be referred to as the first dielectric layer 270'. A planarization process may be performed until reaching and / or exposing, as shown in the diagram. Figure 13A and Figure 13B The top surface 288a of the metal filler 288 at layer 289 is depicted. After the planarization process is completed, the back surface of the back source / drain contact 285' and the back surface of the first dielectric layer 270' form a substantially flat surface.

[0058] Figure 16A As shown Figure 15 An enlarged view of the back-side source / drain contact 285' in part F of the structure 200 shown. Figure 16B It shows Figure 16A Optional views. Figure 18A As shown Figure 17An enlarged view of the back-side source / drain contact 285' in part G of the structure 200 shown. Figure 18B It shows Figure 18A Optional views. Figure 16A and Figure 18A Corresponding to by Figure 13A Examples generated from the structure in the example. Figure 16B and Figure 18B Corresponding to by Figure 13B Examples generated from the structure in the example.

[0059] refer to Figure 16A The back-side source / drain contact 285' has a head portion embedded in the first dielectric layer 270' and a body portion embedded in the semiconductor substrate 204 and the source / drain structure 214. The head portion may have a height H1 of about 1 nm to about 15 nm. The body portion may have a height H2 of about 40 nm to about 60 nm. The head portion is wider than the body portion, so the profile of the back-side source / drain contact 285' can be described as a nail-shaped profile or a T-shaped profile. The profile of the back-side source / drain contact 285' can be detected (e.g., by transmission electron microscopy (TEM)). By having a wider head portion, the resistance of the back-side source / drain contact 285' is reduced, thus increasing the current and speed of the structure 200 during operation. By having a narrower body portion, the back-side source / drain contact 285' is separated from nearby conductive components (e.g., adjacent gate structures), and electrical leakage between them can be avoided or reduced. The back-side source / drain contact 285' may have a width W5 at the layer level of the interface between the first dielectric layer 270' and the semiconductor substrate 204. W5 may be from about 5 nm to about 25 nm. The back-side source / drain contact 285' may have a maximum width W6. W6 may be located at the back-side surface of the head portion. W6 is greater than W5. W6 may be from about 5 nm to about 35 nm. W5 and W6 are along the X direction. The lateral advance W7 on each side may be defined as the maximum horizontal distance between the apex of the sidewall of the head portion and the sidewall of the body portion of the back-side source / drain contact 285' (e.g., at the layer level of the interface between the first dielectric layer 270' and the semiconductor substrate 204). W7 may be along the X direction and greater than 0, such as in the range of from about 1 nm to about 10 nm. W7 may be about half the difference between W6 and W5. Reference Figure 16B The optional back-side source / drain contact 285' can have the same characteristics as... Figure 16A The embodiments shown have different contours; however, the dimensions can be different. Figure 16A Similar to those described in the text.

[0060] refer to Figure 18A In the YZ plane, the back-side source / drain contact 285' can have the same characteristics as... Figure 16ASimilar profiles, except for the dimensions described below. The back-side source / drain contact 285' may have a width W8 at the layer level of the interface between the first dielectric layer 270' and the semiconductor substrate 204. W8 may be from about 5 nm to about 75 nm. The back-side source / drain contact 285' may have a maximum width W9. W9 may be located at the back-side surface of the head portion. W9 is greater than W8. W9 may be from about 5 nm to about 85 nm. W8 and W9 are along the Y-direction. The lateral advancement along the Y-direction in the YZ plane may be W7 as described above. W7 may be about half the difference between W9 and W8. Reference Figure 18B The optional back-side source / drain contact 285' can have the same characteristics as... Figure 18A The embodiments shown have different contours; however, the dimensions can be similar. Figure 18A Those described in the text.

[0061] refer to Figure 1 and Figures 19 to 20 Method 100 includes a frame 122, wherein a back-side metal line 294 is formed above and electrically connected to the back-side source / drain contact 285'.

[0062] Prior to forming the back-side metalline 294, a CESL 290 and an ILD layer 292 may be formed over the back-side source / drain contacts 285' and the first dielectric layer 270'. The CESL 290 and ILD layer 292 may be formed using materials and methods similar to those used for the CESLs (e.g., 262-0, 262-1, 262-2) and dielectric layers (e.g., 264-0, 264-1, 263-2, 264-2) in the dielectric structure 250, respectively. The back-side metalline 294 may be formed by patterning the CESL 290 and ILD layer 292 to form openings to expose the back-side source / drain contacts 285', filling the openings with a conductive material, and performing a planarization process to remove excess material. The conductive material may include metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or another suitable material. The backside metalline 294 may include a barrier layer and a metal filler layer deposited above the barrier layer. The backside metalline 294 may be powered and is referred to as a backside power rail. The CESL 290, ILD layer 292, and backside metalline 294 may be located in the BM0 level of a backside multilayer interconnect (BMLI) structure. The BMLI may include additional metal levels (e.g., BM1, BM2), which include the CESL, ILD layers, and metal lines and / or metal vias embedded in the CESL and ILD layers.

[0063] Semiconductor device 200 may undergo further processing to form various components and regions known in the art. For example, subsequent processing may form additional back-side dielectric layers and contacts / vias / lines over the back side of substrate 202, configured to connect various components to form a functional circuit that may include one or more devices, including semiconductor device 200. In one example, damascene and / or dual damascene processes are used to form copper-associated multilayer interconnect structures.

[0064] Although Figures 3 to 20 A GAA transistor is shown. Other examples of semiconductor devices (e.g., FinFET, Complementary Field-Effect Transistor (CFET), other multi-gate devices) and other contact components (e.g., front-side source / drain contacts, gate vias) can benefit from aspects of this disclosure.

[0065] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor structures. For example, by forming back-side source / drain contacts with enlarged heads, the resistance of the back-side source / drain contacts can be reduced, the current and speed of the semiconductor structure can be increased, and the overall performance of the semiconductor structure can be improved.

[0066] In one exemplary aspect, this disclosure relates to a method. The method includes providing a structure. The structure includes a substrate; a channel region disposed over the substrate; a source / drain structure disposed over the substrate and connected to the channel region; a contact etch stop layer (CESL) disposed over the source / drain structure; an interlayer dielectric (ILD) layer disposed over the CESL; and a metal gate structure disposed over the channel region. The source / drain structure includes a first layer adjacent to the sidewalls of the channel region and a second layer away from the sidewalls of the channel region. The method also includes a flipped structure, depositing a first dielectric layer over the substrate, depositing a second dielectric layer over the first dielectric layer, performing a first etch process to form a trench in the first and second dielectric layers, performing a second etch process to extend the trench through the substrate and into the source / drain structure, and forming contact members in the trench. In a cross-sectional view, a first interface between the contact member and the first dielectric layer has a first angle with a vertical line, and a second interface between the contact member and the substrate has a second angle with a vertical line. The first angle is greater than the second angle.

[0067] In some embodiments, the first dielectric layer has a dielectric constant of less than about 6. In some embodiments, the method further includes performing a cleaning process after performing the first etching process and before performing the second etching process. In some embodiments, after performing the first etching process, a first sidewall of the first dielectric layer in the trench is laterally recessed from a second sidewall of the second dielectric layer in the trench. In some embodiments, performing the second etching process causes the first dielectric layer to be laterally recessed from the trench. In some embodiments, the method further includes performing a planarization process to remove portions of the second dielectric layer and the contact components surrounded by the second dielectric layer. In some embodiments, forming the contact components in the trench includes depositing a dielectric pad on the sidewall of the trench, forming a silicide layer on the exposed surface of the source / drain structure in the trench, and filling a metal filler over the silicide layer and the dielectric pad. In some embodiments, depositing the first dielectric layer includes depositing a metal filler comprising C x H y Si z The gas contains ammonia, where x is about 1 to about 6, y is about 6 to about 20, and z is about 1 to about 3. In some embodiments, in the first etching process, the first etching rate of the first dielectric layer is greater than the second etching rate of the second dielectric layer.

[0068] In another exemplary aspect, this disclosure relates to a method. The method includes providing a structure. The structure includes an active region and a gate structure, the active region including a source / drain region and a channel region, the gate structure disposed above the channel region. The source / drain region includes a first layer adjacent to the sidewalls of the channel region and a second layer away from the sidewalls of the channel region. In a top view, the active region extends longitudinally along a first direction, and the gate structure extends longitudinally along a second direction different from the first direction. The method further includes depositing a low-k dielectric layer below the active region, depositing a dielectric layer below the low-k dielectric layer, patterning the dielectric layer and the low-k dielectric layer from a back side of the structure to form an initial trench in the dielectric layer and the low-k dielectric layer, performing an etching process to extend the initial trench to form a trench exposing the source / drain region, and forming a back-side source / drain contact in the trench. In the initial trench, the exposed sidewalls of the low-k dielectric layer are laterally recessed from the exposed sidewalls of the dielectric layer.

[0069] In some embodiments, the low-k dielectric layer comprises about 40% to about 50% silicon, about 15% to about 40% carbon, and about 20% to about 45% nitrogen. In some embodiments, performing an etching process further recesses the low-k dielectric layer laterally. In some embodiments, a first width of an initial trench in the dielectric layer is smaller than a second width of an initial trench in the low-k dielectric layer, the first width and the second width being along a first direction. In some embodiments, forming a back-side source / drain contact in the trench includes depositing a dielectric liner on the sidewalls of the trench, forming a silicide layer on the exposed surface of the source / drain region in the trench, and depositing a metal fill layer in the trench. In some embodiments, the source / drain region includes an interposer and an epitaxial member located above the interposer, the epitaxial member including a first layer and a second layer, and performing an etching process includes etching through the interposer to expose the epitaxial member. In some embodiments, the method further includes performing a planarization process from the back side of the structure to expose the low-k dielectric layer, thereby removing a portion of the back-side source / drain contact in the dielectric layer. In some embodiments, after performing a planarization process, the remaining portion of the back-side source / drain contact includes a first portion embedded in a low-k dielectric layer and a second portion embedded in an active region, the first portion having a first sidewall and the second portion having a second sidewall connected to the first sidewall, the first sidewall having a first slope and the second sidewall having a second slope greater than the first slope.

[0070] In yet another exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate; a channel region disposed over the substrate; source / drain components disposed over the substrate and connected to the channel region; a metal gate structure disposed over the channel region; a contact etch stop layer (CESL) disposed over the source / drain components; an interlayer dielectric (ILD) layer disposed over the CESL; a first contact component extending through the ILD layer to be electrically coupled to the source / drain components; a dielectric layer disposed below the substrate; and a second contact component extending through the dielectric layer and the substrate and electrically connected to the source / drain components. The second contact component includes a first portion embedded in the substrate and a second portion embedded in the dielectric layer, the first portion having a first sidewall having a first slope, and the second portion having a second sidewall having a second slope less than the first slope.

[0071] In some embodiments, the dielectric layer has a dielectric constant of less than about 6. In some embodiments, the first sidewall is inclined at a first angle from the vertical direction, and the second sidewall is inclined at a second angle from the vertical direction at a angle less than the first angle.

[0072] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A structure is provided, the structure comprising: Substrate; The channel region is disposed above the substrate; A source / drain structure is disposed above the substrate and connected to the channel region, wherein the source / drain structure includes a first layer adjacent to the sidewall of the channel region and a second layer away from the sidewall of the channel region; A contact etch stop layer (CESL) is located above the source / drain structure; An interlayer dielectric (ILD) layer is located above the contact etch stop layer; and A metal gate structure is disposed above the channel region; Flip the structure; A first dielectric layer is deposited over the substrate; A second dielectric layer is deposited above the first dielectric layer; Perform a first etching process to form trenches in the first dielectric layer and the second dielectric layer; Perform a second etching process to extend the trench through the substrate and into the source / drain structure; and Contact components are formed in the groove. In the cross-sectional view, the first interface between the first dielectric layer and the contact component has a first angle with the vertical line, and the second interface between the substrate and the contact component has a second angle with the vertical line. Wherein, the first angle is greater than the second angle.

2. The method according to claim 1, wherein, The first dielectric layer has a dielectric constant of less than about 6.

3. The method according to claim 1, wherein, The method further includes performing a cleaning process after performing the first etching process and before performing the second etching process.

4. The method according to claim 1, wherein, After the first etching process is performed, the first sidewall of the first dielectric layer in the trench is laterally recessed from the second sidewall of the second dielectric layer in the trench.

5. The method according to claim 1, wherein, The second etching process is performed to make the first dielectric layer laterally recessed from the trench.

6. The method of claim 1, further comprising performing a planarization process to remove the second dielectric layer and a portion of the contact member surrounded by the second dielectric layer.

7. The method according to claim 1, wherein, Forming the contact member in the trench includes: A dielectric liner is deposited on the sidewall of the trench; A silicide layer is formed on the exposed surface of the source / drain structure in the trench; and A metal filler is filled over the silicide layer and the dielectric pad.

8. The method according to claim 1, wherein, Depositing the first dielectric layer includes depositing C x H y Si z Ammonia gas, Where x is approximately 1 to approximately 6, y is approximately 6 to approximately 20, and z is approximately 1 to approximately 3.

9. A method for manufacturing a semiconductor structure, comprising: A structure is provided, the structure comprising: The active region includes a source / drain region and a channel region, and A gate structure, wherein the gate structure is disposed above the channel region. The source / drain region includes a first layer adjacent to the sidewall of the channel region and a second layer away from the sidewall of the channel region. In the top view, the active region extends longitudinally along a first direction, and the gate structure extends longitudinally along a second direction different from the first direction. A low-k dielectric layer is deposited beneath the active region; A dielectric layer is deposited beneath the low-k dielectric layer; Patterning the dielectric layer and the low-k dielectric layer from the back side of the structure to form initial trenches in the dielectric layer and the low-k dielectric layer; An etching process is performed to extend the initial trench, thereby forming a trench that exposes the source / drain regions; and Back-side source / drain contacts are formed in the trench. In the initial trench, the exposed sidewall of the low-k dielectric layer is laterally recessed from the exposed sidewall of the dielectric layer.

10. A semiconductor structure, comprising: Substrate; The channel region is disposed above the substrate; Source / drain components are disposed above the substrate and connected to the channel region; A metal gate structure is disposed above the channel region; A contact etch stop layer (CESL) is disposed above the source / drain components; An interlayer dielectric (ILD) layer is disposed above the contact etch stop layer; The first contact component extends through the interlayer dielectric layer to be electrically coupled to the source / drain component; A dielectric layer is disposed beneath the substrate; as well as A second contact component extends through the dielectric layer and the substrate, and the second contact component is electrically connected to the source / drain component. The second contact component includes a first portion embedded in the substrate and a second portion embedded in the dielectric layer. The first part has a first sidewall with a first slope, and the second part has a second sidewall with a second slope that is less than the first slope.

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