Semiconductor device including wire protection film and method of manufacturing the same

Abstract

To improve device performance and reliability by forming an air gap and a wiring protective film on the sidewalls of a wiring structure, a semiconductor device may include: a lower conductive pattern; a wiring structure located on the lower conductive pattern, extending in a first direction and including an upper surface and a bottom surface opposite each other in a second direction, the bottom surface of the wiring structure facing the lower conductive pattern, and sidewalls connecting the upper surface and the bottom surface of the wiring structure; and a first wiring protective film contacting the wiring structure and extending along the sidewalls of the wiring structure, wherein the first wiring protective film includes a covering region covering the sidewalls of the wiring structure and a plurality of protruding regions, each of the plurality of protruding regions protruding from the covering region in a third direction.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device comprising wiring formed in a BEOL (back-end) process and a method for manufacturing the semiconductor device. Background Technology

[0002] With the development of electronic technology, and the rapid progress in miniaturization of semiconductor components in recent years, there has been a demand for high integration and low power consumption in semiconductor chips. To meet the requirements for high integration and low power consumption in semiconductor chips, the feature size of semiconductor devices continues to shrink.

[0003] Because various contact types are used for connections between wiring, the contact length can be increased. Therefore, the contact resistance can be increased. Summary of the Invention

[0004] This disclosure provides a semiconductor device that can improve device performance and reliability by forming air gaps and wiring protective films on the sidewalls of a wiring structure.

[0005] This disclosure also provides a method for manufacturing a semiconductor device that can improve device performance and reliability by forming air gaps and wiring protective films on the sidewalls of a wiring structure.

[0006] According to one aspect of this disclosure, a semiconductor device is provided, the semiconductor device including a lower conductive pattern and a first wiring structure, the first wiring structure being disposed on the lower conductive pattern, extending in a first direction, and including an upper surface and a bottom surface opposite to each other in a second direction different from the first direction, the bottom surface of the first wiring structure facing the lower conductive pattern; the first wiring structure further including: a sidewall connecting the upper surface and the bottom surface of the first wiring structure; and a first wiring protective film contacting the first wiring structure and extending along the sidewall of the first wiring structure, wherein the first wiring protective film includes a covering region and a plurality of protruding regions, the covering region covering the sidewall of the first wiring structure, and each of the plurality of protruding regions of the first wiring protective film protruding from the covering region of the first wiring protective film in a third direction different from the first direction and the second direction.

[0007] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a lower conductive pattern and a first wiring structure, the first wiring structure being disposed on the lower conductive pattern, extending in a first direction, and including an upper surface and a bottom surface opposite to each other in a second direction different from the first direction, the bottom surface of the first wiring structure facing the lower conductive pattern; the first wiring structure further comprising: a sidewall connecting the upper surface of the first wiring structure and the bottom surface of the first wiring structure; and a wiring protective film contacting the first wiring structure and extending along the sidewall of the first wiring structure, wherein a first thickness of the wiring protective film at a first point in a third direction different from the first and second directions is greater than a second thickness of the wiring protective film at a second point in the third direction, a third thickness of the wiring protective film at a third point in the third direction is greater than the second thickness, the height from the bottom surface of the first wiring structure to the first point is less than the height from the bottom surface of the first wiring structure to the second point, and the height from the bottom surface of the first wiring structure to the third point is greater than the height from the bottom surface of the first wiring structure to the second point.

[0008] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a lower conductive pattern; a first wiring structure disposed on the lower conductive pattern and extending in a first direction; a second wiring structure extending in the first direction and spaced apart from the first wiring structure in a second direction perpendicular to the first direction; a wiring protective film disposed on the lower conductive pattern, extending along the sidewalls of the first wiring structure and the second wiring structure, and contacting the first wiring structure and the second wiring structure; a wiring air gap disposed between the first wiring structure and the second wiring structure; a padding cover film disposed on the wiring protective film and the wiring air gap, extending along the sidewalls of the first wiring structure and the second wiring structure, and contacting the first wiring structure and the second wiring structure; and a filling cover film disposed on the padding cover film between the first wiring structure and the second wiring structure, wherein the wiring protective film includes a covering region and a plurality of protruding regions, the covering region covering the sidewall of the first wiring structure, and each of the plurality of protruding regions of the wiring protective film protruding from the covering region of the wiring protective film in the second direction.

[0009] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a lower conductive pattern; sequentially forming a metal material film and a cover film on the lower conductive pattern; patterning the metal material film and the cover film to form a plurality of wiring structures, each of the plurality of wiring structures including a line wiring and a wiring insulating cover film; forming a sacrificial material film between adjacent wiring structures, the sacrificial material film covering a portion of a sidewall of the wiring structure; forming a pad cover film on the wiring structure and the sacrificial material film, the pad cover film extending along an upper surface of the wiring structure, an upper surface of the sacrificial material film, and the remainder of a sidewall of the wiring structure; removing the sacrificial material film to form a wiring air gap between the wiring structures; after forming the wiring air gap, depositing a flowable insulating material to form a fill cover film on the pad cover film, and during the formation of the fill cover film, forming a wiring protective film on the sidewall of the wiring structure by a portion of the flowable insulating material passing through the pad cover film.

[0010] However, the aspects of this disclosure are not limited to those set forth herein. The foregoing and other aspects of this disclosure will become clearer to those skilled in the art upon reference to the detailed description of this disclosure given below. Attached Figure Description

[0011] The above and other aspects and features of this disclosure will become clearer from the detailed description of embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is an example layout diagram used to illustrate a semiconductor device according to some embodiments.

[0012] Figure 2 It is along Figure 1 The sectional view taken by line AA.

[0013] Figure 3 yes Figure 2 A magnified view of part P.

[0014] Figure 4 yes Figure 3 A magnified view of part of Q.

[0015] Figure 5 and Figure 6 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0016] Figure 7 and Figure 8 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0017] Figure 9 and Figure 10This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0018] Figure 11 and Figure 12 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0019] Figure 13 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0020] Figure 14 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0021] Figure 15 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0022] Figure 16 , Figure 17 and Figure 18 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0023] Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0024] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the first element, component, region, layer, or part described below may be referred to as the second element, component, region, layer, or part without departing from the spirit and scope of this disclosure.

[0025] Although the accompanying drawings of semiconductor devices according to some embodiments illustrate fin transistors (FinFETs) including channel regions with fin-patterned shapes, transistors including nanowires or nanosheets, and MBCFETs... TM (Multi-channel field-effect transistor) or vertical transistor (vertical FET), but this disclosure is not limited thereto. Of course, semiconductor devices according to some embodiments may include tunneling transistors (tunneling FETs) or three-dimensional (3D) stacked transistors. Of course, semiconductor devices according to some embodiments may include planar transistors. Furthermore, the technical ideas of this disclosure can be applied to transistors based on two-dimensional materials (FETs based on 2D materials) and their heterostructures.

[0026] In addition, the semiconductor device according to some embodiments may also include a bipolar junction transistor, a laterally diffused metal-oxide semiconductor (LDMOS), or the like.

[0027] Figure 1 This is an example layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 2 It is along Figure 1 The sectional view taken by line AA. Figure 3 yes Figure 2 A magnified view of part P. Figure 4 yes Figure 3 A magnified view of part of Q.

[0028] Reference Figures 1 to 4 According to some embodiments, a semiconductor device may include a lower wiring structure 110ST, an upper wiring structure 210ST, a pad cover film 140, a fill cover film 145, and a wiring protection film 150.

[0029] The semiconductor device according to some embodiments may further include an interlayer insulating film 50 and a lower conductive pattern 60 disposed within the interlayer insulating film 50. Although the lower conductive pattern 60 is shown as a single film, this is for illustrative purposes only, and the embodiments are not limited thereto. Unlike the example shown, the lower conductive pattern 60 may include a filler film and a barrier film extending along the sidewalls and bottom surface of the filler film, such as... Figure 11 The same as the bottom wiring structure in 110ST.

[0030] The lower interlayer insulating film 50 can cover the gate electrode and source / drain electrode of the transistor formed in the front-end (FEOL) process. Alternatively, the lower interlayer insulating film 50 can be an interlayer insulating film formed in the back-end (BEOL) process.

[0031] In other words, as an example, the lower conductive pattern 60 can be a contact or contact wiring formed in the middle-end (MOL) process. As another example, the lower conductive pattern 60 can be a connection wiring formed in the back-end (BEOL) process.

[0032] The lower interlayer insulating film 50 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material. The low dielectric constant material may be, for example, silicon oxide having moderately high carbon and hydrogen content, and may be a material such as SiCOH. On the other hand, the dielectric constant of the insulating material can be reduced due to the inclusion of carbon in the insulating material. However, to further reduce the dielectric constant of the insulating material, the insulating material may include pores, such as cavities, through which gas or air is filled.

[0033] Low dielectric constant materials may include, for example, but not limited to, tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butoxysilane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Toran silazane), FSG (fluorosilicate glass), polyimide nanofoams such as polypropylene oxide, CDO (carbon-doped silicon dioxide), OSG (organosilicon glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof.

[0034] The lower wiring structure 110ST can be disposed on the first metal layer. The lower wiring structure 110ST can be disposed on the lower interlayer insulating film 50. The lower wiring structure 110ST can be connected to the lower conductive pattern 60.

[0035] The lower routing structure 110ST can extend in the second direction DR2. The lower routing structures 110ST can be spaced apart from each other in the first direction DR1. The lower routing structures 110ST can be separated in the first direction DR1 by routing isolation trenches 110_T.

[0036] The lower wiring structure 110ST may include an upper surface 110ST_US and a bottom surface 110ST_BS opposite to each other on the third-direction DR3. The bottom surface 110ST_BS of the lower wiring structure may face the lower conductive pattern 60 and the lower interlayer insulating film 50.

[0037] The lower wiring structure 110ST may include a sidewall 110ST_SW that connects the bottom surface 110ST_BS and the upper surface 110ST_US of the lower wiring structure. The sidewall of the wiring isolation trench 110_T may be defined by the lower wiring structure 110ST.

[0038] In a semiconductor device according to some embodiments, the width W11 of the bottom surface 110ST_BS of the lower wiring structure in the first direction DR1 may be equal to the width W12 of the upper surface 110ST_US of the lower wiring structure in the first direction DR1.

[0039] The lower wiring structure 110ST may include an upper portion 110ST_UP and a lower portion 110ST_BP. The upper portion 110ST_UP of the lower wiring structure is disposed on the lower portion 110ST_BP of the lower wiring structure. The standard used to divide the upper portion 110ST_UP and the lower portion 110ST_BP of the lower wiring structure will be described below.

[0040] For example, the under-wiring structure 110ST may include under-line wiring 120 and under-line wiring insulation cover 130.

[0041] The lower line wiring 120 may extend long in the second direction DR2. The lower line wiring 120 may have a line shape extending in the second direction DR2. For example, the first direction DR1 may be the width direction of the lower line wiring 120, and the second direction DR2 may be the length direction of the lower line wiring 120.

[0042] Here, the first direction DR1 intersects with the second direction DR2 and the third direction DR3. The second direction DR2 intersects with the third direction DR3. For example, the first direction DR1 can be orthogonal to the second direction DR2 and the third direction DR3. The second direction DR2 can be orthogonal to the third direction DR3.

[0043] The lower wiring 120 can extend long along the upper surface of the lower interlayer insulating film 50. For example, the lower wiring 120 can contact the upper surface of the lower interlayer insulating film 50.

[0044] The lower wiring insulation cover film 130 can be disposed on the lower wiring 120. The lower wiring insulation cover film 130 can extend along the upper surface 120_US of the lower wiring.

[0045] The bottom surface 110ST_BS of the lower wiring structure may include the bottom surface of the lower wiring 120. The upper surface 110ST_US of the lower wiring structure may include the upper surface of the lower wiring insulating cover film 130. The lower wiring 120 and the lower wiring insulating cover film 130 may include a common sidewall of the lower wiring structure (e.g., sidewall 110ST_SW).

[0046] For example, the lower line wiring 120 may include at least one selected from ruthenium (Ru), rhodium (Rh), iridium (Ir), molybdenum (Mo), RuAl, NiAl, NbB2, MoB2, TaB2, V2AlC, and CrAlC. In a semiconductor device according to some embodiments, the lower line wiring 120 may include ruthenium. For example, the lower line wiring 120 may be a ruthenium wiring.

[0047] Although the lower wiring 120 is shown as a single film, this is for illustrative purposes only, and the embodiment is not limited thereto. Unlike the example shown, the lower wiring 120 may include a first sub-lower wiring and a second sub-lower wiring. The first and second sub-lower wirings may be sequentially disposed on the lower interlayer insulating film 50 along a third direction DR3. The second sub-lower wiring may be disposed between the first sub-lower wiring and the lower wiring insulating cover film 130. The sidewalls of the lower wiring 120 may be defined by the first and second sub-lower wirings. The first sub-lower wiring may include at least one of a metal, a metal nitride, or a two-dimensional (2D) material. The second sub-lower wiring may include at least one of ruthenium (Ru), rhodium (Rh), iridium (Ir), molybdenum (Mo), tungsten (W), RuAl, NiAl, NbB2, MoB2, TaB2, V2AlC, and CrAlC.

[0048] The under-wiring insulating cover film 130 may include, for example, an insulating material. The under-wiring insulating cover film 130 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. In a semiconductor device according to some embodiments, the under-wiring insulating cover film 130 may include silicon nitride.

[0049] The wiring protection film 150 can be disposed on the lower conductive pattern 60 and the lower interlayer insulating film 50. The wiring protection film 150 can be disposed between adjacent lower wiring structures 110ST in the first direction DR1.

[0050] The wiring protection film 150 may contact the lower wiring structure 110ST. For example, the wiring protection film 150 may contact the sidewall 110ST_SW of the lower wiring structure.

[0051] The wiring protection film 150 may extend along the sidewall 110ST_SW of the lower wiring structure. For example, the wiring protection film 150 may extend along a portion of the sidewall 110ST_SW of the lower wiring structure. The wiring protection film 150 does not extend upward to the upper surface 110ST_US of the lower wiring structure.

[0052] In other words, the wiring protection film 150 can extend along the sidewall of the wiring isolation trench 110_T. The wiring protection film 150 can extend along a portion of the sidewall of the wiring isolation trench 110_T.

[0053] In a semiconductor device according to some embodiments, a wiring protection film 150 may extend along the upper surface of a lower interlayer insulating film 50. The wiring protection film 150 extending along the upper surface of the lower interlayer insulating film 50 may connect to a wiring protection film 150 extending along the sidewall 110ST_SW of the lower wiring structure facing the first direction DR1. From a cross-sectional view, the wiring protection film 150 may have a "U" shape.

[0054] The lower portion 110ST_BP of the lower wiring structure may be the part of the lower wiring structure 110ST that contacts the wiring protective film 150. The upper portion 110ST_UP of the lower wiring structure may contact the padding cover film 140, which will be described below. The lower portion 110ST_BP and the upper portion 110ST_UP of the lower wiring structure may be distinguished based on whether they contact the wiring protective film 150.

[0055] The lower routing structure 110ST may include a first lower routing structure 111ST and a second lower routing structure 112ST that are adjacent to each other in the first direction DR1. The first lower routing structure 111ST may be spaced apart from the second lower routing structure 112ST in the first direction DR1. The sidewall 110ST_SW of the first lower routing structure 111ST faces the sidewall 110ST_SW of the second lower routing structure 112ST.

[0056] The wiring protection film 150 extends along the sidewall 110ST_SW of the first lower wiring structure 111ST and the sidewall 110ST_SW of the second lower wiring structure 112ST. The wiring protection film 150 can contact the first lower wiring structure 111ST and the second lower wiring structure 112ST.

[0057] The wiring protection film 150 may include a first wiring protection film 150_S1 and a second wiring protection film 150_S2.

[0058] The first wiring protection film 150_S1 may extend along a portion of the sidewall 110ST_SW of the first lower wiring structure 111ST. The first wiring protection film 150_S1 may contact the sidewall 110ST_SW of the first lower wiring structure 111ST. For example, the first wiring protection film 150_S1 may extend to the bottom surface 110ST_BS of the first lower wiring structure 111ST.

[0059] The second wiring protection film 150_S2 may extend along a portion of the sidewall 110ST_SW of the second lower wiring structure 112ST. The second wiring protection film 150_S2 may contact the sidewall 110ST_SW of the second lower wiring structure 112ST. For example, the second wiring protection film 150_S2 may extend to the bottom surface 110ST_BS of the second lower wiring structure 112ST.

[0060] In a semiconductor device according to some embodiments, the wiring protection film 150 may include a connection wiring protection film 150_B extending along the bottom surface of the wiring isolation trench 110_T. The connection wiring protection film 150_B may extend along the upper surface of the lower interlayer insulating film 50.

[0061] For example, the connecting wiring protection film 150_B can connect to the first wiring protection film 150_S1 and the second wiring protection film 150_S2. The connecting wiring protection film 150_B can also be directly connected to the first wiring protection film 150_S1 and the second wiring protection film 150_S2.

[0062] The first wiring protection film 150_S1 may include a covered area 150CR_S1 and multiple protruding areas 150PR_S1. The covered area 150CR_S1 of the first wiring protection film is directly connected to the multiple protruding areas 150PR_S1 of the first wiring protection film.

[0063] The coverage area 150CR_S1 of the first wiring protective film can cover the side wall 110ST_SW of the first lower wiring structure 111ST. The coverage area 150CR_S1 of the first wiring protective film can contact the side wall 110ST_SW of the first lower wiring structure 111ST.

[0064] From a cross-sectional view, there may be an imaginary coverage line drawn parallel to the sidewall 110ST_SW of the first lower wiring structure 111ST. In this case, the coverage area 150CR_S1 of the first wiring protective film may be the first wiring protective film 150_S1 located between the sidewall 110ST_SW of the first lower wiring structure 111ST and the imaginary coverage line. For example, the imaginary coverage line may pass through the point of minimum thickness in the first wiring protective film 150_S1 in the first direction DR1. For example, the coverage area 150CR_S1 of the first wiring protective film extending along the sidewall 110ST_SW of the first lower wiring structure 111ST may have a uniform thickness.

[0065] The protruding area 150PR_S1 of the first wiring protective film can protrude from the coverage area 150CR_S1 of the first wiring protective film along the first direction DR1 toward the second lower wiring structure 112ST. In this way, the inner surface of the first wiring protective film 150_S1 can be an uneven surface.

[0066] The second wiring protection film 150_S2 may include a covered area 150CR_S2 and multiple protruding areas 150PR_S2. The covered area 150CR_S2 of the second wiring protection film is directly connected to the multiple protruding areas 150PR_S2 of the second wiring protection film.

[0067] The coverage area 150CR_S2 of the second wiring protective film can cover the sidewall 110ST_SW of the second lower wiring structure 112ST. The coverage area 150CR_S2 of the second wiring protective film can contact the sidewall 110ST_SW of the second lower wiring structure 112ST. For example, the coverage area 150CR_S2 of the second wiring protective film extending along the sidewall 110ST_SW of the second lower wiring structure 112ST can have a uniform thickness.

[0068] As an example, the thickness of the coverage area 150CR_S2 of the second wiring protection film can be the same as the thickness of the coverage area 150CR_S1 of the first wiring protection film. As another example, the thickness of the coverage area 150CR_S2 of the second wiring protection film can be different from the thickness of the coverage area 150CR_S1 of the first wiring protection film.

[0069] The protruding area 150PR_S2 of the second wiring protective film can protrude from the coverage area 150CR_S2 of the second wiring protective film toward the first lower wiring structure 111ST along the first direction DR1. In this way, the inner surface of the first wiring protective film 150_S1 can be an uneven surface.

[0070] The connection wiring protective film 150_B may include a covered area 150CR_B and at least one or more protruding areas 150PR_B. The covered area 150CR_B of the connection wiring protective film may extend along the upper surface of the lower interlayer insulating film 50.

[0071] The protruding area 150PR_B of the connecting wiring protective film can protrude from the covered area 150CR_B of the connecting wiring protective film along the third direction DR3. The protruding area 150PR_B of the connecting wiring protective film is directly connected to the covered area 150CR_B of the connecting wiring protective film. In this way, the inner surface of the connecting wiring protective film 150_B can be an uneven surface.

[0072] The shape of the wiring protection film 150 will be described in different ways below. The following description will use the first wiring protection film 150_S1 as an example. It goes without saying that the description of the first wiring protection film 150_S1 can be applied to the second wiring protection film 150_S2.

[0073] The first wiring protection film 150_S1 may include a first point PS1, a second point PS2, a third point PS3, and a fourth point PS4. The height H11 from the bottom surface 110ST_BS of the first lower wiring structure 111ST to the first point PS1 is less than the height H12 from the bottom surface 110ST_BS of the first lower wiring structure 111ST to the second point PS2. The height H12 from the bottom surface 110ST_BS of the first lower wiring structure 111ST to the second point PS2 is less than the height H13 from the bottom surface 110ST_BS of the first lower wiring structure 111ST to the third point PS3. The height H13 from the bottom surface 110ST_BS of the first lower wiring structure 111ST to the third point PS3 is less than the height H14 from the bottom surface 110ST_BS of the first lower wiring structure 111ST to the fourth point PS4.

[0074] The thickness t11 of the first wiring protection film 150_S1 at the first point PS1 is greater than the thickness t12 of the first wiring protection film 150_S1 at the second point PS2. The thickness t12 of the first wiring protection film 150_S1 at the second point PS2 is less than the thickness t13 of the first wiring protection film 150_S1 at the third point PS3. The thickness t13 of the first wiring protection film 150_S1 at the third point PS3 is greater than the thickness t14 of the first wiring protection film 150_S1 at the fourth point PS4.

[0075] From the perspective of the cross-sectional view, based on the bottom surface 110ST_BS of the lower wiring structure, although the uppermost portion of the first wiring protection film 150_S1 and the uppermost portion of the second wiring protection film 150_S2 are shown as being lower than the upper surface 120_US of the lower wiring, the embodiment is not limited thereto. Unlike the example shown, as an example, the uppermost portion of the first wiring protection film 150_S1 and the uppermost portion of the second wiring protection film 150_S2 may be arranged on the same plane as the upper surface 120_US of the lower wiring. As another example, the uppermost portion of the first wiring protection film 150_S1 and the uppermost portion of the second wiring protection film 150_S2 may be higher than the upper surface 120_US of the lower wiring.

[0076] The wiring protection film 150 may include an insulating material containing silicon (Si) and oxygen (O). In semiconductor devices according to some embodiments, the wiring protection film 150 may also include at least one of carbon (C), nitrogen (N), or hydrogen (H). For example, the wiring protection film 150 may include, but is not limited to, one of silicon oxide (SiO), silicon oxynitride (SiON), silicon carbon oxynitride (SiCO), or silicon carbon oxyhydride (SiCOH).

[0077] The padding cover film 140 can be disposed on the wiring protection film 150. The padding cover film 140 can be disposed between adjacent lower wiring structures 110ST in the first direction DR1.

[0078] The padding cover film 140 may contact the wiring protection film 150. The padding cover film 140 may contact the uppermost part of the wiring protection film 150.

[0079] The pad cover film 140 may contact the lower wiring structure 110ST. For example, the pad cover film 140 may contact the sidewall 110ST_SW of the lower wiring structure.

[0080] The padding cover film 140 can contact the upper portion 110ST_UP of the lower wiring structure. For example, the padding cover film 140 can contact the sidewall 110ST_SW of the upper portion 110ST_UP of the lower wiring structure.

[0081] The pad cover film 140 may extend along the sidewall 110ST_SW of the lower wiring structure. For example, the pad cover film 140 may contact the remainder of the sidewall 110ST_SW of the lower wiring structure. The pad cover film 140 may extend to the upper surface 110ST_US of the lower wiring structure.

[0082] The padding cover film 140 disposed on the sidewall 110ST_SW of the adjacent lower wiring structure in the first direction DR1 is connected to each other. For example, the padding cover film 140 may have a "U" shape when viewed from a cross-sectional view.

[0083] The padding cover film 140 may extend along the sidewall 110ST_SW of the first lower wiring structure 111ST and the sidewall 110ST_SW of the second lower wiring structure 112ST. The padding cover film 140 may include a connecting portion that connects the sidewall 110ST_SW of the first lower wiring structure 111ST and the sidewall 110ST_SW of the second lower wiring structure 112ST.

[0084] In one embodiment, the upper surface 120_US of the lower wiring 120 may be positioned above the bottom surface of the pad cover film 140 to form a stepped portion therebetween, but the embodiment is not limited thereto.

[0085] The pad cover film 140 may include one of silicon oxide, silicon nitride, or silicon oxynitride. In a semiconductor device according to some embodiments, the pad cover film 140 may include silicon oxide.

[0086] The filler cover film 145 can be disposed on the pad cover film 140. The filler cover film 145 can be disposed between adjacent lower wiring structures 110ST in the first direction DR1.

[0087] The upper surface of the filling cover film 145 may be arranged on the same plane as the upper surface 110ST_US of the lower wiring structure, but the embodiments are not limited thereto.

[0088] The filler cover film 145 may include an insulating material containing silicon (Si) and oxygen (O). The filler cover film 145 may also include at least one of carbon (C), nitrogen (N), or hydrogen (H). The filler cover film 145 comprises the same material as the wiring protection film 150.

[0089] A wiring air gap 110_AG can be provided between adjacent lower wiring structures 110ST on the first direction DR1. The wiring air gap 110_AG can be provided between the first lower wiring structure 111ST and the second lower wiring structure 112ST.

[0090] A wiring air gap 110_AG may be disposed between the wiring protective film 150 and the pad cover film 140. In a semiconductor device according to some embodiments, from a cross-sectional view, the wiring air gap 110_AG may be surrounded by the wiring protective film 150 and the pad cover film 140.

[0091] The padding cover film 140 and the filling cover film 145 can be disposed on the wiring protection film 150 and the wiring air gap 110_AG.

[0092] From a cross-sectional view, the wiring protection film 150 may include an outer surface that contacts the lower wiring structure 110ST, and an inner surface that surrounds the wiring air gap 110_AG. The inner surface of the wiring protection film 150 may be defined by a protruding region 150PR_S1 of a first wiring protection film, a protruding region 150PR_S2 of a second wiring protection film, and a protruding region 150PR_B connecting the wiring protection films. The inner surface of the wiring protection film 150 may include irregularities due to the protruding regions 150PR_S1, 150PR_S2, and 150PR_B. Irregularities formed on the inner surface of the wiring protection film 150 can extend the leakage current path between adjacent lower wiring structures 110ST. In other words, irregularities formed on the inner surface of the wiring protection film 150 can reduce the leakage current between adjacent lower wiring structures 110ST. Therefore, the performance and reliability of the semiconductor device can be improved.

[0093] The upper wiring structure 210ST can be set in a second metal layer that is different from the first metal layer. The upper wiring structure 210ST can be set in a second metal layer that is higher than the first metal layer.

[0094] The upper wiring structure 210ST, which is located on the second metal layer, can be connected to the lower wiring structure 110ST, which is located on the first metal layer.

[0095] For example, the upper wiring structure 210ST may include upper wiring 220 and upper wiring insulation cover film 230.

[0096] The upper wiring 220 may extend long along the first direction DR1. The upper wiring 220 may include a wiring portion extending along the first direction DR1 and a pass portion connecting to the lower wiring structure 110ST. The pass portion of the upper wiring 220 may protrude from the wiring portion of the upper wiring 220 along the third direction DR3.

[0097] For example, the upper line wiring 220 may have an integrated structure, but the embodiments are not limited thereto.

[0098] An upper wiring insulation cover film 230 can be disposed on the upper wiring 220. The upper wiring insulation cover film 230 can extend along the upper surface of the upper wiring 220.

[0099] The upper wiring 220 may include at least one of ruthenium (Ru), rhodium (Rh), iridium (Ir), molybdenum (Mo), tungsten (W), RuAl, NiAl, NbB2, MoB2, TaB2, V2AlC, or CrAlC. The upper wiring insulating cover film 230 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.

[0100] The upper interlayer insulating film 190 can be disposed on the lower wiring structure 210ST and the filler cover film 145. The upper interlayer insulating film 190 can surround the upper wiring structure 210ST.

[0101] The upper interlayer insulating film 190 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant materials.

[0102] Figure 5 and Figure 6 This is a diagram used to illustrate a semiconductor device according to some embodiments. Figure 7 and Figure 8 This is a diagram used to illustrate a semiconductor device according to some embodiments. Figure 9 and Figure 10 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main description and use will be... Figures 1 to 4 The differences described.

[0103] Reference Figures 5 to 8 In a semiconductor device according to some embodiments, a wiring protection film 150 between adjacent lower wiring structures 110ST on a first direction DR1 can be divided into two parts.

[0104] The wiring protective film 150 that contacts the first lower wiring structure 111ST does not contact the wiring protective film 150 that contacts the second lower wiring structure 112ST.

[0105] exist Figure 5 and Figure 6 In the first direction DR1, the wiring protection film 150 between adjacent lower wiring structures 110ST can have an "L" shape.

[0106] The wiring protection film 150 may include a first wiring protection film 150_S1, a second wiring protection film 150_S2, and a connecting wiring protection film 150_B divided into two parts. Each of the two parts of the connecting wiring protection film 150_B may extend or protrude from the first wiring protection film 150_S1 and the second wiring protection film 150_S2 along a first direction DR1.

[0107] From a cross-sectional view, a portion of the upper surface of the lower interlayer insulating film 50 can be exposed. The wiring air gap 110_AG can be surrounded by the wiring protection film 150, the padding cover film 140, and the lower interlayer insulating film 50.

[0108] exist Figure 7 and Figure 8 In the middle, the wiring protection film 150 does not include the connecting wiring protection film ( Figure 3 150_B).

[0109] Reference Figure 9 In a semiconductor device according to some embodiments, the width W11 of the bottom surface 110ST_BS of the lower wiring structure in the first direction DR1 may be different from the width W12 of the upper surface 110ST_US of the lower wiring structure in the first direction DR1.

[0110] The width W11 of the bottom surface 110ST_BS of the lower wiring structure in the first direction DR1 can be greater than the width W12 of the top surface 110ST_US of the lower wiring structure in the first direction DR1.

[0111] Reference Figure 10 According to some embodiments, the semiconductor device may also include a sacrificial material residue 150_RD disposed between the wiring protection film 150 and the lower wiring structure 110ST.

[0112] The sacrificial material residue 150_RD can be disposed on the sidewall 110ST_SW of the lower wiring structure and / or the upper surface of the lower interlayer insulating film 50. The sacrificial material residue 150_RD can be the sacrificial material film 110SC that was not removed during the formation of the wiring air gap 110_AG.

[0113] The sacrificial material residue 150_RD may include a polymer containing carbon (C) and hydrogen (H). For example, the sacrificial material residue 150_RD may also include at least one of oxygen (O) or nitrogen (N).

[0114] When sacrificial material residue 150_RD is present on the sidewall 110ST_SW of the lower wiring structure Figure 4 The thickness of the first wiring protective film 150_S1 can be measured based on the sidewall 110ST_SW of the lower wiring structure.

[0115] Figure 11 and Figure 12 This is a diagram used to illustrate a semiconductor device according to some embodiments. Figure 13 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main description and use will be... Figures 1 to 4 The differences described.

[0116] Reference Figure 11 and Figure 12 In a semiconductor device according to some embodiments, the lower wiring structure 110ST may include a lower wiring barrier film 121 and a lower wiring fill film 122.

[0117] The lower wiring filler 122 can be disposed on the lower wiring barrier 121. The lower wiring barrier 121 can extend along the sidewall 122_SW and the bottom surface 122_BS of the lower wiring filler.

[0118] The sidewalls 110ST_SW and bottom surface 110ST_BS of the lower wiring structure can be defined by the lower wiring barrier film 121. The upper surface 110ST_US of the lower wiring structure can be defined by the lower wiring barrier film 121 and the lower wiring filler film 122.

[0119] As an example, the width W11 of the bottom surface 110ST_BS of the lower wiring structure in the first direction DR1 can be the same as the width W12 of the upper surface 110ST_US of the lower wiring structure in the first direction DR1. As another example, the width W11 of the bottom surface 110ST_BS of the lower wiring structure in the first direction DR1 can be smaller than the width W12 of the upper surface 110ST_US of the lower wiring structure in the first direction DR1.

[0120] The bottom wiring barrier film 121 may include at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, a conductive metal oxynitride, or a two-dimensional material (2D material). The bottom wiring barrier film 121 may include, but is not limited to, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), silicon titanium nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), molybdenum (Mo), and two-dimensional materials. The bottom wiring barrier film 121 is shown as a single film, but is not limited thereto.

[0121] The underwire filling film 122 may include a metal. For example, the underwire filling film 122 may include at least one of aluminum (Al), copper (Cu), tungsten (W), or cobalt (Co).

[0122] Two-dimensional materials (2D materials) may include 2D allotropes or 2D compounds, such as, but not limited to, at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide. That is, since the above-described two-dimensional materials are listed by way of example only, the 2D materials that may be included in the semiconductor devices of this disclosure are not limited to the materials described above.

[0123] The etch stop film 191 extends along the upper surface 110ST_US of the lower wiring structure and the upper surface of the fill cover film 145. The etch stop film 191 may include at least one of silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, silicon oxide, or silicon carbonitride.

[0124] The upper wiring structure 210ST can penetrate the etch stop film 191 and connect to the lower wiring structure 110ST.

[0125] Reference Figure 13 In a semiconductor device according to some embodiments, the upper wiring structure 210ST may include an upper wiring barrier film 221 and an upper wiring fill film 222.

[0126] The upper wiring filler film 222 can be disposed on the upper wiring barrier film 221. The upper wiring barrier film 221 can extend along the sidewalls and bottom surface of the upper wiring filler film 222.

[0127] The material included in the upper wiring barrier film 221 may be substantially the same as that described with respect to the lower wiring barrier film 121. The material included in the upper wiring filler film 222 may be substantially the same as that described with respect to the lower wiring filler film 122.

[0128] Figure 14 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main description and use will be... Figures 1 to 4 The differences described.

[0129] For reference only. Figure 14 An example diagram is shown, taken along the first gate electrode GE.

[0130] exist Figure 14 In the diagram, the fin pattern AF is shown extending in the second direction DR2, and the first gate electrode GE is shown extending in the first direction DR1, but the embodiment is not limited thereto.

[0131] Reference Figure 14 According to some embodiments, a semiconductor device may include a transistor TR disposed between a substrate 10 and a lower wiring structure 110ST.

[0132] The substrate 10 may be a silicon substrate or silicon-on-insulator (SOI). In contrast, the substrate 10 may include, but is not limited to, silicon-germanium, silicon-germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0133] The transistor TR includes a fin pattern AF, a first gate electrode GE located on the fin pattern AF, and a first gate insulating film GI located between the fin pattern AF and the first gate electrode GE.

[0134] Although not shown, the transistor TR may include source / drain patterns disposed on both sides of the first gate electrode GE.

[0135] The fin pattern AF may protrude from the substrate 10. The fin pattern AF may extend elongatedly in the second direction DR2. The fin pattern AF may be part of the substrate 10 and may include an epitaxial layer grown from the substrate 10. The fin pattern AF may include, for example, silicon or germanium as an elemental semiconductor material. Furthermore, the fin pattern AF may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0136] Group IV-IV compound semiconductors may include, for example, binary or ternary compounds comprising at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds obtained by doping these elements with group IV elements. Group III-V compound semiconductors may be, for example, at least one of binary, ternary, or quaternary compounds formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), and antimony (Sb), which are group V elements.

[0137] A field insulating film 15 may be formed on the substrate 10. The field insulating film 15 may be formed on a portion of the sidewall of the fin pattern AF. The fin pattern AF may protrude upward from the upper surface of the field insulating film 15. For example, the field insulating film 15 may include an oxide film, a nitride film, an oxide oxynitride film, or a combination thereof.

[0138] The first gate electrode GE can be disposed on the fin pattern AF. The first gate electrode GE can extend in the first direction DR1. The first gate electrode GE can intersect with the fin pattern AF.

[0139] The first gate electrode GE may include at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal nitride, and a conductive metal oxide.

[0140] A first gate insulating film GI may be disposed between the first gate electrode GE and the fin pattern AF, and between the first gate electrode GE and the field insulating film 15. The first gate insulating film GI may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a material with a high dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, at least one of boron nitride, metal oxide, or metal silicon oxide.

[0141] The semiconductor device according to some embodiments may include an NC (negative capacitance) FET that uses a negative capacitor. For example, the first gate insulating film GI may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0142] Ferroelectric films can have negative capacitance, and paraelectric films can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance is less than the capacitance of each individual capacitor. On the other hand, if at least one of the two or more capacitors connected in series has a negative capacitance, the total capacitance can be positive while being greater than the absolute value of each individual capacitor.

[0143] When a ferroelectric film with negative capacitance and a paraelectric film with positive capacitance are connected in series, the total capacitance of the two films connected in series can be increased. By using the increased total capacitance, a transistor including a ferroelectric film can have a subthreshold swing (SS) of less than 60 mV / ten times at room temperature.

[0144] Ferroelectric material films can possess ferroelectric properties. Ferroelectric material films can include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanate, barium titanate, or lead zirconate titanate. Here, as an example, hafnium zirconium oxide can be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide can be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0145] Ferroelectric material films may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the type of ferroelectric material included in the film.

[0146] When the ferroelectric material film includes hafnium oxide, the dopants included in the ferroelectric material film may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) or yttrium (Y).

[0147] When the dopant is aluminum (Al), the ferroelectric film can include 3 at% to 8 at% (atomic percentage) aluminum. Here, the dopant ratio can be the sum of aluminum and hafnium aluminum.

[0148] When the dopant is silicon (Si), the ferroelectric film may include 2 at% to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric film may include 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric film may include 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric film may include 50 at% to 80 at% zirconium.

[0149] The paraelectric material film may possess paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, or aluminum oxide, but is not limited thereto.

[0150] Ferroelectric and paraelectric material films can comprise the same material. Ferroelectric material films exhibit ferroelectric properties, but paraelectric material films may not. For example, when both ferroelectric and paraelectric material films include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film differs from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0151] Ferroelectric material films can have a thickness that exhibits ferroelectric properties. The thickness of a ferroelectric material film can be, for example, but not limited to, 0.5 nm to 10 nm. Since the critical thickness for exhibiting ferroelectric properties can vary for each ferroelectric material, the thickness of the ferroelectric material film can vary depending on the ferroelectric material.

[0152] As an example, the first gate insulating film GI may include a single ferroelectric material film. As another example, the first gate insulating film GI may include multiple ferroelectric material films spaced apart from each other. The first gate insulating film GI may have a stacked film structure in which multiple ferroelectric material films and multiple paraelectric material films are stacked alternately.

[0153] The gate overlay pattern GE_CAP can be disposed on the first gate electrode GE. The lower wiring structure 110ST can be disposed on the first gate electrode GE. The lower wiring structure 110ST is shown not connected to the first gate electrode GE, but is not limited thereto.

[0154] The first interlayer insulating film 180 may be disposed on the gate cover pattern GE_CAP. The first interlayer insulating film 180 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material.

[0155] The lower wiring structure 110ST can be disposed in the first interlayer insulating film 180. As an example, the first interlayer insulating film 180 can correspond to... Figure 2 The lower interlayer insulating film 50. Although not shown, a lower conductive pattern may be provided inside the first interlayer insulating film 180. Figure 2 (60).

[0156] As another example, the first interlayer insulating film 180 and the gate cover pattern GE_CAP can correspond to Figure 2 The lower interlayer insulating film 50. Although not shown, a lower conductive pattern may be provided inside the first interlayer insulating film 180 and the gate cover pattern GE_CAP. Figure 2 (60).

[0157] Figure 15 This is a diagram used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the main description and use will be... Figure 14 The differences described.

[0158] Reference Figure 15 In a semiconductor device according to some embodiments, a transistor TR may include a nanosheet NS, a first gate electrode GE surrounding the nanosheet NS, and a first gate insulating film GI located between the nanosheet NS and the first gate electrode GE.

[0159] Nanosheets NS can be disposed on the lower fin pattern BAF. The nanosheets NS can be spaced apart from the lower fin pattern BAF on the third-direction DR3. The transistor TR is shown as comprising three nanosheets NS spaced apart on the third-direction DR3, but the embodiment is not limited thereto. It goes without saying that the number of nanosheets NS disposed on the lower fin pattern BAF on the third-direction DR3 can be greater than three or less than three.

[0160] Each of the lower fin pattern BAF and the nanosheet NS can include, for example, silicon or germanium as an elemental semiconductor material. Each of the lower fin pattern BAF and the nanosheet NS can include a compound semiconductor, and can include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The lower fin pattern BAF and the nanosheet NS can include the same material or different materials.

[0161] Figures 16 to 18 These are diagrams used to illustrate semiconductor devices according to some embodiments. For reference, Figure 16 This is a top view used to illustrate a semiconductor device according to some embodiments. Figure 17 It is along Figure 16 The sectional view taken by lines BB and CC. Figure 18 It is along Figure 16 The sectional view taken by line DD.

[0162] Reference Figures 16 to 18 The logic cell LC can be disposed on the substrate 10. The logic cell LC can refer to a logic element that performs a specific function (e.g., an inverter, a flip-flop, etc.). The logic cell LC can include vertical transistors (vertical FETs) that constitute the logic element and wiring that connects the vertical transistors to each other.

[0163] The logic cell LC on the substrate 10 may include a first active region RX1 and a second active region RX2. For example, the first active region RX1 may be a PMOSFET region, and the second active region RX2 may be an NMOSFET region. The first active region RX1 and the second active region RX2 may be defined by a trench T_CH formed in the upper portion of the substrate 10. The first active region RX1 and the second active region RX2 may be spaced apart from each other in a first direction DR1.

[0164] A first lower epitaxial pattern SPO1 can be disposed on a first active region RX1, and a second lower epitaxial pattern SPO2 can be disposed on a second active region RX2. From a top view, the first lower epitaxial pattern SPO1 can overlap with the first active region RX1, and the second lower epitaxial pattern SPO2 can overlap with the second active region RX2. The first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 can be epitaxial patterns formed by a selective epitaxial growth process. The first lower epitaxial pattern SPO1 can be disposed within a first recessed region RS1 of the substrate 10, and the second lower epitaxial pattern SPO2 can be disposed within a second recessed region RS2 of the substrate 10.

[0165] A first active pattern AP1 can be disposed on a first active region RX1, and a second active pattern AP2 can be disposed on a second active region RX2. Each of the first active pattern AP1 and the second active pattern AP2 can have a vertically protruding fin shape. From a top view perspective, each of the first active pattern AP1 and the second active pattern AP2 can have a strip shape extending in a first direction DR1. The first active pattern AP1 can be arranged along a second direction DR2, and the second active pattern AP2 can be arranged along a second direction DR2.

[0166] Each of the first active patterns AP1 may include a first channel pattern CHP1 that protrudes vertically from the first lower epitaxial pattern SpO1 and a first upper epitaxial pattern DOP1 located on the first channel pattern CHP1. Each of the second active patterns AP2 may include a second channel pattern CHP2 that protrudes vertically from the second lower epitaxial pattern SpO2 and a second upper epitaxial pattern DOP2 located on the second channel pattern CHP2.

[0167] A device isolation film ST can be disposed on the substrate 10 to fill the trench T_CH. The device isolation film ST can cover the upper surfaces of the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2. The first active pattern AP1 and the second active pattern AP2 can protrude vertically above the device isolation film ST.

[0168] A plurality of second gate electrodes 420 extending parallel to each other in a first direction DR1 can be disposed on an element isolation film ST. The second gate electrodes 420 can be arranged along a second direction DR2. The second gate electrodes 420 can surround a first channel pattern CHP1 of a first active pattern AP1 and a second channel pattern CHP2 of a second active pattern AP2. For example, the first channel pattern CHP1 of the first active pattern AP1 can have first sidewalls SW1 to fourth sidewalls SW4. The first sidewalls SW1 and second sidewalls SW2 can be opposite each other in the second direction DR2, and the third sidewalls SW3 and fourth sidewalls SW4 can be opposite each other in the first direction DR1. The second gate electrodes 420 can be disposed on the first sidewalls SW1 to fourth sidewalls SW4. In other words, the second gate electrodes 420 can surround the first sidewalls SW1 to fourth sidewalls SW4.

[0169] The second gate insulating film 430 may be located between each of the first channel pattern CHP1 and the second channel pattern CHP2 and the second gate electrode 420. The second gate insulating film 430 may cover the bottom surface of the second gate electrode 420 and the inner sidewall of the second gate electrode 420. For example, the second gate insulating film 430 may directly cover the first sidewall SW1 to the fourth sidewall SW4 of the first active pattern AP1.

[0170] The first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 protrude vertically above the second gate electrode 420. The upper surface of the second gate electrode 420 may be lower than the bottom surface of each of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. In other words, each of the first active pattern AP1 and the second active pattern AP2 may have a structure that protrudes vertically from the substrate 10 and penetrates the second gate electrode 420.

[0171] The semiconductor device according to some embodiments may include a vertical transistor in which charge carriers move along a third-direction DR3. For example, when a voltage is applied to the second gate electrode 420 and the transistor is “turned on,” charge carriers can move from the lower epitaxial patterns SOP1 and SOP2 to the upper epitaxial patterns DOP1 and DOP2 through the channel patterns CHP1 and CHP2. In the semiconductor device according to some embodiments, the second gate electrode 420 may completely surround the sidewalls SW1 to SW4 of the channel patterns CHP1 and CHP2. The transistor according to this disclosure may be a three-dimensional field-effect transistor (e.g., a VFET) with a gate-all-around structure. Because the gate surrounds the channel, the semiconductor device according to some embodiments may have excellent electrical characteristics.

[0172] Spacers 440 covering the second gate electrode 420 and the first active pattern AP1 and the second active pattern AP2 can be disposed on the device isolation film ST. Spacers 440 may comprise silicon nitride or silicon oxynitride. Spacers 440 may comprise a lower spacer 440LS, an upper spacer 440US, and a gate spacer 440GS located between the lower spacer 440LS and the upper spacer 440US.

[0173] The lower spacer 440LS can directly cover the upper surface of the device isolation film ST. The lower spacer 440LS can separate the second gate electrode 420 from the device isolation film ST on the third-direction DR3. The gate spacer 440GS can cover the upper surface and outer sidewall of each of the second gate electrodes 420. The upper spacer 440 can cover the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. However, the upper spacer 440US can not cover the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2, and can expose the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0174] The first portion 195BP of the second interlayer insulating film can be disposed on the spacer 440. The upper surface of the first portion 195BP of the second interlayer insulating film can be substantially coplanar with the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. The second portion 195UP of the second interlayer insulating film and the first interlayer insulating film 180 can be stacked sequentially on the first portion 195BP of the second interlayer insulating film. The first portion 195BP and the second portion 195UP of the second interlayer insulating film can be included in the second interlayer insulating film 195. The second portion 195UP of the second interlayer insulating film can cover the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0175] At least one first source / drain contact 470 may be provided, penetrating the second portion 195UP of the second interlayer insulating film and connected to the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. At least one second source / drain contact 570 may be provided, penetrating the second interlayer insulating film 195, the lower spacer 440LS, and the element isolation film ST, and connected to the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2. A gate contact 480 may be provided, sequentially penetrating the second portion 195UP of the second interlayer insulating film, the first portion 195BP of the second interlayer insulating film, and the gate spacer 440GS, and connected to the second gate electrode 420.

[0176] A lower etch stop film 156 may be further disposed between the second portion 195UP of the second interlayer insulating film and the first interlayer insulating film 180.

[0177] The lower wiring structure 110ST can be disposed within the first interlayer insulating film 180. Detailed descriptions of the lower wiring structure 110ST, upper wiring structure 210ST, padding cover film 140, filler cover film 145, and wiring protective film 150 can be found in the above reference. Figures 1 to 13 The descriptions are essentially the same.

[0178] Figures 19 to 25 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments.

[0179] Reference Figure 19 A lower conductive pattern 60 can be formed inside the lower interlayer insulating film 50.

[0180] Next, a metal material film 120P and a cover film 130P can be sequentially formed on the lower interlayer insulating film 50 and the lower conductive pattern 60.

[0181] Unlike the example shown, the lower interlayer insulating film 50 can be disposed on the substrate ( Figure 14 , Figure 15 , Figure 17 and Figure 18 10) above.

[0182] Reference Figure 20 The metal material film 120P and the cover film 130P can be patterned through an etching process.

[0183] More specifically, an etching mask can be formed on the cover film 130P. Some of the metal material film 120P and the cover film 130P can be removed using the etching mask. Next, the etching mask can be removed.

[0184] Thus, multiple lower wiring structures 110ST can be formed on the lower interlayer insulating film 50. Each lower wiring structure 110ST may include a lower wiring 120 and a lower wiring insulating cover film 130.

[0185] The lower cabling structure 110ST can be separated in the first direction DR1 by the cabling isolation trench 110_T.

[0186] Reference Figure 21 A sacrificial material film 110SC can be formed between adjacent lower wiring structures 110ST on the first direction DR1.

[0187] The sacrificial material film 110SC can be formed on the lower interlayer insulating film 50 and the lower conductive pattern 60. The sacrificial material film 110SC can fill a portion of the wiring isolation trench 110_T.

[0188] The sacrificial material film 110SC may cover a portion of the sidewall 110ST_SW of the lower wiring structure. The sacrificial material film 110SC is not formed on the upper surface 110ST_US of the lower wiring structure. The sacrificial material film 110SC does not cover the upper surface 110ST_US of the lower wiring structure.

[0189] The sacrificial material membrane 110SC may include a polymer containing carbon (C) and hydrogen (H). For example, the sacrificial material membrane 110SC may further include at least one of oxygen (O) or nitrogen (N) in the polymer containing carbon (C) and hydrogen (H).

[0190] The sacrificial material film 110SC can be formed by a deposition process or a coating process. As an example, the sacrificial material film 110SC may have the property of decomposing into monomers when heat of 150°C or higher is applied to the sacrificial material film 110SC. As another example, the sacrificial material film 110SC may have the property of decomposing into monomers when irradiated with ultraviolet light (UV).

[0191] Reference Figure 22 A padding cover film 140 can be formed on the sacrificial material film 110SC and the lower wiring structure 110ST.

[0192] The liner cover film 140 may extend along the upper surface 110ST_US of the lower wiring structure and the upper surface of the sacrificial material film 110SC. The liner cover film 140 may extend along the remainder of the sidewall 110ST_SW of the lower wiring structure. The remainder of the sidewall 110ST_SW of the lower wiring structure may be a sidewall of the lower wiring structure 110ST that protrudes beyond the upper surface of the sacrificial material film 110SC.

[0193] For example, the liner cover film 140 can be formed using an atomic layer deposition (ALD) method. Although not shown, pinholes can be formed in the liner cover film 140 during its formation.

[0194] Reference Figure 22 and Figure 23 The sacrificial material membrane 110SC can be removed using the post-processing technology 110HT.

[0195] Therefore, a wiring air gap 110_AG can be formed between adjacent lower wiring structures 110ST in the first direction DR1.

[0196] As an example, post-processing 110HT may include a heat treatment process. As another example, post-processing 110HT may include an ultraviolet irradiation process. During post-processing 110HT, the sacrificial material film 110SC is broken down into monomers and discharged through pinholes included in the liner cover film 140.

[0197] Reference Figure 24 Flowable insulating material can be deposited on the liner cover film 140, and a filler cover film 145 can be formed on the liner cover film 140.

[0198] During the formation of the fill cover film 145, some of the flowable insulating material can pass through the pinholes included in the pad cover film 140. That is, the flowable insulating material can diffuse into the wiring air gap 110_AG through the pinholes included in the pad cover film 140.

[0199] Flowable insulating material passing through pinholes included in the liner cover film 140 can be deposited on the sidewall 110ST_SW of the lower wiring structure. Therefore, a wiring protection film 150 can be formed on the sidewall 110ST_SW of the lower wiring structure. The fluid insulating material can be cured simultaneously with the process.

[0200] Reference Figure 25 The padding cover film 140 and the filling cover film 145 located on the upper surface 110ST_US of the lower wiring structure can be removed.

[0201] The upper surface 110ST_US of the lower wiring structure can be exposed.

[0202] Next, refer to Figure 2 An upper wiring structure 210ST can be formed on the lower wiring structure 110ST.

[0203] In one embodiment, a method of manufacturing a semiconductor device is provided, the method comprising: forming a lower conductive pattern; sequentially forming a metal material layer and a capping film on the lower conductive pattern; patterning the metal material layer and the capping film to form a plurality of wiring structures, each of the wiring structures including a line wiring and a wiring insulating capping film; forming a sacrificial material layer between adjacent wiring structures in the wiring structures, the sacrificial material layer covering a portion of the sidewall of each wiring structure; forming a padding capping film on the wiring structures and the sacrificial material layer, the padding capping film extending along an upper surface of each wiring structure, an upper surface of the sacrificial material layer, and the remainder of the sidewall of each wiring structure; removing the sacrificial material layer to form a wiring air gap between the wiring structures; after forming the wiring air gap, depositing a flowable insulating material to form a fill capping film on the padding capping film; and simultaneously forming a wiring protective film on the sidewall of each wiring structure by allowing a portion of the flowable insulating material to pass through the padding capping film while forming the fill capping film.

[0204] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be implemented in various different forms. Those skilled in the art will understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

Claims

1. A semiconductor device, the semiconductor device comprising: Lower conductive pattern; A first wiring structure is disposed on the lower conductive pattern, extends in a first direction, and includes an upper surface and a bottom surface opposite to each other in a second direction different from the first direction. The bottom surface of the first wiring structure faces the lower conductive pattern. The first wiring structure also includes a sidewall connecting the upper surface of the first wiring structure to the bottom surface of the first wiring structure. as well as A first wiring protective film is in contact with the first wiring structure and extends along the sidewall of the first wiring structure. The first wiring protective film includes a coverage area covering the sidewall of the first wiring structure, and multiple protruding areas. Each of the plurality of protruding regions of the first wiring protection film protrudes from the covered area of ​​the first wiring protection film along a third direction different from the first direction and the second direction.

2. The semiconductor device according to claim 1, further comprising: A padding cover film is disposed on the first wiring protection film and contacts the sidewall of the first wiring structure; as well as A filling cover film is disposed on the padding cover film.

3. The semiconductor device according to claim 2, in, The filling cover film comprises the same material as the first wiring protection film.

4. The semiconductor device according to claim 1, further comprising: A second wiring structure is disposed on the lower conductive pattern and spaced apart from the first wiring structure in the third direction. as well as A second wiring protective film is in contact with the second wiring structure and extends along the sidewall of the second wiring structure. The sidewall of the second wiring structure faces the sidewall of the first wiring structure. The second wiring protection film includes a coverage area that covers the sidewall of the second wiring structure, and a plurality of protruding areas that protrude from the coverage area of ​​the second wiring protection film in a third direction.

5. The semiconductor device according to claim 4, further comprising: A connecting wiring protection film is provided, which connects the first wiring protection film and the second wiring protection film.

6. The semiconductor device according to claim 4, further comprising: A wiring air gap is provided between the first wiring structure and the second wiring structure.

7. The semiconductor device according to claim 1, in, The first wiring protection film comprises an insulating material containing silicon (Si) and oxygen (O).

8. The semiconductor device according to claim 7, in, The first wiring protection film further includes at least one of carbon (C), nitrogen (N) or hydrogen (H).

9. The semiconductor device according to claim 1, in, The first wiring structure includes wiring and a wiring insulation covering film extending along the upper surface of the wiring. The upper surface of the first wiring structure includes the upper surface of the wiring insulation covering film, and The bottom surface of the first wiring structure includes the bottom surface of the line wiring.

10. The semiconductor device according to claim 1, in, The first wiring structure includes a wiring filler film and a wiring barrier film extending along the sidewalls and bottom surface of the wiring filler film.

11. A semiconductor device, the semiconductor device comprising: Lower conductive pattern; A first wiring structure is disposed on the lower conductive pattern, extends in a first direction, and includes an upper surface and a bottom surface opposite to each other in a second direction different from the first direction. The bottom surface of the first wiring structure faces the lower conductive pattern. The first wiring structure also includes a sidewall connecting the upper surface of the first wiring structure to the bottom surface of the first wiring structure. as well as A wiring protective film, which contacts the first wiring structure and extends along the sidewall of the first wiring structure. Wherein, the first thickness of the wiring protective film at the first point of the wiring protective film in a third direction different from the first direction and the second direction is greater than the second thickness of the wiring protective film at the second point of the wiring protective film in the third direction. At the third point of the wiring protection film, the third thickness of the wiring protection film in the third direction is greater than the second thickness. The height from the bottom surface of the first wiring structure to the first point is less than the height from the bottom surface of the first wiring structure to the second point, and The height from the bottom surface of the first wiring structure to the third point is greater than the height from the bottom surface of the first wiring structure to the second point.

12. The semiconductor device according to claim 11, in, At the fourth point of the wiring protection film, the fourth thickness of the wiring protection film in the third direction is less than the third thickness, and The height from the bottom surface of the first wiring structure to the fourth point is greater than the height from the bottom surface of the first wiring structure to the third point.

13. The semiconductor device of claim 11, further comprising: A padding cover film is disposed on the wiring protection film and extends along the sidewall of the first wiring structure; as well as A filling cover film, wherein the filling cover film is disposed on the padding cover film. The padding covering film is in contact with the wiring protection film and the first wiring structure.

14. The semiconductor device according to claim 13, in, The wiring protection film comprises an insulating material containing silicon (Si) and oxygen (O), and The filling cover film comprises the same material as the wiring protection film.

15. The semiconductor device of claim 11, further comprising: A second wiring structure is disposed on the lower conductive pattern and spaced apart from the first wiring structure in the third direction. The wiring protective film extends along the sidewall of the second wiring structure and contacts the second wiring structure.

16. The semiconductor device of claim 15, further comprising: A wiring air gap is provided between the first wiring structure and the second wiring structure.

17. The semiconductor device according to claim 11, in, The first wiring structure includes wiring and a wiring insulation covering film extending along the upper surface of the wiring. The upper surface of the first wiring structure includes the upper surface of the wiring insulation covering film, and The bottom surface of the first wiring structure includes the bottom surface of the line wiring.

18. A semiconductor device, the semiconductor device comprising: Lower conductive pattern; A first wiring structure is disposed on the lower conductive pattern and extends in a first direction; A second wiring structure extends in the first direction and is spaced apart from the first wiring structure in a second direction perpendicular to the first direction; A wiring protection film is disposed on the lower conductive pattern, extends along the sidewalls of the first wiring structure and the second wiring structure, and contacts the first wiring structure and the second wiring structure; A wiring air gap is provided between the first wiring structure and the second wiring structure; A padding cover film is disposed on the wiring protection film and the wiring air gap, extends along the sidewalls of the first wiring structure and the second wiring structure, and contacts the first wiring structure and the second wiring structure; as well as A filling cover film is disposed on the padding cover film between the first wiring structure and the second wiring structure. The wiring protection film includes a coverage area covering the sidewall of the first wiring structure, and multiple protruding areas. Each of the plurality of protruding regions of the wiring protection film protrudes from the coverage area of ​​the wiring protection film along the second direction.

19. The semiconductor device according to claim 18, in, In the cross-sectional view of the semiconductor device, the wiring air gap is covered by the wiring protective film and the padding cover film.

20. The semiconductor device according to claim 18, in, The first wiring structure includes an upper surface and a bottom surface facing each other in a third direction, the third direction being perpendicular to the first direction and the second direction. The bottom surface of the first wiring structure faces the lower conductive pattern. The width of the upper surface of the first wiring structure in the second direction is less than or equal to the width of the bottom surface of the first wiring structure in the second direction.

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