Wafer hybrid bonding structure and method

Abstract

A wafer hybrid bonding structure and method are disclosed. The method includes: a bonding structure comprising a first wafer structure and a second wafer structure bonded together, the first wafer structure comprising a first wafer with opposing first and second surfaces, the first wafer structure further comprising a first dielectric layer on the first surface and a first electrical interconnect layer within the first dielectric layer, the first surface facing the second wafer structure, the bonding structure having a grinding groove at its edge extending from the second surface toward the first surface; a second dielectric layer on the second surface of the first wafer; a conductive plug within the second dielectric layer and the first wafer structure, the conductive plug penetrating the second dielectric layer and the first wafer and located on the surface of the first electrical interconnect layer; and a protective layer on the sidewall of the grinding groove, wherein the protective layer reduces the risk of circuit failure by protecting the sidewall of the grinding groove.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer hybrid bonding structure and method. Background Technology

[0002] As the development of very large-scale integrated circuits (VLSI) approaches its physical limits, three-dimensional integrated circuits, with their advantages in physical size and cost, represent an effective way to extend Moore's Law and solve advanced packaging problems. Wafer bonding is a technology that uses external energy to bond atoms at the wafer interface together through van der Waals forces, molecular forces, and even atomic forces.

[0003] Hybrid bonding is a commonly used wafer bonding method widely applied in the 3D chip industry, such as in the bonding of CMOS image sensors, Dynamic Random Access Memory (DRAM), and logic devices. Hybrid bonding technology can simultaneously bond two wafers together to achieve internal interconnections of thousands of chips, significantly improving chip performance and reducing costs.

[0004] However, existing wafer hybrid bonding technology needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a wafer hybrid bonding structure and method to improve the performance of the formed hybrid bonding structure.

[0006] To address the aforementioned technical problems, the present invention provides a wafer hybrid bonding structure, comprising: a bonding structure including a first wafer structure and a second wafer structure bonded together, the first wafer structure including a first wafer with opposing first and second surfaces, the first wafer structure further including a first dielectric layer located on the first surface and a first electrical interconnect layer located within the first dielectric layer, the first surface facing the second wafer structure, the bonding structure having a grinding groove at its edge extending from the second surface towards the first surface; a second dielectric layer located on the second surface of the first wafer; a conductive plug located within the second dielectric layer and the first wafer structure, the conductive plug penetrating the second dielectric layer and the first wafer, and located on the surface of the first electrical interconnect layer; a protective layer located on the sidewall of the grinding groove; and a redistribution layer located on the surface of the conductive plug and a portion of the surface of the second dielectric layer.

[0007] Optionally, it further includes: a first passivation layer located on the surfaces of the second dielectric layer and the redistribution layer, the first passivation layer having a solder pad layer located on a portion of the surface of the redistribution layer.

[0008] Optionally, the material of the protective layer includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0009] Optionally, the included angle between the sidewall surface and the bottom surface of the grinding port ranges from 88 degrees to 92 degrees.

[0010] Optionally, the ratio of the height of the grinding chute to the width of the grinding chute is in the range of 40:1 to 60:1.

[0011] Optionally, the thickness of the protective layer ranges from 800 angstroms to 1500 angstroms.

[0012] Accordingly, the technical solution of the present invention also provides a wafer hybrid bonding method, comprising: providing a bonding structure, the bonding structure comprising a first wafer structure and a second wafer structure bonded together, the first wafer structure comprising a first wafer, the first wafer comprising a first surface and a second surface opposite to each other, the first wafer structure further comprising a first dielectric layer located on the first surface and a first electrical interconnect layer located within the first dielectric layer, the first surface facing the second wafer structure, the edge of the bonding structure having a grinding port, the grinding port extending from the second surface toward the first surface; forming a second dielectric layer on the second surface of the first wafer; forming a conductive plug within the second dielectric layer and the first wafer structure, the conductive plug penetrating the second dielectric layer and the first wafer, and located on the surface of the first electrical interconnect layer; and forming a protective layer on the sidewall of the grinding port.

[0013] Optionally, after forming the protective layer, the method further includes: forming a redistribution layer on the surface of the conductive plug and a portion of the surface of the second dielectric layer; forming a first passivation layer on the surfaces of the second dielectric layer and the redistribution layer, and forming a solder pad layer on the first passivation layer, the solder pad layer being located on a portion of the surface of the redistribution layer.

[0014] Optionally, the method for forming the protective layer includes: forming a protective material layer on the second surface of the first wafer structure and the sidewall of the grinding port; etching the protective material layer along the normal direction of the second surface until the second surface is exposed to form the protective layer.

[0015] Optionally, the process for forming the protective material layer includes atomic layer deposition (ALD); the process parameters of ALD include: the reaction gas includes one or both of O2 and H2O, the protective gas includes H2, the gas flow rate ranges from 600 sccm to 800 sccm, and the gas pressure ranges from 2 bar to 4 bar.

[0016] Optionally, before forming the protective material layer, the bonding structure is further treated with EBR edge cleaner.

[0017] Optionally, the etching process for the protective material layer includes anisotropic dry etching; the process parameters of the anisotropic dry etching process include: the etching gas includes one or both of C4F8 and CH3F, the radio frequency is 40MHz, and the gas pressure in the etching chamber is in the range of 30mT to 50mT.

[0018] Optionally, the method for forming the protective layer includes: forming a mask layer on the second surface of the first wafer structure; forming the protective layer on the sidewall of the first wafer structure; and removing the mask layer after forming the protective layer.

[0019] Optionally, the material of the protective layer includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0020] Optionally, the included angle between the sidewall surface and the bottom surface of the grinding port ranges from 88 degrees to 92 degrees.

[0021] Optionally, the ratio of the height of the grinding chute to the width of the grinding chute is in the range of 40:1 to 60:1.

[0022] Optionally, the thickness of the protective layer ranges from 800 angstroms to 1500 angstroms.

[0023] Optionally, the protective layer is formed after the conductive plug is formed.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0025] In the wafer hybrid bonding structure provided by the technical solution of the present invention, the protective layer protects the metal material that may be exposed at the edge of the bonding structure, reducing the abnormal discharge that may occur in the subsequent plasma etching process, thereby reducing the risk of circuit failure and improving the stability of device performance.

[0026] In the wafer hybrid bonding method provided by the present invention, the protective layer protects the metal material exposed during the grinding process, reducing the abnormal discharge that may occur in the subsequent plasma etching process, thereby reducing the risk of circuit failure and improving the stability of device performance.

[0027] Furthermore, forming the protective layer after forming the conductive plug can reduce the probability of the conductive plug being exposed at the edge of the bonding structure, reduce the occurrence of abnormal discharges in subsequent plasma etching processes, thereby reducing the risk of circuit failure and improving the stability of device performance. Attached Figure Description

[0028] Figures 1 to 3 This is a schematic diagram of the steps in a wafer hybrid bonding method;

[0029] Figures 4 to 8 This is a schematic diagram of the structure of each step of a hybrid bonding method according to an embodiment of the present invention. Detailed Implementation

[0030] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0031] As mentioned in the background section, the performance of hybrid bonding structures formed using existing hybrid bonding technologies urgently needs improvement. This paper will now illustrate and analyze a wafer hybrid bonding method.

[0032] Figures 1 to 3 This is a schematic diagram of the steps in a wafer hybrid bonding method.

[0033] Please refer to Figure 1 A first wafer structure 10 and a second wafer structure 20 are provided bonded to each other. The first wafer structure 10 includes a first wafer 100, which includes a first surface 10a and a second surface 10b opposite to each other. The first wafer structure 10 also includes a first dielectric layer 101 located on the first surface 10a and an electrical interconnect layer 102 located within the first dielectric layer 101. The first surface faces the second wafer structure 20.

[0034] Please refer to Figure 2 The edge of the first wafer structure 10 is trimmed, forming a trimming opening 103 between the sidewall of the first wafer structure 10 and the surface of the second wafer structure 20.

[0035] Please refer to Figure 3 The first wafer 100 is thinned from the second surface 10b; after the thinning process, a second dielectric layer 104 is formed on the second surface 10b; a through-silicon via (TSV) structure 105 is formed in the second dielectric layer 104 and within the first wafer structure 10; a redistribution layer 106 is formed on the surface of the TSV structure 105 and a portion of the surface of the second dielectric layer 104; a passivation layer 107 is formed on the surface of the second dielectric layer 104, the passivation layer 107 having an opening (not shown in the figure); and a pad layer 108 is formed within the opening.

[0036] In the above-mentioned wafer hybrid bonding process, during the grinding process, there is a certain probability that the metal material of the electrical interconnect layer 102 will be exposed on the sidewall of the first wafer structure 10.

[0037] However, since the sidewall of the first wafer structure 10 is perpendicular to the surface of the second wafer structure 20, and the grinding port 103 is relatively high, in subsequent material deposition processes, such as photoresist deposition and chemical vapor deposition of dielectric materials, it is difficult for the material film to cover the sidewall of the first wafer structure 10, which will cause the metal material to remain exposed. In some processes, such as plasma etching to form the passivation layer 107, the exposed metal material is prone to arcing abnormalities, which may even cause the circuit area inside the wafer to be destroyed, resulting in circuit failure.

[0038] To address the aforementioned issues, the present invention provides a wafer hybrid bonding structure and method in which a protective layer protects the metal material exposed during the grinding process, reducing abnormal discharges during subsequent plasma etching processes, thereby reducing the risk of circuit failure and improving the stability of device performance.

[0039] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] Figures 4 to 8 This is a schematic diagram of the structure of each step of a hybrid bonding method according to an embodiment of the present invention.

[0041] Please refer to Figure 4 A bonding structure is provided, the bonding structure including a first wafer structure 31 and a second wafer structure 32 bonded to each other, the first wafer structure 31 including a first wafer 300, the first wafer 300 including a first surface 30a and a second surface 30b opposite to each other, the first wafer structure 31 also including a first dielectric layer 301 located on the first surface 30a and a first electrical interconnect layer 302 located within the first dielectric layer 301, the first surface 30a facing the second wafer structure 32, the bonding structure having a grinding hole 33 at its edge, the grinding hole 33 extending from the second surface 30b toward the first surface 30a.

[0042] The included angle α between the sidewall of the first wafer structure 31 and the surface of the second wafer structure 32 ranges from 88 degrees to 92 degrees. In this embodiment, the included angle α between the sidewall surface and the bottom surface of the grinding port 33 is 90 degrees.

[0043] The ratio of the height H of the grinding aperture 33 to the width L of the grinding aperture 33 ranges from 40:1 to 60:1. In this embodiment, the ratio of the height H of the grinding aperture 33 to the width L of the grinding aperture 33 is 50:1.

[0044] In this embodiment, the first electrical interconnect layer 302 includes several interconnected first metal layers (not shown in the figure).

[0045] In this embodiment, the first wafer structure 31 further includes a first bonding metal layer (not shown in the figure) located within the first dielectric layer 301, and the first bonding metal layer is electrically connected to the first electrical interconnect layer 302.

[0046] In this embodiment, the second wafer structure 32 includes a second wafer (not shown in the figure), a third dielectric layer (not shown in the figure) located on the surface of the second wafer, a second electrical interconnect layer (not shown in the figure) located within the third dielectric layer, and a second bonding metal layer (not shown in the figure). The second electrical interconnect layer and the second bonding metal layer are electrically connected to each other, the second bonding metal layer and the first bonding metal layer are bonded to each other, and the first dielectric layer and the third dielectric layer are bonded to each other.

[0047] In this embodiment, the method for forming the mutually bonded first wafer structure 31 and second wafer structure 32 includes: forming mutually bonded initial first wafer structure (not shown in the figure) and second wafer structure 32, wherein the initial first wafer structure includes an initial second wafer (not shown in the figure), an initial first dielectric layer (not shown in the figure) located on the surface of the initial second wafer, a first electrical interconnect layer and a second bonding metal layer located within the initial first dielectric layer, the second bonding metal layer and the first bonding metal layer being mutually bonded, and the initial first dielectric layer and the third dielectric layer being mutually bonded; grinding the initial first wafer structure and the second wafer from the edge to form the bonding structure and the grinding hole 33, forming the first dielectric layer 301 with the initial first dielectric layer, and forming the first wafer 300 with the initial first wafer.

[0048] In this embodiment, the bottom of the grinding port 33 is located within the third medium layer.

[0049] In another embodiment, the bottom surface of the grinding port may expose the surface of the second wafer structure.

[0050] In another embodiment, the bottom of the grinding port may be located within the second wafer.

[0051] Here, during the grinding process, there is a certain probability that the metal material of the first electrical interconnect layer 302 will be exposed on the sidewall of the first wafer structure 31. Figure 4 (The area indicated by the dashed circle).

[0052] Please refer to Figure 5 A second dielectric layer 303 is formed on the second surface 30b of the first wafer 300; a conductive plug 304 is formed in the second dielectric layer 303 and the first wafer structure 31, the conductive plug 304 penetrating the second dielectric layer 303 and the first wafer 300, and located on the surface of the first electrical interconnect layer 302.

[0053] The formation process of the second dielectric layer 303 includes chemical vapor deposition. In this embodiment, the chemical vapor deposition process is plasma enhanced chemical vapor deposition (PECVD), which has a faster deposition rate but poor coverage of the sidewall of the grinding port 33.

[0054] The conductive plug 304 can be formed on any of the first metal layers. In this embodiment, the conductive plug 304 is formed on the first metal layer closest to the first wafer 300.

[0055] In this embodiment, the method for forming the conductive plug 304 includes: forming a via (not shown in the figure) in the second dielectric layer 303 and the first wafer structure 31, wherein the via exposes a portion of the first electrical interconnect layer 302; forming a barrier material layer (not shown in the figure) on the surface of the via and the second dielectric layer 303; forming a seed material layer (not shown in the figure) on the surface of the barrier material layer; forming a metal material layer (not shown in the figure) on the surface of the seed material layer; planarizing the metal material layer, the seed material layer and the barrier material layer until the surface of the second dielectric layer 303 is exposed, and forming the conductive plug 304 in the via.

[0056] In this embodiment, the formation process of the barrier material layer and the seed crystal material layer includes atomic layer deposition process to improve the filling capacity in the via.

[0057] In another embodiment, the formation process of the barrier material layer and the seed crystal material layer can be a physical vapor deposition process.

[0058] In this embodiment, the process for forming the metal material layer includes electrochemical plating (ECP).

[0059] In this embodiment, the second surface 30b is further thinned, and after the thinning process, the second dielectric layer 303 is formed.

[0060] Subsequently, a protective layer is formed on the sidewall of the grinding port 33 to protect the metal material exposed during the grinding process.

[0061] In this embodiment, the protective layer is formed after the conductive plug 304 is formed. The method for forming the protective layer is described in [reference needed]. Figures 6 to 7 .

[0062] In another embodiment, a protective layer may be formed on the sidewall of the grinding port after the second dielectric layer is formed and before the conductive plug is formed.

[0063] Please refer to Figure 6 A protective material layer 305 is formed on the second surface 30b of the first wafer structure 31 and the sidewall of the grinding port 33.

[0064] In this embodiment, the protective material layer 305 is formed using an atomic layer deposition (ALD) process. ALD processes improve the uniformity of the thickness of the protective material layer 305 deposited on the sidewall of the grinding head 33.

[0065] In this embodiment, the process parameters of the atomic layer deposition process include: the reactant gas includes one or both of O2 and H2O, the protective gas includes H2, the gas flow rate ranges from 600 sccm to 800 sccm, and the gas pressure ranges from 2 bar to 4 bar. The reason for selecting these process parameters is to make it easier for the protective material layer 305 to be deposited on the sidewall of the grinding nozzle 33, and to obtain a material film with a relatively uniform thickness.

[0066] In this embodiment, before forming the protective material layer 305, the bonding structure is further treated with EBR edge cleaning agent to reduce the adhesion of metal materials to the sidewall of the grinding port 33.

[0067] The material of the protective material layer 305 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0068] In this embodiment, the material of the protective material layer 305 is silicon nitride.

[0069] The thickness d0 of the protective material layer 305 ranges from 800 angstroms to 1500 angstroms. In this embodiment, the thickness d0 of the protective material layer 305 is 1000 angstroms. The reason for choosing this thickness d0 is that it can adequately protect the exposed metal material while avoiding excessive thickness that would increase production costs.

[0070] Please refer to Figure 7The protective material layer 305 is etched along the normal direction of the second surface 30b until the second surface 30b is exposed to form a protective layer 306.

[0071] Thus, the protective layer 306 protects the metal material exposed during the grinding process, reducing the occurrence of abnormal discharges in the subsequent plasma etching process, thereby reducing the risk of circuit failure and improving the stability of device performance.

[0072] In this embodiment, after forming the conductive plug 304, the protective layer 306 is formed, which can reduce the probability of the conductive plug 304 being exposed at the edge of the bonding structure, reduce the abnormal discharge that occurs in the subsequent plasma etching process, thereby reducing the risk of circuit failure and improving the stability of device performance.

[0073] In this embodiment, the etching process for the protective material layer 305 includes anisotropic dry etching.

[0074] In this embodiment, the protective material layer 305 at the bottom of the grinding port 33 is also etched away, leaving only the protective material layer 305 on the sidewall of the grinding port 33.

[0075] In this embodiment, the process parameters of the anisotropic dry etching process include: the etching gas includes one or both of C4F8 and CH3F, the radio frequency is 40MHz, and the gas pressure range in the etching chamber is 30mT to 50mT.

[0076] The thickness d1 of the protective layer 306 ranges from 800 angstroms to 1500 angstroms. In this embodiment, the thickness d1 of the protective layer 306 is 1000 angstroms.

[0077] The material of the protective layer 306 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0078] In this embodiment, the protective layer 306 is made of silicon nitride.

[0079] In another embodiment, the method of forming the protective layer includes: forming a mask layer on the second surface of the first wafer structure; forming the protective layer on the sidewall of the grinding port; and removing the mask layer after forming the protective layer.

[0080] Please refer to Figure 8After the protective layer 306 is formed, a redistribution layer 307 is formed on the surface of the conductive plug 304 and a portion of the surface of the second dielectric layer 303; a first passivation layer 308 is formed on the surfaces of the second dielectric layer 303 and the redistribution layer 307, and a solder pad layer 309 is formed on the first passivation layer 308, the solder pad layer 309 being located on a portion of the surface of the redistribution layer 307.

[0081] In this embodiment, the method for forming the first passivation layer 308 and the pad layer 309 includes: forming a first passivation material layer (not shown in the figure) on the surface of the second dielectric layer 303 and the redistribution layer 307; etching the first passivation material layer using a plasma etching process until the surface of the redistribution layer 307 is exposed, forming the first passivation layer 308 and the opening (not shown in the figure); and forming the pad layer 309 in the opening.

[0082] The solder pad layer 309 is used for electrical lead-out to external circuits.

[0083] In this embodiment, after the redistribution layer 308 is formed, a second passivation layer (not shown in the figure) is also formed on the surface of the first passivation layer 308 and the redistribution layer 309.

[0084] Accordingly, embodiments of the present invention also provide a wafer hybrid bonding structure formed using the above method. Please refer to [link / reference needed]. Figure 8 The bonding structure includes a first wafer structure 31 and a second wafer structure 32 bonded together. The first wafer structure 31 includes a first wafer 300, which includes a first surface 30a and a second surface 30b facing each other. The first wafer structure 31 also includes a first dielectric layer 301 located on the first surface 30a and a first electrical interconnect layer 302 located within the first dielectric layer 301. The first surface 30a faces the second wafer structure 32. The edge of the bonding structure has a grinding groove 33. The grinding groove 33 is located at the edge of the second wafer structure 32. The second surface 30b extends toward the first surface 30a; a second dielectric layer 303 is located on the second surface 30b of the first wafer 300; a conductive plug 304 is located within the second dielectric layer 303 and the first wafer structure 31, the conductive plug 304 penetrating the second dielectric layer 303 and the first wafer 300, and located on the surface of the first electrical interconnect layer 302; a protective layer 306 is located on the sidewall of the grinding port 33; and a redistribution layer 307 is located on the surface of the conductive plug 304 and part of the surface of the second dielectric layer 303.

[0085] Here, the protective layer 306 protects the metal material that may be exposed on the sidewalls of the bonding structure, reducing the occurrence of abnormal discharges in subsequent plasma etching processes, thereby reducing the risk of circuit failure and improving the stability of device performance.

[0086] In this embodiment, it further includes: a first passivation layer 308 located on the surface of the second dielectric layer 303 and the redistribution layer 307, wherein the first passivation layer 308 has a solder pad layer 309 located on a portion of the surface of the redistribution layer 307.

[0087] The protective layer 306 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbide. In this embodiment, the protective layer is made of silicon nitride.

[0088] The included angle between the sidewall surface and the bottom surface of the grinding port 33 ranges from 88 degrees to 92 degrees. In this embodiment, the included angle between the sidewall surface and the bottom surface of the grinding port 33 is 90 degrees.

[0089] The height H of the grinding opening 33 and the width L of the grinding opening 33 (e.g.) Figure 4 The ratio (as shown) ranges from 40:1 to 60:1. In this embodiment, the ratio of the height H of the grinding opening 33 to the width L of the grinding opening 33 is 50:1.

[0090] The thickness d1 of the protective layer 306 ranges from 800 angstroms to 1500 angstroms. In this embodiment, the thickness d1 of the protective layer 306 is 1000 angstroms.

[0091] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A wafer hybrid bonding structure, characterized in that, include: A bonding structure comprising a first wafer structure and a second wafer structure bonded together, the first wafer structure comprising a first wafer, the first wafer comprising a first surface and a second surface opposite to each other, the first wafer structure further comprising a first dielectric layer located on the first surface and a first electrical interconnect layer located within the first dielectric layer, the first surface facing the second wafer structure, the bonding structure having a grinding groove at its edge, the grinding groove extending from the second surface toward the first surface; A second dielectric layer located on the second surface of the first wafer; A conductive plug located within the second dielectric layer and the first wafer structure, the conductive plug penetrating the second dielectric layer and the first wafer, and located on the surface of the first electrical interconnect layer; A protective layer located on the sidewall of the grinding port.

2. The wafer hybrid bonding structure as described in claim 1, characterized in that, Also includes: A redistribution layer located on the surface of the conductive plug and a portion of the surface of the second dielectric layer; A first passivation layer is located on the surfaces of the second dielectric layer and the redistribution layer, the first passivation layer having a solder pad layer located on a portion of the surface of the redistribution layer.

3. The wafer hybrid bonding structure as described in claim 1, characterized in that, The material of the protective layer includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

4. The wafer hybrid bonding structure as described in claim 1, characterized in that, The angle between the sidewall surface and the bottom surface of the grinding port ranges from 88 degrees to 92 degrees.

5. The wafer hybrid bonding structure as described in claim 1, characterized in that, The ratio of the height of the grinding kerf to the width of the grinding kerf ranges from 40:1 to 60:

1.

6. The wafer hybrid bonding structure as described in claim 1, characterized in that, The thickness of the protective layer ranges from 800 angstroms to 1500 angstroms.

7. A wafer hybrid bonding method, characterized in that, include: A bonding structure is provided, the bonding structure including a first wafer structure and a second wafer structure bonded to each other, the first wafer structure including a first wafer, the first wafer including a first surface and a second surface opposite to each other, the first wafer structure further including a first dielectric layer located on the first surface and a first electrical interconnect layer located within the first dielectric layer, the first surface facing the second wafer structure, the bonding structure having a grinding groove at its edge, the grinding groove extending from the second surface towards the first surface; A second dielectric layer is formed on the second surface of the first wafer; A conductive plug is formed within the second dielectric layer and the first wafer structure, the conductive plug penetrating the second dielectric layer and the first wafer, and located on the surface of the first electrical interconnect layer; A protective layer is formed on the sidewall of the grinding hole.

8. The wafer hybrid bonding method as described in claim 7, characterized in that, After forming the protective layer, the method further includes: forming a redistribution layer on the surface of the conductive plug and a portion of the surface of the second dielectric layer; forming a first passivation layer on the surfaces of the second dielectric layer and the redistribution layer, and forming a solder pad layer on the first passivation layer, the solder pad layer being located on a portion of the surface of the redistribution layer.

9. The wafer hybrid bonding method as described in claim 7, characterized in that, The method for forming the protective layer includes: forming a protective material layer on the second surface of the first wafer structure and the sidewall of the grinding port; etching the protective material layer along the normal direction of the second surface until the second surface is exposed to form the protective layer.

10. The wafer hybrid bonding method as described in claim 9, characterized in that, The process for forming the protective material layer includes atomic layer deposition (ALD); the process parameters for ALD include: the reaction gas includes one or both of O2 and H2O, the protective gas includes H2, the gas flow rate ranges from 600 sccm to 800 sccm, and the gas pressure ranges from 2 bar to 4 bar.

11. The wafer hybrid bonding method as described in claim 9, characterized in that, Before forming the protective material layer, the bonding structure is also treated with EBR edge cleaning agent for edge washing.

12. The wafer hybrid bonding method as described in claim 9, characterized in that, The etching process for the protective material layer includes anisotropic dry etching; the process parameters of the anisotropic dry etching process include: the etching gas includes one or both of C4F8 and CH3F, the radio frequency is 40MHz, and the gas pressure in the etching chamber is in the range of 30mT to 50mT.

13. The wafer hybrid bonding method as described in claim 7, characterized in that, The method for forming the protective layer includes: forming a mask layer on the second surface of the first wafer structure; forming the protective layer on the sidewall of the first wafer structure; and removing the mask layer after forming the protective layer.

14. The wafer hybrid bonding method as described in claim 7, characterized in that, The material of the protective layer includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

15. The wafer hybrid bonding method as described in claim 7, characterized in that, The angle between the sidewall surface and the bottom surface of the grinding port ranges from 88 degrees to 92 degrees.

16. The wafer hybrid bonding method as described in claim 7, characterized in that, The ratio of the height of the grinding kerf to the width of the grinding kerf ranges from 40:1 to 60:

1.

17. The wafer hybrid bonding method as described in claim 7, characterized in that, The thickness of the protective layer ranges from 800 angstroms to 1500 angstroms.

18. The wafer hybrid bonding method as described in claim 7, characterized in that, After the conductive plug is formed, the protective layer is formed.

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