Barrier structures for conductive layers in semiconductor devices and methods of making the same

Abstract

This application relates to a barrier structure for a conductive layer in a semiconductor device and a method for manufacturing the same. A semiconductor device and a method for manufacturing the same are disclosed herein. The device (200) includes a first semiconductor region (232) disposed above a substrate (202) and having a first conductivity type. The device further includes a second semiconductor region (220) disposed above the substrate and having a second conductivity type opposite to the first conductivity type. The device further includes an isolation structure (208) disposed above the substrate and adjacent to the second semiconductor region. The device further includes a barrier structure (244) spanning a first portion of the second semiconductor region and a portion of the isolation structure. The device further includes a conductive layer (252b) disposed above a second portion of the second semiconductor region and adjacent to the barrier structure.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to barrier structures for conductive layers in semiconductor devices, including silicide barrier structures that block the formation of silicides. Background Technology

[0002] Integrated circuits may involve the formation of silicides on various components during semiconductor manufacturing processes. In some instances, silicides can be used to improve conductivity between different layers of a semiconductor device. In other instances, silicides can be used to reduce the interface resistance between an overlying conductive feature (e.g., a metal layer) and the underlying semiconductor layer. Furthermore, in other instances, silicides can act as diffusion barriers to prevent atoms (e.g., metal atoms) from diffusing from an overlying layer (e.g., a metal layer) into the underlying semiconductor layer. Therefore, the formation of silicides during semiconductor manufacturing processes can play a significant role in the overall performance and reliability of the device. Summary of the Invention

[0003] This document discloses an apparatus comprising a first semiconductor region disposed above a substrate. The first semiconductor region has a first conductivity type. The apparatus further comprises a second semiconductor region disposed above the first semiconductor region. The second semiconductor region has a second conductivity type opposite to the first conductivity type. The apparatus further comprises an isolation structure disposed above the substrate. The isolation structure is adjacent to the second semiconductor region. The apparatus further comprises a barrier structure spanning a first portion of the second semiconductor region and a portion of the isolation structure. The apparatus further comprises a conductive layer disposed above a second portion of the second semiconductor region. The conductive layer is adjacent to the barrier structure.

[0004] This document also discloses an apparatus comprising a first semiconductor region and a second semiconductor region disposed above a substrate. The first semiconductor region has a first conductivity type, and the second semiconductor region has a second conductivity type opposite to the first conductivity type. The apparatus further comprises an isolation region disposed adjacent to and laterally surrounding the first and second semiconductor regions. The apparatus further comprises a barrier structure spanning a first portion of the second semiconductor region and a portion of the isolation region. The apparatus further comprises a conductive layer disposed above a second portion of the second semiconductor region.

[0005] This document also discloses a method comprising forming a dielectric isolation structure in a semiconductor layer. The method further comprises forming a barrier layer over a first portion of the semiconductor layer and over a portion of the dielectric isolation structure. The method further comprises forming a conductive layer over a second portion of the semiconductor layer.

[0006] Unless otherwise expressly stated herein, the foregoing features and elements can be combined in any combination without exclusivity. The operation of these features and elements, and the disclosed examples, will become more apparent from the following description and accompanying drawings. Attached Figure Description

[0008] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale. While the drawings illustrate various examples employing the principles described herein, they do not limit the scope of the claims.

[0009] Figure 1 A flowchart illustrating methods for forming semiconductor devices according to various examples is shown.

[0010] Figure 2A , 2B 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, and 2O show the values ​​according to... Figure 1 Cross-sectional views of various semiconductor devices and various examples of the process and related technologies.

[0011] Figure 3A , 3B 3C, 3D, 3E, and 3F show the results based on Figure 1 Top plan view of various semiconductor devices and various examples of the process and related technologies.

[0012] Figure 4A and 4B It shows that according to Figure 1 Cross-sectional views of various semiconductor devices and various examples of the process and related technologies. Detailed Implementation

[0013] The following detailed description is presented for illustrative purposes and not for limitation. Various examples may be referenced to describe the benefits, advantages, and / or solutions to problems. The detailed description utilizes various examples and refers to the accompanying drawings illustrating the various examples described herein. The drawings, descriptions, and examples are described in sufficient detail to practice this disclosure. It should be understood that the connecting lines shown in the various drawings are intended to illustrate exemplary functional relationships and / or physical couplings between various elements, but other relationships and / or couplings are possible while remaining within the scope of this disclosure. It should also be understood that the various drawings may not be drawn to scale for the purpose of simplifying and clarifying the detailed description herein. Furthermore, it should be understood that the descriptions and examples contained herein may allow for the practice of other examples using logical, chemical, and / or mechanical variations without departing from the spirit and scope of this disclosure. For example, the steps described in the methods and processes may be performed in a different order, additional process steps may be added, and / or process steps may be removed, while remaining within the scope of this disclosure.

[0014] Any reference to a single project and / or instance may contain multiple projects and / or instances, and any reference to more than one project and / or instance may contain a single project and / or instance. Similarly, unless otherwise stated, a reference to “a,” “an,” or “the” may contain one or more of the referenced projects. Any reference to the words and / or phrases of connection, coupling, fixing, attachment, or similar terms may contain partial connection, full connection, temporary connection, removable connection, permanent connection, or other connection options. Any reference to the phrase “contact” or similar terms may contain minimal or reduced contact. All scopes used herein may include the upper and lower limits of the scopes disclosed herein, including ratio limits. The values ​​may include at least the variations expected within the field of practice of this disclosure, and, as will be understood and accepted, values ​​within 10% of the values. Similarly, the use of “approximately,” “about,” “substantially,” or other similar terms indicates an amount close to the value and still capable of achieving the stated or desired result and / or performing the stated or desired function, and may refer to an amount within 10% of the value.

[0015] The accompanying drawings and their detailed description contain reference numerals that may be repeated in multiple instances. The repetition of reference numerals is for the sake of simplicity and clarity of description, and not to establish or define a relationship between the different instances described herein. The examples and descriptions provided herein are intended to be illustrative and not to limit the scope beyond the claims. For example, the use of the terms “above” and “over” can indicate that a first feature is formed in direct contact with a second feature, or can indicate a relationship between the two where there is no direct contact, such as when an additional feature is formed between them. For example, “above” can be used to indicate direct contact between the two, and “over” can be used to indicate that there is one or more intermediate layers between them.

[0016] Spatial relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used herein for ease of discussion and are not intended to limit the orientation of various components, systems, devices, apparatuses, or other features. Therefore, it should be understood and recognized that the use of spatial relative terms in different orientations in practicing this disclosure remains within the scope of this disclosure.

[0017] This disclosure relates generally, but not exclusively, to semiconductor manufacturing processes for forming barrier structures that prevent (or block) the formation of conductive layers in semiconductor devices. In some instances, forming barrier structures that prevent (or block) the formation of silicides (e.g., conductive layers) along portions (e.g., edges) of semiconductor regions (e.g., doped semiconductor regions, source / drain regions, active regions, etc.) can help reduce leakage current in semiconductor devices, as described in further detail below.

[0018] In this regard, silicides (e.g., conductive layers, silicide layers, metal silicide layers, or silicide features) can be composed of silicon and metals such as titanium (Ti), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), platinum (Pt), chromium (Cr), etc. For example, the formation of silicides can involve forming a metal layer over a semiconductor region containing silicon (e.g., a doped semiconductor region, source / drain region, active region, etc.), and then subjecting the metal layer to an annealing process, causing the metal layer to react with (or diffuse into) the semiconductor region. That is, metal atoms from the metal layer react with silicon from the semiconductor region to form silicides over the semiconductor region of the semiconductor device. In various examples, the semiconductor device can be or includes diodes, bipolar junction transistors (BJTs), field-effect transistors (FETs), etc., or combinations thereof. Such examples will be described in more detail below.

[0019] In some instances, semiconductor regions (e.g., doped semiconductor regions, source / drain regions, active regions, etc.) can be isolated by isolation structures (e.g., shallow trench isolation structures, deep trench isolation structures, localized oxidation of silicon structures, etc.) disposed adjacent to the semiconductor regions. Due to the various processing steps that can be used to form the semiconductor regions and / or isolation structures, in various instances, the respective top surfaces of the semiconductor regions and isolation structures may or may not be substantially planar relative to each other. For example, etching and / or planarization processes (e.g., chemical mechanical polishing (CMP), etc.) can cause the top surface of the isolation structure to be (i) substantially planar relative to the top surface of the semiconductor region, (ii) recessed (e.g., lower) relative to the top surface of the semiconductor region, and / or (iii) raised (e.g., higher) relative to the top surface of the semiconductor region.

[0020] In instances where the top surface of the isolation structure is recessed relative to the top surface of the semiconductor region, the sidewall surfaces (e.g., side edges) of the semiconductor region may be unintentionally exposed. Therefore, silicides may form along the exposed sidewall surfaces in addition to the top surface of the semiconductor region. Furthermore, regardless of the relative orientation of the top surfaces of the isolation structure and the semiconductor region, certain undesirable properties associated with adjacent dissimilar materials (e.g., stresses caused by the interface between the dissimilar materials forming the isolation structure and the semiconductor region) may allow silicides to form along the sidewall surfaces (or edges) of the semiconductor region. The formation of silicides along the sidewall surfaces of the semiconductor region can lead to leakage current problems that are detrimental to the performance and reliability of the semiconductor device.

[0021] To address these issues, a patterned silicide barrier layer (e.g., a barrier structure) can be formed above the interface between the semiconductor region and the isolation structure before silicide formation. In other words, the patterned silicide barrier layer can span (or overlap with) portions of the semiconductor region and the isolation structure, such that the interface between the semiconductor region and the isolation structure is covered by the patterned silicide barrier layer. In various instances, this positioning (or orientation) of the patterned silicide barrier layer prevents silicide formation at and / or on portions of the semiconductor region at the interface between the semiconductor region and the isolation structure, which can reduce leakage current in the semiconductor device.

[0022] For example, a silicide barrier layer may be formed over a semiconductor device, encompassing the exposed top surface (and any exposed sidewall surfaces) of the semiconductor region and the top surface of the isolation structure. This silicide barrier layer may be or comprise an oxide, nitride, high-k dielectric, or a combination thereof. A patterned mask (e.g., a hard mask, photoresist layer, etc.) may then be formed over the silicide barrier layer. One or more removal processes (e.g., etching processes) may then be performed to remove portions of the silicide barrier layer to form the patterned silicide barrier layer. In various examples, the patterned silicide barrier layer may be formed over a portion of the semiconductor region and a portion of the isolation structure. In various other examples, the patterned silicide barrier layer may be formed over a portion of the semiconductor region, over the entire isolation structure, and over a portion of an adjacent second semiconductor region. Other examples and configurations are also possible based on design parameters.

[0023] After forming a patterned silicide barrier layer, a metal layer can be formed above the semiconductor device, encompassing both the patterned silicide barrier layer and the semiconductor region. The placement of the patterned silicide barrier layer prevents the formation of the metal layer on the corresponding portions of the semiconductor region covered by the patterned silicide barrier layer and the isolation structure (including the interface between the semiconductor region and the isolation structure). An annealing process can then be performed, after which silicide is formed due to the reaction (or diffusion) of the metal layer with the semiconductor region. In other words, metal atoms from the metal layer react with (or diffuse into) silicon from the semiconductor region, but not with the isolation structure or the patterned silicide barrier layer, to form silicide above the top surface of the semiconductor region (and not along the sidewall surfaces of the semiconductor region covered by the patterned silicide barrier layer). Therefore, the patterned silicide barrier layer prevents the formation of silicide at the interface between the semiconductor region and the isolation structure and / or on portions of the surrounding semiconductor region, which can reduce leakage current in the semiconductor device.

[0024] Now for reference Figure 1 A flowchart of a method 100 for forming a semiconductor device on a substrate according to various embodiments of the present disclosure is shown. In various embodiments, method 100 can be used to form a diode, a bipolar junction transistor (BJT), a field-effect transistor (FET), and / or other semiconductor devices. In various embodiments, the semiconductor device formed using method 100 can be a diode comprising a pn junction. Additional processes may be provided before, during, and after method 100. Reference is made below. Figure 2A-2O and Figures 3A-3F Description method 100.

[0025] In this regard, based on all aspects of this disclosure, Figure 2A-2O This is a schematic cross-sectional view of the example device, and Figures 3A-3F It is at various stages of manufacturing (e.g., with) Figure 1 A top plan view of an example device (related to those manufacturing stages of Method 100). Figure 2A-2O References to relevant points in the discussion of cross-sectional views Figures 3A-3F A top view. Additional features can be added to the example device, and some features described below can be replaced, modified, or eliminated in other instances of the example device.

[0026] exist Figure 1 Step 102 involves forming an isolation structure that interfaces with the semiconductor region. For example... Figure 2AAs shown, device 200 includes a semiconductor substrate 202. In various embodiments, the semiconductor substrate 202 may comprise one or more layers of silicon (Si), silicon-germanium (SiGe), or combinations thereof. For example, substrate 202 may comprise a silicon-germanium layer disposed over a silicon layer. In other embodiments, substrate 202 may comprise a strained silicon layer disposed over a silicon-germanium layer. In various other embodiments, one or more layers of semiconductor substrate 202 may comprise n-type dopants, p-type dopants, or combinations thereof. In various embodiments, semiconductor substrate 202 may comprise one or more epitaxial growth layers. In some embodiments, semiconductor substrate 202 may comprise an insulating layer, such that semiconductor substrate 202 can be considered as a silicon-on-insulator (SOI) substrate.

[0027] like Figure 2B As shown and continuing with step 102, the device 200 further includes a semiconductor region 204 having a top surface 206 and an isolation structure 208 having a top surface 210. The semiconductor region 204 includes a first semiconductor region 204a having a first top surface 206a, a second semiconductor region 204b having a second top surface 206b, and a third semiconductor region 204c having a third top surface 206c. The semiconductor region 204 can be formed by one or more processes. For example, a patterned photoresist layer can be formed over the semiconductor substrate 202, for example, by a photolithography process. In various examples, the patterned photoresist layer can contain a negative photoresist material or a positive photoresist material. The patterned photoresist layer can be patterned using one or more exposure and development processes. In various examples, the patterned photoresist layer can be used as a mask to form one or more trenches in the semiconductor substrate 202. In various instances, patterned hard mask layers (e.g., oxide layers, nitride layers) can be formed in addition to or instead of patterned photoresist layers.

[0028] In various instances, one or more etching processes can be used to form one or more trenches using a patterned photoresist layer and / or a patterned mask layer. In various instances, the one or more etching processes can include dry etching, wet etching, or a combination thereof. The patterned photoresist layer can then be removed using one or more removal processes.

[0029] An isolation structure 208 (e.g., an isolation region, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, etc.) can be formed in one or more trenches between semiconductor regions 204 using one or more processes. In various examples, the one or more processes may include sputtering, deposition, chemical mechanical polishing (CMP) (e.g., removing excess dielectric material filling the trenches), etching (e.g., removing a hard mask layer, recessing a portion of the isolation structure 208, etc.), or combinations thereof. In various examples, after one or more processes, the isolation structure 208 can be formed to a height greater than the height of the semiconductor region 204 (e.g., in the positive y-direction). In various examples, after one or more processes, the isolation structure 208 can be formed to a height equal to or less than the height of the semiconductor region 204 (e.g., in the positive y-direction). The isolation structure 208 may comprise, for example, oxides, nitrides, high-k dielectric materials, or combinations thereof. In some instances, when the isolation structure 208 is formed of one or more dielectric materials, these structures may be referred to as dielectric isolation structures.

[0030] In some instances, one or more planarization processes may be performed to planarize the top surface of the device 200, which includes the isolation structure 208 and the semiconductor region 204. In various instances, the one or more planarization processes may include CMP processes, etc. In various instances, due to statistical variations in one or more processes used to form the isolation structure 208, the top surface 210 of the isolation structure 208 may be (i) substantially planar relative to the top surfaces 206a-c of the semiconductor regions 204a-c, (ii) recessed (e.g., lower) relative to the top surfaces 206a-c of the semiconductor regions 204a-c, and / or (iii) raised (e.g., higher) relative to the top surfaces 206a-c of the semiconductor regions 204a-c. In various instances, this may be caused by variations in the removal rate (e.g., etch rate) between the isolation structure 208 and the semiconductor regions (e.g., the first semiconductor region 204a, the second semiconductor region 204b, and the third semiconductor region 204c). Due to the difference in etching rates, subsequent process steps can take into account the relative differences (if any) between the corresponding top surfaces of the isolation structure 208 and the semiconductor region 204. Here, as... Figure 2B As shown, for illustrative purposes, the top surface 210 of the isolation structure 208 is depicted as substantially planar with the top surfaces 206a-c of the semiconductor regions 204a-c.

[0031] In various other instances, isolation structure 208 may comprise a combination of one or more STI structures and / or DTI structures. In such instances, one or more process steps forming isolation structure 208 (e.g., patterning of DTI and / or STI) may affect the edges of isolation structure 208 (e.g., corner rounding). For example, the patterning process of the DTI structure may cause the edges of the STI structure adjacent to the semiconductor region (e.g., semiconductor regions 204a-c) to be more rounded. This rounding effect may cause more silicide to form along the side edges (or sidewall surfaces) of the semiconductor region adjacent to the STI structure. In other words, the rounding effect may cause silicide to surround the side edges of the semiconductor region. This surrounding may lead to leakage current problems as described above. However, as described below, a patterned silicide barrier layer (e.g., a barrier structure) may be formed above the interface between the semiconductor region and the STI structure before the silicide is formed, such that, in various instances, the patterned silicide barrier layer prevents the formation of silicide at and / or on portions of the semiconductor region at and around the interface between the semiconductor region and the STI structure, which can reduce leakage current in the semiconductor device.

[0032] like Figure 2C As shown and continuing with step 102, a first implantation process 212 can be performed on device 200. A first dopant type can be used to perform the first implantation process 212. In various instances, the first dopant type can be an n-type dopant or a p-type dopant. As a result of the first implantation process 212, a first doped semiconductor region 214a, a second doped semiconductor region 214b, and a third doped semiconductor region 214c (also referred to as doped semiconductor region 214) are formed. In various instances, the first implantation process can include one or more processes. In various instances, one or more processes can include ion implantation, annealing, etc., or combinations thereof.

[0033] For example, a first ion implantation process can be performed to implant a first dopant type (n-type or p-type) into the first semiconductor region 204a, the second semiconductor region 204b, and the third semiconductor region 204c. In various examples, the n-type dopant may include phosphorus (P), antimony (Sb), arsenic (As), etc., or combinations thereof. In various examples, the p-type dopant may include boron (B), indium (In), etc., or combinations thereof. In other examples, the semiconductor substrate 202 may be pre-doped (e.g., before forming the isolation structure 208). In such examples, the first implantation process 212 can be omitted.

[0034] In other examples, the first semiconductor region 204a, the second semiconductor region 204b, and the third semiconductor region 204c can be formed by an epitaxial growth process (e.g., before forming the isolation structure 208). As described above, the semiconductor substrate 202 can include one or more epitaxial growth layers. In such examples, the epitaxial growth process can include a first dopant, such that the first implantation process 212 can be omitted. That is, in some examples, the first doped semiconductor region 214a, the second doped semiconductor region 214b, and the third doped semiconductor region 214c are formed by patterning one or more epitaxial growth layers of the semiconductor substrate 202 without using the first implantation process 212. In other examples, the epitaxially grown semiconductor regions can be subjected to the first implantation process 212 to form the first doped semiconductor region 214a, the second doped semiconductor region 214b, and the third doped semiconductor region 214c.

[0035] like Figure 2D As shown, continuing with step 102, a first patterned photoresist layer 216 is formed over device 200, and a second implantation process 218 is performed to form a fourth doped semiconductor region 220. The first patterned photoresist layer 216 covers the first doped semiconductor region 214a, the isolation structure 208, and the third doped semiconductor region 214c, while exposing the second doped semiconductor region 214b. For example, a photoresist layer can be formed over device 200, including over the isolation structure 208, the first doped semiconductor region 214a, the second doped semiconductor region 214b, and the third doped semiconductor region 214c. An exposure and removal process can be performed to form an opening in the photoresist layer exposing the second doped semiconductor region 214b, thereby producing the first patterned photoresist layer 216. Furthermore, as shown, the first doped semiconductor region 214a, the second doped semiconductor region 214b, and the third doped semiconductor region 214c are mated (or adjacent) to the isolation structure 208.

[0036] The second implantation process 218 can be performed using a second dopant type. In various instances, the second dopant type has the opposite conductivity to the first dopant type and can be either an n-type or p-type dopant. For example, when the first dopant type is an n-type dopant, the second dopant type is a p-type dopant, and vice versa. As a result of the second implantation process 218, a fourth doped semiconductor region 220 is formed.

[0037] The fourth doped semiconductor region 220 has a top surface 222 and opposing sidewall surfaces 224a-b or side edges. The fourth doped semiconductor region 220 is formed above the second doped semiconductor region 214b (e.g., in the positive y-direction). The second doped semiconductor region 214b has opposing sidewall surfaces 226a-b or side edges. In some instances, as shown, the sidewall surfaces 226a-b are aligned with the sidewall surfaces 224a-b of the fourth doped semiconductor region 220 (e.g., extending along the same plane). Furthermore, as shown, the fourth doped semiconductor region 220 (e.g., sidewall surfaces 224a-b) and the second doped semiconductor region 214b (e.g., sidewall surfaces 226a-b) are mated (or adjacent to) the isolation structure 208.

[0038] In various instances, a pn junction 223 (or an np junction) can be formed between the fourth doped semiconductor region 220 and the second doped semiconductor region 214b, such as Figure 2D As shown. In other words, due to the difference in the type of dopant used in the fourth doped semiconductor region 220 and the second doped semiconductor region 214b (e.g., opposite conductivity types), a pn junction is formed at the interface between the fourth doped semiconductor region 220 and the second doped semiconductor region 214b.

[0039] like Figure 2E As shown, and continuing with step 102, a second patterned photoresist layer 228 is formed over device 200, and a third implantation process 230 is performed to form a fifth doped semiconductor region 232 and a sixth doped semiconductor region 234. The second patterned photoresist layer 228 covers the fourth doped semiconductor region 220 and the isolation structure 208, while exposing the first doped semiconductor region 214a and the third doped semiconductor region 214c. The second patterned photoresist layer 228 can be configured as described above regarding... Figure 2D The first patterned photoresist layer 216 in the process is formed using a process similar to that described.

[0040] The third implantation process 230 can be performed using a first dopant type (e.g., a dopant having the same dopant type as those contained in the first doped semiconductor region 214a and the third doped semiconductor region 214c). In various instances, as described above, the first dopant type can be an n-type dopant or a p-type dopant. In various instances, the dopant used in the third implantation process 230 can be the same dopant used in the first implantation process 212. In various instances, the dopant used in the third implantation process 230 can be different from the dopant used in the first implantation process 212. As a result of the third implantation process 230, a fifth doped semiconductor region 232 and a sixth doped semiconductor region 234 are formed. The fifth doped semiconductor region 232 has opposing sidewall surfaces 238a-b or side edges, and a top surface 236 extending therebetween. The sixth doped semiconductor region 234 has opposing sidewall surfaces 242a-b or side edges, and a top surface 240 extending therebetween. Furthermore, as shown in the figure, the fifth doped semiconductor region 232 (e.g., sidewall surfaces 238a-b) and the sixth doped semiconductor region 234 (e.g., sidewall surfaces 242a-b) are docked (or adjacent to) the isolation structure 208.

[0041] In some instances, the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 have a higher concentration of the first dopant type than the first doped semiconductor region 214a and the third doped semiconductor region 214c. The relatively higher concentration in the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 helps to reduce the total resistance of the device 200. Due to the difference in the concentration of the first dopant type, an interface 233 exists between the fifth doped semiconductor region 232 and the first doped semiconductor region 214a, and an interface 235 exists between the sixth doped semiconductor region 234 and the third doped semiconductor region 214c, such as... Figure 2E The center is indicated by a dashed line.

[0042] In step 104, a barrier structure is formed spanning the semiconductor region and the isolation structure. For ease of understanding, refer now to... Figure 2F and Figure 3A ,in Figure 2F yes Figure 3A A cross-sectional view along line A-A', and Figure 3A This is a top view of device 200 during step 104. (See example...) Figure 2F and 3AAs shown, device 200 includes a patterned silicide barrier layer 244 (e.g., a barrier structure) spanning a fourth doped semiconductor region 220 and an isolation structure 208 (or overlapping therewith). Specifically, the patterned silicide barrier layer 244 is formed over a portion 222a of the top surface 222 of the fourth doped semiconductor region 220 and a portion 210a of the top surface 210 of the isolation structure 208. In other words, the patterned silicide barrier layer 244 partially overlaps with both the fourth doped semiconductor region 220 and the isolation structure 208, such that the interface between the fourth doped semiconductor region 220 and the isolation structure 208 is covered by the patterned silicide barrier layer 244. In various instances, as shown, a portion 222b of the top surface 222 of the fourth doped semiconductor region 220, a portion 210b of the top surface 210 of the isolation structure 208, the top surface 236 of the fifth doped semiconductor region 232, and the top surface 240 of the sixth doped semiconductor region 234 are exposed (e.g., not covered) by a patterned silicide barrier layer 244. Figure 3A The interface between the isolation structure 208 and the fourth doped semiconductor region 220 is further illustrated, with dashed line 302 used for reference, as portions of the isolation structure 208 and the fourth doped semiconductor region 220 are covered by a patterned silicide barrier layer 244, as shown. Figure 2F As shown.

[0043] In addition, refer to Figure 2F and 3A A patterned silicide barrier layer 244 surrounds (e.g., laterally surrounds) the outer periphery of the fourth doped semiconductor region 220. That is, the patterned silicide barrier layer 244 overlaps (or spans) portions 210a of the top surface 210 of the isolation structure 208 and 222a of the top surface 222 of the fourth doped semiconductor region 220. As described in more detail below, in various examples, this positioning (or orientation) of the patterned silicide barrier layer 244 prevents the interface between the fourth doped semiconductor region 220 and the isolation structure 208 (e.g., Figure 3A Silice formation is observed at and / or around the fourth doped semiconductor region 220 at the dashed line 302 in the diagram. This prevents silicide formation at the interface between the isolation structure 208 and the fourth doped semiconductor region 220 (e.g., ...). Figure 3A Forming silicide at and / or around the dashed line 302 in the diagram can reduce leakage current in device 200.

[0044] The patterned silicide barrier layer 244 may include any material that resists or prevents silicide formation and is disposed on a portion of the fourth doped semiconductor region 220 where silicide formation would otherwise be undesirable (e.g., degrading device performance and / or reliability). In other words, the patterned silicide barrier layer 244 may be or contains any material suitable for blocking silicide formation. In various examples, the patterned silicide barrier layer 244 may be or contains oxides, nitrides, high-k dielectric materials, etc., or combinations thereof. In various examples, oxides may contain silicon oxide. In various examples, nitrides may contain silicon nitride and / or silicon oxynitride. In various examples, high-k dielectric materials may contain hafnium dioxide, zirconium dioxide, etc.

[0045] In various instances, the patterned silicide barrier layer 244 may be or comprise a material similar to that of the isolation structure 208. In various instances, the patterned silicide barrier layer 244 may use the same material as the isolation structure 208. In various instances, the patterned silicide barrier layer 244 may use one or more materials different from the isolation structure 208. Furthermore, the quality (e.g., atomic composition, material uniformity, etc.) of the material used for the patterned silicide barrier layer 244 may have a higher, the same, or lower quality than the material of the isolation structure 208. In instances where the patterned silicide barrier layer 244 uses a material different from the isolation structure 208 (different atomic composition or quality), the change from the isolation structure 208 to the patterned silicide barrier layer 244 may be detectable in the final device (e.g., using transmission electron microscopy (TEM), scanning electron microscopy (SEM), etc.).

[0046] In various embodiments, the patterned silicide barrier layer 244 can be formed by first forming a dielectric material layer (such as those previously described) over device 200. A patterned mask layer can then be formed over the dielectric material layer. In various embodiments, the patterned mask layer may comprise a photoresist, a hard mask material (e.g., TiN), or a combination thereof. The dielectric material layer can then be etched using the patterned mask layer. As a result of the etching process, the patterned silicide barrier layer 244 can be formed. Other processes can be used to form the patterned silicide barrier layer 244.

[0047] In various other instances, the patterned silicide barrier layer 244 may extend continuously from over the fourth doped semiconductor region 220 to over the fifth doped semiconductor region 232 and / or the sixth doped semiconductor region 234. For ease of understanding, reference is now made to... Figure 2G and 3D Other such examples are shown. Figure 2G yes Figure 3D The cross-sectional view at line D-D', and Figure 3D This is a top view of device 246 during step 104. Device 246 differs from device 200 in the orientation (or configuration) of the patterned silicide barrier layer. Figure 2G and 3D As shown, device 246 includes a patterned silicide barrier layer 248 formed on a fourth doped semiconductor region 220, the patterned silicide barrier layer extending over the isolation structure 208 to both the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234.

[0048] Specifically, a patterned silicide barrier layer 248 is formed on a portion 222a of the top surface 222 of the fourth doped semiconductor region 220, on the top surface 210 of the isolation structure 208, on a portion 236a of the top surface 236 of the fifth doped semiconductor region 232, and on a portion 240a of the top surface 240 of the sixth doped semiconductor region 234. In other words, the patterned silicide barrier layer 248 overlaps with (or spans across) portions of the fourth doped semiconductor region 220, the fifth doped semiconductor region 232, the sixth doped semiconductor region 234, and the isolation structure 208. In various examples, as shown, portions 222b of the top surface 222 of the fourth doped semiconductor region 220, portions 236b of the top surface 236 of the fifth doped semiconductor region 232, and portions 240b of the top surface 240 of the sixth doped semiconductor region 234 are exposed (e.g., not covered) by the patterned silicide barrier layer 248. Figure 3D The interfaces between the isolation structure 208 and the fourth doped semiconductor region 220, the fifth doped semiconductor region 232, and the sixth doped semiconductor region 234 are further illustrated, with dashed lines 302 and 304 used for reference because portions of the isolation structure 208, the fourth doped semiconductor region 220, the fifth doped semiconductor region 232, and the sixth doped semiconductor region 234 are covered by a patterned silicide barrier layer 248, as shown. Figure 2G As shown.

[0049] In addition, such as Figure 3D As shown, a patterned silicide barrier layer 248 surrounds (e.g., laterally surrounds) the outer periphery of the fourth doped semiconductor region 220 and the inner peripheries of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234. That is, the patterned silicide barrier layer 248 overlaps (or spans) portions 222a of the top surface 222 of the fourth doped semiconductor region 220, the top surface 210 of the isolation structure 208, portions 236a of the top surface 236 of the fifth doped semiconductor region 232, and portions 240a of the top surface 240 of the sixth doped semiconductor region 234. As described in more detail below, in various examples, this positioning (or orientation) of the patterned silicide barrier layer 248 prevents the interface between the fourth doped semiconductor region 220 and the isolation structure 208 (e.g., Figure 3D Silicide is formed on a portion of the fourth doped semiconductor region 220 at and / or around the dashed line 302 in the diagram, which can reduce leakage current in the device 246. Additionally, in various embodiments, this positioning (or orientation) of the patterned silicide barrier layer 248 prevents the interface (e.g., between the fifth doped semiconductor region 232, the sixth doped semiconductor region 234, and the isolation structure 208) from being blocked. Figure 3D Silices are formed on portions of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 at and / or around the dashed line 304 in the diagram.

[0050] The patterned silicide barrier layer 248 may be or include the features described above. Figure 2F The material is similar to that described in the patterned silicide barrier layer 244. Furthermore, materials similar to those previously used for... Figure 2F The patterned silicide barrier layer 244 described in the text is formed using a process similar to that described in the text to form the patterned silicide barrier layer 248. Using a wider barrier structure, such as the patterned silicide barrier layer 248 (e.g., a barrier structure extending over both the fifth doped semiconductor region 232 and / or the sixth doped semiconductor region 234 above the isolation structure 208), allows method 100 to be used on semiconductor devices with smaller feature sizes (e.g., smaller technology nodes, pitch dimensions, etc.). Therefore, in various instances, the patterned silicide barrier layer 248 can allow method 100 to be performed using a lower resolution photolithography process to reduce cost and / or processing time.

[0051] In various instances, the fourth doped semiconductor region 220, the fifth doped semiconductor region 232, and the sixth doped semiconductor region 234 can be formed after forming a patterned silicide barrier layer (e.g., patterned silicide barrier layer 244 or patterned silicide barrier layer 248). In this regard, a patterned silicide barrier layer (e.g., over one or more of the first doped semiconductor region 214a, the second doped semiconductor region 214b, or the third doped semiconductor region 214c and the isolation structure 208) can be formed as described above. A first patterned photoresist layer 216 can then be formed, contained over the patterned silicide barrier layer. A second implantation process 218 can then be performed, as described above, to form the fourth doped semiconductor region 220. Thereafter, the first patterned photoresist layer 216 is removed, and subsequently, a second patterned photoresist layer 228 can be formed, contained over the patterned silicide barrier layer. A third implantation process 230 can then be performed, as described above, to form the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234. Therefore, the steps of method 100 can be performed in different orders while remaining within the scope of this disclosure.

[0052] In step 106, a conductive layer (e.g., a silicide layer) is formed over the semiconductor region adjacent to the barrier layer. Figure 2F Continuing with method 100, a patterned silicide barrier layer 244 is formed above device 200, such as... Figure 2H As shown, a metal layer 250 is formed above device 200. The metal layer 250 may be or include titanium (Ti), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), platinum (Pt), chromium (Cr), or combinations thereof. The metal layer 250 may be formed above the fourth doped semiconductor region 220, the fifth doped semiconductor region 232, the sixth doped semiconductor region 234, the patterned silicide barrier layer 244, and the isolation structure 208. However, as shown, the patterned silicide barrier layer 244 prevents the formation of the metal layer 250 on a portion 222a of the top surface 222 of the fourth doped semiconductor region 220 and a portion 210a of the top surface 210 of the isolation structure 208. As described in more detail below, because the patterned silicide barrier layer 244 prevents the formation of a metal layer 250 on a portion 222a of the top surface 222 of the fourth doped semiconductor region 220, it also prevents the formation of silicide in these regions, at and / or around the interface between the fourth doped semiconductor region 220 and the isolation structure 208.

[0053] like Figure 2H As shown, metal layer 250 can be formed above the horizontal surface (e.g., along the x-axis) and vertical surface (e.g., along the y-axis) of device 200. For example, metal layer 250 can be formed above the top surface of isolation structure 208, fourth doped semiconductor region 220, fifth doped semiconductor region 232, sixth doped semiconductor region 234, and patterned silicide barrier layer 244, as well as above the sidewall surface of patterned silicide barrier layer 244. In various other embodiments, metal layer 250 can be further formed above the sidewall surface of fifth doped semiconductor region 232 and / or sixth doped semiconductor region 234 (see below for reference). Figure 2K (As described). However, as mentioned above, the patterned silicide barrier layer 244 blocks the interface between the fourth doped semiconductor region 220 and the isolation structure 208 (e.g., Figure 3A A metal layer 250 is formed on a portion of the fourth doped semiconductor region 220 at and / or around the dashed line 302 in the diagram.

[0054] In various instances, the metal layer 250 may be thicker in a first direction (e.g., the y-direction) than in a second direction (e.g., the x-direction). In other words, the metal layer 250 may be thicker on the horizontal surface of the device 200 (e.g., the top surface of the isolation structure 208, the top surface of the patterned silicide barrier layer 244, etc.) than on the vertical surface (e.g., the sidewall surface of the patterned silicide barrier layer 244, etc.).

[0055] A metal layer 250 can be formed over apparatus 200 using one or more processes. In various examples, the one or more processes may include chemical vapor deposition (CVD), physical vapor deposition (PVD), or combinations thereof. In various examples, the PVD process may include sputtering, evaporation, or combinations thereof. In various examples, the CVD process may include low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0056] like Figure 2I As shown, proceeding to step 106, a silicide layer 252 (e.g., a conductive layer) is formed by reacting the underlying doped semiconductor regions (e.g., 220, 232, and 234) with the metal layer 250. In various instances, a silicide process, a self-aligned titanium silicide process, and / or other suitable processes can be performed to form the silicide layer 252. In various instances, an annealing process can be performed to cause the metal layer 250 to react (or diffuse into) the fourth doped semiconductor region 220, the fifth doped semiconductor region 232, and the sixth doped semiconductor region 234. That is, metal atoms from the metal layer 250 react (or diffuse into) silicon from the various doped semiconductor regions to form the silicide layer 252. As a result of the annealing process, portions of the metal layer 250 (e.g., titanium (Ti), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), platinum (Pt), and chromium (Cr)) disposed on the fourth doped semiconductor region 220, the fifth doped semiconductor region 230, and the sixth doped semiconductor region 232 can be consumed and converted into a silicide layer 252 (e.g., Ti). x Si y Ni x Si y Co x Si y W x Si y Mo x Si y Pt x Si y Cr x Si y (etc.). In various instances, a removal process can then be performed to remove unreacted portions of the metal layer 250 (if present) from above the device 200 (e.g., removing unreacted metal layer 250 from above the isolation structure 208 and the patterned silicide barrier layer 244).

[0057] As shown, the silicide layer 252 includes segments 252a, 252b, and 252c (e.g., conductive layers) formed over the fifth doped semiconductor region 232, the fourth doped semiconductor region 220, and the sixth doped semiconductor region 234, respectively. In this regard, as shown, the patterned silicide barrier layer 244 prevents silicide formation over a portion 222a of the top surface 222 of the fourth doped semiconductor region 220. In other words, in various embodiments, this positioning (or orientation) of the patterned silicide barrier layer 244 prevents the formation of silicide at the interface between the fourth doped semiconductor region 220 and the isolation structure 208 (e.g., Figure 3A Silicide is formed on a portion of the fourth doped semiconductor region 220 at and / or around the dashed line 302 in the diagram. Therefore, the patterned silicide barrier layer 244 prevents the formation of silicide along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220.

[0058] Conversely, segments 252b of the silicide layer 252 are formed only on the exposed (e.g., uncovered / uncovered) portions 222b of the patterned silicide barrier layer 244 on the top surface 222 of the fourth doped semiconductor region 220. Furthermore, in some instances, segments 252b of the silicide layer 252 are adjacent (e.g., in physical contact, butt joint, etc.) to the patterned silicide barrier layer 244. Additionally, as shown, segments 252b of the silicide layer 252 do not extend along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220. By not extending along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220, leakage current in the device 200 can be reduced or prevented. This is because when the silicide layer 252 extends along the sidewall surfaces 224a-b (or around its edges) of the fourth doped semiconductor region 220 toward the second doped semiconductor region 214b (e.g., the pn junction 223 between the fourth doped semiconductor region 220 and the second doped semiconductor region 214b), unintentional leakage current may occur.

[0059] Conversely, in various instances, segments 252a and 252c of the silicide layer 252 extend to the interface between the isolation structure 208 and the fifth doped semiconductor region 232 and / or the sixth doped semiconductor region 234. As described above, the stress induced at the interface between the different materials forming the isolation structure 208, the fifth doped semiconductor region 232, and / or the sixth doped semiconductor region 234 can allow silicide to form along the sidewall surfaces 238a-b, 242a-b (or around their edges) of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively. This is because no patterned silicide barrier layer 244 is formed above (e.g., overlapping with or across) the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234. Therefore, segments 252a and 252c of the silicide layer 252 can extend along the sidewall surfaces 238a-b, 242a-b and the top surfaces 236, 240 of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively. However, as shown in the figure, because the top surface 210 of the isolation structure 208 is substantially coplanar with the top surfaces 236 and 240 of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 respectively before step 106, the segments 252a and 252c of the silicide layer 252 are restricted (or suppressed) from extending too far along the sidewall surfaces 238a-b and 242a-b of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 respectively.

[0060] Furthermore, any extension of segments 252a and 252c of the silicide layer 252 along the sidewall surfaces 238a-b and 242a-b of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 has minimal (or no) impact on device performance and / or reliability. For example, unlike the pn junction formed at the interface between the fourth doped semiconductor region 220 and the second doped semiconductor region 214b, the interfaces 233 and 235 between the fifth doped semiconductor region 232 and the first doped semiconductor region 214a, or between the sixth doped semiconductor region 234 and the third doped semiconductor region 214c, do not form a pn junction. Instead, as discussed above in various examples, the first doped semiconductor region 214a, the third doped semiconductor region 214c, the fifth doped semiconductor region 232, and the sixth doped semiconductor region 234 all have the same conductivity type, wherein the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 have a higher dopant concentration than the first doped semiconductor region 214a and the third doped semiconductor region 214c, respectively. Therefore, the extension of segments 252a and 252c of silicide layer 252 along the sidewall surfaces 238a-b and 242a-b of the fifth doped semiconductor region 232 and / or the sixth doped semiconductor region 234 may not cause leakage current problems.

[0061] In step 108, additional processing steps may be performed. For example... Figure 2J and Figure 3B As shown, the additional processing steps of the device 200 are completed. Figure 3B A top view of device 200 is shown, and Figure 2J A cross-sectional view of the device 200 along line B-B' is shown. Figure 2J As shown, a pad layer 254, a dielectric layer 256, and contacts 258a-c are formed above the device 200. Specifically, the pad layer 254, also known as a metal front dielectric (PMD) pad, is formed above the isolation structure 208, the patterned silicide barrier layer 244, and the silicide layer 252. The dielectric layer 256, also known as an interlayer dielectric (ILD), is formed above the pad layer 254. The contacts 258a-c, including a first contact 258a, a second contact 258b, and a third contact 258c, are formed through the dielectric layer 256 and the pad layer 254 and are bonded to the silicide layer 252. Figure 3B A dielectric layer 256 is shown formed above the device 200, through which contacts 258a-c are formed (additional horizontal row contacts (e.g., along the x-direction) are also shown, but are not labeled for ease of understanding). Figure 3B The isolation structure 208 and the patterned silicide barrier layer 244 are further illustrated, with the dashed outline used for reference, as both the isolation structure 208 and the patterned silicide barrier layer 244 are covered by the silicide layer 252, the pad layer 254, and the dielectric layer 256, as shown. Figure 2J As shown. For ease of understanding, Figure 3B Focusing on the isolation structure 208, patterned silicide barrier layer 244, fourth doped semiconductor region 220, fifth doped semiconductor region 232 and sixth doped semiconductor region 234 shown in dashed lines below dielectric layer 256.

[0062] The padding layer 254 may comprise one or more layers of dielectric material. The one or more layers of dielectric material in the padding layer 254 may comprise oxide, nitride, and / or carbide materials, such as silicon oxide, silicon nitride, silicon oxynitride, and / or silicon carbide, or combinations thereof. The term silicon oxide, as used throughout this disclosure, includes, for example, non-stoichiometric mixtures of silicon monoxide (SiO) and / or silicon dioxide (SiO2) and / or both.

[0063] The dielectric layer 256 (or interlayer dielectric (ILD)) may be a single dielectric layer or may comprise multiple dielectric layers of the same or different dielectric materials. In various examples, the dielectric layer 256 may comprise silicon nitride, silicon oxide-based materials (e.g., phosphosilicate glass (PSG), borosilicate glass (BPSG), or tetraethyl orthosilicate (TEOS) oxide), polytetrafluoroethylene, etc.

[0064] Contacts 258a-c may be formed through the dielectric layer 256 and the pad layer 254 to bond to segments 252a, 252b, and 252c of the silicide layer 252 disposed over the fifth doped semiconductor region 232, the fourth doped semiconductor region 220, and the sixth doped semiconductor region 234, respectively. In various embodiments, contacts 258a-c may each include (i) one or more metal barriers and / or adhesive layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) conformally present in the respective openings through the dielectric layer 256 and the pad layer 254, and (ii) filler metal (e.g., aluminum (Al), copper (Cu), tungsten (W), etc., or combinations thereof) located above and / or on the metal barriers and / or adhesive layers. Furthermore, one or more metal wires may be formed above and on (and electrically connected to) the contacts 258-c. Each metal wire may include one or more metal barriers and / or adhesive layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof), and filler metal (e.g., aluminum (Al), copper (Cu), etc., or combinations thereof) located above and / or on the metal barriers and / or adhesive layers.

[0065] In other instances, device 200 may contain more than [a certain number of elements] in each horizontal row (e.g., along the x-direction). Figure 2J and 3B More contacts are shown. For ease of understanding, please refer to [reference needed]. Figure 3C It shows a top view of device 200', which includes the same components as described above. Figure 3B The device 200 described herein is a similar component. In various instances, each of the first contact 258a, the second contact 258b, and the third contact 258c may now contain multiple contacts (e.g., 2, 3, 4, etc.). For example, the first contact 258a and the third contact 258c may each contain two contacts, such as... Figure 3C As shown. As another example, the second contact 258b can contain four contacts, such as... Figure 3C As shown. Figure 3C Additional horizontal row contacts (e.g., along the x-direction) are shown, but are labeled for ease of understanding. In various instances, the device 200' may be designed and manufactured to include more than one discrete metal contact for each of the first contact 258a, the second contact 258b, and the third contact 258c. In other words, depending on the design requirements of a given semiconductor device, the first contact 258a, the second contact 258b, and / or the third contact 258c may comprise one or more discrete metal contacts.

[0066] As described above, in various instances, due to one or more process variations used to form the isolation structure 208, the top surface 210 of the isolation structure 208 may be recessed (e.g., lowered) relative to the top surfaces 222, 236, and 240 of the fourth doped semiconductor region 220, the fifth doped semiconductor region 232, and / or the sixth doped semiconductor region 234, respectively. In such instances, portions of the sidewall surfaces 224a-b of the fourth doped semiconductor region 220 (e.g., side edges), portions of the sidewall surfaces 236a-b of the fifth doped semiconductor region 232, and portions of the sidewall surfaces 242a-b of the sixth doped semiconductor region 234 may be exposed after step 102 of method 100.

[0067] Because a pn junction 223 is formed between the fourth doped semiconductor region 220 and the second doped semiconductor region 214b, silicide formation along the exposed sidewall surfaces 224a-b of the fourth doped semiconductor region 220 may cause leakage current problems, thereby adversely affecting the reliability and performance of the device. To prevent this leakage current problem, refer to the following... Figure 2K Further described, prior to forming the silicide layer at step 106 of method 100, a patterned silicide barrier layer (e.g., barrier structure) may be formed over the interface between the fourth doped semiconductor region 220 and the isolation structure 208 (including along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220) during step 104.

[0068] in this regard, Figure 2K The apparatus 298 following processing steps 106 and 108 of method 100 is shown. As shown, apparatus 298 is formed such that the top surface 210 of the isolation structure 208 is recessed (e.g., lower in the negative y direction) relative to the top surfaces 222, 236, and 240 of the fourth doped semiconductor region 220, the fifth doped semiconductor region 232, and the sixth doped semiconductor region 234, respectively. For ease of understanding and for brevity, apparatus 298 is similar to apparatus 200 except as described herein. Descriptions of similar features may not be repeated below.

[0069] As shown, a patterned silicide barrier layer 244' is formed across (or overlapping with) a portion of the fourth doped semiconductor region 220 and the isolation structure 208. Specifically, the patterned silicide barrier layer 244' is formed over a portion 222a of the top surface 222 of the fourth doped semiconductor region 220 (and along portions of the sidewall surfaces 224a-b of the fourth doped semiconductor region) and over a portion 210a of the top surface 210 of the isolation structure 208. In other words, the patterned silicide barrier layer 244' is disposed along each of the sidewall surfaces 224a-b of the fourth doped semiconductor region 220, while overlapping with portions 210a of the top surface 210 of the isolation structure 208 and portions 222a of the top surface 222 of the fourth doped semiconductor region 220. In various examples, as shown in the figure, the patterned silicide barrier layer 244' does not cover the portion 222b of the top surface 222 of the fourth doped semiconductor region 220, the portion 210b of the top surface 210 of the isolation structure 208, the portion of the top surface 236 and sidewall surfaces 238a-b of the fifth doped semiconductor region 232, and the portion of the top surface 240 and sidewall surfaces 242a-b of the sixth doped semiconductor region 234.

[0070] As shown, the silicide layer 252' includes segments 252a', 252b', and 252c' (e.g., conductive layers) formed over the fifth doped semiconductor region 232, the fourth doped semiconductor region 220, and the sixth doped semiconductor region 234, respectively. In this respect, because the patterned silicide barrier layer 244' prevents silicide formation along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220, segment 252b' of the silicide layer 252' is formed only on the exposed (e.g., uncovered / uncovered) portion 222b of the patterned silicide barrier layer 244' on the top surface 222 of the fourth doped semiconductor region 220. Furthermore, in some embodiments, segment 252b' of the silicide layer 252 is adjacent (e.g., in physical contact, butt joint, etc.) to the patterned silicide barrier layer 244'. Furthermore, as shown, segment 252b' of silicide layer 252' does not extend along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220. By not extending along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220 (e.g., by limiting (or including) segment 252b' of silicide layer 252 away from the sidewall surfaces 224a-b), leakage current in device 298 can be reduced or prevented. This is because unintentional leakage current may occur when silicide layer 252' extends along (or around the edges of) the sidewall surfaces 224a-b of the fourth doped semiconductor region 220 toward the second doped semiconductor region 214b (e.g., the pn junction 223 between the fourth doped semiconductor region 220 and the second doped semiconductor region 214b).

[0071] Instead, segments 252a' and 252c' of the silicide layer 252' extend to and along the sidewall surfaces 238a-b and 242a-b (or around their edges) of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively. This is because no patterned silicide barrier layer 244' is formed above the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234. Therefore, segments 252a' and 252c' of the silicide layer 252' extend along the sidewall surfaces 238a-b and 242a-b and the top surfaces 236 and 240 of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively. Furthermore, since segments 252a' and 252c' of silicide layer 252 extend along the sidewall surfaces 238a-b and 242a-b of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively, these segments can extend closer to the semiconductor substrate 202 than segment 252b' of silicide layer 252'.

[0072] In other examples, such as those mentioned above... Figure 2G As described, the patterned silicide barrier layer 248 can extend continuously from over the fourth doped semiconductor region 220 in the device 246 over the fifth doped semiconductor region 232 and / or the sixth doped semiconductor region 234. In such an example, processing steps 106 and 108 of method 100 are similar to those described above regarding... Figure 2H-2I The descriptions, aside from those concerning the orientation (or configuration) of the silicide barrier layers in those figures, are for the sake of brevity and ease of understanding. Figure 2L and 3E The apparatus 246 is shown after processing steps 106 and 108 of method 100, wherein a patterned silicide barrier layer 248 extends from over the fourth doped semiconductor region 220 and over the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 in the apparatus 246.

[0073] in this regard, Figure 2L The device 246 is shown along Figure 3E A cross-sectional view of line E-E'. Figure 3E A top view of device 246 is shown. (As shown) Figure 2L As shown and similar Figure 2J The device 246 includes a pad layer 254 formed over the isolation structure 208, the silicide layer 252, and the patterned silicide barrier layer 248. A dielectric layer 256 is formed over the pad layer 254, and contacts 258a-c pass through the dielectric layer 256 and the pad layer 254 and are formed on the silicide layer 252, as described above. Figure 2J As described in the text. Figure 3EThe isolation structure 208 and the patterned silicide barrier layer 248 are further illustrated, with the dashed outline used for reference, as both the isolation structure 208 and the patterned silicide barrier layer 248 are covered by the silicide layer 252, the pad layer 254, and the dielectric layer 256. For ease of understanding, Figure 3E Focusing on the isolation structure 208, patterned silicide barrier layer 248, fourth doped semiconductor region 220, fifth doped semiconductor region 232 and sixth doped semiconductor region 234 shown in dashed lines below dielectric layer 256.

[0074] Reference Figure 2F and 2H Compared to the patterned silicide barrier layer 244 described in -2J, the patterned silicide barrier layer 248 further covers portions of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, thereby preventing the formation of a silicide layer 252 on the covered portions. Figure 2L As shown, the patterned silicide barrier layer 248 prevents the formation of silicide layer 252 on the sidewall surfaces 224a-b and portion 222a of the top surface 222 of the fourth doped semiconductor region 220, on the sidewall surface 238b and portion 236a of the top surface 236 of the fifth doped semiconductor region 232, and on the sidewall surface 242a and portion 240a of the top surface 240 of the sixth doped semiconductor region 234.

[0075] In this regard, such as Figure 2L As shown, the silicide layer 252 includes segments 252a, 252b, and 252c (e.g., conductive layers) formed over the fifth doped semiconductor region 232, the fourth doped semiconductor region 220, and the sixth doped semiconductor region 234, respectively. As shown, the patterned silicide barrier layer 248 prevents silicide formation over a portion 222a of the top surface 222 of the fourth doped semiconductor region 220. In other words, in various embodiments, this positioning (or orientation) of the patterned silicide barrier layer 248 prevents the formation of silicide at the interface between the fourth doped semiconductor region 220 and the isolation structure 208 (e.g., Figure 3D Silicide is formed on a portion of the fourth doped semiconductor region 220 at and / or around the dashed line 302 in the diagram. Therefore, the patterned silicide barrier layer 248 prevents the formation of silicide along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220.

[0076] Conversely, the segment 252b of the silicide layer 252 is formed only on the exposed (e.g., uncovered / uncovered) portion 222b of the patterned silicide barrier layer 248 on the top surface 222 of the fourth doped semiconductor region 220. Because the patterned silicide barrier layer 248 prevents silicide formation along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220, leakage current in the device 200 can be reduced or prevented. This is because unintentional leakage current may occur when the silicide layer 252 extends along the sidewall surfaces 224a-b (or around their edges) of the fourth doped semiconductor region 220 toward the second doped semiconductor region 214b (e.g., the pn junction 223 between the fourth doped semiconductor region 220 and the second doped semiconductor region 214b).

[0077] Furthermore, the patterned silicide barrier layer 248 formed over portions 236a and 240a of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively, prevents the formation of a silicide layer 252 thereon. In other words, segments 252a and 252c of the silicide layer 252 do not extend to the interface between the isolation structure 208 and the fifth doped semiconductor region 232 and / or the sixth doped semiconductor region 234 (e.g., Figure 3D (dashed line 304 in the diagram). Therefore, segments 252a and 252c of the silicide layer 252 will not extend along the sidewall surfaces 238b and 242a of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively.

[0078] Conversely, because no patterned silicide barrier layer 248 is formed over the sidewall surface 238a of the fifth doped semiconductor region 232 or the sidewall surface 242b of the sixth doped semiconductor region 234, a silicide layer 252 is allowed to form on these surfaces. As described above, the stress caused by the interface between the different materials forming the isolation structure 208, the fifth doped semiconductor region 232, and / or the sixth doped semiconductor region 234 allows silicide to form along (or around the edges of) the sidewall surfaces 238a and 242b of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively. This is because no patterned silicide barrier layer 248 is formed over (e.g., overlapping with or across) the portion 236b of the fifth doped semiconductor region 232 and the portion 240b of the sixth doped semiconductor region 234. Therefore, segments 252a and 252c of silicide layer 252 can extend along portions of the sidewall surfaces 238a and 242b of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, and portions 236b and 240b of the top surfaces 236 and 240, respectively.

[0079] However, as shown in the figure, because the top surface 210 of the isolation structure 208 is substantially coplanar with the top surfaces 236 and 240 of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively, prior to step 106, the extension of segments 252a and 252c of the silicide layer 252 along the sidewall surfaces 238a and 242b of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 is limited (or suppressed). Furthermore, as mentioned above, any extension of segments 252a and 252c of the silicide layer 252 along the sidewall surfaces 238a and 242b of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 has minimal (or no) impact on device performance because these segments do not extend toward the underlying pn junction interface. Therefore, the extension of segments 252a and 252c of silicide layer 252 along the sidewall surfaces 238a and 242b of the fifth doped semiconductor region 232 and / or the sixth doped semiconductor region 234 will not cause leakage current problems.

[0080] In other instances, device 246 may contain more than [a certain number of elements] in each horizontal row (e.g., along the x-direction). Figure 2L and 3E More contacts are shown. For ease of understanding, please refer to [reference needed]. Figure 3F It shows a top view of device 246', which includes the same components as described above. Figure 3E The device 246 described herein is a similar component. In various instances, each of the first contact 258a, the second contact 258b, and the third contact 258c may now contain multiple contacts (e.g., 2, 3, 4, etc.). For example, the first contact 258a and the third contact 258c may each contain two contacts, such as... Figure 3F As shown. As another example, the second contact 258b can contain four contacts, such as... Figure 3F As shown. Figure 3F Additional horizontal row contacts (e.g., along the x-direction) are shown, but are labeled for ease of understanding. In various instances, the device 246' may be designed and manufactured to include more than one discrete metal contact for each of the first contact 258a, the second contact 258b, and the third contact 258c. In other words, depending on the design requirements of a given semiconductor device, the first contact 258a, the second contact 258b, and / or the third contact 258c may comprise one or more discrete metal contacts.

[0081] Now for reference Figure 2M The image shows a device 260 with an misaligned patterned silicide barrier layer. In various instances, the misalignment of the patterned silicide barrier layer may be described above regarding... Figure 2F and 2GThe patterned silicide barrier layer at processing step 104 occurs during its formation. For example, as... Figure 2M As shown, an misaligned patterned silicide barrier layer 262 is formed, which covers a larger portion (e.g., on one side) of the top surface 222 of the fourth doped semiconductor region 220 than intended. That is, as a result of one or more semiconductor processing alignment and / or processing steps, the misaligned patterned silicide barrier layer 262 is unintentionally offset over the fourth doped semiconductor region 220. In such an example, a portion of the misaligned patterned silicide barrier layer 262 may be present as described above regarding... Figure 2J and 2L The step 108 described is removed during the formation process of the second contact 258b.

[0082] As shown, the second contact 258b extends through the dielectric layer 256, the pad layer 254, and the misaligned patterned silicide barrier layer 262, and is bonded to a segment 252b of the silicide layer 252 and the top surface 222 of the fourth doped semiconductor region 220. In other words, in such an example, the second contact 258b is abutted (e.g., laterally connected) to the misaligned patterned silicide barrier layer 262, the silicide layer 252, and the top surface 222 of the fourth doped semiconductor region 220 (e.g., adjacent, physical contact, etc.). Although the misalignment shown may not be intended, it has little negative impact on the device 260. Therefore, the method disclosed herein provides a tolerance that allows for misalignment of the patterned silicide barrier layer without negatively impacting the fabricated device.

[0083] In other instances, the gate structure (e.g., a dummy gate structure) can be used as a patterned silicide barrier layer. For example, see reference... Figure 2N Device 264 is shown to have similar features to device 200, except for the gate structures 266, 272 which serve as patterned silicide barrier layers (e.g., barrier structures). In this respect, the gate structures 266, 272 are formed during step 104 of method 100 instead of the patterned silicide barrier layer 244. In some instances, one or more of the gate structures 266, 272 may be dummy gate structures, since the gate structures are non-functional gate structures. In some instances, the gate structures 266, 272 may be formed simultaneously with functional gate structures (e.g., the gate structure of a field-effect transistor (FET) formed in other regions of the semiconductor substrate 202).

[0084] As shown in the figure, gate structures 266 and 272 respectively include gate dielectric layers 271 and 277 and gate electrode layers 268 and 274. Gate dielectric layers 271 and 277 are formed above a portion 210a of the top surface 210 of the isolation structure 208 and a portion 222a of the top surface 222 of the fourth doped semiconductor region 220. Gate electrode layers 268 and 274 are formed above gate dielectric layers 271 and 277, respectively. Gate spacers 270 and 276 are formed along the sidewalls of gate structures 266 and 272, more specifically, along the sidewalls of gate dielectric layers 271 and 277 and gate electrode layers 268 and 274, respectively.

[0085] In various embodiments, the gate dielectric layers 271, 277 may comprise any dielectric material, including high-k dielectric materials. For example, the gate dielectric layers 271, 277 may comprise dielectric materials such as silicon oxide, silicon dioxide, hafnium oxide, zirconium oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the gate dielectric layers 271, 277 may further comprise an interface layer formed by a dielectric material, such as an oxide material, disposed beneath the high-k dielectric material. In various embodiments, the gate dielectric layers 271, 277 may be formed by thermal oxidation, one or more chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, plasma-enhanced CVD (PECVD), or combinations thereof.

[0086] In various embodiments, gate electrode layers 268, 274 may comprise metallic materials such as titanium, nickel, titanium nitride, tungsten titanate, tungsten, or combinations thereof. Other metals and / or metal alloys may be used in gate electrode layers 268, 274 and within the scope of this disclosure, such that gate electrode layers 268, 274 may comprise or comprise any suitable metal and / or metal alloy, or combinations thereof. In various other embodiments, gate electrode layers 268, 274 may comprise polycrystalline silicon, also known as polysilicon. In various embodiments, gate electrode layers 268, 274 may be formed using one or more deposition processes, such as sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., or any combination thereof.

[0087] In various embodiments, the gate spacers 270, 276 (also referred to as dielectric spacers or sidewall spacers) may comprise one or more layers of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride and / or silicon oxynitride), or combinations thereof. The gate spacers 270, 276 may be formed using any known process, such as chemical vapor deposition (CVD) and / or physical vapor deposition (PVD). In various embodiments, a dielectric material may be formed over device 264, and subsequently etched to form the gate spacers 270, 276.

[0088] As shown, the silicide layer 252 includes segments 252a, 252b, and 252c (e.g., conductive layers) formed over the fifth doped semiconductor region 232, the fourth doped semiconductor region 220, and the sixth doped semiconductor region 234, respectively. In this regard, as shown, the gate structures 266, 272 and the gate spacers 270, 276 (e.g., barrier structures) prevent the formation of silicide over a portion 222a of the top surface 222 of the fourth doped semiconductor region 220. In other words, in various embodiments, this positioning (or orientation) of the gate structures 266, 272 and the gate spacers 270, 276 prevents the formation of silicide on and / or around a portion of the fourth doped semiconductor region 220 at the interface between the fourth doped semiconductor region 220 and the isolation structure 208. Therefore, the gate structures 266, 272 and the gate spacers 270, 276 (e.g., silicide barrier structures) prevent the formation of silicide along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220.

[0089] Conversely, segments 252b of the silicide layer 252 are formed only on the portion 222b of the top surface 222 of the fourth doped semiconductor region 220 that is exposed (e.g., uncovered / uncovered) by the gate structures 266, 272 and the gate spacers 270, 276 (e.g., silicide barrier structures). That is, segments 252b of the silicide layer 252 do not extend along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220. By not extending along the sidewall surfaces 224a-b of the fourth doped semiconductor region 220, leakage current in the device 264 can be reduced or prevented. This is because unintentional leakage current may occur when the silicide layer 252 extends along (or around the edges of) the sidewall surfaces 224a-b of the fourth doped semiconductor region 220 toward the second doped semiconductor region 214b (e.g., the pn junction 223 between the fourth doped semiconductor region 220 and the second doped semiconductor region 214b).

[0090] Conversely, in various instances, segments 252a and 252c of the silicide layer 252 extend to the interface between the isolation structure 208 and either the fifth doped semiconductor region 232 or the sixth doped semiconductor region 234. As shown, the stress induced at the interface between the different materials forming the isolation structure 208, the fifth doped semiconductor region 232, and / or the sixth doped semiconductor region 234 allows silicide to form along the sidewall surfaces 238a-b, 242a-b (or around their edges) of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively. This is because gate structures 266, 272 and gate spacers 270, 276 (e.g., silicide barrier structures) are not formed above (e.g., overlapping with or across) the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234. Therefore, segments 252a and 252c of silicide layer 252 can extend along the sidewall surfaces 238a-b, 242a-b and top surfaces 236, 240 of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively.

[0091] However, as shown in the figure, because the top surface 210 of the isolation structure 208 is substantially coplanar with the top surfaces 236 and 240 of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively, prior to step 106 of method 100, the extension of segments 252a and 252c of the silicide layer 252 along the sidewall surfaces 238a and 242b of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively, is limited (or suppressed). Furthermore, as described above, any extension of segments 252a and 252c of the silicide layer 252 along the sidewall surfaces 238a-b and 242a-b of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234 has minimal (or no) impact on device performance because these segments do not extend toward the underlying pn junction interface. Therefore, the extension of segments 252a and 252c of silicide layer 252 along the sidewall surfaces 238a-b and 242a-b of the fifth doped semiconductor region 232 and / or the sixth doped semiconductor region 234 will not cause leakage current problems.

[0092] In other examples, such as reference Figure 2O As shown, the gate structure and gate spacers can be used as a patterned silicide barrier layer that extends continuously from above the fourth doped semiconductor region 220 to above the fifth doped semiconductor region 232 and / or the sixth doped semiconductor region 234. In this respect, Figure 2O It shows the relationship with Figure 2N The device 264 is similar to the device 278, except for the orientation (or configuration) of the gate structure and gate spacers used as the barrier structure. Descriptions of similar features may not be repeated below.

[0093] Reference Figure 2N Compared to the described device 264, device 278 has gate structures 280 and 288 that extend continuously from above the fourth doped semiconductor region 220 to above the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively. As shown, gate structures 280 and 288 include gate dielectric layers 282 and 290 and gate electrode layers 284 and 292, respectively. Gate dielectric layers 282 and 290 are formed above a portion 222a of the top surface 222 of the fourth doped semiconductor region 220, above the top surface 210 of the isolation structure 208, above a portion 236a of the top surface 236 of the fifth doped semiconductor region 232, and above a portion 240a of the top surface 240 of the sixth doped semiconductor region 234. Gate electrode layers 284 and 292 are formed above the gate dielectric layers 282 and 290, respectively. Gate spacers 286 are formed along the sidewalls of gate structures 280 and 288, more specifically, along the sidewalls of gate dielectric layers 282 and 290 and gate electrode layers 284 and 292, respectively. Gate structures 280 and 288 (including gate dielectric layers 282 and 290, gate electrode layers 284 and 292, and gate spacers 286 and 294) can be referenced above. Figure 2N Similar manner and material formation are described for gate structures 266 and 272 (including gate dielectric layers 271 and 277, gate electrode layers 268 and 274, and gate spacers 270 and 276).

[0094] As shown in the figure, gate structures 280 and 288 (including gate spacers 286 and 294) further cover portions of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, thereby preventing the formation of a silicide layer 252 on the covered portions. Specifically, gate structures 280 and 288 and gate spacers 286 and 294 are further formed on portions 236a and 240a of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively, preventing the formation of a silicide layer 252 thereon. In other words, segments 252a and 252c of the silicide layer 252 do not extend to the interface between the isolation structure 208 and the sidewall surfaces 238b and 242a of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively. Therefore, segments 252a and 252c of the silicide layer 252 do not extend along the sidewall surfaces 238b and 242a of the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234, respectively. Therefore, as Figure 2OAs shown, the gate structures 280, 288 and the gate spacers 286, 294 (e.g., silicide barrier structures) prevent the formation of a silicide layer 252 on the sidewall surfaces 224a-b and portion 222a of the top surface 222 of the fourth doped semiconductor region 220, on the sidewall surface 238b and portion 236a of the top surface 236 of the fifth doped semiconductor region 232, and on the sidewall surface 242a and portion 240a of the top surface 240 of the sixth doped semiconductor region 234.

[0095] In various other instances, depending on the materials used, the silicide layer 252 may be formed on the gate electrode layer (e.g., Figure 2N and Figure 2O It is located above at least a portion of the gate electrode layers 268, 274, 284, 292 depicted herein. In this respect, when the gate electrode layer comprises polysilicon, silicides may be formed on the exposed surface of the polysilicon.

[0096] In various instances, the fourth doped semiconductor region 220, the fifth doped semiconductor region 232, and the sixth doped semiconductor region 234 can be formed after the formation of the gate structure (e.g., gate structures 266, 272, 280, 288) and the sidewall spacers (e.g., sidewall spacers 270, 276, 286, 294). In this regard, the gate structure and sidewall spacers (e.g., over one or more of the first doped semiconductor region 214a, the second doped semiconductor region 214b, or the third doped semiconductor region 214c) and the isolation structure 208 can then be formed as described above. A first patterned photoresist layer 216 can then be formed to cover the first doped semiconductor region 214a and the third doped semiconductor region 214c and expose the second semiconductor region 214b. A second implantation process 218, as described above, can then be performed to form the fourth doped semiconductor region 220. Subsequently, the first patterned photoresist layer 216 is removed, and a second patterned photoresist layer 228 can then be formed to cover the fourth doped semiconductor region 220 and expose the first doped semiconductor region 214a and the third doped semiconductor region 214c. A third implantation process 230, as described above, can then be performed to form the fifth doped semiconductor region 232 and the sixth doped semiconductor region 234. Therefore, the steps of method 100 can be performed in a different order while remaining within the scope of this disclosure.

[0097] Now for reference Figure 4A This illustrates various aspects of the disclosure (e.g., with) Figure 1This is a cross-sectional view of the device 400 manufactured using methods associated with method 100. In various instances, device 400 may be a field-effect transistor (FET), a metal-oxide-semiconductor FET (MOSFET), a complementary metal-oxide-semiconductor FET (CMOS), etc. Device 400 includes aspects similar to those of device 200 described above, including a semiconductor substrate 412, an isolation structure 408, a patterned silicide barrier layer 444, a silicide layer 452, a dielectric layer 456, and contacts 458a-c (e.g., first contact 458a, second contact 458b, and third contact 458c), which will likely not be described again below. Device 400 further includes a source 432, a drain 434, a gate structure 464, and a gate spacer 470.

[0098] Source 432 and drain 434 are formed on either side of gate structure 464 in semiconductor substrate 412. In various embodiments, source 432 and drain 434 may be doped with n-type or p-type dopant. In various embodiments, a channel region (within semiconductor substrate 412) extends from source 432 to drain 434 below gate structure 464. In various embodiments, source 432 and / or drain 434 may extend from below gate spacer 470 (or gate structure 464) to isolation structure 408.

[0099] In various instances, the source 432 and drain 434 are doped to have a first conductivity type, and the semiconductor substrate (including the channel region) is doped to have a second conductivity type opposite to the first conductivity type. Therefore, in various instances, a pn junction can be formed between the source 432 or drain 434 and the semiconductor substrate 412 (including the channel region). In other words, the interface between the source 432 or drain 434 and the semiconductor substrate 412 forms a pn junction due to the difference in the type of dopant used in the source 432 or drain 434 and the semiconductor substrate 412 (e.g., opposite conductivity types).

[0100] Gate structure 464 further includes a gate dielectric layer 466 and a gate electrode layer 468. The gate dielectric layer 466 is formed over the semiconductor substrate 412, and the gate electrode layer 468 is formed over the gate dielectric layer 466. A gate spacer 470 is formed along the sidewalls of gate structure 464, and more specifically, along the sidewalls of gate dielectric layer 466 and gate electrode layer 468. Gate structures 280, 288 (including gate dielectric layer 466, gate electrode layer 468, and gate spacer 470) can be referenced above. Figure 2N Similar manner and material formation are described for gate structures 266 and 272 (including gate dielectric layers 271 and 277, gate electrode layers 268 and 274, and gate spacers 270 and 276).

[0101] like Figure 4A As shown, a silicide layer 452 is formed on the source 432 and drain 434, and extends between the gate spacer 470 and the patterned silicide barrier layer 444. In some embodiments, the silicide layer 452 is adjacent (e.g., a physical contact, interface, etc.) to the patterned silicide barrier layer 444. Furthermore, as described above, the patterned silicide barrier layer 444 prevents the formation of the silicide layer 452 on the portions of the source 432 and drain 434 covered by the patterned silicide barrier layer 444. Specifically, as... Figure 4A As shown, a patterned silicide barrier layer 444 (e.g., a barrier structure) is formed over a portion of the top surface 436 of the source 432, a portion of the top surface 440 of the drain 434, and a portion of the top surface 410 of the isolation structure 408. In other words, the patterned silicide barrier layer 444 spans (or overlaps with) a portion of the top surface 436 of the source 432, a portion of the top surface 440 of the drain 434, and a portion of the top surface 410 of the isolation structure 408.

[0102] In various instances, this positioning (or orientation) of the patterned silicide barrier layer 444 prevents silicide formation at and / or around the covered portions of the source and drain 434 at the interface between the source and drain 432 and the isolation structure 408, which reduces leakage current in the device 400. Thus, as shown, the patterned silicide barrier layer 444 prevents the formation of silicide layers 452 along portions of the respective top surfaces 436, 440 and sidewall surfaces 438a, 442a of the source and drain 432. By not extending along the sidewall surfaces 438a, 442a of the source and drain 434, leakage current in the device 400 can be reduced or prevented. This is because when the silicide layer 452 extends along the sidewall surfaces 438a, 442a (or around their edges) of the source 432 and drain 434 toward the semiconductor substrate 412 (e.g., the pn junction between the source 432 or drain 434 and the semiconductor substrate 412), unintentional leakage current may occur.

[0103] In other instances, as described above, the gate structure (e.g., a dummy gate structure) can be used as a patterned silicide barrier layer. For example, see reference... Figure 4B Device 460 is shown to have similar features to device 400, except for the gate structures 480, 488 which serve as patterned silicide barrier layers. In this respect, the gate structures 480, 488 of device 460 have replaced... Figure 4AThe device 460 has a patterned silicide barrier layer 444. In some instances, one or more of the gate structures 480, 488 may be dummy gate structures because the gate structures are non-functional gate structures. In other instances, one or more of the gate structures 480, 488 may be functional gate structures.

[0104] As shown in the figure, gate structures 480 and 488 respectively include gate dielectric layers 482 and 490 and gate electrode layers 484 and 492. Gate dielectric layers 482 and 490 are formed above a portion of the top surface 410 of the isolation structure 408, a portion of the top surface 436 of the source 432, and a portion of the top surface 440 of the drain 434. Gate electrode layers 484 and 492 are formed above gate dielectric layers 482 and 490, respectively. Gate spacers 486 and 494 are formed along the sidewalls of gate structures 480 and 488, more specifically, along the sidewalls of gate dielectric layers 482 and 490 and gate electrode layers 484 and 492, respectively. Gate structures 480 and 488 (including gate dielectric layers 482 and 490, gate electrode layers 484 and 492, and gate spacers 486 and 494) can be compared with those described above. Figure 4A The gate structure 464 (which includes a gate dielectric layer 466, a gate electrode layer 468, and a gate spacer 470) is formed in a similar manner and with similar materials.

[0105] Gate structures 480, 488 and gate spacers 486, 494 are formed on a portion of the top surface 436 of the source 432, a portion of the top surface 440 of the drain 434, and a portion of the top surface 410 of the isolation structure 408, as shown below. Figure 4B As shown. In other words, gate structures 480, 488 (including gate spacers 486, 494) span a portion of the top surface 436 of the source 432, a portion of the top surface 440 of the drain 434, and a portion of the top surface 410 of the isolation structure 408 (or overlap with it). In various instances, this positioning (or orientation) of the gate structures 480, 488 and the gate spacers 486, 494 prevents the formation of silicide at and / or around the interface between the source 432 or drain 434 and the isolation structure 408, which can reduce leakage current in device 460.

[0106] Therefore, as shown, the gate structures 480, 488 and gate spacers 486, 494 prevent the formation of a silicide layer 452 along portions of the respective top surfaces 436, 440 and sidewall surfaces 438a, 442a of the source 432 and drain 434. By not extending along the sidewall surfaces 438a, 442a of the source 432 and drain 434, leakage current in the device 460 can be reduced or prevented. This is because unintentional leakage current may occur when the silicide layer 452 extends along (or around its edges) the sidewall surfaces 438a, 442a of the source 432 and drain 434 toward the semiconductor substrate 412 (e.g., the pn junction between the source 432 or drain 434 and the semiconductor substrate 412).

[0107] Therefore, the methods and apparatus disclosed herein provide improved processes for reducing leakage current in semiconductor devices. As described herein, a barrier structure (e.g., a patterned silicide barrier layer) can be formed over the interface between a semiconductor region (e.g., a doped semiconductor region, source / drain region, active region, etc.) and an isolation structure. That is, the barrier structure spans at least a portion of the semiconductor region and at least a portion of the isolation structure (or overlaps with it). In various instances, this positioning (or orientation) of the barrier structure prevents the formation of silicide at and / or on portions of the semiconductor region at the interface between the semiconductor region and the isolation structure, which can reduce leakage current in the semiconductor device.

[0108] In this regard, after forming the barrier structure (e.g., a patterned silicide barrier layer), a metal layer can be formed above the semiconductor device, encompassing both the barrier structure and the semiconductor region. The barrier structure prevents the formation of the metal layer on the portions of the semiconductor region covered by the barrier structure. An annealing process can then be performed, after which a silicide (e.g., a conductive layer) is formed due to the reaction of the metal layer with the semiconductor region. In other words, metal atoms from the metal layer react with silicon from the semiconductor region to form a silicide above the top surface of the semiconductor region not covered by the barrier structure (rather than along the sidewall surfaces of the semiconductor region). Therefore, the patterned silicide barrier layer prevents the formation of silicide along the sidewall surfaces of the semiconductor region, which reduces leakage current in the semiconductor device.

[0109] Leakage current in a semiconductor device can be reduced or prevented by preventing the formation of silicides along the sidewalls of the semiconductor region. Leakage current in a semiconductor device can be caused and / or amplified by silicides allowed to extend along the sidewalls (or edges) of the semiconductor region toward the pn junction. Reducing and / or avoiding the formation of silicides along the sidewalls (or edges) of the semiconductor region reduces and / or prevents leakage current that may be caused by silicides. Devices formed using the methods and processes disclosed herein exhibit reduced leakage current compared to baseline methods. This improvement may be attributed to the patterned silicide barrier layer preventing the formation of silicide layers along the sidewalls of the semiconductor region (e.g., doped semiconductor region, source / drain region, active region, etc.).

[0110] Finally, it should be understood that any of the foregoing concepts may be used alone or in combination with any or all of the other foregoing concepts. Although various examples have been disclosed and described, it should be understood, recognized, and / or anticipated that certain modifications will fall within the scope of this disclosure. Therefore, this description is not intended to be exhaustive or to limit the principles described or illustrated herein to any precise form. In light of the foregoing teachings, many modifications and variations are possible.

Claims

1. An apparatus comprising: A first semiconductor region is disposed above a substrate, and the first semiconductor region has a first conductivity type; A second semiconductor region is disposed above the first semiconductor region, and the second semiconductor region has a second conductivity type opposite to the first conductivity type; An isolation structure is disposed above the substrate, the isolation structure being adjacent to the second semiconductor region; A barrier structure that spans a first portion of the second semiconductor region and a portion of the isolation structure; as well as A conductive layer is disposed above a second portion of the second semiconductor region, the conductive layer being adjacent to the barrier structure.

2. The apparatus of claim 1, wherein the conductive layer comprises a silicide layer.

3. The apparatus according to claim 1, further comprising: A third semiconductor region, disposed above the substrate, having the first conductivity type, wherein: The isolation structure extends from the second semiconductor region to the third semiconductor region; and The blocking structure docks with the portion of the isolation structure.

4. The apparatus of claim 3, wherein the conductive layer is a first conductive layer, and the apparatus further comprises: Second conductive layer; and The second conductive layer is disposed above the third semiconductor region.

5. The apparatus of claim 3, wherein the blocking structure extends continuously from above the second semiconductor region to above the third semiconductor region.

6. The apparatus of claim 5, wherein the conductive layer is a first conductive layer, the apparatus further comprising: A second conductive layer is disposed above a first portion of the third semiconductor region, and a blocking structure is disposed above a second portion of the third semiconductor region.

7. The apparatus of claim 1, wherein the second semiconductor region has a sidewall having a first portion abutting the isolation structure and a second portion abutting the barrier structure.

8. The apparatus of claim 1, wherein a pn junction is formed at the interface between the second semiconductor region and the first semiconductor region.

9. The apparatus of claim 1, wherein the blocking structure comprises a dielectric material or polysilicon.

10. The apparatus of claim 1, further comprising: A contact feature that extends into the conductive layer, wherein the blocking structure is laterally mated to the contact feature.

11. The apparatus of claim 10, wherein a first portion of the contact feature is bonded to the conductive layer, and a second portion of the contact feature is bonded to the second semiconductor region.

12. An apparatus comprising: A first semiconductor region and a second semiconductor region are disposed above a substrate, the first semiconductor region having a first conductivity type and the second semiconductor region having a second conductivity type opposite to the first conductivity type; An isolation region is disposed adjacent to and laterally surrounds the first semiconductor region and the second semiconductor region; A barrier structure that spans a first portion of the second semiconductor region and a portion of the isolation region; as well as A conductive layer is disposed above the second portion of the second semiconductor region.

13. The apparatus of claim 12, wherein the conductive layer comprises a silicide layer.

14. The apparatus of claim 13, wherein the silicide layer comprises a metal selected from the group consisting of titanium (Ti), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo), platinum (Pt), and chromium (Cr).

15. The apparatus of claim 12, wherein the second semiconductor region has a sidewall having a first portion abutting the isolation region and a second portion abutting the barrier structure.

16. The apparatus of claim 12, further comprising: A third semiconductor region is disposed above the substrate, and an isolation region is further disposed adjacent to the third semiconductor region, wherein the blocking structure is further disposed above a portion of the third semiconductor region.

17. The apparatus of claim 12, further comprising: The gate structure of the transistor is disposed above the first semiconductor region, wherein: The first semiconductor region is the channel region of the transistor; The second semiconductor region is the source / drain region of the transistor; and The isolation zone is a shallow trench isolation structure.

18. A method comprising: A dielectric isolation structure is formed in the semiconductor layer; A barrier layer is formed over a first portion of the semiconductor layer and over a portion of the dielectric isolation structure; as well as A conductive layer is formed over the second portion of the semiconductor layer.

19. The method of claim 18, further comprising: A first semiconductor region is formed in the semiconductor layer, and the first semiconductor region has a first conductivity type; A second semiconductor region is formed in the semiconductor layer, the second semiconductor region having a second conductivity type opposite to the first conductivity type; as well as Forming the barrier layer over the first portion of the semiconductor layer includes forming the barrier layer on a portion of the second semiconductor region but not on any portion of the first semiconductor region.

20. The method of claim 18, further comprising: An interlayer dielectric layer is formed over the conductive layer and the barrier layer; Remove portions of the interlayer dielectric layer and the barrier layer to form an opening; as well as A contact feature is formed within the opening.

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