Semiconductor element comprising a spacer structure

Abstract

This application discloses a spacer structure, a semiconductor device having the spacer, and a method for manufacturing the semiconductor device having the spacer. The spacer structure includes: an inner spacer located on one side of the bit line structure, wherein the material of the inner spacer includes silicon carbide; an intermediate spacer located on the inner spacer; and an outer spacer located on the intermediate spacer.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Application No. 19 / 174,181, filed on April 9, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a spacer structure, a semiconductor element including the spacer structure, and a method for manufacturing the semiconductor element. More specifically, it relates to an isolation structure including silicon carbide, a semiconductor element having the isolation structure, and a method for manufacturing the semiconductor element including the isolation structure. Background Technology

[0004] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, this shrinkage process also introduces many problems, and these problems are constantly increasing. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0005] The discussion in the prior art paragraph is for background information only. The statements in the discussion of the prior art paragraph are not an admission that the content disclosed in this paragraph constitutes prior art to this disclosure, and nothing in the discussion of the prior art paragraph shall be construed as an admission that any part of this application, including the part in the discussion of the prior art paragraph, constitutes prior art to this disclosure. Summary of the Invention

[0006] One aspect of this disclosure provides a spacer structure, comprising: an inner spacer located on one side of a bit line structure, wherein the inner spacer comprises silicon carbide; an intermediate spacer located on the inner spacer; and an outer spacer located on the intermediate spacer.

[0007] Another aspect of this disclosure provides a semiconductor device comprising: a substrate; a bit line structure disposed on the substrate; and a spacer structure including an inner spacer compliantly disposed on one side of the bit line structure, an intermediate spacer compliantly disposed on the inner spacer, and an outer spacer compliantly disposed on the intermediate spacer. The inner spacer comprises silicon carbide.

[0008] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a plurality of bit line contact structures in the substrate; forming a plurality of bit line structures on the plurality of bit line contact structures, wherein the plurality of bit line structures are separated by a plurality of trenches and a plurality of grooves extending downward from the plurality of trenches and adjacent to the bit line contact structures; conformally forming a first spacer material covering the plurality of bit line structures, the plurality of bit line contact structures, the plurality of trenches and the plurality of grooves; forming a plurality of fill layers to fill the plurality of grooves; conformally forming a second spacer material covering the first spacer material and the plurality of fill layers; performing a first spacer etching process to transform the first spacer material into a plurality of internal spacers and the second spacer material into a plurality of intermediate spacers; and conformally forming a plurality of external spacers on the plurality of intermediate spacers to constitute a plurality of spacer structures. The first spacer material includes silicon oxide.

[0009] Due to the design of the semiconductor device disclosed herein, the internal spacers formed of silicon carbide can effectively protect the bit line structure during subsequent etching processes. Their strong chemical resistance helps reduce defects such as bit line leakage current, thereby improving the yield of the semiconductor device. Furthermore, the low dielectric constant of the silicon carbide internal spacers can reduce parasitic capacitance between adjacent bit line structures, thereby improving the overall performance of the semiconductor device.

[0010] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0011] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and the scope of the claim. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0012] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0013] Figure 2 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure;

[0014] Figure 3 and Figure 4 This is a cross-sectional view, illustrating along... Figure 2 The section lines A-A' and B-B' in the figure represent a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 5 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure;

[0016] Figures 6 to 8 This is a cross-sectional view, illustrating along... Figure 5 The section lines A-A' and B-B' in the figure represent a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 9 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure;

[0018] Figure 10 and Figure 11 This is a cross-sectional view, illustrating along... Figure 9 The section lines A-A' and B-B' in the figure represent a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 12 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure;

[0020] Figure 13 It is along Figure 12 The cross-sectional views taken by sections A-A' and B-B' in the diagram;

[0021] Figure 14 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure;

[0022] Figure 15 and Figure 16 This is a cross-sectional view, illustrating along... Figure 14 The section lines A-A' and B-B' in the figure represent a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 17 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure;

[0024] Figure 18 It is along Figure 17 The cross-sectional views taken by sections A-A' and B-B' in the diagram;

[0025] Figure 19 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure;

[0026] Figure 20 It is along Figure 19 The cross-sectional views taken by sections A-A' and B-B' in the diagram;

[0027] Figure 21 The top view illustrates a semiconductor element at an intermediate stage according to an embodiment of the present disclosure; and

[0028] Figures 22 to 29 This is a cross-sectional view, illustrating along... Figure 21 The section lines A-A' and B-B' in the diagram represent a portion of the manufacturing process of a semiconductor device according to an embodiment of this disclosure.

[0029] The reference numerals in the attached figures are explained as follows:

[0030] 1A: Semiconductor components

[0031] 10: Method

[0032] 101: Substrate

[0033] 103: Isolation layer

[0034] 105: Impurity Zone

[0035] 105a: Common source pole region

[0036] 105b: Drain region

[0037] 107: Bottom Insulation Layer

[0038] 210: Spacer Structure

[0039] 211: Internal spacers

[0040] 213: Intermediate spacer

[0041] 215: External spacers

[0042] 310: Filler layer

[0043] 310TS: Top surface

[0044] 510: Character Line Structure

[0045] 511: Character line dielectric layer

[0046] 513: Conductive layer at the bottom of the character line

[0047] 515: Top conductive layer of character line

[0048] 517: Character Line Overlay

[0049] 520: Bitline Structure

[0050] 520TS: Top Surface

[0051] 521: Bottom conductive layer of bit line

[0052] 523: Top conductive layer of bit line

[0053] 525: Bitline overlay

[0054] 530: Bit line contact structure

[0055] 530B: Bottom surface

[0056] 531: Bit line contact

[0057] 533: Contact isolation partition

[0058] 533S: Sidewall

[0059] 701: First Insulation Material

[0060] 707: Second Insulation Material

[0061] 711: First mask layer

[0062] 713: Second mask layer

[0063] 715: Hard mask layer

[0064] 723: Contact isolation layer

[0065] 723a: Part 1

[0066] 723b: Part Two

[0067] 731: First conductive material

[0068] 733: Second conductive material

[0069] 741: First spacer material

[0070] 743: Second spacer material

[0071] 745: Third spacer material

[0072] AA: Active Zone

[0073] OP1: Bit line contact opening

[0074] R1: Groove

[0075] R1B: Bottom

[0076] R1S: Surface

[0077] S1: First side

[0078] S2: Second side

[0079] S3: Side

[0080] S11: Steps

[0081] S13: Steps

[0082] S15: Steps

[0083] S17: Steps

[0084] S19: Steps

[0085] S21: Steps

[0086] S23: Steps

[0087] SW: Sidewall

[0088] TR: Character line groove

[0089] TR1: Trench

[0090] TR1B: Bottom

[0091] TR1S: Surface

[0092] W1: Width

[0093] W2: Width

[0094] W3: Width Detailed Implementation

[0095] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0096] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used herein to describe the relative relationship between one element or feature and another shown in the accompanying drawings. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the element in use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein may be interpreted accordingly.

[0097] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to the other component or layer, or there may be intermediate components or intermediate layers.

[0098] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one component from another. Thus, for example, the first component, first member, or first part discussed below may be referred to as the second component, second member, or second part without departing from the teachings of this disclosure.

[0099] Unless the context otherwise indicates, terms such as “identical,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean exactly identical orientations, layouts, locations, shapes, dimensions, quantities, or other measures of reference, but are intended to cover substantially identical orientations, layouts, locations, shapes, dimensions, quantities, or other measures of reference within an acceptable range of possible variations (e.g., due to manufacturing processes). The term “substantially” may be used herein to reflect this meaning. For example, articles described as “substantially identical,” “substantially equal,” or “substantially coplanar” may be exactly identical, equal, or coplanar, or may be substantially identical, equal, or coplanar within an acceptable range of possible variations (e.g., due to manufacturing processes).

[0100] In this disclosure, semiconductor element generally refers to an element that can operate using semiconductor properties, and electro-optic elements, light-emitting display elements, semiconductor circuits and electronic components are all included in the category of semiconductor element.

[0101] It should be noted that, in the description of this disclosure, "above" (or "up") corresponds to the direction of the arrow in the Z direction, and "below" (or "down") corresponds to the opposite direction of the arrow in the Z direction.

[0102] Figure 1This is a flowchart illustrating a method 10 for manufacturing a semiconductor element 1A according to an embodiment of the present disclosure. Figure 2 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 3 and Figure 4 This is a cross-sectional view, illustrating along... Figure 2 The section lines A-A' and B-B' in the figure represent a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 5 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figures 6 to 8 This is a cross-sectional view, illustrating along... Figure 5 The section lines A-A' and B-B' in the figure represent a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0103] See Figures 1 to 8 In step S11, a substrate 101 can be provided, an isolation layer 103 can be formed in the substrate 101 to define multiple active regions AA, multiple impurity regions 105 can be formed in the multiple active regions AA, and multiple word line structures 510 can be formed in the substrate 101 and intersect with the multiple active regions AA, thereby transforming the multiple impurity regions 105 into multiple common source regions 105a and multiple drain regions 105b.

[0104] See Figure 2 and Figure 3 The substrate 101 may include a main semiconductor substrate. The main semiconductor substrate may be formed of materials such as: elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0105] In some embodiments, substrate 101 may include a semiconductor-on-insulator structure comprising, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer may be formed of the same material as the aforementioned main semiconductor substrate. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is that the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides, such as silicon oxide stacked with silicon nitride or boron nitride in any order. The insulating layer may have a thickness between about 10 nm and 200 nm. The insulating layer can eliminate leakage current between adjacent elements in substrate 101 and reduce source / drain-related parasitic capacitance.

[0106] It should be noted that the term "about," which modifies the amount of ingredients, components, or reactants in this disclosure, refers, for example, to numerical variations that may occur through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to unintentional errors in the measurement procedures, differences in the manufacture, source, or purity of the ingredients used to prepare the composition or to carry out the method, etc. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0107] See Figure 2 and Figure 3 An isolation layer 103 can be formed in substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on substrate 101. Photolithography and subsequent etching processes, such as anisotropic dry etching, can be performed to form trenches that penetrate the pad oxide layer, the pad nitride layer, and extend into substrate 101. An insulating material can be deposited into these trenches, followed by planarization processes, such as chemical mechanical polishing, until the top surface of substrate 101 is exposed to remove excess filler material and provide a substantially flat surface for subsequent process steps, while simultaneously forming isolation layer 103. The insulating material can be, for example, silicon oxide or other suitable insulating materials. Isolation layer 103 can define multiple active regions AA in substrate 101.

[0108] It should be noted that, in the description of this disclosure, the surface of the element (or feature) at its highest vertical height along the Z-axis is referred to as the top surface of this element (or feature). The surface of the element (or feature) at its lowest vertical height along the Z-axis is referred to as the bottom surface of this element (or feature).

[0109] It should be noted that each of the plurality of active regions AA may include a portion of substrate 101 and the space above that portion of substrate 101. When describing a component as being disposed on an active region AA, it means that the component is disposed on the top surface of that portion of substrate 101. When describing a component as being disposed within an active region AA, it means that the component is disposed within that portion of substrate 101; however, the top surface of the component may be flush with the top surface of that portion of substrate 101. When describing a component as being disposed above an active region AA, it means that the component is disposed above the top surface of that portion of substrate 101.

[0110] See Figure 2 and Figure 3Multiple impurity regions 105 can be formed, respectively and correspondingly, in multiple active regions AA. In some embodiments, multiple impurity regions 105 can be formed by a placement process. That is, multiple impurity regions 105 can be transformed from portions of multiple active regions AA. The dopants in the placement process can include p-type impurities (dopants) or n-type impurities (dopants). P-type impurities can be added to the intrinsic semiconductor to generate defects for valence electrons. Examples of p-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, boron, aluminum, gallium, and indium. N-type impurities can be added to the intrinsic semiconductor to contribute free electrons to the intrinsic semiconductor. Examples of n-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus. In some embodiments, the dopant concentration of the multiple impurity regions 105 can be between about 1E19 atoms / cm³. 3 With approximately 1E21 atoms / cm 3 Between. After the implantation process, multiple impurity regions 105 can have conductivity types such as n-type or p-type.

[0111] See Figure 4 A bottom insulating layer 107 can be formed on the substrate 101 and the isolation layer 103. In some embodiments, the bottom insulating layer 107 can be formed of a material that is etch-selective to the substrate 101 and the isolation layer 103. In some embodiments, the bottom insulating layer 107 can be formed of materials such as silicon nitride, boron nitride, boron silicon nitride, boron phosphorus nitride, silicon carbide nitride, or combinations thereof. In some embodiments, the bottom insulating layer 107 can be formed of, for example, silicon nitride. In some embodiments, the bottom insulating layer 107 can be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0112] See Figure 4 A first mask layer 711 may be formed on the bottom insulating layer 107. In some embodiments, the first mask layer 711 may be a photoresist layer and may include a pattern of a plurality of character line structures 510.

[0113] It should be noted that, for clarity, in Figure 5 The bottom insulating layer 107 is not shown in the image.

[0114] See Figure 5 and Figure 6The first mask layer 711 can be used as a mask for etching to form a plurality of word line trenches TR in the substrate 101. In some embodiments, the plurality of word line trenches TR may have a linear cross-sectional profile and extend along the Y direction and pass through (or intersect) a plurality of impurity regions 105 in a top perspective view. For example, each impurity region 105 may intersect with two word line trenches TR. The plurality of word line trenches TR can divide the plurality of impurity regions 105 into a plurality of common source regions 105a and a plurality of drain regions 105b. For one impurity region 105, a common source region 105a may be formed between two word line trenches TR, and two drain regions 105b may be formed respectively and correspondingly between the isolation layer 103 and the two word line trenches TR.

[0115] See Figure 7 A word line dielectric layer 511 can be compliantly formed on the inner surface of the word line trench TR and on the top surface of the bottom insulating layer 107. The word line dielectric layer 511 may have a U-shaped cross-sectional profile in the word line trench TR. In some embodiments, the word line dielectric layer 511 may be formed by a thermal oxidation process. For example, the word line dielectric layer 511 may be formed by oxidizing the inner surface of the word line trench TR. In some embodiments, the word line dielectric layer 511 may be formed by a deposition process, such as chemical vapor deposition or atomic layer deposition. The word line dielectric layer 511 may include a high-k material, oxide, nitride, oxynitride, or a combination thereof. In some embodiments, the word line dielectric layer 511 may be formed by free radical oxidation of the pad polysilicon layer after deposition of a pad polysilicon layer (not shown for clarity). In some embodiments, after forming a pad silicon nitride layer (not shown for clarity), the word line dielectric layer 511 can be formed by free radical oxidation of the pad silicon nitride layer.

[0116] In some embodiments, the high dielectric constant material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high dielectric constant material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0117] See Figure 7Multiple bottom conductive layers 513 of the character lines can be formed respectively and correspondingly on the character line dielectric layer 511 and within the multiple character line trenches TR. In some embodiments, in order to form the multiple bottom conductive layers 513 of the character lines, a conductive layer (not shown for clarity) can be formed to fill the multiple character line trenches TR, and a recessing process can be subsequently performed. The recessing process can be an etch-back process, or a planarization process and an etch-back process performed sequentially. The multiple bottom conductive layers 513 of the character lines can have a recessed shape that partially fills the multiple character line trenches TR. That is, the top surface of the multiple bottom conductive layers 513 of the character lines can be lower than the top surface of the substrate 101.

[0118] In some embodiments, the plurality of bottom conductive layers 513 for character lines may include a metal, a metal nitride, or a combination thereof. For example, the plurality of bottom conductive layers 513 for character lines may be formed of titanium nitride, tungsten, or titanium nitride / tungsten. After conformally forming titanium nitride, titanium nitride / tungsten may have a structure in which tungsten partially fills the plurality of character line trenches TR. Titanium nitride or tungsten may be used alone in the plurality of bottom conductive layers 513 for character lines. In some embodiments, the plurality of bottom conductive layers 513 for character lines may be formed of conductive materials such as doped polysilicon, doped polysilicon germanium, or a combination thereof. In some embodiments, the plurality of bottom conductive layers 513 for character lines may be formed of materials such as tungsten, aluminum, titanium, copper, similar materials, or a combination thereof.

[0119] See Figure 7 Multiple top conductive layers 515 of character lines can be formed correspondingly on the bottom conductive layers 513 of multiple character lines and within the multiple character line trenches TR. In some embodiments, in order to form the multiple top conductive layers 515 of character lines, conductive layers (not shown for clarity) can be formed to fill the multiple character line trenches TR, and a recessing process can be subsequently performed. The recessing process can be an etch-back process, or a planarization process and an etch-back process performed sequentially. The multiple top conductive layers 515 of character lines can have a recessed shape that partially fills the multiple character line trenches TR. That is, the top surface of the multiple top conductive layers 515 of character lines can be lower than the top surface of the substrate 101.

[0120] In some embodiments, the top conductive layer 515 of the plurality of character lines may include materials such as polysilicon, polycrystalline germanium, polycrystalline silicon-germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or combinations thereof. In some embodiments, the top conductive layer 515 of the plurality of character lines may be doped with p-type or n-type dopants. In some embodiments, doping may be performed by introducing dopants during the deposition process used to form the conductive layer.

[0121] See Figure 8Dielectric material can be deposited, for example, by chemical vapor deposition, to completely fill the multiple word line trenches TR and cover the top surface of the bottom insulating layer 107. A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent process steps and form the word line capping layer 517. In some embodiments, the word line capping layer 517 may include, for example, silicon nitride or other suitable dielectric material. The word line dielectric layer 511, the multiple word line bottom conductive layers 513, the multiple word line top conductive layers 515, and the word line capping layer 517 together constitute multiple word line structures 510. The multiple word line structures 510 may, respectively and correspondingly, separate the multiple common source regions 105a and the multiple drain regions 105b.

[0122] Figure 9 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 10 and Figure 11 This is a cross-sectional view, illustrating along... Figure 9 The section lines A-A' and B-B' in the figure represent a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 12 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 13 It is along Figure 12 The cross-sectional views taken by sections A-A' and B-B' in the diagram.

[0123] See Figure 1 and Figures 9 to 13 In step S13, multiple bit line contact openings OP1 can be formed to expose multiple common source regions 105a, and multiple contact isolation layers 723 can be formed to cover the sidewalls SW of the multiple bit line contact openings OP1.

[0124] See Figure 9 and Figure 10 Multiple bitline contact openings OP1 can be formed by photolithography and subsequent etching processes. The bitline contact openings OP1 can penetrate the word line capping layer 517, the word line dielectric layer 511, and the bottom insulating layer 107, and extend to the substrate 101. The common source region 105a can be exposed through the bitline contact openings OP1. In some embodiments, the bitline contact openings OP1 can have a rectangular or square cross-sectional profile in a top perspective view.

[0125] See Figure 11A first insulating material 701 is compliantly formed within the plurality of bit line contact openings OP1 and on the top surface of the word line cover layer 517. In some embodiments, the first insulating material 701 may include, for example, a material having etch selectivity to the substrate 101. In some embodiments, the first insulating material 701 may include, for example, silicon nitride or other suitable insulating materials. In some embodiments, this first insulating material 701 may be formed by, for example, atomic layer deposition, chemical vapor deposition or other suitable deposition processes.

[0126] See Figure 12 and Figure 13 An etching process can be performed to remove the first insulating material 701 formed on the common source region 105a. In some embodiments, the etching process can be an anisotropic etching process. For example, the etching process can be an anisotropic dry etching process. After the etching process, the remaining first insulating material 701 located on the sidewalls SW of the plurality of bit line contact openings OP1 can be referred to as a plurality of contact isolation layers 723.

[0127] See Figure 12 and Figure 13 Each of the plurality of contact isolation layers 723 may include two first portions 723a and two second portions 723b. In a top perspective view, the two first portions 723a may be parallel to each other and extend along the X direction. The two second portions 723b may be parallel to each other and extend along the Y direction. In a top perspective view, the first portions 723a and the second portions 723b together form a cross-sectional profile of a rectangular ring or a square ring.

[0128] Figure 14 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 15 and Figure 16 This is a cross-sectional view, illustrating along... Figure 14 The section lines A-A' and B-B' in the figure represent a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 17 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 18 It is along Figure 17 The cross-sectional views taken by sections A-A' and B-B' in the diagram.

[0129] See Figure 1 and Figures 14 to 18 In step S15, multiple contact isolation layers 723 may be partially removed to form multiple contact isolation spacers 533.

[0130] See Figure 14 and Figure 15A plurality of hard mask layers 715 may be formed on the character line overlay layer 517 to selectively mask the first portion 723a. In some embodiments, the plurality of hard mask layers 715 may comprise a material having etch selectivity for both the character line overlay layer 517 and the substrate 101. In some embodiments, the plurality of hard mask layers 715 may be formed of materials such as boron nitride, silicon boron nitride, boron phosphorus nitride, silicon boron carbon nitride, or similar materials. In some alternative embodiments, the plurality of hard mask layers 715 may be photoresist layers.

[0131] See Figure 16 Multiple hard mask layers 715 can be used as masks for the etching process to selectively remove the second portion 723b. In some embodiments, the etching process can be an anisotropic etching process, such as anisotropic dry etching. The remaining first portion 723a can be referred to as contact spacer 533.

[0132] See Figure 17 and Figure 18 Multiple hard mask layers 715 can be removed. For each of the bitline contact openings OP1, two contact spacers 533 can be provided on the sidewall SW of the bitline contact opening OP1, parallel to each other and extending along the X direction in the top perspective view. In some embodiments, the width W1 of the contact spacers 533 may be substantially the same as the width W2 of the bitline contact opening OP1. In some embodiments, the width W1 of the contact spacers 533 may be smaller than the width W2 of the bitline contact opening OP1. In some embodiments, the ratio of the width W1 of the contact spacers 533 to the width W2 of the bitline contact opening OP1 may be between about 0.90 and 1.00 or between about 0.95 and 1.00.

[0133] Figure 19 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 20 It is along Figure 19 The cross-sectional views taken by sections A-A' and B-B' in the diagram.

[0134] See Figure 1 and Figure 19 and Figure 20 In step S17, multiple bit line contacts 531 can be formed in multiple bit line contact openings OP1, thereby forming multiple bit line contact structures 530 together with multiple contact isolation spacers 533.

[0135] See Figure 19 and Figure 20A conductive material (not shown) can be formed to completely fill the plurality of bit line contact openings OP1. A planarization process, such as chemical mechanical polishing, can be performed until the top surface of the word line overlay 517 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming the plurality of bit line contacts 531. In some embodiments, the conductive material may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof. In some embodiments, the conductive material may be formed by, for example, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes.

[0136] In some embodiments, the plurality of bit line contacts 531 may have a square or rectangular cross-sectional profile in a top perspective view. In some embodiments, each of the plurality of bit line contacts 531 may include two first sides S1 and two second sides S2. The two first sides S1 may be parallel to each other and extend along the X direction. The two second sides S2 may be parallel to each other and extend along the Y direction. Two contact spacers 533 may respectively and correspondingly cover the two first sides S1. In some embodiments, the width W3 of the bit line contact 531 (the distance between the two second sides S2) may be substantially the same as the width W1 of the contact spacer 533. In some embodiments, the width W3 of the bit line contact 531 may be greater than the width W1 of the contact spacer 533. In some embodiments, the ratio of the width W1 of the contact spacer 533 to the width W3 of the bit line contact 531 may be between about 0.90 and 1.00 or between about 0.95 and 1.00.

[0137] Figure 21 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figures 22 to 29 This is a cross-sectional view, illustrating along... Figure 21 The section lines A-A' and B-B' in the figure represent a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0138] See Figure 1 and Figures 21 to 23 In step S19, multiple bit line structures 520 can be formed on multiple bit line contact structures 530. These multiple bit line structures 520 are separated by multiple grooves TR1, and multiple grooves R1 extending from the multiple grooves TR1 and adjacent to the multiple bit line contact structures 530 can be formed.

[0139] See Figure 21 and Figure 22A first conductive material 731 can be formed on the character line overlay layer 517 and the plurality of bit line contact structures 530. In some embodiments, the first conductive material 731 may include, for example, doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, the dopants used for this first conductive material 731 may include boron, aluminum, gallium, indium, antimony, arsenic, or phosphorus. In some embodiments, this first conductive material 731 may be formed by, for example, chemical vapor deposition or other suitable deposition processes.

[0140] See Figure 21 and Figure 22 A second conductive material 733 may be formed on the first conductive material 731. In some embodiments, the second conductive material 733 may include, for example, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other suitable conductive materials, or combinations thereof. In some embodiments, the second conductive material 733 may be formed by, for example, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes.

[0141] See Figure 21 and Figure 22 A second insulating material 707 can be formed on this second conductive material 733. In some embodiments, the second insulating material 707 may include, for example, silicon nitride or other suitable insulating materials. In some embodiments, this second insulating material 707 can be formed by, for example, chemical vapor deposition or other suitable deposition processes.

[0142] See Figure 21 and Figure 22 A second mask layer 713 may be formed on this second insulating material 707. In some embodiments, the second mask layer 713 may be a photoresist layer and may include a pattern of a plurality of bit line structures 520. In some embodiments, in a top perspective view, the pattern of the second mask layer 713 may include a plurality of linear profiles extending along the X direction and staggered along the Y direction.

[0143] See Figure 23The second mask layer 713 can be used as a mask for etching to remove portions of the second insulating material 707, the second conductive material 733, and the first conductive material 731. In some embodiments, the etching process can be an anisotropic etching process, such as anisotropic dry etching. After the etching process, the remaining first conductive material 731 can be referred to as the plurality of bit line bottom conductive layers 521. The remaining second conductive material 733 can be referred to as the plurality of bit line top conductive layers 523. The remaining second insulating material 707 can be referred to as the plurality of bit line cover layers 525. The plurality of bit line bottom conductive layers 521, the plurality of bit line top conductive layers 523, and the plurality of bit line cover layers 525 together constitute a plurality of bit line structures 520.

[0144] The space between the multiple bitline structures 520 can be referred to as multiple trenches TR1. The multiple trenches TR1 can extend along the X direction. Multiple recesses R1 can be formed to extend from the multiple trenches TR1 and are positioned adjacent to the multiple bitline contact structures 530. Contact spacers 533 can be exposed through the multiple recesses R1. In some embodiments, the bottom R1B of the multiple recesses R1 can be lower than the bottom surface 530B of the bitline contact structure 530.

[0145] After forming multiple bit line structures 520, the second mask layer 713 can be removed by ashing or other applicable processes.

[0146] See Figure 1 and Figures 24 to 26 In step S21, a first spacer material 741 can be compliantly formed to cover multiple bit line structures 520 and located within multiple grooves R1, multiple filling layers 310 can be formed to fill multiple grooves R1, and a second spacer material 743 can be compliantly formed on the first spacer material 741 and the multiple filling layers 310.

[0147] See Figure 24 The first spacer material 741 can be compliantly formed on the surfaces TR1S of the multiple bit line structures 520, the multiple trenches TR1, and the multiple grooves R1. That is, the top surface 520TS and side edges S3 of the multiple bit line structures 520, as well as the sidewalls 533S of the contact spacers 533, can be covered by this first spacer material 741.

[0148] In some embodiments, the first spacer material 741 may be, for example, silicon carbide. The molecular formula of a silicon carbide film is commonly referred to as SiCO. This notation does not limit the bonding or chemical state of silicon (Si), oxygen (O), or carbon (C). In some embodiments, the first spacer material 741 may include other elements besides Si, O, and / or C, such as sulfur (S). In some embodiments, this first spacer material 741 may include Si-C bonds and / or Si-O bonds. In some embodiments, this first spacer material 741 may include both Si-C and Si-O bonds, and may not include Si-N bonds. In addition to Si-C and / or Si-O bonds, Si-S bonds may also be present. In some embodiments, the number of Si-O bonds in this first spacer material 741 may be greater than the number of Si-C bonds, with a ratio ranging from about 1:1 to about 10:1.

[0149] In some embodiments, the carbon content of the first spacer material 741, on an atomic basis, may range from about 0.1% to about 40%, about 0.5% to about 30%, about 1% to about 30%, or about 5% to about 20%. In some embodiments, the oxygen content of the first spacer material 741, on an atomic basis, may be at least about 20%, about 40%, or about 50%. In some embodiments, the oxygen content of the first spacer material 741, on an atomic basis, may range from 10% to about 70%, about 15% to about 50%, or about 20% to about 40%. In some embodiments, the silicon content of the first spacer material 741, on an atomic basis, may be up to about 50%. In some embodiments, the silicon content of the first spacer material 741, on an atomic basis, may be at least about 15%, about 20%, about 25%, or about 30%. In some embodiments, the silicon content of the first spacer material 741, on an atomic basis, may range from about 10% to about 50%, about 15% to about 40%, or about 20% to about 35%. In some embodiments, the sulfur content of the first spacer material 741, on an atomic basis, can be as high as about 40%. In some embodiments, the sulfur content of the first spacer material 741, on an atomic basis, can range from about 0.01% to about 40%, about 0.1% to about 40%, about 0.5% to about 30%, or about 1% to about 20%. In some embodiments, the sulfur content of the first spacer material 741, on an atomic basis, can be at least about 1%, about 10%, or about 20%.

[0150] In some embodiments, the first spacer material 741 may not contain a significant amount of nitrogen. In some embodiments, the nitrogen content of the first spacer material 741, on an atomic basis, may be less than about 30%, less than about 20%, less than about 15%, less than about 10%, less than about 5%, less than about 1%, or less than about 0.1%. In some embodiments, the first spacer material 741 does not contain nitrogen.

[0151] In some embodiments, the deposition of this first spacer material 741 can be performed using a plasma-enhanced atomic layer deposition (PEALD) process. The PEALD process may include at least one deposition cycle. Each cycle can start from... Figure 23 The intermediate semiconductor element shown is initially exposed to a nitrogen-free gaseous silicon-containing precursor (referred to as the precursor step). This step allows the silicon-containing material to adsorb onto the surface of the intermediate semiconductor element.

[0152] After exposure to the precursor, a purge gas and / or vacuum can be applied to remove any excess silicon precursor and reaction byproducts (referred to as the first purging step). Next, the surface of the intermediate semiconductor element can be exposed to a reactant, comprising hydrogen-based reactive substances, generated by plasma (referred to as the reactant step). The plasma energy promotes the transformation of the adsorbed silicon material into this first spacer material 741, which comprises SiCO. Similar to the precursor step, a purge gas and / or vacuum can be used to remove any excess reactants and byproducts (referred to as the second purging step).

[0153] These successive exposure and removal steps form a complete deposition cycle. To achieve the required thickness and composition of this first spacer material 741, the deposition cycle can be repeated multiple times.

[0154] In some embodiments, the silicon-containing precursor must be nitrogen-free. In some embodiments, the silicon-containing precursor may be halogen-free. In some embodiments, the silicon-containing precursor may be, for example, bis(triethoxysilyl)ethane (BTESE), 3-methoxypropyltrimethoxysilane (MPTMS), and / or (3-mercaptopropyl)trimethoxysilane. In some embodiments, more than one silicon-containing precursor may be used simultaneously or in alternating deposition cycles to optimize film properties. In some embodiments, the pulse duration of the precursor step may be between about 4 seconds and about 10 seconds.

[0155] In some embodiments, the reactants may include hydrogen, which is used to generate reactive substances by means of plasma. In some embodiments, the reactants may not contain any oxygen. In some embodiments, the reactants may include a low atomic percentage of oxygen (less than about 50 atomic% to less than 0.001 atomic%). In some embodiments, the reactants may not contain nitrogen. In some embodiments, the reactants may include a low atomic percentage of nitrogen (less than about 25 atomic% to less than 0.001 atomic%). In some alternative embodiments, nitrogen-containing substances may be intentionally introduced. In some embodiments, the reactive substances generated by the reactants may include hydrogen plasma, hydrogen atoms, hydrogen radicals, and / or hydrogen ions.

[0156] In some embodiments, the reactants may be, for example, substantially pure hydrogen; a mixture of hydrogen and an inert gas; or a mixture of hydrogen and nitrogen. In some embodiments, the inert gas may include helium, neon, argon, krypton, and xenon. In some embodiments, the atomic percentage of nitrogen in the hydrogen and nitrogen mixture may be less than 20%. In some embodiments, the reactants may include compounds having both N and H (e.g., NH3 and N2H4).

[0157] In some embodiments, the plasma power used to generate reactive material from reactants may be between about 5 W and about 5000 W, or between about 100 W and about 300 W. In some embodiments, the plasma pulse duration may be between about 2 seconds and about 6 seconds, or about 4 seconds. In some embodiments, the generation of plasma or reactive material in the reactant step may be performed remotely before the reactants contact the intermediate semiconductor element.

[0158] In some embodiments, the purge gas used for the first / second purge step may include, for example, argon, helium, and / or nitrogen. The purpose of the purge gas is to remove unreacted precursors / reactants and byproducts from the reaction chamber after each exposure step. In some embodiments, the purge time may be 0.5 seconds, 4 seconds, or 10 seconds. In some alternative embodiments, the first / second purge step may use a vacuum, which may involve evacuating the reaction chamber. In some cases, the first / second purge step may include a continuous flow of purge gas while stopping the flow of precursors or reactants, or even moving intermediate semiconductor elements to a different chamber that includes purge gas or is under vacuum.

[0159] In some embodiments, the temperature of the plasma-enhanced atomic layer deposition process can be below 200°C, 150°C, 100°C, 75°C, or 50°C. In some embodiments, the pressure of the plasma-enhanced atomic layer deposition process (e.g., for the precursor and reactant steps) can be between about 6 Torr and about 500 Torr.

[0160] The first spacer material 741, comprising SiCO, exhibits strong chemical resistance. For example, the wet etch rate of this first spacer material 741 relative to the wet etch rate of the thermally etched silicon oxide layer can be significantly less than 5, 0.3, or even 0.1. Therefore, this first spacer material 741 can effectively protect the bit line structure 520 in subsequent etching processes, thereby reducing defects such as bit line leakage current. This improves the yield of the semiconductor device 1A. Furthermore, the dielectric constant of the first spacer material 741 comprising SiCO can be less than 5, 4.5, or even 4.4, thereby reducing parasitic capacitance between adjacent bit line structures 520. This improves the performance of the semiconductor device 1A.

[0161] See Figure 25 Multiple filler layers 310 can be formed to fill multiple recesses R1. In some embodiments, the filler layers 310 can be formed of silicon nitride. These layers can be deposited using two consecutive deposition processes: low-pressure chemical vapor deposition (LPCVD) as a first deposition stage, followed by plasma-enhanced chemical vapor deposition (PECVD) as a second deposition stage. In some embodiments, the ratio of filler layer 310 deposited in the first stage to filler layer 310 deposited in the second stage can be approximately 20:80, 30:70, 40:60, or 50:50. In some embodiments, low-pressure chemical vapor deposition must be performed before plasma-enhanced chemical vapor deposition. In some embodiments, the two deposition stages can be performed within the same reaction chamber.

[0162] For the first deposition stage (e.g., low-pressure chemical vapor deposition), the process temperature can be between about 800°C and about 820°C. The process pressure can be between about 150 mTorr and 250 mTorr. Precursors may include ammonia and dichlorosilane. The ratio of ammonia to dichlorosilane can be maintained at about 4 to about 6. In some embodiments, the hydrogen content of silicon nitride formed by low-pressure chemical vapor deposition can be less than 5 atomic%.

[0163] For the second deposition stage (e.g., plasma-enhanced chemical vapor deposition), the precursors may include silane, ammonia, and nitrogen. The ammonia to silane ratio may be between about 2 and about 15. The ammonia to nitrogen ratio may be between about 0.3 and about 2.3. The nitrogen to silane ratio may be between about 5.8 and about 20.8. The ammonia flow rate may be between about 9600 sccm and about 13500 sccm. The nitrogen flow rate may be between about 15000 sccm and about 28000 sccm, and the silane flow rate may be between about 1450 sccm and about 2800 sccm. The RF power supply may be between about 7 MHz and about 13.56 MHz. The process pressure may be between about 0.5 Torr and about 1.5 Torr, or between about 0.7 Torr and about 1.0 Torr. The process temperature may be between about 120°C and about 360°C, or between about 120°C and about 300°C.

[0164] The portion of the filler layer 310 formed by low-pressure chemical vapor deposition (e.g., the lower portion) is denser than the portion formed solely by plasma-enhanced chemical vapor deposition (PECVD), thus providing better protection for the layers beneath it. Furthermore, the upper portion of the filler layer 310 does not require such protection for the layers beneath it, therefore PECVD can be used for deposition to reduce the overall deposition time. It should be noted that the boundary between the filler layer 310 deposited by low-pressure chemical vapor deposition (lower portion) and the filler layer 310 deposited by PECVD (upper portion) may not be visible, as the ratio between low-pressure chemical vapor deposition and PECVD can be adjusted to meet different requirements.

[0165] See Figure 26 The second spacer material 743 can be compliantly formed on the first spacer material layer 741 and the plurality of filler layers 310. In some embodiments, the second spacer material 743 can be formed of materials such as silicon oxide or other suitable insulating oxides. In some embodiments, the second spacer material 743 can be formed by atomic layer deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition or other suitable deposition processes.

[0166] See Figure 1 and Figures 27 to 29 In step S23, a first spacer etching process can be performed to transform the first spacer material 741 into multiple internal spacers 211, transform the second spacer material 743 into multiple intermediate spacers 213, and form multiple external spacers 215 on the multiple intermediate spacers 213 to form multiple spacer structures 210.

[0167] See Figure 27 The first spacer etching process can be an anisotropic etching process, such as anisotropic dry etching. During this process, multiple filler layers 310 can be recessed. Furthermore, the first spacer material 741 formed on the bit line capping layer 525 and located at the bottom TR1B of the trench TR1 can be removed. The remaining first spacer material 741 can be referred to as multiple internal spacers 211.

[0168] For the sake of brevity, clarity, and convenience, only one internal spacer 211 is described. The internal spacer 211 can be compliantly disposed on the side S3 of the bitline structure 520. It can extend downward along the contour of the groove R1 to the substrate 101 and cover the sidewall 533S of the contact spacer 533. Furthermore, the internal spacer 211 can surround the filler layer 310, while exposing its top surface 310TS to the trench TR1.

[0169] During the first spacer etching process, the second spacer material 743 formed on the bit line capping layer 525, on the plurality of fill layers 310, and located at the bottom TR1B of the trench TR1 can be removed. The remaining second spacer material 743 can be referred to as a plurality of intermediate spacers 213. For the sake of brevity, clarity, and convenience, only one intermediate spacer 213 is described. In some embodiments, the intermediate spacers 213 can be compliantly disposed on the inner spacers 211.

[0170] See Figure 28 A third spacer material 745 can be compliantly formed to cover the plurality of bit line structures 520, the plurality of internal spacers 211, the plurality of intermediate spacers 213, and the plurality of filler layers 310. In some embodiments, the third spacer material 745 may be formed of materials such as silicon nitride or other suitable insulating materials. In some embodiments, the third spacer material 745 may be formed by atomic layer deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0171] See Figure 29 A second spacer etching process can be performed to remove the third spacer material 745 on the bit line capping layer 525 and located at the bottom TR1B of the trench TR1. The remaining third spacer material 745 can be referred to as a plurality of external spacers 215. The plurality of external spacers 215 can be respectively and correspondingly conformally disposed on a plurality of intermediate spacers 213. The plurality of external spacers 215, the plurality of intermediate spacers 213, and the plurality of internal spacers 211 together constitute a plurality of spacer structures 210.

[0172] Multiple internal spacers 211 formed of silicon carbide provide enhanced protection for the multiple bit-line structures 520 due to their excellent chemical resistance. This helps reduce defects in the semiconductor device 1A and improves its yield. Furthermore, multiple filler layers 310 formed by a two-stage deposition process combining low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition can provide better protection for the underlying layers without affecting manufacturing efficiency. This, in turn, improves the yield and manufacturing efficiency of the semiconductor device 1A.

[0173] One aspect of this disclosure provides a spacer structure, comprising: an inner spacer located on one side of a bit line structure, wherein the inner spacer comprises silicon carbide; an intermediate spacer located on the inner spacer; and an outer spacer located on the intermediate spacer.

[0174] Another aspect of this disclosure provides a semiconductor device comprising: a substrate; a bit line structure disposed on the substrate; and a spacer structure including an inner spacer compliantly disposed on one side of the bit line structure, an intermediate spacer compliantly disposed on the inner spacer, and an outer spacer compliantly disposed on the intermediate spacer. The inner spacer comprises silicon carbide.

[0175] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a plurality of bit line contact structures in the substrate; forming a plurality of bit line structures on the plurality of bit line contact structures, wherein the plurality of bit line structures are separated by a plurality of trenches and a plurality of grooves extending downward from the plurality of trenches and adjacent to the bit line contact structures; conformally forming a first spacer material covering the plurality of bit line structures, the plurality of bit line contact structures, the plurality of trenches and the plurality of grooves; forming a plurality of fill layers to fill the plurality of grooves; conformally forming a second spacer material covering the first spacer material and the plurality of fill layers; performing a first spacer etching process to transform the first spacer material into a plurality of internal spacers and the second spacer material into a plurality of intermediate spacers; and conformally forming a plurality of external spacers on the plurality of intermediate spacers to constitute a plurality of spacer structures. The first spacer material includes silicon oxide.

[0176] Due to the design of the semiconductor device disclosed herein, the internal spacer 211 formed of silicon carbide can effectively protect the bit line structure 520 during subsequent etching processes. Its strong chemical resistance helps reduce defects such as bit line leakage current, thereby improving the yield of the semiconductor device 1A. In addition, the low dielectric constant of the silicon carbide internal spacer 211 can reduce the parasitic capacitance between adjacent bit line structures 520, thereby improving the overall performance of the semiconductor device 1A.

[0177] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0178] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One substrate; A single-line structure is located on the substrate; as well as A spacer structure, comprising: An internal spacer is compliantly located on one side of the bit line structure; An intermediate spacer, compliantly positioned on the inner spacer; and An outer spacer is compliantly located on the intermediate spacer, wherein the inner spacer comprises silicon dioxide.

2. The semiconductor device of claim 1 further includes a bit line contact structure located between the bit line structure and the substrate, wherein the internal spacer extends downward to the substrate and covers one sidewall of the bit line contact structure.

3. The semiconductor device of claim 2 further includes a filler layer adjacent to the bit line contact structure.

4. The semiconductor device of claim 3, wherein the internal spacer is located between the bit line contact structure and the fill layer.

5. The semiconductor device of claim 4, wherein the carbon content of the internal spacer ranges from about 0.1% to about 40% on an atomic basis.

6. The semiconductor device of claim 4, wherein the oxygen content of the internal spacer is at least about 20% on an atomic basis.

7. The semiconductor device of claim 4, wherein the silicon content of the internal spacer is at least about 15% on an atomic basis.

8. The semiconductor device of claim 4, wherein the intermediate spacer comprises silicon oxide.

9. The semiconductor element of claim 4, wherein the external spacer comprises silicon nitride.

10. The semiconductor device of claim 4, wherein the bit line contact structure comprises: A bit line contact is located between the bit line structure and the substrate; as well as A contact isolation spacer is located between the internal spacer and the bit line.

11. The semiconductor device of claim 10, wherein the material of the bit line contact includes tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum nitrides, or combinations thereof.

12. The semiconductor device of claim 10, wherein the material of the contact spacer comprises silicon nitride.

13. The semiconductor device of claim 4, wherein the material of the filling layer comprises silicon nitride.

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