Semiconductor device and method of manufacturing a semiconductor device

Abstract

According to various embodiments, a semiconductor device includes: a semiconductor substrate having a front side and a back side opposite to the front side; a first active region and a second active region located on the front side of the semiconductor substrate and extending longitudinally along a first direction parallel to a plane of the semiconductor substrate; an isolation member located between the first active region and the second active region; a back-side circuit located on the back side of the semiconductor substrate, including a conductor in a dielectric layer; and a first conductive via extending through the semiconductor substrate and electrically connecting the conductor to the first active region. The conductor extends longitudinally along the first direction and substantially does not overlap with the first active region and the second active region in a view along a direction perpendicular to a plane of the semiconductor substrate. Embodiments of this application also relate to semiconductor devices and methods of manufacturing semiconductor devices.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth, driven by continuous technological advancements in materials and circuit design. These advancements have enabled successive generations of ICs to have components with smaller and more complex circuitry than their predecessors. Over time, the functional density of ICs (i.e., the number of interconnect devices per unit chip area) has generally increased, while the minimum geometry (the smallest component or line that can be formed using a given manufacturing process) has decreased. This trend of device scaling has already provided significant benefits, including improved production efficiency and reduced manufacturing costs. However, continued scaling also introduces greater complexity into IC handling and manufacturing, requiring corresponding innovations in manufacturing technologies to fully realize the advantages of advanced IC designs. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor device comprising: a semiconductor substrate having a front side and a back side opposite to the front side; a first active region and a second active region located on the front side of the semiconductor substrate and extending longitudinally along a first direction parallel to a plane of the semiconductor substrate; an isolation member located between the first active region and the second active region; a back-side circuit located on the back side of the semiconductor substrate, including a conductor in a dielectric layer; and a first conductive via extending through the semiconductor substrate and electrically connecting the conductor to the first active region, wherein the conductor extends longitudinally along the first direction and substantially does not overlap with the first active region and the second active region in a view along a direction perpendicular to the plane of the semiconductor substrate.

[0004] Other embodiments of this application provide a semiconductor device, including: a substrate having a front side and a back side; a first active region and a second active region located above the front side of the substrate and extending longitudinally along a first direction; an isolation member located above the front side of the substrate and between the first active region and the second active region, and separating the first active region and the second active region along a second direction different from the first direction; a first gate structure and a second gate structure, the first gate structure being located above the first active region and the second gate structure being located above the second active region; and a gate isolation member located between the first gate structure and the second active region. The first gate structure is separated from the second gate structure along the second direction between the second gate structures, wherein the gate isolation member includes a first portion located above the isolation member and a second portion extending into the isolation member; a back-side circuit located on the back side of the substrate; a first conductive via extending through the substrate and electrically connecting the back-side circuit to the first active region; and a second conductive via extending through the substrate and electrically connecting the back-side circuit to the second active region, wherein the back-side circuit substantially does not overlap with the first active region and the second active region in a view along a direction perpendicular to the plane of the substrate.

[0005] Further embodiments of this application provide a method for manufacturing a semiconductor device, comprising: performing a processing operation to form an interconnect structure on a back side of a substrate, wherein a first active region and a second active region are located on a front side of the substrate, wherein the first active region and the second active region extend longitudinally along a first direction and are spaced apart from each other along a second direction different from the first direction; the processing operation comprising: performing a first etching operation to form a first opening in the back side of the substrate above a first source / drain component of the first active region in a view along a direction perpendicular to a plane of the substrate, wherein the first source / drain component includes a metal silicide layer formed above an epitaxial semiconductor layer; depositing a first conductive material in the first opening to form an extension through the substrate and electrically connected to the first source. The first source / drain component has a first conductive via; a dielectric layer is deposited over the back side of the substrate, and a second etching operation is performed on the dielectric layer to form a trench in the dielectric layer; and a second conductive material is deposited in the trench in the dielectric layer to form an interconnect structure electrically connected to the first conductive via, wherein: the interconnect structure extends longitudinally along the first direction and substantially does not overlap with the first active region and the second active region in the view along the direction perpendicular to the plane of the substrate; the first source / drain component includes a thickness along a third direction and a width along the first direction and the second direction, and the thickness is different from the width; and the first conductivity of the metal silicide layer is between the second conductivity of the epitaxial semiconductor layer and the third conductivity of the first conductive via. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 It is a block diagram of a semiconductor device according to various embodiments.

[0008] Figure 2A This is a vertical cross-sectional view of a semiconductor device according to various embodiments.

[0009] Figure 2B This is a vertical cross-sectional view showing the front-side interconnect structure and the back-side interconnect structure of a semiconductor device structure according to various embodiments.

[0010] Figure 2C According to various embodiments Figure 2B A vertical cross-sectional view of the components of a semiconductor device structure.

[0011] Figure 2D According to various embodiments Figure 2B A vertical cross-sectional view of the components of a semiconductor device structure.

[0012] Figure 3 These are circuit diagrams of static random access memory (SRAM) cells according to various embodiments.

[0013] Figure 4 This is a layout diagram showing a plan view of a semiconductor device according to various embodiments.

[0014] Figure 5A This is a layout diagram showing a plan view of a semiconductor device according to various embodiments.

[0015] Figure 5B According to various embodiments Figure 5A A vertical cross-sectional view of a portion of a semiconductor device.

[0016] Figure 5C According to various embodiments Figure 5A A vertical cross-sectional view of a portion of a semiconductor device.

[0017] Figure 6A This is a layout diagram showing a plan view of a semiconductor device according to various embodiments.

[0018] Figure 6B According to various embodiments Figure 6A A vertical cross-sectional view of a portion of a semiconductor device.

[0019] Figure 7A This is a layout diagram showing a plan view of a semiconductor device according to various embodiments.

[0020] Figure 7B This is a layout diagram showing a plan view of a semiconductor device according to various embodiments.

[0021] Figure 7C According to various embodiments Figure 7B A vertical cross-sectional view of a portion of a semiconductor device.

[0022] Figures 8A to 8C This is a vertical cross-sectional view of a semiconductor structure for forming a semiconductor device having front and back contacts, according to various embodiments.

[0023] Figures 9A to 9D This is a vertical cross-sectional view of a semiconductor structure for forming a semiconductor device having front and back contacts, according to various embodiments.

[0024] Figure 9E According to various embodiments Figure 9DThe amplified portion of the semiconductor structure.

[0025] Figures 10A to 10D This is a vertical cross-sectional view of a semiconductor structure for forming a semiconductor device having front and back contacts, according to various embodiments.

[0026] Figure 11 This is a flowchart of the operation of a method for manufacturing a semiconductor device according to various embodiments.

[0027] Figure 12 It is a block diagram of an integrated circuit (IC) manufacturing system and the associated IC manufacturing process according to various embodiments.

[0028] Figure 13 This is a block diagram of an electronic design automation (EDA) system according to some embodiments. Detailed Implementation

[0029] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0030] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Furthermore, the term “made of” may mean either “comprising” or “consisting of.” In embodiments of this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C) and does not mean an element from A, an element from B, and an element from C, unless otherwise described.

[0031] The disclosed embodiments advantageously describe a semiconductor device and a method of manufacturing a semiconductor device, wherein an active region disposed on the front side of a substrate is electrically connected to a back-side circuit configured to have reduced capacitance. In this respect, the active regions formed on the front side of the semiconductor device are separated from each other by isolation components, and the back-side interconnect structure is substantially above the isolation components in a plan view. Therefore, the back-side interconnect structure substantially does not overlap with the active regions, except for a small overlap in some embodiments with the conductive side pattern that primarily overlaps with the conductive via structure.

[0032] In other embodiments, the conductive side pattern is eliminated, and the wires, substantially above the isolation member, are electrically connected to a first conductive connector aligned with the wires and a second conductive connector laterally aligned with the wires, overlapping the conductive via structure. The minimal overlap between the back-side circuitry and the active region results in reduced capacitance, compared to a comparative embodiment where there is greater overlap between the back-side circuitry and the active region.

[0033] Figure 1 This is a block diagram of a semiconductor device 100 according to various embodiments. The block diagram is a simplified representation of the semiconductor device 100, in which many components are omitted or shown in a simplified form. Figure 1 In addition to other components, the semiconductor device 100 also includes a processing circuit 110 and a memory circuit 120. In some embodiments, at least one of the processing circuit 110 and the memory circuit 120 includes one or more circuit blocks. For example, the memory circuit 120 includes a first circuit block 122 corresponding to a memory cell array, a second circuit block 124 corresponding to a first portion of the control circuit of the memory circuit 120, and a third circuit block 126 corresponding to a second portion of the control circuit of the memory circuit 120.

[0034] In some embodiments, the second circuit block 124 includes a column decoder, a plurality of precharge drivers, a plurality of sense amplifiers, and / or a plurality of bit line drivers. The third circuit block 126 may include a row decoder and / or a plurality of word line drivers. Furthermore, in some embodiments, the second circuit block 124 and / or the third circuit block 126 may also include one or more clock generators configured to provide clock signals to various components of the memory circuit 120, one or more input / output (I / O) circuits for data exchange with external devices, and / or one or more control circuit blocks configured to control various operations within the memory circuit 120.

[0035] exist Figure 1In this work, as a non-limiting example, memory circuitry 120 is shown comprising an array of memory cells, such as a first circuit block 122. In some embodiments, memory circuitry 120 includes a plurality of memory cells arranged to be accessible via corresponding control circuitry or a shared control circuitry. For the purpose of forming a group of pseudo-structures, two boundary regions 132 and 134 are defined on opposite sides of the first circuit block 122 (i.e., the memory cell array) along a first horizontal direction (e.g., the X direction). For example, in some embodiments, a plurality of pseudo-gate structures are disposed within boundary regions 132 and 134, located outside the memory cell array and adjacent to their corresponding boundaries. In some embodiments, one or more active regions extend across the boundary between the memory cell array and boundary regions 132 or 134. In some embodiments, pseudo-gate structures and pseudo-structures extending active regions may be included to maintain the continuity of the layout pattern of the semiconductor device, reduce manufacturing complexity, and thereby improve the performance and manufacturing yield of the semiconductor device.

[0036] In some embodiments, the dummy gate structures and extended active regions within boundary regions 132 and 134 also define non-functional transistors. In some embodiments, the non-functional transistors are electrically disabled or electrically isolated from the memory cell array to reduce current leakage. In some embodiments, a gate-bonded turn-off configuration is employed, wherein wires are electrically coupled to one or more dummy gate structures and configured to apply a reference voltage to turn off the corresponding non-functional transistor. Such a gate-bonded turn-off configuration establishes a balanced gate setup for the non-functional transistor, thereby reducing the likelihood of plasma-induced damage, particularly in applications utilizing back-side power rail schemes (e.g., power rails located on the back side of the substrate, such as reference rails). Figures 2A to 2D (As further described below). Furthermore, in other embodiments, non-functional transistors from the memory cell array are isolated using a continuous polysilicon on diffused edge (CPODE) structure, as described in more detail below.

[0037] Figure 2A This is a vertical cross-sectional view of a semiconductor device 200a according to various embodiments. In some embodiments, the cross-sectional view is a simplified representation of the semiconductor device 200a, wherein many components are omitted or depicted in a simplified form. In some embodiments, as a non-limiting example, the semiconductor device 200a ( Figure 2A ) corresponds to Figure 1 The semiconductor device 100 is depicted in the figure.

[0038] Semiconductor device 200a ( Figure 2AThe device includes a substrate 210 having an active region 212 formed on or partially within the substrate 210 and a gate structure 214. In this embodiment, the semiconductor device 200a includes a metal-to-drain / source (MD) structure 222 coupled to the active region 212. The device also includes a via-to-drain / source (VD) structure coupled to the MD structure 222, referred to as a via structure at the VD layer. Furthermore, a via-to-gate (VG) structure is coupled to the gate structure 214, referred to as a via structure at the VG layer. In some embodiments, the semiconductor device 200a also includes vias to metal-to-diffusion rails (VDRs), each via being formed as a conductive segment or wire configured to connect to one or more MD structures 222. These VDRs are also referred to as wires at the VDR layer. In some embodiments, the VD layer, VG layer, and VDR layer may overlap or merge with each other and are collectively referred to as the VD / VG / VDR layer.

[0039] In some embodiments, the semiconductor device 200a further includes a plurality of metallization layers (e.g., M0, M1, M2, ..., Mx-1 and Mx layers) and a plurality of via layers (e.g., V0, V1, V2, ..., Vx-2 and Vx-1 layers) disposed above the VD / VG / VDR layers and the substrate 210, where x is a positive integer. Each metallization layer includes a corresponding dielectric layer in which a wire extends horizontally (along a plane spanned by the X and Y directions) and is embedded. Similarly, each via layer includes a corresponding dielectric layer having a via structure embedded therein. The metallization layers and via layers are arranged in an alternating stack along a vertical direction (e.g., the Z direction).

[0040] In some embodiments, the Vx-1 layer includes a via structure connecting wires in the Mx-1 and Mx layers. The M0 layer represents the bottommost metallization layer positioned above the substrate 210. The plurality of metallization layers and via layers include conductive materials such as copper, aluminum, gold, tungsten, or combinations thereof. Figure 2A In this context, reference numeral 232 denotes the dielectric layer of a metallization layer, a via layer, a VD / VG / VDR layer, and any dielectric layer present on the front side of the substrate 210. In some embodiments, these dielectric layers 232 include silicon dioxide, a low-k dielectric material (i.e., a material having a dielectric constant lower than that of silicon dioxide), and / or an air gap.

[0041] As a non-restrictive example, Figure 2AThe semiconductor device 200a also includes conductive structures located beneath the substrate 210. For example, the device includes back-side metallization layers BMO and BM1, and back-side via layers BVD and BVO. In this embodiment, the BVD layer includes a back-side via structure connecting the active region 212 to back-side conductors in the BMO layer. The BVO layer includes a back-side via structure connecting back-side conductors in the BMO layer to those in the BM1 layer. In some embodiments, the BMO layer represents the uppermost back-side metallization layer located beneath the substrate 210.

[0042] exist Figure 2A In some embodiments, semiconductor device 200a includes two back-side metallization layers (BM0, BM1) and corresponding back-side via layers (BVD, BVO). In some embodiments, the number of back-side metallization layers beneath substrate 210 ranges from two to six. Some or all of these back-side conductive structures—such as back-side metallization layers BM0 and BM1 and back-side via layers BVD and BVO—may be at least partially embedded within substrate 210. In other embodiments, the back-side conductive structures are omitted entirely from the semiconductor device.

[0043] In some embodiments, the back-side metallization layers BMO and BM1, and the back-side via layers BVD and BV0, comprise conductive materials such as copper, aluminum, gold, tungsten, or combinations thereof. Similar to the metallization and via layers on the front side of substrate 210, each back-side metallization layer includes a corresponding dielectric layer with embedded wires therein, and each back-side via layer includes a corresponding dielectric layer with embedded via structures. Figure 2A In this context, reference numeral 234 indicates a dielectric layer associated with a metallization layer, a via layer, and any dielectric layer present on the back side of the substrate 210. In some embodiments, these dielectric layers 234 include silicon dioxide, a low dielectric constant material, and / or air gaps.

[0044] In some embodiments, the semiconductor device 200a includes one or more redistribution layers and a conductive pad structure located above the redistribution layers. Figure 2A (Not shown in the image). In some embodiments, the semiconductor device 200a includes a conductive terminal structure located above the conductive pad structure, such as a conductive bump, copper pillar bump, solder bump, or similar structure (also not shown in the image). Figure 2A (As shown in the figure). Furthermore, in some embodiments, the semiconductor device 200a includes one or more back-side redistribution layers and a back-side conductive pad structure located beneath the back-side redistribution layers (as shown in the figure). Figure 2A (Not shown in the image). In some embodiments, conductive bumps, copper pillar bumps, solder bumps, or similar structures are included (…). Figure 2A The back-side conductive terminal structure (not shown) is located below the back-side conductive pad structure.

[0045] In some embodiments, semiconductor device 200a includes transistors formed based on active regions 212 and gate structures 214 in a front-end process (FEOL) portion of the device. For example, the channel of the transistor is defined by a portion of the active region overlapping the gate structure, and two drain / source regions are defined by adjacent portions of the active region located on either side of the channel. One or more functional circuit blocks of semiconductor device 200a, such as memory cells in a memory cell array or control circuitry, are formed by electrically connecting transistors within the FEOL portion. In some embodiments, portions of semiconductor device 200a located at and above a given metallization layer (e.g., M5 layer and above) correspond to back-end process (BEOL) portions. According to various embodiments, functional circuit blocks are formed by electrically connecting transistors, capacitors, and / or resistors formed in the BEOL portion.

[0046] Figure 2B This is a vertical cross-sectional view of a semiconductor device structure 200b according to various embodiments, showing the front-side interconnect structure and the back-side interconnect structure. Figure 2C and Figure 2D According to various embodiments Figure 2B Vertical cross-sectional view of the components (200c, 200d1, 200d2) of the semiconductor device structure 200b.

[0047] refer to Figure 2B The semiconductor device structure 200b includes a transistor structure formed in a substrate 210, having a gate structure 214 formed over an active region 212. In this embodiment, the transistor structure is configured as a gate-all-around (GAA) field-effect transistor, having a stacked channel region 216 extending longitudinally along a first direction (X direction) between a first source / drain (S / D) region and a second S / D region. The gate structure 214 surrounds the channel region 216, and the S / D region is an epitaxial semiconductor layer electrically coupled to the channel region 216. The GAA transistor also includes an insulating internal spacer layer 220 electrically insulating the gate from the S / D region. Although in Figure 2B The illustration shows three stacked channel regions 216, but the embodiments disclosed herein are not limited thereto, and various other embodiments include different numbers of channel regions 216, such that the number of channel regions 216 is ≥1. Figure 2B The embodiments (including GAA transistors) are provided by way of example only, and various other semiconductor devices (e.g., planar field-effect transistors (FETs), fin field-effect transistors (FinFETs), complementary field-effect transistors (CFETs), etc.) are possible in other embodiments.

[0048] Semiconductor device structure 200b includes an S / D contact structure (MD) electrically connected to the S / D region. A via (VD) is electrically connected to the S / D contact structure MD. A front-side interconnect structure includes metallization layers (M0, M1, M2) embedded within a front-side dielectric layer 232. The via VD electrically connects the S / D contact MD to the first metallization layer M0, and a via-to-gate (VG) structure electrically connects the gate structure 214 to the first metallization layer M0. Semiconductor device structure 200b also includes back-side metallization layers (BM0, BM1) configured to provide power to transistor structures formed in substrate 210 and to route signals to and from transistor structures formed in substrate 210, as follows.

[0049] refer to Figure 2B and Figure 2C Semiconductor device structure 200b includes component 200c, wherein a back-side via (BVD) extends through the back layer of substrate 210 and electrically connects the S / D region of the transistor structure to a first back-side metallization layer BMO. Therefore, component 200c is configured to provide power to the interconnect structure of the transistor structure. In this respect, the BVD connects the S / D structure to a back-side power rail formed in the first back-side metallization layer BMO. Component 200c also includes an etch stop layer 218 and a metal-to-diffusion rail (VDR) structure, the VDR structure electrically connecting the S / D contact MD of the transistor structure to other circuit elements. Metal silicide layers 514 are also provided between the BVD and the S / D structure, and between the S / D structure and the S / D contact MD.

[0050] refer to Figure 2B and Figure 2D The semiconductor device structure 200b also includes components (200d1, 200d2) in which feedthrough vias (FTVs) extend through the substrate 210 and through the respective dielectric layers (232, 234) to electrically connect the first back-side metallization layer BMO to the first front-side metallization layer M0 via contact MD structures. Therefore, component 200d is configured as an interconnect structure that provides signal paths connecting the transistor structure to the front-side interconnect structures (M0, M1, M2) and the back-side interconnect structures (BM0, BM1). Figure 2B and Figure 2D It is not drawn to scale, and for clarity, in Figure 2B The structures (200d1, 200d2) were enlarged.

[0051] exist Figure 2B and Figure 2DIn one embodiment, the first component 200d1 includes a first FTV electrically connecting the S / D contact MD to the back-side interconnect structure (BM0, BM1), and the second component 200d2 includes a second FTV electrically connecting the gate structure 214 to the back-side interconnect structure (BM0, BM1). Components (200d1, 200d2) also include an etch stop layer 218 and a metal-to-diffusion-rail (VDR) structure, the VDR structure electrically connecting the FTV to other circuit elements.

[0052] Figure 3 This is a circuit diagram of a static random access memory (SRAM) cell 300 according to various embodiments. In some embodiments, the SRAM cell 300 can be used to form a memory cell array, such as... Figure 1 The first circuit block 122, reference Figure 2A An example is shown below. In this embodiment, SRAM cell 300 includes pull-up transistors PU1 and PU2 and pull-down transistors PD1 and PD2. In some embodiments, pull-up transistors PU1 and PU2 are p-type metal-oxide-semiconductor (PMOS) transistors, while pull-down transistors PD1 and PD2 are n-type metal-oxide-semiconductor (NMOS) transistors. Pull-up transistor PU1 and pull-down transistor PD1 are configured as a first inverter coupled between a first power node CVDD and a second power node CVSS, having an input terminal coupled to node 302 and an output terminal coupled to node 304. Similarly, pull-up transistor PU2 and pull-down transistor PD2 are configured as a second inverter coupled between the first power node CVDD and the second power node CVSS, having an input terminal coupled to node 304 and an output terminal coupled to node 302.

[0053] In some embodiments, the first power node CVDD is electrically coupled to the resulting memory cell array (e.g., Figure 1 The first circuit block 122 in the array supplies a voltage node via its drain (VDD) and is configured to carry a first supply voltage. A second power node CVSS is electrically coupled to either the ground reference node or the voltage source (VSS) supply node of the resulting memory cell array and is configured to carry a second supply voltage. In some embodiments, the voltage level of the first supply voltage is greater than the voltage level of the second supply voltage. The voltage difference between the first and second supply voltages can range from 0.5 volts to 2.5 volts.

[0054] In this embodiment, the SRAM cell 300 further includes a first write transmission gate transistor WPG1 and a second write transmission gate transistor WPG2, both of which are NMOS transistors. Figure 3In this configuration, the second write transmission gate transistor WPG2 is coupled between node 302 and the write bit line WBL, while the first write transmission gate transistor WPG1 is coupled between node 304 and the complementary write bit line WBLB. The gate terminals of both the first write transmission gate transistor WPG1 and the second write transmission gate transistor WPG2 are coupled to the write word line WWL. The SRAM cell 300 also includes a read transmission gate transistor RPG, which is a PMOS transistor. Figure 3 In this configuration, the read transmission gate transistor RPG is coupled between node 302 and the read bit line RBL, and has its gate terminal coupled to the read word line RWL.

[0055] In operation, pull-up transistors PU1 and PU2 and pull-down transistors PD1 and PD2 form a latch to store data bit values ​​and complementary data bit values ​​at nodes 302 and 304. In some embodiments, when the SRAM cell 300 is selected for a write operation, the write word line WWL is configured to carry a first reference voltage to turn on the first write transmission gate transistor WPG1 and the second write transmission gate transistor WPG2, allowing the input data bit values ​​and complementary input data bit values ​​on the write bit line WBL and the complementary write bit line WBLB to be transferred to nodes 302 and 304. In some embodiments, when the SRAM cell 300 is selected for a read operation, the read word line RWL is configured to carry a second reference voltage to turn on the read transmission gate transistor RPG, enabling the data bit value stored at node 302 to be transferred to the read bit line RBL.

[0056] In this embodiment, SRAM cell 300 corresponds to a 7-transistor (7T) SRAM cell formed based on seven transistors, including pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, write transmission gate transistors WPG1 and WPG2, and read transmission gate transistor RPG. SRAM cell 300 includes three p-type transistors (i.e., transistors PU1, PU2, and RPG) and four n-type transistors (i.e., transistors PD1, PD2, WPG1, and WPG2). Other configurations of SRAM cell 300 are possible in other embodiments. For example, in other embodiments, n-type transistors RPG, WPG1, and WPG2 can be replaced with p-type transistors.

[0057] Figure 4This is a plan view of a layout diagram 400 of a portion of a semiconductor device 100 according to various embodiments. Layout diagram 400 includes layout patterns corresponding to an oxide diffusion (OD) layer (referred to as "OD" in the legend) and a gate polysilicon (PO) layer (referred to as "PO" in the legend). In some embodiments, the layout pattern included in the OD layer (referred to as the "OD layout pattern") indicates the formation of various active regions of the semiconductor device, and the layout pattern included in the PO layer (referred to as the "PO layout pattern") indicates the formation of a corresponding gate structure. In a corresponding embodiment, the gate structure 214 (e.g., see...) Figure 2A This corresponds to a polysilicon gate structure or a metal gate structure formed using a polysilicon structure as a sacrificial placeholder.

[0058] Figure 4 Some of the OD layout patterns in the diagram correspond to patterns formed by subtracting the removed portions defined by the cut OD (COD) pattern group from a repeating OD pattern group. Similarly, Figure 4 The PO layout pattern in the diagram corresponds to the pattern formed by subtracting the removed portion defined by the cut PO (CPO) pattern group from the repeating PO pattern group (CPO pattern, sometimes also called "cut metal gate" (CMG) pattern).

[0059] exist Figure 4 In the layout diagram 400, the portion corresponding to a circuit block, such as a memory cell array, includes multiple circuit cells (e.g., based on...). Figure 3 (Example SRAM cell 300 memory cell). For example, cell regions 402 and 404 represent two memory cells in a memory cell array, each corresponding to... Figure 3 The configuration shown includes a p-type read transfer gate transistor (RPG).

[0060] exist Figure 4 In the layout diagram 400, among other aspects, OD layout patterns 411, 412, 414, 415, 416, 417, 418, and 419 are included to indicate the active regions of the resulting semiconductor device. In this embodiment, the semiconductor device includes active regions corresponding to OD layout patterns 411, 414, 415, and 418 for forming p-type transistors, and active regions corresponding to OD layout patterns 412, 416, 417, and 419 for forming n-type transistors. In some embodiments, the active regions extend along a first horizontal direction (e.g., the X direction) and are located on or at least partially embedded in the substrate 210 of the semiconductor device. Figure 4In this context, layout diagram 400 also includes, among other things, layout patterns 422, 426, 427, 428, and 429 indicating the gate structure of the resulting semiconductor device. In some embodiments, the gate structure extends along a second horizontal direction (e.g., the Y direction) and is positioned above the corresponding active region.

[0061] For example, in order to form a memory cell corresponding to cell region 402, two pull-down transistors PD1 and PD2 are defined based on the gate structures corresponding to the active regions corresponding to OD layout patterns 426 and 427 (e.g., Figure 3 The pull-down transistors PD1 and PD2 are defined based on the gate structures of the PO layout patterns 426 and 427, which correspond to the active regions corresponding to the OD layout pattern 414. (e.g., the pull-up transistors PD1 and PD2 in the diagram). Figure 3 Pull-up transistors PU1 and PU2 in the diagram). Furthermore, two write transmission gate transistors WPG1 and WPG2 are defined based on the gate structures corresponding to the active regions corresponding to the OD layout pattern 422 and 428 (e.g., ). Figure 3 The write transmission gate transistors WPG1 and WPG2 in the diagram), and the read transmission gate transistor RPG is defined based on the gate structure corresponding to the active region corresponding to the OD layout pattern 429. Figure 3 (Read transmission gate transistor RPG in the middle).

[0062] Figure 5A This is a layout diagram of a plan view of a semiconductor device 500a according to various embodiments. Figure 5A The layout diagram corresponds to a portion of a circuit block that includes multiple transistors configured as an inverter circuit (see...). Figure 5A (Illustrative inverter circuit diagram in the diagram). For example, each of cell regions 502a and 502b includes a corresponding pull-up transistor (PU1, PU2) and a corresponding pull-down transistor (PD1, PD2) connected to form an inverter circuit, as described in more detail below. Figure 5A The inverter circuit is formed in a configuration having a front side and a front side (in Figure 5B and Figure 5C (Middle face down) opposite dorsal side (in) Figure 5B and Figure 5C Substrate 210 (with center facing upward) (e.g., Figure 5B and Figure 5CAs shown in the diagram. Multiple OD (distribution-out) layout patterns (504a, 504b, 504c, 504d, 504e, 504f) indicating the active regions of semiconductor device 500a are formed on the front side of the substrate. The OD layout patterns (504a, 504b, 504c, 504d, 504e, 504f) extend longitudinally along a first direction (i.e., the X direction) parallel to the plane of the semiconductor substrate. The OD layout patterns (504a, 504b, 504c, 504d, 504e, 504f) are separated from each other by isolation members 506.

[0063] Semiconductor device 500a includes a back-side circuit on the back side of a semiconductor substrate. The back-side circuit includes multiple interconnect structures (BM0a, BM0b, BM0c) formed at a first back-side metallization layer BMO. For clarity, from... Figure 5A The center of the layout diagram is moved to the position of the first back-side interconnect structure BM0a. Each interconnect structure (BM0a, BM0b, BM0c) includes a conductor segment 508 and a conductive side portion (510a, 510b). Each conductor segment 508 extends longitudinally along a first direction (X direction) and is positioned above the isolation member 506.

[0064] The width W of the conductive segment 508 is comparable to the width of the isolation member 506, such that the conductive segment 508 substantially overlaps with the corresponding isolation member 506 in a view along a plane perpendicular to the semiconductor substrate (i.e., along the Z direction). Therefore, the conductive segment 508 substantially does not overlap with the OD layout patterns (504a, 504b, 504c, 504d, 504e, 504f) in a view along a plane perpendicular to the semiconductor substrate. This configuration, in which the conductive segment 508 substantially does not overlap with the OD layout patterns (504a, 504b, 504c, 504d, 504e, 504f), advantageously exhibits reduced capacitance compared to the alternative configuration in the comparative embodiment where the conductive segment 508 overlaps with the OD layout patterns (504a, 504b, 504c, 504d, 504e, 504f).

[0065] Each conductive side pattern (510a, 510b) extends along a first direction (e.g., having a first width w1 in the X direction) and also extends laterally to the wire along a second direction perpendicular to the first direction and parallel to the plane of the semiconductor substrate (e.g., having a second width w2 in the Y direction). The semiconductor device 500a also includes a back-side conductive via (BVD) penetrating the substrate 210 and electrically connecting the back-side interconnect structures (BM0a, BM0b, BM0c) to the OD layout patterns (504a, 504b, 504c, 504d, 504e, 504f). For example, a first back-side via BVD1 electrically connects the first back-side interconnect structure BMV0a to the first OD layout pattern 504a. At this point, the first conductive side pattern 510a of the first back-side interconnect structure BMV0a is electrically connected to the first back-side via BVD1, which in turn is electrically connected to the p-type doped S / D component of the first OD layout pattern 504a. In this respect, the first back-side via BVD1 is connected to the first back-side interconnect structure BMV0a under the operating condition of the voltage drain (VDD) supply to form the source terminal of the first pull-up transistor PU1 (PMOS).

[0066] The second back-side via BVD2 electrically connects the first back-side interconnect structure BMV0a to the second OD layout pattern 504b. At this point, the second conductive side pattern 510b of the first back-side interconnect structure BMV0a is electrically connected to the second back-side via BVD2, which in turn is electrically connected to the p-type doped S / D component of the second OD layout pattern 504b. At this point, the second back-side via BVD2 forms the source terminal of the second PMOS pull-up transistor PU2 under operating conditions where the first back-side interconnect structure BMV0a is connected to a voltage drain (VDD) supply.

[0067] The third back-side via BVD3 electrically connects the second back-side interconnect structure BMV0b to the third OD layout pattern 504c. At this point, the second conductive side pattern 510b of the second back-side interconnect structure BMV0b is electrically connected to the third back-side via BVD3, which in turn is electrically connected to the n-type doped S / D component of the third OD layout pattern 504c. At this point, the third back-side via BVD3 forms the source terminal of the first (NMOS) pull-down transistor PD1 under the operating condition that the second back-side interconnect structure BMV0b is connected to the voltage source (VSS) supply.

[0068] The fourth back-side via BVD4 electrically connects the third back-side interconnect structure BMV0c to the fourth OD layout pattern 504d. At this point, the first conductive side pattern 510a of the third back-side interconnect structure BMV0c is electrically connected to the fourth back-side via BVD4, which in turn is electrically connected to the n-type doped S / D component of the fourth OD layout pattern 504d. At this point, the fourth back-side via BVD4 forms the source terminal of the second NMOS pull-down transistor PD2 under operating conditions where the third back-side interconnect structure BMV0c is connected to a voltage source (VSS) supply.

[0069] As described above, transistors are formed at locations where the gate segments (214a, 214b) overlap with the channel regions of the corresponding OD patterns (504a, 504b, 504c, 504d). Figure 5A In the embodiment of semiconductor device 500a, Figure 5A The structures on the right and left sides are identical, but in the following description, for clarity, only the structures on the right and left sides are considered identical. Figure 5A The right-hand side shows reference characters indicating gate segments (214a, 214b). At this point, in Figure 5A On the right-hand side, the first gate segment 214a overlaps with the first OD pattern 504a and the third OD pattern 504c, corresponding to the connection gate of the first pull-up transistor PU1 and the first pull-down transistor PD1. Figure 5A As shown on the left-hand side (along with a schematic circuit diagram). Similarly, the second gate segment 214b overlaps with both the second OD pattern 504b and the fourth OD pattern 504d, corresponding to the connection gates of the second pull-up transistor PU2 and the second pull-down transistor PD2. Figure 5A As shown on the left side (along with a schematic circuit diagram).

[0070] As described above, the gate segments (214a, 214) are separated from each other by a gate isolation structure 512 (also known as a "cut-PO" (CPO) pattern or a "cut-metal gate" (CMG) pattern). Reference Figure 5AA gate isolation structure is formed between adjacent OD layout patterns (504a, 504b, 504c, 504d, 504e, 504f) within the isolation member 506. At this point, the gate structure 214 is initially formed above the OD layout patterns (504a, 504b, 504c, 504d, 504e, 504f) and extends along a second direction (i.e., the Y direction). The gate structure 214 is then segmented into segments (214a, 214b) by forming a gate isolation member 512, which extends longitudinally along a first direction (i.e., the X direction) and separates the gate segments (214a, 214b) from each other along the second direction. Each cell region (e.g., cell regions 502a and 502b) is further isolated from adjacent cells by a CPODE region 519. At this point, the CPODE region 519 is formed by replacing the conductive material of the gate region with a dielectric material.

[0071] The first VDR structure (VDR1) connects the p-type S / D structure of the first OD pattern 504a to the n-type S / D structure of the third OD pattern 504c. Therefore, the VDR1 structure forms an electrical connection between the drains of the first pull-up transistor PU1 and the first pull-down transistor PD1. Similarly, the second VDR structure (VDR2) connects the p-type S / D structure of the second OD pattern 504b to the n-type S / D structure of the fourth OD pattern 504d. Therefore, the VDR2 structure forms an electrical connection between the drains of the second pull-up transistor PU2 and the second pull-down transistor PD2.

[0072] Each inverter circuit has an input terminal (IN), which is a via-to-gate (VG) structure electrically connected to the corresponding gate segment (214a, 214b). For example, in cell region 502a, the input terminal IN is connected to the VG structure of the first gate segment 214a (see the equivalent structure on the right-hand side of the figure), which connects the gate of the first pull-up transistor PU1 to the first pull-down transistor PD1. Similarly, each inverter circuit has an output terminal (OUT), which is a via-to-drain / source (VD) structure electrically connected to the corresponding VDR structure. For example, in cell region 502a, the output terminal OUT is connected to the VD structure of the first VDR structure VDR1, which connects the drain of the first pull-up transistor PU1 to the first pull-down transistor PD1. In the second cell region 502b and in Figure 5A The layout diagram indicates that similar connections are made in other inverter circuits.

[0073] Figure 5B According to various embodiments Figure 5A A vertical cross-sectional view of portion 500b of semiconductor device 500a. (Limited) Figure 5BThe vertical plane of the cross-sectional view is composed of Figure 5A The section marked B-B' is indicated by the plane cut through a segment of OD layout pattern 504b that includes multiple transistor structures configured as gate-all-around (GAA) transistor devices. Figure 5A A portion 500b of the semiconductor device 500a is shown in an inverted configuration, with the back side component shown at the top of the figure and the front side component shown at the bottom of the figure.

[0074] Each GAA device includes a plurality of stacked semiconductor nanostructure layers configured as channel regions 216. Each device also includes a gate structure 214, which includes a conductive gate electrode layer 214a surrounding each channel layer 216. The gate electrode layer 214a includes a conductive material separated from the plurality of channel layers 216 by a gate dielectric layer 214b. The GAA transistor device also includes an S / D component formed above an end of each of the plurality of channel layers 216. According to some embodiments, the S / D component is of a similar structure and is collectively referred to as a source / drain component. Each GAA device also includes an insulating internal spacer layer 220 electrically insulating the gate electrode 214a from the S / D layer. According to various embodiments, a semiconductor device 500a is formed on a front side (in... Figure 5B (Middle side down) and dorsal side (in) Figure 5B Above the semiconductor substrate 210 (center facing upwards). In this embodiment, Figure 5B The plane intersects the semiconductor layer 210 along the longitudinal direction (i.e., along the 110 crystal direction of the S / D component). In some embodiments, the S / D layer has a thickness T along a third direction (Z direction) and a width W along a first direction and a second direction, and the thickness T is different from the width W.

[0075] The GAA device also includes a front contact MD and a back contact BVD. Each of the front contact MD and the back contact BVD includes a conductive material coupled to the S / D component. Each of the front contact MD and the back contact BVD also includes a metal silicide layer 514 formed between the contact structure (MD, BVD) and the S / D component. According to various embodiments, the S / D component is formed of a doped semiconductor material (e.g., silicon, SiGe, etc.), and the conductive material of the front contact MD and the back contact BVD is metallic. Therefore, the silicide layer 514 is selected as a metal / semiconductor alloy, such as TiSi. According to various embodiments, the silicide layer 514 has a thickness between about 0.5 nm and about 10 nm. According to various embodiments, the first conductivity of the metal silicide layer 514 is between the second conductivity of the epitaxial semiconductor layer S / D and the third conductivity of the front contact MD and the back contact BVD.

[0076] The gate structure 214 further includes a first gate spacer layer 516a and a second gate spacer layer 516b. In some embodiments, the dielectric constant of the second gate spacer layer 516b exceeds that of the first gate spacer layer 516a, and the second gate spacer layer 516b exhibits greater etch resistance compared to the first gate spacer layer 516a. According to various embodiments, the first gate spacer layer 516a includes silicon oxide, silicon carbide, or a suitable low-k dielectric material in some embodiments. The second gate spacer layer 516b includes silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material in some embodiments.

[0077] Figure 5B The structure also includes a front etch stop layer 518a, a front dielectric layer 232 formed above the front etch stop layer 518a, a back etch stop layer 518b, and a back dielectric layer 234 formed above the back etch stop layer 518b. A VD structure is formed within the front dielectric layer 232 and electrically connects the front contact MD to a first front metallization layer M0, which is also formed within the front dielectric layer 232. A first back metallization layer BMOa is formed above the back etch stop layer 518b within the back dielectric layer 234. As indicated, a second conductive side pattern 510b (e.g., see...) Figure 5A It overlaps with and is connected to the back contact BVD.

[0078] Figure 5B The structure also includes a contact etch stop layer (CESL) 518c. According to various embodiments, CESL 518c comprises silicon nitride, silicon oxynitride, and / or similar materials, and is formed by atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition or oxidation processes.

[0079] Figure 5B The structure also includes a pad layer L0 and an isolation structure 520 formed between the S / D structure and the pad layer. According to some embodiments, the pad layer L0 is an epitaxially formed semiconductor layer. The isolation structure 520 is a dielectric layer and is referred to in some embodiments as a “flexible bottom isolation” (FBI) structure. The isolation structure 520 reduces or substantially prevents current leakage between the S / D components and the semiconductor layer 210 or additional back-side components (such as back-side contacts BVD). In some embodiments, the isolation structure 520 comprises silicon oxide, silicon nitride, SiCN, SiCON, SiOC, SiC, or other suitable materials and is formed by oxidation (e.g., to form silicon oxide) or by a conformal deposition process and subsequent further processing, as follows. In other embodiments, the isolation structure 520 is an epitaxial semiconductor layer.

[0080] Figure 5CAccording to various embodiments Figure 5A A vertical cross-sectional view of a portion 500c of semiconductor device 500a. (Limited) Figure 5C The vertical plane of the cross-sectional view is composed of Figure 5A The cross-section is marked C-C'. This plane cuts through the segment of the device that intersects with the OD patterns 504d, 504b, 504a, and 504c (including the isolation member 506 between adjacent OD patterns) (in this order). As indicated, adjacent OD patterns 504b and 504a include p-type doped S / D components separated by gate isolation member 512. These OD patterns (504b, 504a) are electrically connected to the corresponding BVD structures, which are in turn connected via a first back-side interconnect structure BM0a, as referenced above. Figure 5A and Figure 5B As described.

[0081] The first conductive side pattern 510a of the first back-side interconnect structure BM0a (for example, see...) Figure 5A The BVD structure of the p-type S / D component is electrically connected to the OD pattern 504a, and the second conductive side pattern 510b of the first back-side interconnect structure BM0a (see, for example, see...) Figure 5A The BVD structure is electrically connected to the p-type S / D component of the OD pattern 504b. The conductor segment 508 of the first back-side interconnect structure BM0a (e.g., see...) Figure 5A The OD patterns (504a, 504b) do not overlap. Instead, the conductor segment 508 (in the plane of the diagram) of the first back-side interconnect structure BM0a substantially overlaps with the gate isolation member 512 and the isolation member 506 adjacent to the gate isolation member 512 along the line in the plane of the diagram (i.e., the X direction), and therefore... Figure 5C It is not explicitly stated in the document, but in Figure 5A As shown in the image. Additionally, see references... Figure 5C The gate isolation member 512 includes a first portion above the isolation member 506 and a second portion extending into the isolation member 506.

[0082] Figure 6A This is a layout diagram showing a plan view of a semiconductor device 600a according to various embodiments. The components of the semiconductor device 600a are... Figure 5A The semiconductor device 500a is the same as those, except for the electrical connection between the first back-side via BVD1 and the second back-side via BVD2. Therefore, for clarity, details are omitted. Figure 5A The many component tags presented in the text. (and) Figure 5A Compared to the 500a semiconductor device, Figure 6AThe semiconductor device 600a in one embodiment includes an additional conductive connector 602 electrically connected to a first back-side via BVD1 and a second back-side via BVD2. In some embodiments, the additional conductive connector 602 provides a larger surface area for electrical connection between the first back-side interconnect structure BMOa and the additional conductive connector 602.

[0083] In this respect, according to some embodiments, the additional conductive connector 602 has a rectangular shape extending longitudinally in a second direction (i.e., the Y direction) between the first back-side through-hole BVD1 and the second back-side through-hole BVD2. Therefore, the area of ​​the additional conductive connector 602 is larger than the combined area of ​​the first back-side through-hole BVD1 and the second back-side through-hole BVD2. Therefore, the conductive connection area between the additional conductive connector 602 and the first back-side interconnect structure BMOa is larger than... Figure 5A The embodiment shows a corresponding conductive connection region between the first back-side interconnect structure BMOa and the first back-side vias (BVD1, BVD2) of the semiconductor device 500a. Therefore, in some embodiments, this enlarged connection region results in a reduced contact resistance between the first back-side interconnect structure BMOa and the semiconductor device 600a.

[0084] Figure 6B According to various embodiments Figure 6A A vertical cross-sectional view of portion 600b of semiconductor device 600a. As described above, the components of portion 600b of semiconductor device 600a are... Figure 5A The semiconductor device 500a is the same as those, except for the electrical connection between the first back-side via BVD1 and the second back-side via BVD2. Figure 5A Compared to the 500a semiconductor device, Figure 6A The semiconductor device 600a in one embodiment includes an additional conductive connector 602 electrically connected to a first back-side via BVD1 and a second back-side via BVD2. In some embodiments, the additional conductive connector 602 provides a larger surface area for electrical connection between the first back-side interconnect structure BMOa and the additional conductive connector 602, resulting in reduced contact resistance, as described above.

[0085] Figure 7A This is a layout diagram showing a plan view of a semiconductor device 700a according to various embodiments. The components of the semiconductor device 700a are... Figure 6A and Figure 6B The same applies to all of them except for the configuration of the first back-side interconnect structure BM0a. In this respect, the first back-side interconnect structure BM0a is configured to include only a single conductive side pattern 510b. This configuration of the first back-side interconnect structure BM0a (in which another conductive side pattern 510a is omitted) eliminates the overlap between the first back-side interconnect structure BM0a and the first OD layout pattern 504a.

[0086] By eliminating the overlap with the first OD layout pattern 504a, the capacitance associated with the first back-side interconnect structure BM0a is reduced, as capacitance is a function of the spatial overlap of conductive structures separated by insulating or dielectric layers. The presence of the additional conductive connector 602 allows for the elimination of one of the conductive side patterns 510a, as the conductive connector 602 provides electrical connection between the first back-side vias BVD1 without requiring the first conductive side pattern 510a to overlap with the first back-side via BVD1.

[0087] Figure 7B This is a layout diagram showing a plan view of a semiconductor device 700b according to various embodiments. The components of the semiconductor device 700b are... Figure 7A The first conductive connection 602 is the same as the second conductive connection 604, except for the configuration of the first back-side interconnect structure BM0a and the configuration of the additional conductive connection 602. In this respect, in the embodiment semiconductor device 700b, the first conductive connection 602 is further connected to the second conductive connection 604. The first conductive connection 602 extends along a second direction (i.e., the Y direction) between the first back-side via BVD1 and the second back-side via BVD2, and the second conductive connection 604 extends along a first direction (i.e., along the X direction). This results in the first conductive connection 602 and the second conductive connection 604 forming a cross shape in a view along a plane perpendicular to the substrate (i.e., viewed in a plan view along the Z direction).

[0088] exist Figure 7B In the embodiment of semiconductor device 700b, the first back-side interconnect structure BM0a is also modified to eliminate the two conductive side patterns (510a, 510b). With this configuration, the first back-side interconnect structure BM0a includes only the portion of the conductor 508, which has a width comparable to the width of the isolation member 506. Furthermore, the conductor 508 is configured to substantially overlap only with the isolation member 506.

[0089] Other back-side interconnect structures (BM0b, BM0c) are similarly configured. Therefore, the conductor 508 and the second conductive connector 604 of the back-side interconnect structure BM0 substantially do not overlap with the active regions (i.e., OD patterns 504a, 504b, 504c, 504d) in a view along a direction perpendicular to the plane of substrate 210 (i.e., along the Z direction). For example, only the first conductive connector 602 overlaps with the first active region 504a and the second active region 504b. At this point, the spatial overlap between the back-side interconnect structure BM0 and the active regions (504a, 504b, 504c, 504d) is relatively small compared to... Figure 7A In some embodiments, the semiconductor device 700a is even further reduced in size. Therefore, in some embodiments, Figure 7B The semiconductor device 700b has reduced capacitance associated with the back-side interconnect structure BMO.

[0090] Figure 7C According to various embodiments Figure 7B A vertical cross-sectional view of portion 700c of semiconductor device 700b. As described above, the components of semiconductor device 700c are... Figure 6B The same as those described above, except for the configuration of the back-side interconnect structures (BM0a, BM0b, BM0c) and the presence of the second conductive connector 604. (See reference...) Figure 7C The width of the back-side interconnect structures (BM0a, BM0b, BM0c) is reduced due to the elimination of the conductive side patterns (510a, 510b). Furthermore, the width of the back-side interconnect structures (BM0a, BM0b, BM0c) is comparable to the width of the second conductive connector 604, thus reducing the width of the back-side interconnect structures (BM0a, BM0b, BM0c) and the active region (e.g., Figure 7C The overlap between the S / D components in the back-side interconnect structure (BM0a, BMOb, BMOc) is reduced. According to various embodiments, the reduction in spatial overlap leads to a reduction in capacitance associated with the back-side interconnect structure (BM0a, BMOb, BMOc).

[0091] Figures 8A to 8C This is a vertical cross-sectional view of a semiconductor structure (800a, 800b, 800c) for forming a semiconductor device having front and back contacts according to various embodiments. Figures 8A to 8C cross-sectional view and Figure 5B The view of semiconductor device 500b is the same. In this respect, the semiconductor structures (800a, 800b, 800c) are shown in an inverted configuration, with the back side of substrate 210 facing upwards and the front side of substrate 210 facing downwards.

[0092] The semiconductor structures (800a, 800b, 800c) include multiple GAA transistor structures, each including a gate structure 214 and a source / drain region 215 formed above a channel region. Each source / drain region 215 includes a pad layer L0 formed between a substrate 210 and an isolation structure 520. Figures 8A to 8C In this embodiment, the pad layer L0 is an epitaxial silicon layer, and the substrate 210 is a silicon substrate. The S / D structure is formed over the isolation structure 520 and is an epitaxial doped semiconductor layer. A silicide layer 514 is formed over the S / D structure, and source / drain contacts MD are formed to contact the S / D components. VD structures coupled to every other MD structure are formed in the front dielectric layer 232. Back contacts BVD are formed as follows.

[0093] refer to Figure 8BIn one embodiment, a hard mask stack 802 is formed over the back side of substrate 210, including a first hard mask layer 802a of silicon nitride and a second hard mask layer 802b disposed above the first hard mask layer 802a, wherein the second hard mask layer 802b comprises silicon oxide. The hard mask stack 802 is patterned by forming and patterning a photoresist layer over the second hard mask layer 802b using photolithography, and then etching the exposed portions of the second hard mask layer 802b using a fluorine-based dry etching process (such as reactive ion etching (RIE)).

[0094] Then, a patterned second hard mask layer 802b is used as a mask to etch the underlying first hard mask layer 802a using selective etching chemistry (e.g., plasma etching based on CHF3 or CF4). After removing the photoresist, the resulting patterned hard mask stack 802, including the first hard mask layer 802a and the second hard mask layer 802b, is used to etch via openings 804 in the substrate 210 using directional anisotropic etching processes such as deep reactive ion etching (DRIE). The hard mask stack provides high etch selectivity and dimensional control during the via formation process. Reference Figure 8B The isolation structure 520 serves as an etch stop layer for forming the via opening 804. The isolation structure 520 is then removed by a further etching process. Then, a reference is implemented. Figure 8C The process described forms the back-side contact element BVD, as follows.

[0095] In one embodiment, after forming a via 804 extending through the substrate and terminating in the isolation structure 520, a conformal pad layer 806 comprising silicon nitride is deposited along the via sidewalls and bottom surface to provide dielectric isolation and mechanical support. The conformal pad layer 806 is then subjected to a controlled thinning process, referred to herein as silicon nitride removal (SNR), in which the pad is partially etched to reduce its thickness while maintaining sidewall coverage. Following the SNR process, a barrier layer 808 comprising titanium silicon nitride (TSN) is deposited, for example by physical vapor deposition (PVD) or atomic layer deposition (ALD), to suppress the diffusion of conductive material and promote adhesion to the underlying and adjacent layers. According to various embodiments, the barrier layer 808 is configured to provide enhanced thermal and chemical stability compared to a conventional TiN barrier. The TSN layer also reacts with the S / D epitaxial layer to form a metal silicide layer 514 on the surface of the S / D layer. After depositing barrier stacks (806, 808), via 804 is filled with a conductive material such as tungsten using a chemical vapor deposition (CVD) process to form a conductive via contact (BVD). The combination of SNR and TSN enables improved via reliability, reduced contact resistance, and enhanced process integration in high aspect ratio via structures.

[0096] Figures 9A to 9EThese are vertical cross-sectional views of semiconductor structures (900a, 900b, 900c, 900d, 900e) for forming semiconductor devices having front and back contacts according to various embodiments. Figures 9A to 9E cross-sectional view and Figures 8A to 8C The views of the semiconductor structures (800a, 800b, 800c) are the same. In this respect, the semiconductor structures (900a, 900b, 900c, 900d, 900e) are shown in an inverted configuration, with the back side of substrate 210 facing upwards and the front side of substrate 210 facing downwards.

[0097] The semiconductor structures (900a, 900b, 900c, 900d, 900e) include multiple GAA transistor structures, each including a gate structure 214 formed above a channel region and a source / drain region 215. Each source / drain region 215 includes a pad layer L0 formed between a substrate 210 and an isolation structure 520. Figures 8A to 8C In this embodiment, the pad layer L0 is an epitaxial silicon-germanium (SiGe) layer, and the substrate 210 is a silicon substrate. The S / D structure is formed above the isolation structure 520 and is an epitaxial doped semiconductor layer. A silicide layer 514 is formed above the S / D structure, and source / drain contacts MD are formed in contact with the silicide layer 514. A VD structure coupled to the MD structure is formed in the front dielectric layer 232. A back contact BVD is formed as follows.

[0098] refer to Figure 9B In one embodiment, a hard mask stack 802 is formed over the back side of substrate 210, comprising a first hard mask layer 802a of silicon nitride and a second hard mask layer 802b disposed over the first hard mask layer 802a, wherein the second hard mask layer 802b comprises silicon oxide. The hard mask stack 802 is patterned by forming and patterning a photoresist layer over the second hard mask layer 802b using photolithography, and subsequently etching the exposed portions of the second hard mask layer 802b using a fluorine-based dry etching process (such as reactive ion etching (RIE)). According to some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP)) is performed on the front side of the structure prior to forming the hard mask stack 802 to reduce the thickness of the front dielectric layer 232 and the thickness of the VD structure.

[0099] Then, a patterned second hard mask layer 802b is used as a mask to etch the underlying first hard mask layer 802a using selective plasma etching chemistry (e.g., CHF3 or CF4-based etching). After removing the photoresist, the resulting patterned hard mask stack 802 is used to etch narrow, high aspect ratio vias 804 through the silicon layer of substrate 210 using directional anisotropic etching processes optimized for silicon etching characteristics (such as deep reactive ion etching (DRIE) or inductively coupled plasma (ICP) etching).

[0100] When reaching the epitaxial SiGe L0 layer (for example, see...) Figure 9B The etching process parameters are modified to accommodate the different etching behavior of SiGe material relative to single-crystal silicon. In one embodiment, plasma chemistry is adjusted to enhance etch selectivity to the SiGe layer while maintaining anisotropic profile control and minimizing lateral etching. For example, according to various embodiments, the ratio of fluorocarbon to halogen gas, bias power supply, and chamber voltage are adjusted to address the increased etching rate of SiGe due to its germanium content. In some embodiments, additives such as HBr or Cl2 are introduced to stabilize sidewall passivation and maintain etching anisotropy. The etching process continues through the SiGe layer and selectively terminates on the underlying dielectric isolation layer 520 (e.g., see...). Figure 9C The dielectric isolation layer 520 serves as an etch stop layer. The isolation structure 520 is then removed. According to some embodiments, endpoint detection techniques (such as photoemission spectroscopy or time-based control) are used to ensure precise stopping on the dielectric. The adjusted etching process enables the formation of high aspect ratio vias through the silicon and SiGe layers while maintaining critical dimensions and preventing damage to the etch stop layer.

[0101] According to various embodiments, after forming vias 804 extending through the silicon and silicon-germanium layers, a conformal pad layer 806 comprising silicon nitride is deposited along the via sidewalls and bottom surface to provide dielectric isolation and mechanical support. The conformal pad layer 806 then undergoes a controlled thinning process (e.g., referred to as silicon nitride removal (SNR)), in which the conformal pad layer 806 is partially etched to reduce its thickness while maintaining sidewall coverage. Following the SNR process, a barrier layer 808 comprising TSN is deposited, for example by PVD or ALD, to suppress the diffusion of conductive material and promote adhesion to underlying and adjacent layers. According to some embodiments, the barrier layer 808 is configured to provide enhanced thermal and chemical stability. The TSN layer also reacts with the S / D layer to form a metal silicide layer 514 of the S / D layer.

[0102] Figure 9DSemiconductor structure 900d is formed from semiconductor structure 900c by forming a back-side contact BVD and by removing the second hard mask layer 802b. At this point, after depositing the barrier stack (806, 808), the via 804 is filled with a conductive material such as tungsten using a CVD process to form a back-side conductive via contact BVD (e.g., see...). Figure 9D The combined use of SNR and TSN provides improved via reliability, reduced contact resistance, and enhanced process integration in high aspect ratio via structures. According to some embodiments, the second hard mask layer 802b is then removed by etching or by performing a planarization process (e.g., chemical mechanical planarization (CMP)). According to some embodiments, after removing the second hard mask layer 802b, a portion of the remaining first hard mask layer 802a is also removed to reduce the thickness of the first hard mask layer 802a.

[0103] Figure 9E According to various embodiments Figure 9D A magnified vertical cross-sectional view of the semiconductor structure 900d, portion 900e. The portion 900e of the semiconductor structure 900d is composed of... Figure 9D The dashed rectangle marked "900e" indicates this. (See reference.) Figure 9E The back-side contact BVD includes a neck region 902, wherein the back-side contact BVD has a minimum width 904a. The neck region 902 is located approximately at the point where the etching process stops etching the silicon layer of the substrate 210 and begins etching the SiGe pad layer L0. The width of the back-side contact BVD increases in the vertical direction (i.e., along the Z direction) as a function of distance away from the neck region 902 in both directions. For example, the width of the back-side contact BVD increases from its minimum width 904a to a first larger width 904b, and further to a third larger width 904c near the bottom of the back-side contact BVD, wherein the back-side contact BVD is connected to the silicide layer 514 formed above the S / D structure. Furthermore, according to various embodiments, the back-side contact BVD has a depth such that the bottom portion of the back-side contact BVD is located at approximately the same level as the first channel region 216.

[0104] Figures 10A to 10DThis is a vertical cross-sectional view of semiconductor structures (1000a, 1000b, 1000c, 1000d) for forming semiconductor devices having front-side contacts and back-side contacts according to various embodiments. The processing operations for forming the semiconductor structures (1000a, 1000b, 1000c, 1000d) are substantially the same as those for forming the semiconductor structures (900a, 900b, 900c, 900d, 900e), except for the size of the vias (804a, 804b) and the resulting back-side contact structures (602, BVD1, BVD2). In this respect, the hard mask stack 802 is formed above the back side of the substrate 210 (e.g., see...). Figure 10A ), and patterned to form a larger first through-hole 804a (e.g., see Figure 10B In this regard, refer to Figure 10B The via 804a is large enough to span the two source / drain regions 215 separated by the gate region 214 (e.g., see...). Figure 10A and Figure 10B Then, a first etching process is performed to selectively etch the back-side silicon layer of substrate 210 to form the first via 804a. Once the etching process reaches the SiGe pad layer L0, the etching process parameters are changed as described above. Figure 9B More detailed description.

[0105] refer to Figure 10C The etching process parameters were changed to selectively etch the SiGe pad layer L0, but the gate region portion 1002 of the substrate 210 was left substantially intact. Thus, two second vias 804b were created by selectively etching the SiGe pad layer L0 in this manner. The back-side contact structures (602, BVD1, BVD2) were then implemented in accordance with the above reference. Figure 8C and Figure 9D The fundamentally similar operations described are used to form the back-side contact structures (602, BVD1, BVD2). At this point, a barrier stack (806, 808) is deposited, and vias (804a, 804b) are filled with a conductive material such as tungsten using a chemical vapor deposition (CVD) process to form back-side contact structures (602, BVD1, BVD2). Thus, filling the second via 804b generates the first back-side via BVD1 and the second back-side via BVD2, and filling the first via 804a generates additional conductive connectors 602 electrically connected to the first and second back-side vias BVD1 and BVD2. Further processing operations, such as planarization operations (e.g., CMP), are then performed before forming the back-side metallization layer BMO that electrically connects the back-side contact structures (602, BVD1, BVD2) to the S / D components. As described above, a metal silicide layer 514 is formed between the S / D components and the back-side vias (BVD1, BVD2).

[0106] Figure 11 This is a flowchart of the operation of a method 1100 for manufacturing a semiconductor device according to various embodiments. Method 1100 includes performing processing operations (1102, 1104, 1106, 1108) to... Figure 2A The middle face downwards, and in Figure 5A Interconnect structures (BM0a, BM0b, BM0c) are formed on the substrate 210 (with the center facing upwards). On the substrate 210, the first active region 504a and the second active region 504b are disposed on the front side of the substrate 210 (in the middle). Figure 2A The middle is facing upwards, and in Figure 5A (Center facing downwards) Above. The first active region 504a and the second active region 504b extend longitudinally along a first direction (X direction) and are spaced apart from each other along a second direction (Y direction) different from the first direction (X direction).

[0107] In operation 1102, method 1100 includes performing a first etching operation ( Figure 8B , Figure 9B , Figure 9C , Figure 10A , Figure 10B A first opening (804, 804b) is formed in the back side of substrate 210 above a first source / drain component S / D in a view perpendicular to the plane (XY plane) of substrate 210 (i.e., the Z direction), located above a first active region 504a, wherein the first source / drain component S / D includes a metal silicide layer 514 formed above the epitaxial semiconductor layer S / D. In operation 1104, method 1100 includes: depositing a first conductive material in the first opening ( Figure 8C , Figure 9D , Figure 10D To form a first conductive via BVD1 extending through the substrate 210 and to electrically connect the first source / drain component S / D to the first conductive via BVD1.

[0108] In operation 1106, method 1100 includes: depositing a dielectric layer 234 over the back side of substrate 210; and performing a second etching operation on dielectric layer 234 to form trenches in dielectric layer 234. In operation 1108, method 1100 includes depositing a second conductive material in the trenches in dielectric layer 234 to form an interconnect structure electrically connected to the first conductive via BVD1 (e.g., see...). Figure 2A and Figure 5B ).

[0109] According to various embodiments, the interconnect structures (BM0a, BM0b, BM0c) extend longitudinally along a first direction (X direction) and substantially do not overlap with the first active region 504a and the second active region 504b in a view along a plane perpendicular to the substrate 210 (XY plane) (i.e., Z direction). The first source / drain component S / D includes a thickness along a third direction different from the first direction (X direction) and the second direction (Y direction), and the first source / drain component S / D includes a width along the second direction (Y direction), and the thickness is different from the width (B3) (e.g., see...). Figure 5B Furthermore, the first conductivity of the metal silicide layer 514 is between the second conductivity of the epitaxial semiconductor layer S / D and the third conductivity of the first conductive via BVD1.

[0110] According to various embodiments, performing the first etching operation further includes: forming a second opening 804b in the back side of the substrate 210 above the second source / drain component S / D of the second active region 504b (e.g., see...). Figure 10C ); and forming a third opening 804a spanning the first opening 804b and the second opening 804b. According to various embodiments, depositing the first conductive material further includes: depositing the first conductive material in the first opening to form a first conductive via BVD1, and depositing the first conductive material in the second opening to form a second conductive via BVD2, both the first conductive via BVD1 and the second conductive via BVD2 extending through the substrate 210, and respectively, a first source / drain component S / D electrically connected to the first conductive via BVD1 and a second source / drain component S / D electrically connected to the second conductive via BVD2 (e.g., see...). Figure 10D ); and depositing a first conductive material in the third opening 804a to form a first conductive connector 602 that electrically connects the first conductive via BVD1 and the second conductive via BVD2.

[0111] According to various embodiments, performing the first etching operation further includes forming a fourth opening (similar to 804a) in the back side of the substrate 210. The fourth opening is located above a portion of the third opening 804a and extends longitudinally along a first direction (X direction), wherein the fourth opening extends longitudinally along a second direction (Y direction), such that the fourth opening intersects with the third opening and together with the third opening forms a cross shape in a view along a plane perpendicular to the substrate 210 (XY plane) (i.e., Z direction) (e.g., see...). Figure 7B …The fourth opening follows the horizontal dashed line portion of the cross shape.

[0112] According to various embodiments, depositing the first conductive material further includes depositing the first conductive material in the fourth opening to form a second conductive connector 604 extending along a first direction (X direction), such that the first conductive connector 602 and the second conductive connector 604 form a cross shape in a view along a direction perpendicular to the plane (XY plane) of the substrate 210 (i.e., the Z direction) (e.g., see...). Figure 7B The interconnect structure 508 is electrically connected to the second conductive connector 604, and the interconnect structure 508 and the second conductive connector 604 substantially do not overlap with the first active region 504a and the second active region 504b in a view along a plane (XY plane) perpendicular to the substrate 210 (i.e., the Z direction).

[0113] Referring to all the accompanying drawings and various embodiments of this disclosure, semiconductor devices (500a, 600a, 700a, 700b) are disclosed. The semiconductor devices (500a, 600a, 700a, 700b) include: a semiconductor substrate 210 having a front side (in... Figure 2A (Middle surface upward) and with the front side (in) Figure 2A (Middle face upward) opposite dorsal side (in) Figure 2A (facing downwards); the first active region 504a and the second active region 504b are disposed on the front side of the semiconductor substrate 210 (in the middle). Figure 2A The first active region 504a is disposed between the second active region 504b and the second active region 504b. The first active region 504a is disposed between the second active region 504b and the second active region 504b.

[0114] Semiconductor devices (500a, 600a, 700a, 700b) include: a back-side circuit (BM0a, BM0b, BM0c) disposed on the back side of a semiconductor substrate 210, including a conductor 508 disposed in a dielectric layer 234; and a first conductive via BVD1 extending through the semiconductor substrate 210 and electrically connecting the conductor 508 to a first active region 504a. According to various embodiments, the conductor 508 extends longitudinally along a first direction (X direction) and substantially does not overlap with the first active region 504a and the second active region 504b in a view along a direction perpendicular to a plane (XY plane) of the semiconductor substrate 210 (i.e., the Z direction).

[0115] According to various embodiments, the conductor 508 substantially overlaps with the isolation member 506 in a view along a direction perpendicular to the plane (XY plane) of the semiconductor substrate 210 (i.e., the Z direction). According to various embodiments, the back-side circuitry (BM0a, BMOb, BMOc) further includes a first conductive side pattern 510a electrically connected to the conductor 508, and the first conductive side pattern 510a extends along a first direction (see width w1 along the X direction) and also extends laterally to the conductor 508 along a second direction perpendicular to the first direction (X direction) and parallel to the plane (XY plane) of the semiconductor substrate 210 (see width w2 along the Y direction).

[0116] According to various embodiments, the first conductive side pattern 510a is electrically connected to the first conductive via BVD1. According to various embodiments, the first conductive side pattern 510a partially overlaps with the first active region 504a in a view along a direction perpendicular to the plane (XY plane) of the semiconductor substrate 210 (i.e., the Z direction). According to various embodiments, the first conductive side pattern 510a at least partially overlaps with the first conductive via BVD1 in a view along a direction perpendicular to the plane (XY plane) of the semiconductor substrate 210 (i.e., the Z direction).

[0117] According to various embodiments, the semiconductor devices (500a, 600a, 700a, 700b) further include: a first gate structure 214a located above the first active region 504a and extending along a second direction (Y direction); a second gate structure 214b located above the second active region 504b and extending along the second direction (Y direction); and a gate isolation member 512 disposed between the first gate structure 214a and the second gate structure 214b and extending along a first direction (X direction). According to various embodiments, the first conductive side pattern 510a at least partially overlaps with the gate isolation member 512 in a view along a direction perpendicular to the plane (XY plane) of the semiconductor substrate 210 (i.e., the Z direction).

[0118] According to various embodiments, the semiconductor devices (500a, 600a, 700a, 700b) further include: a second conductive via BVD2 extending through the semiconductor substrate 210 and electrically connecting the wire 508 to the second active region 504b. According to various embodiments, the back-side circuitry (BM0a, BM0b, BM0c) further includes: a second conductive side pattern 510b electrically connected to the wire 508, extending along a first direction (see width w1 along the X direction) and also laterally to the wire 508 along a second direction opposite to the first conductive side pattern 510a (see width w2 along the Y direction). According to various embodiments, the second conductive side pattern 510b is electrically connected to the second conductive via BVD2 and overlaps with the second conductive via BVD2 in a view along a direction perpendicular to the plane (XY plane) of the semiconductor substrate 210 (i.e., the Z direction).

[0119] According to various embodiments, the second conductive side pattern 510b partially overlaps with the second active region 504b in a view along a direction perpendicular to the plane (XY plane) of the semiconductor substrate 210 (i.e., the Z direction). According to various embodiments, the semiconductor devices (500a, 600a, 700a, 700b) further include a conductive connector 602 electrically connecting the first conductive via BVD1 and the second conductive via BVD2. According to various embodiments, the wire 508 and the first conductive side pattern 510a do not overlap with the second conductive via BVD2 in a view along a direction perpendicular to the plane (XY plane) of the semiconductor substrate 210 (i.e., the Z direction) (e.g., see...). Figure 7A ).

[0120] Referring to all the accompanying drawings and various embodiments of this disclosure, semiconductor devices (500a, 600a, 700a, 700b) are disclosed. The semiconductor devices (500a, 600a, 700a, 700b) include: a substrate 210 having a front side (in... Figure 2A (Middle side up) and dorsal side (in) Figure 2A (facing downwards); the first active region 504a and the second active region 504b are disposed on the front side of the substrate 210 (in the middle). Figure 2A The first active region 504a extends longitudinally above the first active region 504a and along the first direction (X direction) and the second active region 504b extends longitudinally above the first active region 504a and along the first direction (Y direction) which is different from the first direction (X direction). The second active region 504a separates from the second active region 504b along the second direction (Y direction) which is different from the first direction (X direction).

[0121] The semiconductor devices (500a, 600a, 700a, 700b) further include: a first gate structure 214a and a second gate structure 214b, wherein the first gate structure 214a is located above a first active region 504a, and the second gate structure 214b is located above a second active region 504b; a gate isolation member 512, disposed between the first gate structure 214a and the second gate structure 214b, separating the first gate structure 214a and the second gate structure 214b along a second direction (Y direction), wherein the gate isolation member 512 includes a first portion located above an isolation member 506 (C4) and a second portion extending into the isolation member 506 (C3) (see...). Figure 5C , Figure 6B and Figure 7C ); and back-side circuitry (BM0a, BM0b, BM0c), disposed on the back side of substrate 210 (in Figure 2A (Middle facing down) Above.

[0122] The semiconductor devices (500a, 600a, 700a, 700b) further include: a first conductive via BVD1 extending through the substrate 210 and electrically connecting the back-side circuitry (BM0a, BM0b, BM0c) to the first active region 504a; and a second conductive via BVD2 extending through the substrate 210 and electrically connecting the back-side circuitry (BM0a, BM0b, BM0c) to the second active region 504b. According to various embodiments, the back-side circuitry (BM0a, BM0b, BM0c) substantially does not overlap with the first active region 504a and the second active region 504b in a view along a plane perpendicular to the substrate 210 (XY plane) (i.e., the Z direction).

[0123] According to various embodiments, the back-side circuitry (BM0a, BM0b, BM0c) further includes: a conductor 508 extending longitudinally along a first direction (X direction), the conductor 508 substantially overlapping the isolation member 506 in a view along a plane perpendicular to the substrate 210 (XY plane) (i.e., Z direction); a first conductive side pattern 510a electrically connected to the conductor 508 and extending laterally to the conductor 508 along a second direction (Y direction), and electrically connected to a first conductive via BVD1; and a second conductive side pattern 510b electrically connected to the conductor 508 and extending laterally to the conductor 508 along a second direction opposite to the first conductive side pattern 510a (see width w2 along the Y direction), and electrically connected to a second conductive via BVD2.

[0124] According to various embodiments, the semiconductor devices (500a, 600a, 700a, 700b) further include: a first conductive connector 602 electrically connected to a first conductive via BVD1 and a second conductive via BVD2. According to various embodiments, the back-side circuitry (BM0a, BM0b, BM0c) further includes: a conductor 508 extending longitudinally along a first direction (X direction), substantially overlapping with the isolation member 506 in a view along a plane perpendicular to the substrate 210 (XY plane) (i.e., Z direction); and a first conductive side pattern 510a electrically connected to the conductor 508 and extending laterally to the conductor 508 along a second direction (see width w2 along the Y direction), and electrically connected to the first conductive connector 602.

[0125] According to various embodiments, the back-side circuitry (BM0a, BM0b, BM0c) further includes: a wire 508 extending longitudinally along a first direction (X direction), the wire 508 substantially overlapping the isolation member 506 in a view along a plane perpendicular to the substrate 210 (XY plane) (i.e., Z direction); and a second conductive connector 604 electrically connected to the first conductive connector 602.

[0126] According to various embodiments, the first conductive connector 602 extends along a second direction (Y direction) between the first conductive via BVD1 and the second conductive via BVD2, and the second conductive connector 604 extends along a first direction (X direction), such that the first conductive connector 602 and the second conductive connector 604 form a cross shape in a view along a direction perpendicular to the plane (XY plane) of the substrate 210 (i.e., the Z direction) (see, for example, see...). Figure 7B The wire 508 is electrically connected to the second conductive connector 604, and the wire 508 and the second conductive connector 604 substantially do not overlap with the first active region 504a and the second active region 504b in a view along a plane (XY plane) perpendicular to the substrate 210 (i.e., the Z direction).

[0127] Figure 12 This is a block diagram of an integrated circuit (IC) manufacturing system 1200 and associated IC manufacturing processes according to various embodiments. In some embodiments, the manufacturing system 1200 is used to manufacture at least one of (A) one or more photomasks or (B) one or more components in a layer of a semiconductor device, based on a layout plan for the semiconductor device.

[0128] exist Figure 12In this IC manufacturing system 1200, entities interact with each other throughout the design, development, and manufacturing cycles, such as design studio 1220, mask room 1230, and IC manufacturer / fabrication plant (Fab) 1250, and / or services related to the manufacture of IC devices 1260. The entities in system 1200 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design studio 1220, mask room 1230, and IC fabrication plant 1250 are owned by a single, larger company. In some embodiments, two or more of design studio 1220, mask room 1230, and IC fabrication plant 1250 coexist in a shared facility and use shared resources.

[0129] Design studio (or design team) 1220 generates a layout plan 1222 for an IC design. In some embodiments, layout plan 1222 includes one or more layout diagrams, and each layout diagram includes various geometric patterns designed for an IC device 1260 (e.g., a semiconductor device). The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1260 to be manufactured. The various layers are combined to form various IC components. For example, portions of layout plan 1222 include layout patterns indicating various IC components, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads to be formed based on a semiconductor substrate (such as a silicon wafer); and various material layers disposed on the semiconductor substrate. Design studio 1020 implements appropriate design procedures to form layout plan 1222. Design procedures include one or more of logic design, physical design, or place-and-route. In some embodiments, each layout diagram of layout plan 1222 is presented in one or more data files having geometric pattern information. For example, each layout diagram of layout plan 1222 may be expressed in GDSII file format or DFII file format.

[0130] Mask chamber 1230 includes mask data preparation 1232 and mask fabrication 1244. Mask chamber 1230 uses layout planning 1222 to fabricate one or more masks 1245 for fabricating various layers of IC device 1260 according to layout planning 1222. Mask chamber 1230 implements mask data preparation 1232, where layout planning 1222 is converted into a representative data file (RDF). Mask data preparation 1232 provides the RDF to mask fabrication 1244. Mask fabrication 1244 includes a mask writer that converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1245. Layout planning 1222 is manipulated by mask data preparation 1232 to conform to the specific characteristics of the mask writer and / or the requirements of IC fabrication plant 1250. Figure 12 In this diagram, mask data preparation 1232 and mask manufacturing 1244 are shown as separate elements. In some embodiments, mask data preparation 1232 and mask manufacturing 1244 may be collectively referred to as mask data preparation.

[0131] In some embodiments, mask data preparation 1232 includes various stages, including one or more of the following: Logical Operation (LOP) stage 1232a, Resolution Enhancement Technology (RET) stage 1232b, Mask Rule Checker (MRC) stage 1232c, and Lithography Process Inspection (LPC) stage 1232d. In some embodiments, each of the above stages receives an input layout diagram from the previous stage in GDSII or DFII file format, and outputs the processed result as an output layout diagram to the subsequent stage in GDSII or DFII file format. In some embodiments, some stages and / or operations described herein are omitted, and some additional stages and / or operations are included in mask data preparation 1232. In some embodiments, based on... Figure 12 The instances in the dataset implement these phases in different orders.

[0132] In some embodiments, LOP phase 1232a corresponds to modifying the input layout diagram (e.g., the layout diagram from layout planning 1222 of design room 1220) according to manufacturing rules. In some embodiments, LOP phase 1232a includes: checking whether the input layout diagram satisfies a set of rules derived based on constraints from various manufacturers; and modifying the input layout diagram accordingly to obtain an output layout diagram that satisfies the set of rules.

[0133] In some embodiments, RET stage 1232b corresponds to modifying the input layout diagram (e.g., the output layout diagram from LOP stage 1232a) to obtain an output layout diagram that compensates for various limitations in the lithography process used to manufacture IC device 1260. In some embodiments, RET stage 1232b includes rule-based optical proximity correction (OPC) processes and / or model-based OPC processes, which correspond to using lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. In some embodiments, RET stage 1232b also includes one or more other enhancement techniques, such as off-axis illumination, sub-resolution auxiliary components, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, reverse lithography (ILT) is also used, which treats OPC as a reverse imaging problem.

[0134] In some embodiments, MRC stage 1232c corresponds to checking the layout diagram that has undergone processing in the RET stage with a set of mask creation rules, which includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, MRC stage 1232c also corresponds to modifying the layout diagram to compensate for lithographic implementation effects during mask fabrication 1244, which can undo a portion of the modifications implemented by the OPC of RET stage 1232b to satisfy the mask creation rules.

[0135] In some embodiments, LPC stage 1232d corresponds to the simulation process to be performed by IC manufacturing plant 1250 to manufacture IC device 1260. The simulation at LPC stage 1232d is based on a layout diagram from a previous stage (e.g., MRC stage 1232c) to create one or more simulated manufacturing parts representing corresponding portions of the IC device 1260 to be manufactured, based on the layout diagram from MRC stage 1232c. Processing parameters in the LPC simulation include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The simulation at LPC stage 1232d considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after one or more simulated manufacturing parts have been created at LPC stage 1232d, if the size, shape, and / or spatial relationships of the simulated parts do not conform to design rules or design specifications, the process continues to repeat RET stage 1232b and / or MRC stage 1232c to further refine the layout diagram.

[0136] In this example, following LPC stage 1232d, mask data preparation 1232 further includes a fractal process (FRAC) stage 1232e. In some embodiments, FRAC stage 1232e receives the input layout diagram from the previous stage (e.g., LPC stage 1232d) in GDSII or DFII file format and outputs the processing result to a subsequent stage (e.g., mask manufacturing 1244) as an RDF format mask file. In some embodiments, FRAC stage 1232e corresponds to “fractalizing” the designed part into polygons or other component shapes suitable for mask production.

[0137] Following mask data preparation 1232 and during mask fabrication 1244, masks 1245 or mask sets 1245 (collectively, "one or more masks 1245") are fabricated based on a modified layout diagram and / or a mask file converted from the modified layout diagram. In some embodiments, mask fabrication 1244 includes performing one or more photolithographic exposures based on the modified layout diagram and / or mask file from mask data preparation 1232. In some embodiments, a pattern is formed on the mask (photomask or intermediate mask) (e.g., one or more masks 1245) using an electron beam (e-beam) or a plurality of e-beams based on the modified layout diagram and / or mask file. One or more masks 1245 can be formed using various techniques. In some embodiments, one or more masks 1245 are formed using a binary technique. In some embodiments, the mask pattern of the mask includes opaque areas and transparent areas.

[0138] The radiation beam (such as an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer is blocked by opaque regions and passes through transparent regions. In one example, a binary mask version of mask 1245 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 1245 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1245, the individual components in the pattern formed on the phase-shifting mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be an attenuated PSM or an alternating PSM. The mask generated by mask fabrication 1244 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in semiconductor wafer 1253, in an etching process to form various etched regions in semiconductor wafer 1253, and / or in other suitable processes.

[0139] IC manufacturing plant 1250 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing plant 1250 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (e.g., front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (e.g., back-end process (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility may provide other services to the foundry.

[0140] IC manufacturing plant 1250 includes manufacturing tools 1252 configured to perform various manufacturing operations on semiconductor wafers 1253, thereby enabling IC devices 1260 to be manufactured according to a mask (e.g., mask 1245). In various embodiments, manufacturing tools 1252 include one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber (e.g., chemical vapor deposition (CVD) chamber or low-pressure chemical vapor deposition (LPCVD) furnace), chemical mechanical polishing (CMP) system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of implementing one or more suitable manufacturing processes as discussed herein.

[0141] IC fabrication plant 1250 uses a mask 1245 manufactured by mask chamber 1230 to fabricate IC device 1260. Therefore, IC fabrication plant 1250 uses at least indirectly one or more layout patterns of layout plan 1222 to fabricate IC device 1260. In some embodiments, semiconductor wafer 1253 is fabricated by IC fabrication plant 1250 using one or more masks 1245 to form IC device 1260. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based at least indirectly on one or more layout patterns of layout plan 1222. Semiconductor wafer 1253 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1253 also includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0142] Figure 13 This is a block diagram of an EDA system 1300 according to various embodiments. In some embodiments, the EDA system 1300 includes an automated placement and routing (APR) system. In some embodiments, the EDA system 1300 is a general-purpose computing device including a hardware processor 1302 and a non-transitory, computer-readable storage medium 1304. The storage medium 1304, etc., is encoded with (i.e., stores) computer program code 1306 (i.e., a set of executable instructions). The instructions 1306, executed by the hardware processor 1302, represent (at least partially) an EDA tool that implements some or all of the methods described herein (hereinafter, the mentioned processes and / or methods) according to one or more embodiments.

[0143] Processor 1302 is electrically coupled to computer-readable storage medium 1304 via bus 1308. Processor 1302 is also electrically coupled to I / O interface 1310 via bus 1308. Network interface 1312 is also electrically connected to processor 1302 via bus 1308. Network interface 1312 is connected to network 1314, enabling processor 1302 and computer-readable storage medium 1304 to be connected to external components via network 1314. Processor 1302 is configured to execute computer program code 1306 encoded in computer-readable storage medium 1304, such that system 1300 can be used to implement some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0144] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1304 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video disc (DVD).

[0145] In one or more embodiments, storage medium 1304 stores computer program code 1306 configured to enable system 1300 (where such execution represents (at least partially) EDA tools) to implement some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1304 also stores information that facilitates the implementation of some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1304 stores a library 1307 of standard cells, including standard cells as disclosed herein. In one or more embodiments, storage medium 1304 stores one or more layout diagrams 1309 corresponding to one or more layouts disclosed herein.

[0146] EDA system 1300 includes an I / O interface 1310. The I / O interface 1310 is coupled to external circuitry. In one or more embodiments, the I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1302.

[0147] EDA system 1300 also includes a network interface 1312 coupled to processor 1302. Network interface 1312 allows system 1300 to communicate with network 1314, to which one or more other computer systems are connected. Network interface 1312 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the aforementioned processes and / or methods are implemented in two or more systems 1300. System 1300 is configured to receive information via I / O interface 1310. Information received via I / O interface 1310 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 1302. Information is transmitted to processor 1302 via bus 1308. EDA system 1300 is configured to receive UI-related information via I / O interface 1310. Information is stored as a user interface (UI) 1342 in computer-readable medium 1304.

[0148] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application, which is part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application, which is part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by EDA system 1300. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0149] The disclosed embodiments advantageously provide semiconductor devices (500a, 600a, 700a, 700b) and a method 1100 for manufacturing semiconductor devices (500a, 600a, 700a, 700b), wherein active regions (504a, 504b, 504c, 504d) disposed on the front side of substrate 210 are electrically connected to back-side circuitry (BM0a, BM0b, BM0c) configured to have reduced capacitance. In this respect, the active regions (504a, 504b, 504c, 504d) formed on the front side of the semiconductor devices (500a, 600a, 700a, 700b) are separated from each other by isolation member 506, and the back-side interconnect structure is substantially above isolation member 506 in a plan view. Therefore, the back-side interconnect structures (BM0a, BM0b, BM0c) and the active regions (504a, 504b, 504c, 504d) do not overlap significantly, except for a small overlap in some embodiments of the conductive side patterns (510a, 510b) that primarily overlap with the conductive via structures (BVD1, BVD2).

[0150] In other embodiments, the conductive side patterns (510a, 510b) are eliminated, and a conductor 508, substantially above the isolation member 506, is electrically connected to a first conductive connector 604 aligned with the conductor and a second conductive connector 602 laterally aligned with the conductor 508. The conductor 508 overlaps with the conductive via structures (BVD1, BVD2). Minimal overlap between the back-side circuitry (BM0a, BM0b, BM0c) and the active regions (504a, 504b, 504c, 504d) results in reduced capacitance compared to comparative embodiments where there is greater overlap between the back-side circuitry and the active regions.

[0151] According to various embodiments, the semiconductor device includes: a semiconductor substrate having a front side and a back side opposite to the front side; a first active region and a second active region disposed on the front side of the semiconductor substrate and extending longitudinally along a first direction parallel to a plane of the semiconductor substrate; an isolation member disposed between the first active region and the second active region; a back-side circuit disposed on the back side of the semiconductor substrate, including a wire disposed in a dielectric layer; and a first conductive via extending through the semiconductor substrate and electrically connecting the wire to the first active region. According to various embodiments, the wire extends longitudinally along the first direction and substantially does not overlap with the first active region and the second active region in a view along a direction perpendicular to a plane of the semiconductor substrate.

[0152] According to various embodiments, the conductive wire substantially overlaps with the isolation member in a view along a direction perpendicular to the plane of the semiconductor substrate. According to various embodiments, the back-side circuitry further includes a first conductive side pattern electrically connected to the conductive wire, the first conductive side pattern extending along a first direction and also extending laterally to the conductive wire along a second direction perpendicular to the first direction and parallel to the plane of the semiconductor substrate. According to various embodiments, the first conductive side pattern is electrically connected to a first conductive via. According to various embodiments, the first conductive side pattern partially overlaps with a first active region in a view along a direction perpendicular to the plane of the semiconductor substrate.

[0153] According to various embodiments, the first conductive side pattern at least partially overlaps with the first conductive via in a view along a direction perpendicular to a plane of the semiconductor substrate. According to various embodiments, the semiconductor device further includes: a first gate structure located above a first active region and extending along a second direction; a second gate structure located above a second active region extending along the second direction; and a gate isolation member disposed between the first gate structure and the second gate structure and extending along a first direction. According to various embodiments, the first conductive side pattern at least partially overlaps with the gate isolation member in a view along a direction perpendicular to a plane of the semiconductor substrate.

[0154] According to various embodiments, the semiconductor device further includes: a second conductive via extending through the semiconductor substrate and electrically connecting a wire to a second active region. According to various embodiments, the back-side circuitry further includes: a second conductive side pattern electrically connected to the wire, the second conductive side pattern extending along a first direction and also extending laterally to the wire along a second direction opposite to the first conductive side pattern. According to various embodiments, the second conductive side pattern is electrically connected to the second conductive via and overlaps with the second conductive via in a view along a direction perpendicular to a plane of the semiconductor substrate.

[0155] According to various embodiments, the second conductive side pattern partially overlaps with the second active region in a view along a direction perpendicular to the plane of the semiconductor substrate. According to various embodiments, the semiconductor device further includes a conductive connector electrically connecting the first conductive via and the second conductive via. According to various embodiments, the wire and the first conductive side pattern do not overlap with the second conductive via in a view along a direction perpendicular to the plane of the semiconductor substrate.

[0156] According to various embodiments, a semiconductor device includes: a substrate having a front side and a back side; a first active region and a second active region disposed above the front side of the substrate and extending longitudinally along a first direction; an isolation member disposed above the front side of the substrate and located between the first active region and the second active region, separating the first active region and the second active region along a second direction different from the first direction; a first gate structure and a second gate structure, the first gate structure being located above the first active region and the second gate structure being located above the second active region; and a gate isolation member disposed between the first gate structure and the second gate structure, separating the first gate structure and the second gate structure along a second direction, wherein the gate isolation member includes a first portion located above the isolation member and a second portion extending into the isolation member.

[0157] The semiconductor device further includes: a back-side circuit disposed on the back side of a substrate; a first conductive via extending through the substrate and electrically connecting the back-side circuit to a first active region; and a second conductive via extending through the substrate and electrically connecting the back-side circuit to a second active region. According to various embodiments, the back-side circuit substantially does not overlap with the first and second active regions in a view along a direction perpendicular to the plane of the substrate.

[0158] According to various embodiments, the back-side circuitry further includes: a conductor extending longitudinally along a first direction, the conductor substantially overlapping an isolation member in a view along a plane perpendicular to the substrate; a first conductive side pattern electrically connected to the conductor and extending laterally to the conductor along a second direction, and electrically connected to a first conductive via; and a second conductive side pattern electrically connected to the conductor and extending laterally to the conductor along a second direction opposite to the first conductive side pattern, and electrically connected to a second conductive via.

[0159] According to various embodiments, the semiconductor device further includes: a first conductive connector electrically connected to a first conductive via and a second conductive via. According to various embodiments, the back-side circuitry further includes: a conductor extending longitudinally along a first direction, the conductor substantially overlapping an isolation member in a view along a plane perpendicular to the substrate; and a first conductive side pattern electrically connected to the conductor and extending laterally to the conductor along a second direction, and electrically connected to the first conductive connector.

[0160] According to various embodiments, the back-side circuitry further includes: a wire extending longitudinally along a first direction, the wire substantially overlapping the isolation member in a view along a direction perpendicular to the plane of the substrate; and a second conductive connector electrically connected to the first conductive connector.

[0161] According to various embodiments, a first conductive connector extends along a second direction between a first conductive via and a second conductive via, and a second conductive connector extends along a first direction, such that the first conductive connector and the second conductive connector form a cross shape in a view along a plane perpendicular to the substrate, a wire is electrically connected to the second conductive connector, and the wire and the second conductive connector substantially do not overlap with the first active region and the second active region in a view along a plane perpendicular to the substrate.

[0162] According to various embodiments, a method of manufacturing a semiconductor device includes: performing a processing operation to form an interconnect structure on the back side of a substrate, wherein a first active region and a second active region are disposed on the front side of the substrate, wherein the first active region and the second active region extend longitudinally along a first direction and are spaced apart from each other along a second direction different from the first direction.

[0163] The processing operations include: performing a first etching operation to form a first opening in the back side of a substrate above a first source / drain component located in a first active region in a view along a direction perpendicular to the plane of the substrate, wherein the first source / drain component includes a metal silicide layer formed above an epitaxial semiconductor layer; depositing a first conductive material in the first opening to form a first conductive via extending through the substrate and the first source / drain component being electrically connected to the first conductive via; depositing a dielectric layer above the back side of the substrate and performing a second etching operation on the dielectric layer to form a trench in the dielectric layer; and depositing a second conductive material in the trench in the dielectric layer to form an interconnect structure electrically connected to the first conductive via.

[0164] According to various embodiments, the interconnect structure extends longitudinally along a first direction and substantially does not overlap with the first and second active regions in a view along a plane perpendicular to the substrate. The first source / drain component includes a thickness along a third direction different from the first and second directions, and the first source / drain component includes a width along a second direction, with the thickness being different from the width. The first conductivity of the metal silicide layer is between the second conductivity of the epitaxial semiconductor layer and the third conductivity of the first conductive via.

[0165] According to various embodiments, performing the first etching operation further includes: forming a second opening in the back side of the substrate above a second source / drain component located in the second active region; and forming a third opening spanning the first opening and the second opening. According to various embodiments, depositing the first conductive material further includes: depositing the first conductive material in the first opening to form a first conductive via and depositing the first conductive material in the second opening to form a second conductive via, the first and second conductive vias both extending through the substrate, and respectively, the first source / drain component being electrically connected to the first conductive via and the second source / drain component being electrically connected to the second conductive via; and depositing the first conductive material in the third opening to form a first conductive connector electrically connecting the first and second conductive vias.

[0166] According to various embodiments, performing the first etching operation further includes forming a fourth opening in the back side of the substrate, which is located above a portion of the third opening and extends longitudinally in a first direction, wherein the third opening extends longitudinally in a second direction such that the fourth opening intersects with the third opening and together with the third opening forms a cross shape in a view along a direction perpendicular to the plane of the substrate.

[0167] According to various embodiments, depositing the first conductive material further includes: depositing the first conductive material in the fourth opening to form a second conductive connector extending along a first direction, such that the first conductive connector and the second conductive connector form a cross shape in a view along a plane perpendicular to the substrate, such that the interconnect structure is electrically connected to the second conductive connector, and the interconnect structure and the second conductive connector substantially do not overlap with the first active region and the second active region in a view along a plane perpendicular to the substrate.

[0168] Some embodiments of this application provide a semiconductor device comprising: a semiconductor substrate having a front side and a back side opposite to the front side; a first active region and a second active region located on the front side of the semiconductor substrate and extending longitudinally along a first direction parallel to a plane of the semiconductor substrate; an isolation member located between the first active region and the second active region; a back-side circuit located on the back side of the semiconductor substrate, including a conductor in a dielectric layer; and a first conductive via extending through the semiconductor substrate and electrically connecting the conductor to the first active region, wherein the conductor extends longitudinally along the first direction and substantially does not overlap with the first active region and the second active region in a view along a direction perpendicular to the plane of the semiconductor substrate.

[0169] In some embodiments, the conductor substantially overlaps with the isolation member in the view along the direction perpendicular to the plane of the semiconductor substrate. In some embodiments, the back-side circuitry further includes a first conductive side pattern electrically connected to the conductor, extending along the first direction and also laterally to the conductor along a second direction perpendicular to the first direction and parallel to the plane of the semiconductor substrate. In some embodiments, the first conductive side pattern is electrically connected to the first conductive via. In some embodiments, the first conductive side pattern partially overlaps with the first active region in the view along the direction perpendicular to the plane of the semiconductor substrate. In some embodiments, the first conductive side pattern at least partially overlaps with the first conductive via in the view along the direction perpendicular to the plane of the semiconductor substrate. In some embodiments, the semiconductor device further includes: a first gate structure located above the first active region and extending along the second direction; a second gate structure located above the second active region extending along the second direction; and a gate isolation member located between the first gate structure and the second gate structure and extending along the first direction, wherein the first conductive side pattern at least partially overlaps the gate isolation member in the view along the direction perpendicular to the plane of the semiconductor substrate. In some embodiments, the semiconductor device further includes: a second conductive via extending through the semiconductor substrate and electrically connecting the wire to the second active region. In some embodiments, the back-side circuitry further includes: a second conductive side pattern electrically connected to the wire, and the second conductive side pattern extending along the first direction and also extending laterally to the wire along a second direction opposite to the first conductive side pattern, wherein the second conductive side pattern is electrically connected to the second conductive via and overlaps the second conductive via in the view along the direction perpendicular to the plane of the semiconductor substrate. In some embodiments, the second conductive side pattern partially overlaps the second active region in the view along the direction perpendicular to the plane of the semiconductor substrate. In some embodiments, the semiconductor device further includes a conductive connector electrically connecting the first conductive via and the second conductive via. In some embodiments, the wire and the first conductive side pattern do not overlap with the second conductive via in the view along the direction perpendicular to the plane of the semiconductor substrate.

[0170] Other embodiments of this application provide a semiconductor device, including: a substrate having a front side and a back side; a first active region and a second active region located above the front side of the substrate and extending longitudinally along a first direction; an isolation member located above the front side of the substrate and between the first active region and the second active region, and separating the first active region and the second active region along a second direction different from the first direction; a first gate structure and a second gate structure, the first gate structure being located above the first active region and the second gate structure being located above the second active region; and a gate isolation member located between the first gate structure and the second active region. The first gate structure is separated from the second gate structure along the second direction between the second gate structures, wherein the gate isolation member includes a first portion located above the isolation member and a second portion extending into the isolation member; a back-side circuit located on the back side of the substrate; a first conductive via extending through the substrate and electrically connecting the back-side circuit to the first active region; and a second conductive via extending through the substrate and electrically connecting the back-side circuit to the second active region, wherein the back-side circuit substantially does not overlap with the first active region and the second active region in a view along a direction perpendicular to the plane of the substrate.

[0171] In some embodiments, the back-side circuitry further includes: a conductor extending longitudinally along the first direction, the conductor substantially overlapping the isolation member in a view along the direction perpendicular to the plane of the substrate; a first conductive side pattern electrically connected to the conductor and extending laterally to the conductor along the second direction, and electrically connected to the first conductive via; and a second conductive side pattern electrically connected to the conductor and extending laterally to the conductor along the second direction, opposite to the first conductive side pattern, and electrically connected to the second conductive via. In some embodiments, the semiconductor device further includes: a first conductive connector electrically connecting the first conductive via and the second conductive via. In some embodiments, the back-side circuitry further includes: a conductor extending longitudinally along the first direction, the conductor substantially overlapping the isolation member in a view along the direction perpendicular to the plane of the substrate; and a first conductive side pattern electrically connected to the conductor and extending laterally to the conductor along the second direction, and electrically connected to the first conductive connector. In some embodiments, the back-side circuitry further includes: a wire extending longitudinally along the first direction, the wire substantially overlapping the isolation member in a view along the direction perpendicular to the plane of the substrate; and a second conductive connector electrically connected to the first conductive connector, wherein: the first conductive connector extends along the second direction between the first conductive via and the second conductive via; the second conductive connector extends along the first direction such that the first conductive connector and the second conductive connector form a cross shape in a view along the direction perpendicular to the plane of the substrate; the wire is electrically connected to the second conductive connector; and the wire and the second conductive connector substantially do not overlap with the first active region and the second active region in a view along the direction perpendicular to the plane of the substrate.

[0172] Further embodiments of this application provide a method for manufacturing a semiconductor device, comprising: performing a processing operation to form an interconnect structure on a back side of a substrate, wherein a first active region and a second active region are located on a front side of the substrate, wherein the first active region and the second active region extend longitudinally along a first direction and are spaced apart from each other along a second direction different from the first direction; the processing operation comprising: performing a first etching operation to form a first opening in the back side of the substrate above a first source / drain component of the first active region in a view along a direction perpendicular to a plane of the substrate, wherein the first source / drain component includes a metal silicide layer formed above an epitaxial semiconductor layer; depositing a first conductive material in the first opening to form an extension through the substrate and electrically connected to the first source. The first source / drain component has a first conductive via; a dielectric layer is deposited over the back side of the substrate, and a second etching operation is performed on the dielectric layer to form a trench in the dielectric layer; and a second conductive material is deposited in the trench in the dielectric layer to form an interconnect structure electrically connected to the first conductive via, wherein: the interconnect structure extends longitudinally along the first direction and substantially does not overlap with the first active region and the second active region in the view along the direction perpendicular to the plane of the substrate; the first source / drain component includes a thickness along a third direction and a width along the first direction and the second direction, and the thickness is different from the width; and the first conductivity of the metal silicide layer is between the second conductivity of the epitaxial semiconductor layer and the third conductivity of the first conductive via.

[0173] In some embodiments, performing the first etching operation further includes: forming a second opening in the back side of the substrate above a second source / drain component located in the second active region; and forming a third opening spanning the first opening and the second opening. Depositing the first conductive material further includes: depositing the first conductive material in the first opening to form a first conductive via and depositing the first conductive material in the second opening to form a second conductive via, both the first and second conductive vias extending through the substrate, wherein the first conductive via is electrically connected to the first source / drain component, and the second conductive via is electrically connected to the second source / drain component; and depositing the first conductive material in the third opening to form a first conductive connector electrically connecting the first and second conductive vias. In some embodiments, performing the first etching operation further includes: forming a fourth opening in the back side of the substrate, located above a portion of the third opening and extending longitudinally along the first direction, wherein the third opening extends longitudinally along the second direction such that the fourth opening intersects the third opening and, together with the third opening, forms a cross shape in the view along the direction perpendicular to the plane of the substrate; depositing the first conductive material further includes: depositing the first conductive material in the fourth opening to form a second conductive connector extending along the first direction, such that the first conductive connector and the second conductive connector form the cross shape in the view along the direction perpendicular to the plane of the substrate; and the interconnect structure is electrically connected to the second conductive connector, and the interconnect structure and the second conductive connector substantially do not overlap with the first active region and the second active region in the view along the direction perpendicular to the plane of the substrate.

[0174] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a front side and a back side opposite to the front side; The first active region and the second active region are located on the front side of the semiconductor substrate and extend longitudinally along a first direction parallel to the plane of the semiconductor substrate. An isolation component is located between the first active region and the second active region; A back-side circuit, located on the back side of the semiconductor substrate, includes wires in a dielectric layer; as well as A first conductive via extends through the semiconductor substrate and electrically connects the wire to the first active region. The wire extends longitudinally along the first direction and substantially does not overlap with the first active region and the second active region in a view along the plane perpendicular to the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein, The wire substantially overlaps with the isolation member in the view along the direction perpendicular to the plane of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein, The back-side circuit also includes: A first conductive side pattern is electrically connected to the wire, and the first conductive side pattern extends along the first direction and also extends laterally to the wire along a second direction perpendicular to the first direction and parallel to the plane of the semiconductor substrate.

4. The semiconductor device according to claim 3, wherein, The first conductive side pattern is electrically connected to the first conductive via.

5. The semiconductor device according to claim 3, wherein, The first conductive side pattern partially overlaps with the first active region in the view along the direction perpendicular to the plane of the semiconductor substrate.

6. The semiconductor device according to claim 3, wherein, The first conductive side pattern at least partially overlaps with the first conductive via in the view along the direction perpendicular to the plane of the semiconductor substrate.

7. The semiconductor device according to claim 3, further comprising: A first gate structure is located above the first active region and extends along the second direction; The second gate structure is located above the second active region extending along the second direction; as well as A gate isolation component is located between the first gate structure and the second gate structure and extends along the first direction. The first conductive side pattern at least partially overlaps with the gate isolation member in the view along the direction perpendicular to the plane of the semiconductor substrate.

8. The semiconductor device according to claim 3, further comprising: A second conductive via extends through the semiconductor substrate and electrically connects the wire to the second active region.

9. A semiconductor device, comprising: The substrate has a front side and a back side; The first active region and the second active region are located above the front side of the substrate and extend longitudinally along the first direction; An isolation component is located above the front side of the substrate and between the first active region and the second active region, and separates the first active region and the second active region along a second direction different from the first direction. A first gate structure and a second gate structure, wherein the first gate structure is located above the first active region and the second gate structure is located above the second active region; A gate isolation component is located between the first gate structure and the second gate structure, separating the first gate structure and the second gate structure along the second direction, wherein the gate isolation component includes a first portion located above the isolation component and a second portion extending into the isolation component; Back-side circuitry, located on the back side of the substrate; A first conductive via extends through the substrate and electrically connects the back-side circuitry to the first active region; and A second conductive via extends through the substrate and electrically connects the back-side circuitry to the second active region. The back-side circuitry substantially does not overlap with the first active region and the second active region in a view along a plane perpendicular to the substrate.

10. A method for manufacturing a semiconductor device, comprising: Processing operations are performed to form an interconnect structure on the back side of a substrate, on which a first active region and a second active region are located on the front side of the substrate, wherein the first active region and the second active region extend longitudinally along a first direction and are spaced apart from each other along a second direction different from the first direction. The processing operations include: performing a first etching operation to form a first opening in the back side of the substrate, located above a first source / drain component in the first active region in a view perpendicular to a plane of the substrate, wherein the first source / drain component includes a metal silicide layer formed above an epitaxial semiconductor layer; depositing a first conductive material in the first opening to form a first conductive via extending through the substrate and the first source / drain component being electrically connected to the first conductive via; depositing a dielectric layer over the back side of the substrate and performing a second etching operation on the dielectric layer to form a trench in the dielectric layer; and depositing a second conductive material in the trench in the dielectric layer to form an interconnect structure electrically connected to the first conductive via. in: The interconnect structure extends longitudinally along the first direction and substantially does not overlap with the first active region and the second active region in the view along the direction perpendicular to the plane of the substrate; The first source / drain component includes a thickness along a third direction and a width along both the first and second directions, wherein the thickness is different from the width; and The first conductivity of the metal silicide layer is between the second conductivity of the epitaxial semiconductor layer and the third conductivity of the first conductive via.

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