Power module with high-efficiency heat dissipation structure and manufacturing method thereof

Abstract

This application provides a power module with a high-efficiency heat dissipation structure and its fabrication method. The process includes cleaning and preparing the power chip and substrate, forming a gold-tin eutectic layer on the back of the power chip, aligning the gold-tin eutectic layer on the back of the power chip with the corresponding position on the substrate, and then fully melting the gold-tin eutectic layer at a eutectic temperature to tightly bond it to the substrate, completing the soldering. This application uses a method of directly forming a gold-tin eutectic layer on the back of the chip and then soldering it. Compared with traditional soldering methods, this reduces the thickness of the solder layer, thereby effectively reducing thermal resistance, further optimizing heat dissipation performance, effectively reducing the operating temperature of the power chip, and thus improving its reliability and lifespan. The high-precision eutectic soldering process ensures the accuracy and consistency of the connection, allowing the power chip to perform stably. The connection method formed by gold-tin eutectic soldering has low connection resistance, reduces heat loss during power transmission, and improves the energy utilization efficiency of the system.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a power module with a high-efficiency heat dissipation structure and its fabrication method. Background Technology

[0002] Currently, the connection between power chips and substrates mostly uses traditional soldering processes, such as tin soldering. However, power chips generate significant heat during operation, and traditional soldering methods are insufficient in heat dissipation, resulting in low heat dissipation efficiency. This limits the performance and reliability of power chips and can easily lead to overheating, potentially causing chip damage. Furthermore, for the high current transmission requirements of power chips, traditional connection methods may not provide sufficiently low resistance; higher connection resistance leads to significant power loss during transmission, reducing the overall system efficiency.

[0003] Existing bonding processes for power chips and substrates are insufficient to guarantee long-term stable connection performance when faced with the high power density requirements of power chips. Summary of the Invention

[0004] This application is made in view of the above-mentioned problems, and its purpose is to provide a power chip and substrate connection scheme to solve the problems of insufficient heat dissipation capacity, high connection resistance and poor connection accuracy and consistency in the prior art, thereby improving the working performance and reliability of the power chip.

[0005] The first aspect of this application provides a method for fabricating a power module with a high-efficiency heat dissipation structure, comprising the following steps: S1, Power Chip and Substrate Preparation First, clean the back of the power chip and the substrate separately. Use organic solvents to remove oil and impurities from the surface, then rinse with deionized water, and then blow dry with nitrogen to ensure that the back of the chip is clean and free of contamination. S2, Formation of a gold-tin eutectic layer A gold-tin eutectic layer is formed on the back of the cleaned power chip using a vapor deposition process: the power chip is placed in the vacuum chamber of the vapor deposition equipment, and the vacuum level is set to 10. -3 ~10 -4 Pa, place the gold-tin alloy material in the evaporation source, and evaporate the gold-tin alloy to deposit a uniform gold-tin eutectic layer on the back of the power chip; S3, Complete eutectic welding The gold-tin eutectic layer on the back of the power chip is aligned with the corresponding position on the substrate. Then, it is heated under a pressure of 50 to 150 Newtons until the temperature reaches the eutectic temperature of the gold-tin eutectic layer. This is maintained for 3 to 5 minutes to allow the gold-tin eutectic layer to fully melt and bond tightly to the substrate, thus completing the soldering process.

[0006] In any embodiment, the thickness of the gold-tin eutectic layer is 5 to 10 micrometers.

[0007] In any embodiment, the evaporation source temperature is 1200–1300°C, and the evaporation time is 15–20 minutes.

[0008] In any embodiment, the eutectic welding specifically includes: S21. Use a high-precision pick-and-place machine to place the prepared power chip on the corresponding position of the preheated substrate, and use the pick-and-place machine's vision recognition system to ensure that the gold-tin eutectic layer on the back of the power chip is precisely aligned with the position of the substrate; S22. Place the substrate with the chip positioned on it onto a soldering track protected by nitrogen. The soldering track consists of a preheating section, a heating section, and a cooling section. Preheating section: The substrate enters the preheating section, and under a nitrogen atmosphere, the temperature gradually rises to 180-220°C for 5-8 minutes. Excessive preheating temperature (above 220°C) can exacerbate thermal stress problems. While one purpose of preheating is to reduce welding thermal stress, excessively high preheating temperatures place the power chip and substrate in a state of high thermal expansion before welding. When the temperature is raised again during welding, the difference in their coefficients of thermal expansion leads to a further increase in final thermal stress due to the excessive initial thermal expansion. This excessive thermal stress may cause cracks at the interface between the power chip, the gold-tin eutectic layer, and the substrate, affecting the reliability of the connection and heat dissipation performance, and may even lead to connection failure during long-term use. Material property changes are also a concern. Excessively high temperatures may adversely affect the performance of the semiconductor materials inside the power chip and the gold-tin eutectic layer. For example, excessively high temperatures may alter the electrical properties of the semiconductor materials in the power chip, affecting its normal operation. The gold-tin eutectic layer may undergo premature physical or chemical changes at excessively high temperatures, altering its eutectic characteristics and affecting the bonding effect with the substrate during subsequent welding. Finally, maintaining excessively high preheating temperatures requires more energy, increasing production costs. In addition, high-temperature environments place higher demands on preheating equipment, and the maintenance costs and depreciation rates of the equipment will also increase.

[0009] If the preheating temperature is too low (below 180℃), it will lead to insufficient thermal stress relief. The main function of preheating is to reduce thermal stress during the welding process. If the preheating temperature is too low, the temperature difference between the power chip and the substrate before welding and the high temperature during welding will be too large. Under the thermal shock at the moment of welding, a large thermal stress will still be generated. This may cause microscopic defects in the connection between the power chip and the substrate, reduce the strength of the connection, affect the heat dissipation and electrical performance of the power chip, and may cause problems such as loosening of the connection in the long term.

[0010] Heating Section: After the preheating section, the substrate enters the heating section; under continuous nitrogen protection, the heating device rapidly raises the temperature of the soldering area to the eutectic temperature of the gold-tin eutectic layer, and maintains this temperature for 3-5 minutes to fully melt the gold-tin eutectic layer and bond it tightly to the substrate; under a pressure of 50-150 Newtons; if the pressure is too low during the mounting process, the eutectic effect will be reduced and the target effect cannot be achieved, while if the pressure is too high, the chip may be crushed.

[0011] Cooling section: After welding, the material is allowed to cool naturally to room temperature in a nitrogen atmosphere.

[0012] In any embodiment, the nitrogen flow rate during the preheating stage is controlled at 5–10 L / min; the nitrogen flow rate during the heating stage is 10–15 L / min; and the nitrogen flow rate during the cooling stage is 3–5 L / min.

[0013] In any embodiment, the eutectic temperature of the gold-tin eutectic layer is approximately 275–295°C.

[0014] A second aspect of this application also provides a power module with a high-efficiency heat dissipation structure, which is obtained by the above-described preparation method.

[0015] The beneficial effects of this application are: By directly forming a gold-tin eutectic layer on the back of the chip and then soldering it, the solder layer thickness is reduced compared to traditional soldering methods. This effectively lowers thermal resistance, further optimizes heat dissipation, and lowers the operating temperature of the power chip, thereby improving its reliability and lifespan. The high-precision eutectic soldering process ensures the accuracy and consistency of the connection, allowing the power chip to perform stably. The connection formed by gold-tin eutectic soldering has low connection resistance, reduces heat loss during power transmission, and improves the system's energy efficiency.

[0016] 1) Heat dissipation performance: Traditional soldering methods use solder with limited thermal conductivity and a relatively thick solder layer, resulting in high thermal resistance during heat transfer. This makes it difficult to dissipate the heat generated by the power chip quickly and effectively, leading to high chip operating temperatures. Prolonged exposure to high temperatures accelerates chip aging and reduces its performance and reliability. This application uses gold-tin eutectic (AuSn20) to form a thin eutectic layer on the entire back gold of the chip for soldering, reducing the solder layer thickness and thus lowering thermal resistance. The gold-tin eutectic material itself has relatively high thermal conductivity, enabling more efficient transfer of heat generated by the chip to the substrate, effectively reducing the chip operating temperature, significantly improving heat dissipation performance, and extending chip lifespan.

[0017] 2) Electrical Performance: Existing connection resistance is relatively high, resulting in significant power loss during power transmission and reducing the overall energy efficiency of the system. Furthermore, the difficulty in guaranteeing the precision and consistency of the welding process may lead to poor connections, affecting the stability of electrical performance. The connection method formed by gold-tin eutectic bonding in this application has lower connection resistance, reducing heat loss during power transmission and improving energy efficiency. The high-precision eutectic bonding process ensures the accuracy and consistency of the connection, resulting in more stable electrical performance and better meeting the electrical performance requirements of power chips.

[0018] 3) Process Complexity and Cost: While traditional soldering processes are relatively mature, ensuring sufficient connection strength and reliability often requires a large amount of solder and may necessitate multiple soldering operations or complex fluxing processes. This increases material costs and process complexity. Furthermore, defects such as incomplete soldering and missing solder joints can lead to higher product defect rates, further increasing production costs. The proposed solution directly forms a gold-tin eutectic layer on the back of the chip and performs soldering, resulting in a simpler process that reduces the use of additional solder sheets and lowers material costs. Although the high-precision soldering process places higher demands on equipment and operation, it improves product yield. Overall, this could potentially reduce overall costs during large-scale production.

[0019] By comparing it with existing technologies in terms of heat dissipation performance, electrical performance, process complexity and cost, it is clear that this power chip and substrate connection solution has significant advantages and can better meet the requirements of modern power chip packaging for high performance, high reliability and cost-effectiveness. Detailed Implementation

[0020] The following detailed description discloses the embodiments of the power module with high-efficiency heat dissipation structure and its fabrication method of this application. However, unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repetitive descriptions of actually identical structures may be omitted. This is to avoid making the following description unnecessarily lengthy and to facilitate understanding by those skilled in the art. Furthermore, the following description is provided to enable those skilled in the art to fully understand this application and is not intended to limit the subject matter of the claims.

[0021] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a particular range. Ranges defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, it is expected that ranges of 60-110 and 80-120 are also included. Furthermore, if minimum range values ​​of 1 and 2 are listed, and if maximum range values ​​of 3, 4, and 5 are listed, then the following ranges are all expected: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In this application, unless otherwise stated, the numerical range "ab" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0-5" indicates that all real numbers between "0-5" have been listed in this article; "0-5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is stated as an integer ≥2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0022] Unless otherwise specified, all embodiments and optional embodiments of this application can be combined to form new technical solutions.

[0023] Unless otherwise specified, all technical features and optional technical features of this application may be combined to form new technical solutions.

[0024] Unless otherwise specified, all steps in this application may be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the mention that the method may also include step (c) indicates that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0025] Unless otherwise specified, the terms "comprising" and "including" as used in this application can be open-ended or closed-ended. For example, "comprising" and "including" can mean that other components not listed may also be included, or that only the listed components may be included.

[0026] Unless otherwise specified, the term "or" is inclusive in this application. For example, the phrase "A or B" means "A, B, or both A and B". More specifically, the condition "A or B" is satisfied by any of the following conditions: A is true (or exists) and B is false (or does not exist); A is false (or does not exist) and B is true (or exists); or both A and B are true (or exist).

[0027] In one embodiment of this application, a method for fabricating a power module with a high-efficiency heat dissipation structure is proposed, comprising the following steps: S1, Power Chip and Substrate Preparation First, the back of the power chip and the substrate are cleaned separately. Organic solvents (such as acetone and alcohol) are used to remove oil and impurities from the surface, then deionized water is used to rinse them clean, and then nitrogen is used to dry them to ensure that the back of the chip is clean and free of contamination, providing a good foundation for the subsequent formation of the gold-tin eutectic layer.

[0028] S2, Formation of a gold-tin eutectic layer A gold-tin eutectic layer is formed on the back of the cleaned power chip using a vapor deposition process: the power chip is placed in the vacuum chamber of the vapor deposition equipment, and the vacuum level is set to 10. -3 ~10 -4 Pa, place gold-tin alloy (AuSn20) material in an evaporation source to evaporate the gold-tin alloy and deposit a uniform gold-tin eutectic layer on the back of the power chip.

[0029] S3, Complete eutectic welding The gold-tin eutectic layer on the back of the power chip is aligned with the corresponding position on the substrate. Then, it is heated under a pressure of 50 to 150 Newtons until the temperature reaches the eutectic temperature of gold-tin eutectic (AuSn20). The temperature is maintained for 3 to 5 minutes to allow the gold-tin eutectic layer to fully melt and bond tightly to the substrate, thus completing the soldering.

[0030] The vacuum level is set to reduce gas molecule interference. At the aforementioned vacuum level, the number of gas molecules in the vacuum chamber is extremely low. When the gold-tin alloy evaporates, the probability of gas molecules colliding with the evaporating atoms is greatly reduced, allowing gold-tin atoms to move linearly to the back of the power chip for deposition, ensuring the uniformity and purity of the gold-tin eutectic layer. If the vacuum level is insufficient (above 10), -3 Excessive gas molecules (Pa) will frequently collide with evaporating atoms, altering their motion direction and leading to uneven gold-tin atom deposition, affecting the quality of the eutectic layer. Furthermore, to avoid oxidation reactions, a lower vacuum level means a relatively higher content of oxidizing gases such as oxygen in the chamber. During high-temperature evaporation, the gold-tin alloy easily reacts with these oxidizing gases, forming oxide impurities and reducing the performance of the gold-tin eutectic layer. And 10 -3 ~10 -4A vacuum level of Pa can effectively reduce the occurrence of this oxidation reaction, ensuring that the electrical and thermal properties of the gold-tin eutectic layer are not affected.

[0031] In some embodiments, the thickness of the gold-tin eutectic layer is 5 to 10 micrometers.

[0032] A thinner gold-tin eutectic layer can significantly reduce obstacles in the heat conduction path. Existing solders typically have a thickness of 50–100 μm, while the gold-tin eutectic layer thickness in this application is controlled at 5–10 μm, greatly reducing thermal resistance. Thermal resistance is directly proportional to material thickness; a smaller thickness means easier heat conduction, allowing heat to be transferred more efficiently from the power chip to the substrate, thus improving heat dissipation efficiency. This is crucial for reducing the operating temperature of the power chip and improving its reliability and lifespan. The gold-tin eutectic material has good matching properties with the power chip and substrate in terms of coefficient of thermal expansion. An appropriate thickness helps reduce thermal stress caused by differences in thermal expansion during temperature changes. If the gold-tin eutectic layer is too thick, thermal stress accumulation may lead to problems such as cracks at the connection interface, affecting connection reliability and heat dissipation performance; if it is too thin, it may not be able to effectively buffer differences in thermal expansion. A thickness of 5–10 μm achieves a good balance in terms of thermal expansion matching.

[0033] Reduced connection resistance: The gold-tin eutectic layer itself has good conductivity, and an appropriate thickness can reduce connection resistance while ensuring electrical connection reliability. A thinner gold-tin eutectic layer can reduce electron scattering and obstruction during transmission, making current transmission smoother, reducing heat loss during power transmission, and improving the system's energy efficiency. If the gold-tin eutectic layer is too thick, although it can ensure electrical connection, it may increase unnecessary resistance; if it is too thin, it may not be able to form a good electrical path.

[0034] It is feasible to form a 5-10 micrometer thick gold-tin eutectic layer on the back of a power chip using processes such as vapor deposition or electroplating. These processes allow for relatively precise control of the gold-tin eutectic layer thickness, meeting the requirements within this range. Furthermore, this thickness is beneficial for the melting of the gold-tin eutectic layer and its tight bonding with the substrate in subsequent eutectic bonding processes.

[0035] From a cost perspective, this thickness range meets the requirements for improving power chip performance without significantly increasing costs due to the use of excessive gold-tin eutectic material. If the gold-tin eutectic layer is too thick, not only will material costs increase, but it may also place higher demands on subsequent processes, further increasing production costs.

[0036] In some embodiments, when the evaporation source temperature is 1200–1300°C and the evaporation time is 15–20 minutes, a uniform gold-tin eutectic layer with the required thickness can be obtained.

[0037] Gold-tin alloy (AuSn20) has specific melting point and evaporation characteristics. The evaporation source temperature provides sufficient energy for the gold-tin alloy to evaporate fully, depositing in gaseous form on the back of the chip to form a eutectic layer. If the temperature is below 1200℃, the gold-tin alloy may not evaporate sufficiently, resulting in a low deposition rate and difficulty in forming the required eutectic layer thickness within a reasonable time, potentially leading to uneven deposition.

[0038] A suitable evaporation rate is crucial for forming a uniform, dense gold-tin eutectic layer with the required thickness. If the temperature is too high (above 1300℃), the evaporation rate is too fast, and gold-tin atoms deposit too quickly on the back of the chip, making it difficult to form a uniform eutectic layer structure. This may lead to defects such as voids and cracks in the eutectic layer, affecting its performance.

[0039] Controlling the evaporation time allows for precise control of the thickness, which is closely related to the thickness of the gold-tin eutectic layer. Through numerous experiments under specific vacuum and evaporation source temperatures, a evaporation time of 15–20 minutes has been determined to allow for the deposition of a eutectic layer with a thickness of 5–10 micrometers on the back of the chip. If the time is too short (less than 15 minutes), the gold-tin alloy deposition will be insufficient, failing to achieve the required thickness and affecting the eutectic layer's performance in terms of heat dissipation and electrical connectivity.

[0040] Appropriate evaporation time not only controls the thickness but also ensures a stable structure of the gold-tin eutectic layer, guaranteeing structural and performance stability. Sufficient time allows gold and tin atoms ample opportunity to diffuse and align on the chip surface, forming a uniform, dense, and stable eutectic layer structure. If the evaporation time is too long (exceeding 20 minutes), although the eutectic layer thickness will increase, it may lead to excessive diffusion of gold and tin atoms, affecting the interfacial bonding between the eutectic layer and the chip, and may even alter the composition ratio of the eutectic layer, thereby affecting its performance.

[0041] In some embodiments, the eutectic welding specifically includes: S21. Use a high-precision pick-and-place machine to place the prepared power chip on the corresponding position of the preheated substrate, and use the pick-and-place machine's vision recognition system to ensure that the gold-tin eutectic layer on the back of the power chip is precisely aligned with the position of the substrate; S22. Place the substrate with the chip positioned on it onto a soldering track protected by nitrogen. The soldering track consists of a preheating section, a heating section, and a cooling section. Preheating stage: The substrate enters the preheating stage, where the temperature gradually rises to 180–220°C under a nitrogen atmosphere for 5–8 minutes. The purpose of this stage is to further homogenize the temperature of the substrate and chip, reducing sudden changes in thermal stress during subsequent heating. The preheating time includes the temperature rise process.

[0042] Heating Section: After the preheating section, the substrate enters the heating section; under continuous nitrogen protection, the heating device rapidly raises the temperature of the soldering area to the eutectic temperature of the gold-tin eutectic layer, and maintains this temperature for 3 to 5 minutes to allow the gold-tin eutectic layer to fully melt and bond tightly to the substrate; under a pressure of 50 to 150 Newtons; if the pressure is too low, the eutectic effect will be reduced and the target effect cannot be achieved, and if the pressure is too high, the chip may be crushed.

[0043] Cooling section: After welding, the chip is naturally cooled to room temperature in a nitrogen atmosphere. During the cooling process, the solidification of the gold-tin eutectic layer achieves a stable and reliable connection between the power chip and the substrate.

[0044] Excessive preheating temperature (above 220°C) exacerbates thermal stress problems. While one purpose of preheating is to reduce soldering thermal stress, excessively high preheating temperatures place the power chip and substrate in a state of high thermal expansion before soldering. When the temperature is raised again during soldering, the difference in their coefficients of thermal expansion leads to a further increase in the final thermal stress due to the excessive initial thermal expansion. This excessive thermal stress may cause cracks at the interface between the power chip, the gold-tin eutectic layer, and the substrate, affecting the reliability of the connection and heat dissipation performance, and may even lead to connection failure during long-term use.

[0045] Excessively high temperatures can adversely affect the performance of semiconductor materials and the gold-tin eutectic layer inside the power chip. For example, excessively high temperatures may alter the electrical properties of semiconductor materials in the power chip, affecting its normal operation. The gold-tin eutectic layer may undergo premature physical or chemical changes at excessively high temperatures, altering its eutectic characteristics and affecting the bonding effect with the substrate during subsequent soldering.

[0046] Maintaining excessively high preheating temperatures requires more energy, increasing production costs. Furthermore, high-temperature environments place higher demands on preheating equipment, accelerating maintenance costs and depreciation.

[0047] Insufficient preheating temperature (below 180℃) will lead to inadequate thermal stress relief. The main purpose of preheating is to reduce thermal stress during the soldering process. If the preheating temperature is too low, the temperature difference between the power chip and the substrate before soldering and the high temperature during soldering will be too large. Under the thermal shock at the moment of soldering, significant thermal stress will still be generated. This may cause microscopic defects in the connection between the power chip and the substrate, reduce the strength of the connection, affect the heat dissipation and electrical performance of the power chip, and may lead to problems such as loosening of the connection in the long term.

[0048] Soldering the gold-tin eutectic layer requires appropriate temperature conditions. If the preheating temperature is too low, the process of the gold-tin eutectic layer reaching its eutectic temperature and fully melting during the soldering heating stage will be affected. This may result in uneven melting of the gold-tin eutectic layer, leading to poor bonding with the substrate, forming defects such as voids or incomplete solder joints, severely impacting soldering quality and the thermal conductivity and electrical connection performance between the power chip and the substrate.

[0049] Insufficient preheating temperature may lead to a longer heating time required during the soldering process to compensate for the lack of preheating and ensure that the gold-tin eutectic layer fully melts and bonds well with the substrate. This not only prolongs the soldering cycle of individual products and reduces production efficiency, but may also have adverse effects on surrounding materials due to prolonged heating.

[0050] Regarding preheating time, excessive holding time (over 5 minutes) can lead to over-diffusion of the gold-tin eutectic layer at high temperatures, altering the gold-tin composition and affecting its physical and chemical properties, such as reduced electrical and thermal conductivity. For the semiconductor materials inside the power chip, prolonged high temperatures may change their electrical characteristics, affecting the normal operation of the power chip. Insufficient holding time (less than 3 minutes) results in incomplete eutectic reaction, preventing the gold-tin eutectic layer from fully melting and achieving a good metallurgical bond with the substrate. Incomplete diffusion and fusion of the gold-tin eutectic layer in some areas can lead to defects such as voids and poor solder joints at the connection interface. This severely impacts heat conduction efficiency, hindering heat dissipation from the power chip, increasing operating temperature, and also increasing connection resistance and reducing electrical connection performance. Time is closely related to bonding strength. Due to insufficient eutectic reaction, the bonding strength between the gold-tin eutectic layer and the power chip and substrate cannot reach the ideal state. During subsequent use, when subjected to external forces such as vibration and temperature changes, the connection points are prone to loosening and desoldering, affecting the stability and reliability of the power chip.

[0051] In some embodiments, the evaporation rate of the gold-tin alloy is 0.1-0.5 nm / s.

[0052] Extensive experimental research has shown that the evaporation rate is controlled within the range of 0.1-0.5 nm / s. This ensures the uniformity of the eutectic layer. Within this range, gold and tin atoms have sufficient time to diffuse and align on the power chip surface. This allows the gold-tin eutectic layer to form a uniform and dense structure, thus guaranteeing good thermal and electrical properties. If the evaporation rate is too fast, the gold and tin atoms will not have enough time to distribute evenly before rapid deposition, easily leading to defects such as uneven thickness and voids in the eutectic layer. Conversely, while a slow evaporation rate may result in a more uniform eutectic layer, it significantly prolongs the deposition time and reduces production efficiency.

[0053] Excessive evaporation rate (greater than 0.5 nm / s) leads to defects in the eutectic layer structure, resulting in numerous voids and gaps. These defects reduce the thermal conductivity of the eutectic layer, increase thermal resistance, and affect the heat dissipation of the power chip. Simultaneously, the loose structure reduces the mechanical strength of the eutectic layer, making it prone to cracking or even breakage during subsequent soldering and use, affecting connection reliability. Electrical performance deteriorates; the non-uniform eutectic layer structure causes irregular electron transport paths, increasing the probability of electron scattering and thus increasing connection resistance. Furthermore, this non-uniformity can lead to unstable electrical performance, with significant fluctuations in electrical parameters such as resistance at different locations and times, affecting the normal operation of the power chip. Insufficient evaporation rate (less than 0.1 nm / s) reduces production efficiency. A slow evaporation rate means a longer deposition time is required to achieve the desired gold-tin eutectic layer thickness. This not only increases energy consumption but also significantly reduces production efficiency and increases production costs. In large-scale production, reduced production efficiency can severely impact the product's market competitiveness. The risk of surface oxidation increases because the extended evaporation time makes it difficult to completely avoid the presence of trace amounts of oxidizing gases such as oxygen in a vacuum environment. Prolonged exposure to this environment increases the chances for the gold-tin alloy and the deposited eutectic layer surface to react with oxidizing gases, forming oxide impurities. These oxides reduce the electrical and thermal conductivity of the eutectic layer, thereby affecting the connection performance between the power chip and the substrate.

[0054] In some implementations, the nitrogen flow rate during the preheating stage is controlled at 5–10 L / min to ensure sufficient replacement of the air in the track with nitrogen and prevent oxidation. During the heating stage, the nitrogen flow rate is increased to 10–15 L / min to ensure that the gold-tin eutectic layer and substrate surface are not oxidized at high temperatures. The nitrogen flow rate during the cooling stage can be appropriately reduced to 3–5 L / min to prevent outside air from entering and affecting the solder joints during cooling.

[0055] In any embodiment, the eutectic temperature of gold-tin eutectic (AuSn20) is approximately 275–295°C.

[0056] In one embodiment of this application, a power module with a high-efficiency heat dissipation structure is proposed, which is obtained by the above-described preparation method.

[0057] Example The following describes embodiments of this application. The embodiments described below are exemplary and are only used to explain this application, and should not be construed as limiting this application. Where specific techniques or conditions are not specified in the embodiments, they are performed according to the techniques or conditions described in the literature in this field or according to the product instructions. Reagents or instruments used, unless otherwise specified, are all conventional products that can be obtained commercially.

[0058] Example 1 (1) Power chip preparation First, the back of the power chip is cleaned by using organic solvents (such as acetone and alcohol) to remove oil and impurities from the surface, then rinsing it with deionized water, and finally drying it with nitrogen gas to ensure that the back of the chip is clean and free of contamination, providing a good foundation for the subsequent formation of the gold-tin eutectic layer.

[0059] A gold-tin eutectic layer is formed on the back of the cleaned power chip using a vapor deposition process. The power chip is placed in the vacuum chamber of the vapor deposition equipment, and a suitable vacuum level is set, typically 10. -3 ~10 -4 Pa. A gold-tin alloy (AuSn20) material is placed in an evaporation source and heated to evaporate the alloy, depositing a gold-tin eutectic layer on the back of the power chip. By controlling the evaporation source temperature at 1200–1300°C and the deposition time at 15–20 minutes, the thickness of the gold-tin eutectic layer is precisely controlled between 5 and 10 micrometers, resulting in a uniform gold-tin eutectic layer with the required thickness.

[0060] (2) Substrate preparation The corresponding positions where the substrate connects to the power chip are cleaned using the same method as the cleaning method on the back of the power chip, ensuring that the substrate surface is free of impurities.

[0061] (3) Eutectic welding A high-precision pick-and-place machine is used to place the prepared power chip on the corresponding position of the preheated substrate. The visual recognition system of the pick-and-place machine ensures that the gold-tin eutectic layer on the back of the power chip is precisely aligned with the position of the substrate.

[0062] The substrate with the chip placed is then placed on a soldering track protected by nitrogen. The soldering track is divided into a preheating section, a heating section, and a cooling section. Preheating stage: The substrate enters the preheating stage, where the temperature gradually rises to 180–220°C under a nitrogen atmosphere. The purpose of this stage is to further homogenize the temperature of the substrate and chip, reducing sudden changes in thermal stress during subsequent heating. The nitrogen flow rate is controlled at 5–10 L / min to ensure that the nitrogen fully replaces the air in the track, preventing oxidation. The preheating time is maintained at 5–8 minutes.

[0063] Heating Section: After the preheating section, the substrate enters the heating section. Under continuous nitrogen protection, the heating device rapidly raises the temperature of the soldering area to approximately 280°C, the eutectic temperature of gold-tin eutectic (AuSn20), and maintains this temperature for 3–5 minutes to ensure that the gold-tin eutectic layer fully melts and bonds tightly to the substrate. The nitrogen flow rate is increased to 10–15 L / min to ensure that the gold-tin eutectic layer and the substrate surface are not oxidized at high temperatures.

[0064] Cooling Section: After soldering, the substrate enters the cooling section. It is naturally cooled to room temperature in a nitrogen atmosphere. During cooling, the solidification of the gold-tin eutectic layer ensures a stable and reliable connection between the power chip and the substrate. The nitrogen flow rate can be appropriately reduced to 3–5 L / min to prevent outside air from entering and affecting the solder joints during cooling.

[0065] Comparative Example 1 (Electroplating method for forming a gold-tin eutectic layer) Chip pretreatment: Similar to the present invention, the back of the power chip is cleaned by using organic solvents to remove oil and impurities, rinsing with deionized water and then drying with nitrogen.

[0066] Electroplating process: The cleaned chip is immersed in an electroplating solution containing gold and tin ions. By adjusting parameters such as current density and electroplating time, a gold-tin eutectic layer is formed on the back of the chip. The electroplating conditions are controlled to make the thickness of the gold-tin eutectic layer as close as possible to the 5-10 micrometers of the present invention.

[0067] Subsequent soldering: Using the same eutectic soldering process as the present invention, the chip with the gold-tin eutectic layer is soldered to the substrate.

[0068] Performance comparison: Uniformity: Scanning electron microscopy (SEM) revealed that the uniformity of the electroplated gold-tin eutectic layer in terms of microstructure was slightly inferior to that of the eutectic layer formed by vapor deposition in this invention. The vapor deposition process allows gold and tin atoms to be deposited uniformly in a gaseous state, while during electroplating, factors such as the distribution of the electric field on the chip surface may cause thickness differences in local areas of the eutectic layer.

[0069] Thermal resistance: In the thermal resistance test, the sample with the electroplated gold-tin eutectic layer had a thermal resistance that was about 10% higher than the sample with the vapor-deposited layer of this invention. This is because the inhomogeneity of the microstructure hinders the heat conduction path to some extent, reducing the heat dissipation efficiency.

[0070] Connection resistance: Connection resistance tests showed that the resistance of the electroplated sample was slightly higher than that of the vapor-deposited sample of this invention, by about 8%. The non-uniform eutectic layer structure affected the smoothness of electron transport, resulting in increased resistance.

[0071] Comparative Example 2 (formation of gold-tin eutectic layer by sputtering) Chip preparation: Similarly, the back of the power chip is cleaned first.

[0072] Sputtering process: In a sputtering device, an ion beam is used to bombard a gold-tin target, causing gold-tin atoms to be sputtered onto the back of the chip to form a eutectic layer. By controlling parameters such as sputtering time and power, the thickness of the gold-tin eutectic layer can reach the range of 5-10 micrometers.

[0073] Welding operation: The subsequent eutectic welding process is the same as that of this invention.

[0074] Performance comparison: Bonding strength: The bonding strength between the gold-tin eutectic layer and the chip was evaluated through tensile testing. It was found that the bonding strength of the sputtered eutectic layer was lower than that of the vapor-deposited eutectic layer of this invention. The higher deposition energy of atoms during sputtering may cause localized damage to the chip surface, affecting the bonding force. In the tensile test, the average breaking tensile force of the sputtered sample was approximately 15% lower than that of the vapor-deposited sample of this invention.

[0075] Electrical performance stability: Long-term electrical performance monitoring of the samples revealed significant resistance fluctuations in the samples with sputtered gold-tin eutectic layers. This is likely due to the accumulation of stress within the eutectic layer during sputtering; as time and temperature change, stress release leads to subtle structural alterations in the eutectic layer, thus affecting electrical performance stability. In contrast, the samples deposited using this invention exhibited smaller resistance fluctuations and more stable performance.

[0076] II. Comparison with different welding track parameter settings Comparative Example 3 (Preheating section temperature too high) Chip and substrate preparation: Similar to the present invention, the power chip and substrate are cleaned, and a gold-tin eutectic layer is deposited on the back of the chip.

[0077] Welding process: In the welding track settings, the preheating section temperature is set to 250℃, which is higher than the 180-220℃ range of this invention. Other parameters such as nitrogen flow rate and preheating time remain unchanged. The parameters of the heating and cooling sections are consistent with those of this invention.

[0078] Performance comparison: Thermal stress damage: Microscopic observation of the chip-substrate interface after soldering revealed numerous microcracks in samples with excessively high preheating temperatures. Excessive preheating temperatures placed the chip and substrate in a state of high thermal expansion before soldering, further increasing thermal stress during the soldering process and leading to interface cracking. In contrast, samples within the preheating temperature range of this invention exhibited significantly fewer microcracks.

[0079] Long-term reliability: Accelerated aging tests were conducted on the samples to simulate long-term use. It was found that samples with excessively high preheating temperatures exhibited performance degradation within a short period, such as increased thermal resistance and connection resistance. This is because the presence of microcracks accelerated the deterioration of the connection structure, reducing long-term reliability. In contrast, the samples of this invention maintained more stable performance under the same aging test conditions.

[0080] Comparative Example 4 (Nitrogen flow rate in heating section is too low) Preliminary preparation: The power chip and substrate are processed in accordance with the present invention, and a gold-tin eutectic layer is deposited by vapor deposition.

[0081] Welding process: The parameters of the preheating and cooling sections of the welding track are consistent with those of this invention, but the nitrogen flow rate in the heating section is set to 5L / min, which is lower than the range of 10-15L / min of this invention.

[0082] Performance comparison: Oxidation level: Compositional analysis of the gold-tin eutectic layer surface after welding revealed a significant increase in oxide content in samples with excessively low nitrogen flow rates in the heating section. Lower nitrogen flow rates fail to effectively prevent oxygen from contacting the gold-tin eutectic layer at high temperatures, leading to accelerated oxidation. Samples with suitable nitrogen flow rates, as described in this invention, exhibited lower oxidation levels.

[0083] Connection performance: Due to the presence of the oxide layer, the connection resistance of this sample is increased, and the thermal resistance also rises slightly. Connection resistance tests show that its resistance is about 12% higher than that of the sample of this invention, and the thermal resistance is about 8% higher. The oxide layer hinders electron transport and heat conduction, thus reducing connection performance.

[0084] Performance experiments of the power chip and substrate connection schemes in the embodiments and comparative examples. I. Experimental proof of improved heat dissipation efficiency 1. Experimental setup: 1. Sample selection: Two groups of power chip and substrate samples of the same specifications were selected, with 10 samples in each group. The first group used a traditional soldering process to connect the power chip and substrate as a control group, and the second group used the gold-tin eutectic bonding scheme of the present invention as an experimental group.

[0085] 2. Test environment: The sample is placed in a test chamber that simulates the actual working environment. The ambient temperature is maintained at 25℃ and the humidity at 50%. The ventilation conditions in the chamber are stable to ensure that the experiment is not affected by external environmental factors.

[0086] 3. Loading conditions: Apply the same power load to both groups of samples, setting the power to 500W, to simulate the heat generation of the power chip under high load operation.

[0087] 2. Experimental procedure: 1. After power is applied to the power chip, the temperature distribution on the surface of the power chip is measured every minute using a high-precision infrared thermal imager, and the temperature value at the center of the chip is recorded. Measurements are continued for 30 minutes to obtain temperature change data of the power chip under stable operating conditions.

[0088] 3. Experimental Results: 1. After 30 minutes of continuous measurement, the average stable temperature at the center of the control group power chip reached 120℃, while the average stable temperature at the center of the experimental group power chip was only 90℃.

[0089] 2. According to the thermal resistance calculation formula Rth = (Tj Tj) / P (where Tj is the chip junction temperature, Tc is the substrate temperature, and P is the power), under the same power load P=500W, the steady-state thermal resistance Rth(j) of the control group c) is approximately ℃, while the steady-state thermal resistance Rth(j) of the experimental group c) The temperature was reduced to approximately ℃, a decrease of approximately 25% compared to the control group. This indicates that the connection scheme of the present invention can significantly improve heat dissipation efficiency and effectively reduce the operating temperature of the power chip.

[0090] II. Experimental proof of decreased resistance 1. Experimental setup: 1. Sample preparation: Prepare two groups of 10 power chip and substrate samples with different connection schemes. One group is the control group with traditional solder connection, and the other group is the experimental group with gold-tin eutectic connection.

[0091] 2. Testing Instruments: A four-probe tester is used to accurately measure the connection resistance to ensure the accuracy of the measurement results.

[0092] 3. Test conditions: The measurement should be performed at room temperature of 25℃ to avoid the influence of temperature on the resistance measurement results.

[0093] 2. Experimental procedure: 1. Place the probes of the four-probe tester accurately on the connection point between the power chip and the substrate. Measure each sample 5 times and take the average value as the connection resistance value of that sample.

[0094] 3. Experimental Results: 1. The average connection resistance of the control group samples was 50 mΩ, while the average connection resistance of the experimental group samples was only 30 mΩ. This indicates that the gold-tin eutectic connection scheme of the present invention can effectively reduce connection resistance, reduce heat loss during power transmission, and improve the energy utilization efficiency of the system.

[0095] III. Experimental Demonstration of Improved Connection Accuracy and Consistency Performance 1. Experimental setup: 1. Sample fabrication: Fabricate 20 power chip and substrate samples using the connection scheme of this invention and 20 samples using conventional soldering processes.

[0096] 2. Measurement equipment: A high-precision electron microscope and image analysis software are used to observe and analyze the microstructure of the connection parts, and a coordinate measuring machine is used to measure the positional accuracy of the power chip on the substrate.

[0097] 2. Experimental procedure: 1. Microstructure analysis: The microstructure of the connection area is observed by electron microscopy to analyze the bonding between the gold-tin eutectic layer and the substrate and power chip. The focus is on whether there are defects such as voids and cracks, and the number and area of ​​defects are counted using image analysis software.

[0098] 2. Position Accuracy Measurement: A coordinate measuring machine (CMM) is used to measure the positional deviation of the power chip on the substrate to evaluate the connection accuracy. The position coordinates of the four corners of each sample chip are measured, and the deviation from the designed position is calculated.

[0099] 3. Experimental Results: 1. Microstructure: In samples using traditional welding processes, an average of 5 voids were found per sample, with the total void area accounting for 5% of the connection area; while in samples using the connection scheme of this invention, an average of only 1 void was found per sample, with the total void area accounting for 1% of the connection area. This indicates that the connection scheme of this invention has higher integrity in microstructure and reduces the risk of performance degradation due to defects.

[0100] 2. Regarding positional accuracy: The average positional deviation of power chips in samples using traditional welding processes is ±0.05mm, while the average positional deviation of power chips in samples using the connection scheme of this invention is only ±0.01mm. This fully demonstrates that the high-precision eutectic welding process of this invention ensures high precision and consistency in the connection, enabling the power chip to perform stably.

[0101] It should be noted that this application is not limited to the above-described embodiments. The above embodiments are merely examples, and any embodiments with the same structure and effect as the technical concept within the scope of this application are included in the technical scope of this application. Furthermore, various modifications that can be conceived by those skilled in the art to the embodiments, and other ways of constructing by combining some of the constituent elements of the embodiments, without departing from the spirit of this application, are also included in the scope of this application.

Claims

1. A method for fabricating a power module with a high-efficiency heat dissipation structure, characterized in that, Includes the following steps: S1, Power Chip and Substrate Preparation The back sides of the power chip and the substrate are cleaned separately. S2, Formation of a gold-tin eutectic layer A gold-tin eutectic layer is formed on the back of the cleaned power chip using a vapor deposition process: the power chip is placed in the vacuum chamber of the vapor deposition equipment, and the vacuum level is set to 10. -3 ~10 -4 Pa, place the gold-tin alloy material in the evaporation source, and evaporate the gold-tin alloy to deposit a uniform gold-tin eutectic layer on the back of the power chip; S3, Complete eutectic welding The gold-tin eutectic layer on the back of the power chip is aligned with the corresponding position on the substrate. Then, it is heated under a pressure of 50 to 150 Newtons until the temperature reaches the eutectic temperature of the gold-tin eutectic layer. This is maintained for 3 to 5 minutes to allow the gold-tin eutectic layer to fully melt and bond tightly to the substrate, thus completing the soldering process.

2. The method for fabricating a power module with a high-efficiency heat dissipation structure according to claim 1, characterized in that, The thickness of the gold-tin eutectic layer is 5 to 10 micrometers.

3. The method for fabricating a power module with a high-efficiency heat dissipation structure according to claim 1, characterized in that, The evaporation source temperature is 1200-1300℃, and the evaporation time is 15-20 minutes.

4. The method for fabricating a power module with a high-efficiency heat dissipation structure according to claim 1, characterized in that, The eutectic welding specifically includes: S21. Use a high-precision pick-and-place machine to place the prepared power chip on the corresponding position of the preheated substrate, and use the pick-and-place machine's vision recognition system to ensure that the gold-tin eutectic layer on the back of the power chip is precisely aligned with the position of the substrate; S22. Place the substrate with the chip on it onto a welding track protected by nitrogen. The welding track is divided into a preheating section, a heating section, and a cooling section. Preheating section: The substrate enters the preheating section, and under a nitrogen atmosphere, the temperature gradually rises to 180-220°C for 5-8 minutes. Heating section: After the preheating section, the substrate enters the heating section; under continuous nitrogen protection, the heating device rapidly raises the temperature of the welding area to the eutectic temperature of the gold-tin eutectic layer, and maintains this temperature for 3 to 5 minutes, so that the gold-tin eutectic layer can be fully melted and tightly bonded to the substrate; under a pressure of 50 to 150 Newtons; Cooling section: After welding, the material is allowed to cool naturally to room temperature in a nitrogen atmosphere.

5. A method for fabricating a power module with a high-efficiency heat dissipation structure according to claim 1 or 4, characterized in that, The evaporation rate of the gold-tin alloy is 0.1-0.5 nm / s.

6. The method for fabricating a power module with a high-efficiency heat dissipation structure according to claim 4, characterized in that, The nitrogen flow rate during the preheating stage is controlled at 5–10 L / min; the nitrogen flow rate during the heating stage is 10–15 L / min; and the nitrogen flow rate during the cooling stage is 3–5 L / min.

7. A method for fabricating a power module with a high-efficiency heat dissipation structure according to claim 1 or 4, characterized in that, The eutectic temperature of the gold-tin eutectic layer is 275–295℃.

8. A power module with a high-efficiency heat dissipation structure, obtained by the preparation method described in any one of claims 1 to 7.