Wafer dies and integrated circuit assemblies

Abstract

This disclosure provides a wafer die and an integrated circuit assembly. The wafer die includes multiple functional modules, each functional module including a controller and a physical interface. The controller is used to perform logical processing on data in its respective functional module, and the physical interface is used to perform data transmission processing on its respective functional module. A predetermined interval is formed between at least two adjacent functional modules in the extending direction of the wafer die, and the extending direction is perpendicular to the thickness direction of the wafer die.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more particularly to a wafer die and an integrated circuit assembly. Background Technology

[0002] With the rapid development of fields such as 5G terminals and high-performance computing (HPC), the demand for high-speed signals is increasing. In integrated circuit components composed of bare wafers, the application of high-speed signals leads to increased power consumption, which in turn increases the risk of heat dissipation of the bare wafers.

[0003] Currently, air cooling, liquid cooling plates, and immersion liquid cooling are commonly used to reduce the temperature of bare wafers to address the heat dissipation risks caused by increased power consumption. However, the problems of concentrated power density and uneven heat distribution on bare wafers still exist. Therefore, an efficient method to improve the heat dissipation reliability of bare wafers is needed. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a wafer die and an integrated circuit assembly to at least solve or alleviate the above-mentioned problems.

[0005] According to a first aspect of the present disclosure, a wafer die is provided, comprising: a plurality of functional modules, each functional module including a controller and a physical interface, the controller being used to perform logical processing on data in its respective functional module, and the physical interface being used to perform transmission processing on data in its respective functional module; wherein, in the extending direction of the wafer die, at least two adjacent functional modules among the plurality of functional modules are formed with a preset interval, and the extending direction is perpendicular to the thickness direction of the wafer die.

[0006] According to a second aspect of the present disclosure, an integrated circuit assembly is provided, comprising: a multilayer wafer die arranged in a vertically stacked manner, wherein each wafer die is configured as a wafer die according to the first aspect.

[0007] In the scheme of this embodiment, the controller is used to perform logical processing on the data in the functional module, which generates the power consumption of the functional module. At least two adjacent functional modules are separated by a preset interval, which reduces the power consumption concentration between at least two adjacent functional modules, reduces the thermal non-uniformity of the wafer and the thermal stress caused by the thermal non-uniformity, and thus improves the heat dissipation reliability while ensuring the processing performance of the wafer. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0009] Figure 1 Schematic structural diagrams of integrated circuit components for some examples of this disclosure.

[0010] Figure 2A and Figure 2B Schematic structural diagrams of some example wafer dies.

[0011] Figure 3 This is a schematic structural diagram of a wafer bare die according to some embodiments of the present disclosure.

[0012] Figures 4A-4D According to Figure 3 Schematic structural diagrams of wafer dies for some examples of embodiments.

[0013] Figure 5A and Figure 5B According to Figure 3 Schematic structural diagrams of wafer dies for some examples of embodiments.

[0014] Figure 6A and Figure 6B According to Figure 3 Schematic structural diagrams of wafer dies for some other examples of embodiments.

[0015] Figure 7 This is a schematic structural diagram of an integrated circuit component for some other embodiments of this disclosure.

[0016] Figure 8A According to Figure 7 Schematic structural diagrams of integrated circuit components for some examples of embodiments.

[0017] Figure 8B According to Figure 7 Schematic structural diagrams of integrated circuit components for other examples of embodiments.

[0018] Figure 9 According to Figure 7 Schematic structural diagrams of integrated circuit components for other examples of embodiments.

[0019] Figure 10 According to Figure 7 Schematic structural diagrams of integrated circuit components for other examples of embodiments. Detailed Implementation

[0020] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0021] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0022] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0023] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0024] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0025] Figure 1 Schematic diagrams of some integrated circuit components according to embodiments of this disclosure are shown. For example... Figure 1As shown, in some examples, the integrated circuit assembly 100 includes a wafer die (DIE) 110, a packaging substrate 120, and a heat sink 130. Alternatively, the wafer die 110 can be vertically stacked to form a 3D wafer package structure. 3D wafer packaging, as an advanced packaging solution, enables the packaging of vertically stacked wafer dies. In 3D wafer packaging, connections between different wafer dies are achieved through bonding methods such as through-silicon vias (TSVs) fabricated on the wafer layers and hybrid bonding or metal bonding.

[0026] Specifically, the wafer die 110 is an integrated circuit (IC) chip and includes a substrate 102 and a device layer 105. The substrate 102 is a semiconductor substrate such as a silicon substrate. The device layer 105 may include active devices such as transistors and passive devices such as capacitors. In some examples, the device layer 105 may also be referred to as an active device layer or an active layer. In some examples, the device layer 105 may include functional and non-functional regions. The functional regions include multiple functional modules of the wafer die. The functional modules may include at least one of a controller and a physical interface (PHY, also referred to as a physical layer). The controller can be used to perform logical processing on data in its functional module, and the physical interface can be used to perform data transmission processing on its functional module. The non-functional regions include at least one metal layer between the functional modules. Conductive bumps 115 are disposed on the side of the device layer 105 away from the substrate 102 to provide electrical connections between the wafer die 110 and the package substrate 120. The packaging substrate 120 has a plurality of conductive bumps 125 on the side opposite to the wafer die 110 for external connection of the integrated circuit assembly 100.

[0027] Furthermore, the heat sink 130 is mounted on the packaging substrate 120 and attached to the substrate 102 of the wafer die 110 via a thermal interface material (TIM) layer 135 for heat dissipation of the wafer die 110. For example, the heat from the wafer die 10 is conducted along a direction perpendicular to the main surface of the substrate 102 to the thermal interface material 135, then conducted through the thermal interface material 135 to the heat sink 130, and finally dissipated outward through the heat sink 130.

[0028] In some examples, adjacent functional modules are connected together or spaced very closely together for wiring within the wafer die, for example, in Figure 2A In the various examples of the wafer dies shown, functional module 10 includes a controller 20 and a physical interface 30. For example, in... Figure 2BIn the example, adjacent physical interfaces 30 are located within the controller 20. Therefore, functional modules closer to the center experience higher temperatures, leading to power density concentration and thermal unevenness issues on the wafer.

[0029] To address the issues of concentrated power density and uneven thermal distribution on wafer dies, the junction temperature of the wafer dies or integrated circuit components can be reduced to below a safe range by optimizing the system's heat dissipation scheme. For example, the upper temperature limit of the wafer dies can be lowered by reducing the operating clock frequency of functional modules located at areas of high power density.

[0030] However, if integrated circuit components composed of wafer dies operate under a large and uneven temperature distribution for a long time, it will further cause uneven local stress distribution on the wafer dies. Especially in 3D packaging, such uneven stress distribution on multi-layer wafer dies will introduce greater thermal stress risks.

[0031] In some examples, temperature sensors can be used to monitor and report the real-time temperature of different locations on the wafer. When the temperature difference between different real-time temperatures approaches the set upper limit of the temperature difference, the operating clock frequency of at least some functional modules is reduced by software, which leads to the inability to guarantee the processing performance of integrated circuit components.

[0032] This disclosure provides several embodiments that can reduce thermal non-uniformity in wafer dies and integrated circuit components while ensuring the processing performance of wafer dies, thereby improving the heat dissipation reliability of wafer dies and integrated circuit components.

[0033] Figure 3 Wafer dies representing some embodiments of this disclosure are shown. Specifically, in Figure 3 In some embodiments, the wafer layer in the wafer die 300 has an extension plane, and the extension direction of the wafer die 300 can be any direction on the extension plane of the wafer layer. The extension direction of the wafer die 300 is perpendicular to the thickness direction of the wafer die 300. When the wafer die 300 is stacked into an integrated circuit assembly such as a 3D wafer package structure, the thickness direction of the wafer die 300 can be consistent with the wafer stacking direction of the integrated circuit assembly. The wafer die 300 includes multiple functional modules 10, and in some examples, the wafer die 300 can be... Figure 1 The wafer die 110. Each functional module 10 includes a controller 20 and a physical interface 30.

[0034] It should be understood that the controller 20 and the physical interface 30 are two core components of the functional module 10 in the wafer die 300. The controller 20 is responsible for processing the data logic within the module, ensuring the accuracy and validity of the data, while the physical interface 30 is responsible for transmitting this data to other modules or external devices through physical connections. In the wafer die 300, the controller 20 and the physical interface 30 work together to enable each functional module 10 to complete its design tasks efficiently and accurately.

[0035] Furthermore, the controller 20 is used to perform logical processing on the data in its respective functional module 10, and the physical interface 30 is used to transmit the data in its respective functional module 10. In the wafer die 300, the controller 20 can be configured with computing and storage capabilities, and the design of the physical interface 30 needs to consider transmission speed, signal integrity, compatibility, and possible interference issues to ensure the reliability and efficiency of data transmission.

[0036] Furthermore, in the extension direction of the wafer die 300, a preset interval is formed between at least two adjacent functional modules 10 of the plurality of functional modules 10.

[0037] It should be understood that the preset spacing allows each functional module 10 space for heat dissipation, signal transmission, and maintenance. Besides improving the heat dissipation performance of the functional modules, the preset spacing also reduces electrical interference between modules, improving the overall system stability and reliability. Furthermore, this layout facilitates the partitioning of the wafer dies 300 during production, allowing each functional module 10 to be tested and packaged independently.

[0038] It should be understood that the preset interval can be used to set up wiring between adjacent functional modules, or passive components can be added within the preset interval. This ensures both heat dissipation reliability and the compactness or electrical performance of the functional modules. For example, decoupling capacitors can be installed in the preset interval between adjacent functional modules. These decoupling capacitors are connected in parallel between the power supply and ground terminals of the wafer die, improving both the heat dissipation reliability of the wafer die and the power supply reliability of the functional modules.

[0039] More specifically, the wafer forming the bare die includes a substrate and at least one metal layer. The at least one metal layer is disposed on the substrate, and the controllers for multiple functional modules are configured on the substrate. The physical interfaces of the multiple functional modules are connected to the at least one metal layer. In other words, the electrical connection between functional modules is achieved through at least one metal layer in the wafer, which is compatible with the wafer bare die processing technology framework to a certain extent.

[0040] In the scheme of this embodiment, the controller is used to perform logical processing on the data in the functional module, which generates the power consumption of the functional module. At least two adjacent functional modules are separated by a preset interval, which reduces the power consumption concentration between at least two adjacent functional modules, reduces the thermal non-uniformity of the wafer and the thermal stress caused by the thermal non-uniformity, and thus improves the heat dissipation reliability while ensuring the processing performance of the wafer.

[0041] In some embodiments, in the extension direction of the wafer die, the preset interval between any adjacent functional modules among the plurality of functional modules has the same spacing value, thereby greatly reducing thermal non-uniformity in the extension direction of the wafer die and reducing thermal stress at various locations on the wafer die. For example, in Figure 4A In the example, the spacing between different functional modules is L1. When all preset intervals have equal spacing values, the total spacing value = L1 * N, where N is the number of preset intervals. Additionally, decoupling capacitors can be included in the preset spacing between adjacent functional modules.

[0042] In other embodiments, multiple functional modules form multiple module groups, each module group including at least two functional modules. The spacing between adjacent module groups is greater than the spacing between adjacent functional modules within each module group. That is, within each module group, the connection methods between functional modules can be compatible, improving wiring flexibility. Figures 4B-4D In each of the examples, each module group includes at least two functional modules close together, for example, with a spacing value approximately zero. Figure 4B In the example, multiple functional modules are divided into 4 module groups, with a spacing of L2 between adjacent module groups. Figure 4C In the example, multiple functional modules are divided into 3 module groups, with a spacing of L3 between adjacent module groups. Figure 4D In the example, multiple functional modules are divided into two module groups, with a spacing of L4 between adjacent module groups. Additionally, decoupling capacitors can be included in the preset spacing between adjacent functional modules.

[0043] Without loss of generality, when the spacing value L is equal, the total spacing value = L*N + ∑l, where N represents the number of module group spacings, l represents the sum of the spacings of functional modules within each module group, and ∑l represents the sum of the spacings of each functional module within N+1 module groups.

[0044] In some examples, the number of at least two functional modules within each module group is the same. For example, in Figure 4B In the example, each module group includes two functional modules. For example, in... Figure 4DIn the example, each module group includes four functional modules. Having at least two functional modules in each module group of the same number can improve the design efficiency of the functional modules to some extent, and further reduce thermal non-uniformity in the wafer die's extension direction and improve heat dissipation efficiency.

[0045] In other embodiments, the preset intervals between adjacent functional modules have different spacing values. Specifically, in the extending direction of the wafer die, the spacing value of functional modules adjacent to the edge of the wafer die is smaller than the spacing value of functional modules adjacent to the center of the wafer die. That is, the heat dissipation efficiency of functional modules adjacent to the edge of the wafer die is higher than that of functional modules adjacent to the center of the wafer die, thereby further improving the heat dissipation efficiency of the wafer die while maintaining its structural compactness.

[0046] In other embodiments, the preset intervals between adjacent functional modules have different spacing values. These functional modules include computing modules and storage modules, with the spacing between adjacent storage modules being smaller than that between adjacent computing modules. In other words, the heat dissipation requirements at locations adjacent to storage modules are less than those at locations adjacent to computing modules, thereby further improving the heat dissipation efficiency of the wafer while maintaining the structural compactness of the wafer.

[0047] In other embodiments, increasing the spacing value can reduce the upper temperature limit of the required operating temperature range and the temperature difference between the upper and lower temperature limits (i.e., thermal non-uniformity), thus improving the heat dissipation reliability of the wafer die. Furthermore, decreasing the spacing can improve the structural compactness of the wafer die. In other words, appropriately selecting the spacing value between functional modules can balance the structural compactness and heat dissipation reliability of the wafer die.

[0048] For example, Table 1 shows an exemplary comparison between the spacing parameters and operating temperature parameters between functional modules in different examples of wafer dies.

[0049] Table 1

[0050]

[0051] It should be understood that the examples in Table 1 are highly illustrative examples and should not be construed as limiting the combination and scope of protection of the various embodiments of this disclosure. The interval type indicates the distribution between the preset intervals, for example, whether it is a balanced distribution with equal interval values ​​or a non-balanced distribution with unequal interval values; the interval value indicates the interval distance of the preset intervals, represented by a numerical value; the upper temperature limit indicates the upper limit of the actual operating temperature range of the wafer die, which can be used to adjust the interval parameters for the upper temperature limit of the wafer die's operating temperature requirement range; the temperature difference indicates the actual operating temperature range of the wafer die, which can be used to adjust the interval parameters for the wafer die's operating temperature requirement range; the temperature difference comparison indicates the degree of thermal non-uniformity of the wafer die, with a smaller temperature difference comparison value indicating a lower degree of thermal non-uniformity.

[0052] In some examples, the total spacing value and / or the number of spacings and / or the spacing value can be set according to the operating temperature requirement range of the wafer die. Based on the examples shown in Table 1, without loss of generality, when the preset spacing between any adjacent functional modules has the same spacing value, the spacing value is determined according to the operating temperature requirement range of the wafer die, wherein the upper temperature limit of the operating temperature requirement range is inversely correlated with the spacing value, and the temperature difference between the upper and lower temperature limits of the operating temperature requirement range is inversely correlated with the spacing value. For example, in Figure 5A In the example shown (i.e., the reference example in Table 1), the preset interval between adjacent functional modules is less than [missing information]. Figure 5B The preset interval between adjacent functional modules in the examples (i.e., Examples 1-3 in Table 1).

[0053] Furthermore, as shown in Table 1, the total spacing value of the preset interval between each adjacent functional module can be determined based on the operating temperature requirement range of the wafer die. The upper temperature limit of the operating temperature requirement range is inversely correlated with the total spacing value, and the temperature difference between the upper and lower temperature limits of the operating temperature requirement range is also inversely correlated with the total spacing value. In other words, increasing the total spacing value can reduce the upper temperature limit of the operating temperature requirement range and the temperature difference between the upper and lower temperature limits, thus improving the heat dissipation reliability of the wafer die. Additionally, a smaller total spacing value results in a higher structural compactness of the wafer die. Therefore, by appropriately selecting the total spacing value, a balance is struck between the structural compactness and heat dissipation reliability of the wafer die.

[0054] Furthermore, as shown in Table 1, the number of preset intervals between adjacent functional modules is further determined based on the operating temperature requirement range of the wafer. The upper limit of the operating temperature requirement range is inversely correlated with the number of preset intervals, and the temperature difference between the upper and lower limits of the operating temperature requirement range is also inversely correlated with the number of preset intervals. In other words, the larger the number of preset intervals between adjacent functional modules, the smaller the thermal non-uniformity of each functional module and the higher the heat dissipation reliability.

[0055] Given a given number of preset intervals and a given total spacing value, the upper limit of the operating temperature requirement range when the spacing values ​​of the preset intervals are different is less than the upper limit of the operating temperature requirement range when the spacing values ​​of the preset intervals are the same. Similarly, the temperature difference of the wafer when the spacing values ​​of the preset intervals are different is less than the temperature difference of the wafer when the spacing values ​​of the preset intervals are the same. For example, in... Figure 5B In the example (i.e., Example 3 in Table 1), the 10 functional modules are not divided into 5 module groups, the number of preset intervals is 9, and the preset interval spacing values ​​are the same; Figure 6A In the example (i.e., Example 4 in Table 1), the number of preset intervals is 9, and the 10 functional modules are divided into 5 module groups, forming 4 module group intervals and 5 intra-group intervals, with different spacing values ​​for each preset interval; Figure 6B In the example (i.e., Example 5 in Table 1), the 10 functional modules are not divided into 5 module groups, the number of preset intervals is 9, and the spacing value of each preset interval is different.

[0056] In some examples, given a total spacing value for the preset intervals between adjacent functional modules, the preset intervals between any two adjacent functional modules can have different spacing values. In some examples, the spacing value between adjacent storage modules is smaller than the spacing value between adjacent computing modules, and the heat dissipation requirements at the location of adjacent storage modules are less than those at the location of adjacent computing modules, thereby improving the heat dissipation efficiency of the wafer while maintaining the structural compactness of the wafer. In other examples, the spacing value between functional modules adjacent to the edge of the wafer is smaller than the spacing value between functional modules adjacent to the center of the wafer, and the heat dissipation efficiency of functional modules adjacent to the edge of the wafer is higher than that of functional modules adjacent to the center of the wafer, thus further improving the heat dissipation efficiency of the wafer while maintaining the structural compactness of the wafer.

[0057] It should be understood that in all the above embodiments, decoupling capacitors can be provided in the preset spacing between adjacent functional modules. The decoupling capacitors are connected in parallel between the power supply terminal and the ground terminal of the wafer die, which improves the heat dissipation reliability of the wafer die and also improves the power supply reliability of the functional modules.

[0058] Figure 7 Integrated circuit components according to other embodiments of this disclosure are illustrated. Integrated circuit component 700 includes a multilayer wafer die 300. Exemplarily, integrated circuit component 700 may be... Figure 1 The integrated circuit assembly 100. Multilayer wafer dies 300 are configured to be vertically stacked to form a 3D wafer package. In some examples, the wafer extension direction of the wafer die 300 can be any direction on the extension plane of the wafer layers in the wafer die 300, and the wafer extension direction can be perpendicular to the stacking direction of the multilayer wafer dies in the integrated circuit assembly; that is, the thickness direction of the wafer die 300 can be consistent with the stacking direction.

[0059] Furthermore, in the integrated circuit assembly 700, functional modules located on different wafers in the multilayer wafer assembly are connected via through-hole wiring on the inner wafer. That is, the connection between different wafers 300 is achieved by fabricating through-silicon vias (TSVs) on the wafer layer and by bonding methods such as hybrid bonding or metal bonding.

[0060] In the embodiments of this disclosure, a preset interval is formed between at least two adjacent functional modules in each layer of wafer dies. This reduces power concentration between the at least two adjacent functional modules, reduces thermal non-uniformity of the wafer dies, and reduces thermal stress caused by thermal non-uniformity, thereby improving heat dissipation reliability while ensuring the processing performance of the wafer dies. When multiple wafer dies are arranged in a vertically stacked configuration, heat dissipation reliability is improved while ensuring the processing performance of integrated circuit components.

[0061] In other embodiments, corresponding functional modules in adjacent wafers along the stacking direction of the multilayer wafer dies are staggered along the wafer extension direction, which is perpendicular to the stacking direction of the multilayer wafer dies. For example, in adjacent wafers, a functional module of one wafer corresponds to a predetermined interval in an upper or lower adjacent wafer. That is, by staggering the corresponding functional modules in adjacent wafers, the power concentration along the stacking direction of the multilayer wafer dies is reduced, maintaining the heat dissipation reliability within the wafer dies while also improving the heat dissipation reliability between different wafers.

[0062] For example, such as Figure 8A , Figure 8B , Figure 9 and Figure 10As shown, die DIE#2 (an example of a wafer die) is stacked between die DIE#1 (an example of an upper adjacent die) and die DIE#3 (an example of a lower adjacent die). The functional modules of die DIE#1 correspond to the spacing of DIE#2, and the functional modules of die DIE#2 correspond to the spacing of die DIE#3. Furthermore, the functional modules of die DIE#1 can also correspond to the functional modules of DIE#3, thereby improving the compactness of the functional modules of the integrated circuit assembly.

[0063] In some examples, to ensure the structural compactness of functional modules in integrated circuit components, the staggered distance between corresponding functional modules in adjacent wafer dies does not exceed the spacing between adjacent preset intervals. For example, in Figure 8A and Figure 8B In the example, the offset distance between corresponding functional modules in adjacent wafer dies does not exceed the spacing between adjacent preset intervals (i.e., the width of a functional module in the wafer extension direction). Figure 9 and Figure 10 In the example, the stagger distance between corresponding functional modules in adjacent wafer dies does not exceed the spacing between adjacent preset intervals (i.e., the width of a module group in the wafer extension direction).

[0064] In other embodiments, in a multilayer wafer die, each wafer layer has an extension plane, and the wafer extension direction of each wafer layer can be any direction on the extension plane of that wafer layer. Further, the wafer extension direction of the inner wafer layer includes a first wafer extension direction and a second wafer extension direction. The corresponding functional modules of the inner wafer layer and the adjacent upper wafer layer are offset along the first wafer extension direction, and the corresponding functional modules of the inner wafer layer and the adjacent lower wafer layer are offset along the second wafer extension direction. It should be understood that the first wafer extension direction and the second wafer extension direction mentioned herein are both any directions on the extension plane of the wafer layer in the inner wafer layer, and the first wafer extension direction and the second wafer extension direction can be the same or different.

[0065] Furthermore, in some examples, the extension direction of the first wafer can be the same as or opposite to the extension direction of the second wafer. For example, in Figure 8A and Figure 9 In one example, the extension direction of the first wafer is opposite to that of the extension direction of the second wafer. For example, in other examples, in... Figure 8B and Figure 10 In the example, the extension direction of the first wafer is the same as that of the second wafer.

[0066] In other embodiments, Table 2 shows exemplary comparisons between spacing parameters and operating temperature parameters between functional modules in different examples of integrated circuit components.

[0067] Table 2

[0068]

[0069] It should be understood that the examples in Table 2 are provided as highly illustrative examples and should not be construed as limiting the combination and scope of protection of the various embodiments of this disclosure. Specifically, the stacking type indicates the stacking method of adjacent wafer dies in the wafer extension direction, such as overlapping or staggered stacking; the spacing type indicates the distribution of preset spacings within the wafer dies, such as a balanced distribution with equal spacing values ​​or a non-balanced distribution with unequal spacing values; the spacing value indicates the spacing distance of the preset spacing, expressed numerically; the upper temperature limit indicates the upper limit of the actual operating temperature range of the integrated circuit component, which can be used to adjust the spacing parameters according to the upper temperature limit of the operating temperature requirement range of the integrated circuit component; the temperature difference indicates the actual operating temperature range of the integrated circuit component, which can be used to adjust the spacing parameters according to the operating temperature requirement range of the integrated circuit component; and the temperature difference comparison indicates the degree of thermal non-uniformity of the integrated circuit component, with a smaller temperature difference comparison value indicating a lower degree of thermal non-uniformity.

[0070] As can be seen from the examples shown in Table 2, without loss of generality, for a given spacing value between functional modules in a wafer die, compared to overlapping functional modules along the wafer extension direction, staggering the corresponding functional modules in adjacent wafer dies along the wafer extension direction in the stacking direction of multilayer wafer dies can achieve a lower upper temperature limit and a smaller temperature difference.

[0071] Furthermore, each wafer in an integrated circuit assembly can be made like... Figure 3 The wafer dies described in various embodiments are as follows. In each of the above embodiments, a decoupling capacitor can be provided in the preset spacing between adjacent functional modules. The decoupling capacitor is connected in parallel between the power supply terminal and the ground terminal of the wafer dies, which improves the heat dissipation reliability of the wafer dies and also improves the power supply reliability of the functional modules.

[0072] In other embodiments, in the extension direction of the wafer die, the preset interval between any adjacent functional modules among the plurality of functional modules has the same spacing value.

[0073] In other embodiments, the spacing value is determined based on the operating temperature requirement range of the wafer die, wherein the upper temperature limit of the operating temperature requirement range is inversely correlated with the spacing value, and the temperature difference between the upper and lower temperature limits of the operating temperature requirement range is inversely correlated with the spacing value.

[0074] In other embodiments, the preset interval between each adjacent functional module has different spacing values, wherein, in the extension direction of the wafer die, the spacing value of the functional modules adjacent to the edge of the wafer die is smaller than the spacing value of the functional modules adjacent to the center of the wafer die.

[0075] In other embodiments, the preset intervals between adjacent functional modules have different spacing values, wherein the plurality of functional modules include a computing module and a storage module, and the spacing value of the adjacent storage module is smaller than the spacing value of the adjacent computing module.

[0076] In other embodiments, the total spacing value of the preset interval between each adjacent functional module is determined according to the operating temperature requirement range of the wafer die, wherein the upper temperature limit of the operating temperature requirement range is inversely correlated with the total spacing value, and the temperature difference between the upper temperature limit and the lower temperature limit of the operating temperature requirement range is inversely correlated with the total spacing value.

[0077] In other embodiments, the number of preset intervals between adjacent functional modules is further determined based on the operating temperature requirement range of the wafer, wherein the upper temperature limit of the operating temperature requirement range is inversely correlated with the number of preset intervals, and the temperature difference between the upper and lower temperature limits of the operating temperature requirement range is inversely correlated with the number of preset intervals.

[0078] In other embodiments, the plurality of functional modules form a plurality of module groups, each module group including at least two functional modules, and the interval between adjacent module groups is greater than the interval between adjacent functional modules within each module group.

[0079] In other embodiments, the number of at least two functional modules within each module group is the same.

[0080] In other embodiments, a decoupling capacitor is provided in the preset spacing between adjacent functional modules, wherein the decoupling capacitor is connected in parallel between the power supply terminal and the ground terminal of the wafer die.

[0081] In other embodiments, the wafer forming the wafer die includes a substrate and at least one metal layer disposed on the substrate, a controller for each of the plurality of functional modules is configured on the substrate, and a physical interface of each of the plurality of functional modules is connected to the at least one metal layer.

[0082] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0083] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0084] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0085] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A wafer bare die, comprising: Multiple functional modules, each including a controller and a physical interface, wherein the controller is used to perform logical processing on the data in its respective functional module, and the physical interface is used to perform data transmission processing on its respective functional module; In the extending direction of the wafer, at least two adjacent functional modules among the plurality of functional modules are separated by a preset interval, wherein the extending direction is perpendicular to the thickness direction of the wafer.

2. The wafer bare die according to claim 1, wherein, In the extending direction of the wafer, the preset interval between any adjacent functional modules among the plurality of functional modules has the same spacing value.

3. The wafer bare die according to claim 2, wherein, The spacing value is determined based on the operating temperature requirement range of the wafer die, wherein the upper temperature limit of the operating temperature requirement range is inversely correlated with the spacing value, and the temperature difference between the upper and lower temperature limits of the operating temperature requirement range is inversely correlated with the spacing value.

4. The wafer bare die according to claim 1, wherein, The preset intervals between adjacent functional modules have different spacing values. In the extension direction of the wafer die, the spacing value of the functional modules adjacent to the edge of the wafer die is smaller than the spacing value of the functional modules adjacent to the center of the wafer die.

5. The wafer bare die according to claim 1, wherein, The preset intervals between each adjacent functional module have different spacing values. The multiple functional modules include a computing module and a storage module, and the spacing value of the adjacent storage module is smaller than the spacing value of the adjacent computing module.

6. The wafer bare die according to claim 1, wherein, The total spacing value of the preset interval between each adjacent functional module is determined according to the operating temperature requirement range of the wafer die. The upper temperature limit of the operating temperature requirement range is inversely correlated with the total spacing value, and the temperature difference between the upper temperature limit and the lower temperature limit of the operating temperature requirement range is inversely correlated with the total spacing value.

7. The wafer bare die according to claim 6, wherein, The number of preset intervals between adjacent functional modules is further determined based on the operating temperature requirement range of the wafer. The upper temperature limit of the operating temperature requirement range is inversely correlated with the number of preset intervals, and the temperature difference between the upper and lower temperature limits of the operating temperature requirement range is inversely correlated with the number of preset intervals.

8. The wafer bare die according to claim 1, wherein, The multiple functional modules form multiple module groups, and each module group includes at least two functional modules. The spacing between adjacent module groups is greater than the spacing between adjacent functional modules within each module group.

9. The wafer bare die according to claim 8, wherein, At least two functional modules within each module group must have the same number of modules.

10. The wafer bare die according to claim 1, wherein, A decoupling capacitor is provided in the preset spacing between adjacent functional modules, wherein the decoupling capacitor is connected in parallel between the power supply terminal and the ground terminal of the wafer die.

11. The wafer bare die according to claim 10, wherein, The wafer forming the wafer includes a substrate and at least one metal layer disposed on the substrate, the controllers of the plurality of functional modules are configured on the substrate, and the physical interfaces of the plurality of functional modules are connected to the at least one metal layer.

12. An integrated circuit component, comprising: A multilayer wafer dies, wherein the multilayer wafer dies are arranged in a vertically stacked manner, wherein each layer of wafer dies is configured as a wafer dies according to any one of claims 1-11.

13. The integrated circuit assembly according to claim 12, wherein, The corresponding functional modules in adjacent wafers in the stacking direction of the multilayer wafer dies are staggered along the wafer extension direction, wherein the wafer extension direction is perpendicular to the stacking direction of the multilayer wafer dies.

14. The integrated circuit assembly according to claim 13, wherein, In the multilayer wafer dies, the corresponding functional modules of the inner layer wafer dies and the adjacent upper layer wafers are staggered along the first wafer extension direction, and the corresponding functional modules of the inner layer wafer dies and the adjacent lower layer wafers are staggered along the second wafer extension direction.

15. The integrated circuit assembly according to claim 12, wherein, The functional modules located on different wafers in the multilayer wafer dies are connected via through-hole wiring on the inner wafer dies.

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