Method for manufacturing a wiring substrate

Abstract

This invention provides a method for manufacturing a wiring substrate, resulting in a wiring substrate of good quality. The method for manufacturing a wiring substrate according to an embodiment includes the following steps: preparing a core substrate (100); forming a first laminate (10); forming a second laminate (20); and dividing a laminate (1P) comprising the core substrate (100), the first laminate (10), and the second laminate (20) along a dividing line (BD). The method for manufacturing a wiring substrate further includes the following steps: forming a first metal layer (ML1) and a second metal layer (ML2) in contact with the core substrate (100). The step of dividing the laminate (1P) includes the following steps: forming a first trench (GB1) and a second trench (GB2); cutting the bottom of the first trench (GB1) and the bottom of the second trench (GB2) along the dividing line (BD); the first metal layer (ML1) and the second metal layer (ML2) are formed of a metal different from the material of the conductors exposed on the first surface (1F) and the second surface (1S).

Description

Technical Field

[0001] This invention relates to a method for manufacturing a wiring substrate. Background Technology

[0002] Patent Document 1 discloses a method for monolithically converting a wiring substrate, on which wiring layers and insulating layers are stacked on both sides (two core surfaces) of a core substrate, into a packaging substrate. In the disclosed method, a separation groove is formed by removing a portion of the insulating layer by laser irradiation, and the core substrate is cut from the bottom of the separation groove by a cutting blade. Wiring layers are formed in contact with both sides of the core substrate, and peripheral patterns containing the same material as the wiring layers are formed at positions on both sides of the core substrate corresponding to the positions where the separation grooves are formed.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2018-110150

[0004] In the method disclosed in Patent Document 1, the peripheral pattern exposed at the bottom of the formed separation trench is dissolved and removed by etching. In the disclosed method, the same material (copper) is included in the wiring layer and the peripheral pattern. When the peripheral pattern is dissolved and removed, the wiring layer exposed on the outermost layer of the wiring substrate is sometimes affected by etching, and the surface quality of the outermost wiring layer may be reduced. Summary of the Invention

[0005] The method for manufacturing a wiring substrate according to the present invention includes the following steps: preparing a core substrate having one side and another side opposite to the one side; forming a first laminate portion on the one side, the first laminate portion including a first insulating layer and a first conductor layer, the first laminate portion having a first side opposite to the core substrate; forming a second laminate portion on the other side, the second laminate portion including a second insulating layer and a second conductor layer, the second laminate portion having a second side opposite to the core substrate; and dividing a laminate including the core substrate, the first laminate portion and the second laminate portion into a plurality of wiring substrates along a dividing line. The method for manufacturing the wiring substrate further includes the following steps: forming a first metal layer in contact with one surface and a second metal layer in contact with the other surface at a position overlapping the dividing line when viewed from above; the step of dividing the laminate includes the following steps: forming a first groove extending from the first surface through the first laminate portion and a second groove extending from the second surface through the second laminate portion at a position overlapping the dividing line when viewed from above; and cutting between the bottom of the first groove portion and the bottom of the second groove portion along the dividing line, wherein the first metal layer and the second metal layer are formed of a metal different from the material of the conductor exposed on the first surface and the conductor exposed on the second surface.

[0006] According to an embodiment of the present invention, the first metal layer and the second metal layer are formed of a metal of a different material than the conductor exposed on the first side and the conductor exposed on the second side of the wiring substrate. Therefore, it is possible to suppress the degradation of the surface quality of the conductor exposed on the first side or the second side. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing an example of a wiring substrate manufactured by the wiring substrate manufacturing method according to an embodiment of the present invention.

[0008] Figure 2A This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

[0009] Figure 2B This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

[0010] Figure 2C This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

[0011] Figure 2D This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

[0012] Figure 3A This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

[0013] Figure 3B This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

[0014] Figure 3C This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

[0015] Figure 3D This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment.

[0016] Figure 4A This is a cross-sectional view illustrating another example of a method for manufacturing a wiring substrate according to an embodiment.

[0017] Figure 4B This is a cross-sectional view illustrating another example of a method for manufacturing a wiring substrate according to an embodiment.

[0018] Figure 5A This is a cross-sectional view illustrating another example of a method for manufacturing a wiring substrate according to an embodiment.

[0019] Figure 5B This is a cross-sectional view illustrating another example of a method for manufacturing a wiring substrate according to an embodiment.

[0020] Label Explanation

[0021] 1, 1a, 1b: Wiring substrate; 10: First stacked layer; 20: Second stacked layer; 11: Insulating layer (first insulating layer); 21: Insulating layer (second insulating layer); 12: Conductor layer (first conductor layer); 22: Conductor layer (second conductor layer); 13: Via conductor (first via conductor); 23: Via conductor (second via conductor); 100: Core substrate; 101: Through conductor; 12fp: Conductor pad; 22sp: Conductor pad; 10BP, 20BP: Conductor protrusions; 1F: First surface; 1S: Second surface; BA: Wiring substrate forming area; BD: Divider line; DB: Cutting blade; GB1: First groove; GB2: Second groove; ML1: First metal layer; ML2: Second metal layer. Detailed Implementation

[0022] A method for manufacturing a wiring substrate according to an embodiment of the present invention will be described with reference to the accompanying drawings. Figure 1 A cross-sectional view of wiring substrate 1 is shown as an example of a wiring substrate manufactured by the wiring substrate manufacturing method of the embodiment. However, wiring substrate 1 is merely one example of a wiring substrate manufactured by the manufacturing method of the embodiment. For example, the laminated structure of the manufactured wiring substrate and the number of conductor layers and insulating layers included in the wiring substrate are sometimes different from those of the other three types of wiring substrates. Figure 1 The layered structure of the wiring substrate 1 and the number of conductor layers and insulating layers included in the wiring substrate 1 are different. In addition, in the figures referred to in the following description, certain parts are sometimes depicted in enlarged form for easy understanding of the disclosed embodiments, and the structural elements are sometimes not depicted in precise proportions to each other regarding size and length.

[0023] The wiring substrate 1 is composed of a core substrate 100 and stacked layers 10 and 20. The stacked layers 10 and 20 are composed of insulating layers and conductor layers alternately stacked on both sides of the core substrate 100. The wiring substrate 1 has a first surface 1F and a second surface 1S on the side opposite to the first surface 1F as two main surfaces perpendicular to its thickness direction.

[0024] The wiring substrate 1 includes a core substrate 100 having one surface 100f and another surface 100s opposite to the one surface 100f. A first insulating layer 11 and a first conductor layer 12 are alternately stacked on one surface 100f of the core substrate 100 to form a first stacked portion 10. A second insulating layer 21 and a second conductor layer 22 are alternately stacked on the other surface 100s of the core substrate 100 to form a second stacked portion 20.

[0025] Furthermore, regarding the description of the wiring substrate manufactured by the wiring substrate manufacturing method of the embodiment, in the description of the structural elements of the wiring substrate 1, the side closest to the core substrate 100 is referred to as "lower," "inner," or "lower side," and the side furthest from the core substrate 100 is referred to as "upper," "outer," or "upper side," and "outer side." The surface of each element constituting the wiring substrate 1 facing the core substrate 100 is also referred to as the "lower surface," and the surface facing the side opposite to the core substrate 100 is also referred to as the "upper surface."

[0026] A through conductor 101 extending through the core substrate 100 in the thickness direction is formed therein. A first via conductor 13 is formed in the first insulating layer 11 constituting the first stacked portion 10. The first via conductor 13 extends through the first insulating layer 11 in the thickness direction and connects conductors (first conductor layers 12 to each other or first conductor layer 12 and through conductor 101) that are separated by the first insulating layer 11. A second via conductor 23 is formed in the second insulating layer 21 constituting the second stacked portion 20. The second via conductor 23 extends through the second insulating layer 21 in the thickness direction and connects conductors (second conductor layers 22 to each other or second conductor layer 22 and through conductor 101) that are separated by the second insulating layer 21.

[0027] The through conductor 101 is formed by filling a through hole 101a formed in the core substrate 100 with a conductive material. In the illustrated example, the end face of the through conductor 101 in the extending direction is formed to be substantially coplanar with the surface of the core substrate 100, constituting one surface 100f and another surface 100s of the core substrate 100. The first via conductor 13 is formed by filling a through hole 13a formed in the first insulating layer 11 with a conductive material. The first via conductor 13 is integrally formed with the first conductor layer 12, which is in contact with the surface of the first insulating layer 11 through which the first via conductor 13 penetrates, opposite to the core substrate 100. The second via conductor 23 is formed by filling a through hole 23a formed in the second insulating layer 21 with a conductive material. The second via conductor 23 is integrally formed with the second conductor layer 22, which is in contact with the surface of the second insulating layer 21 through which the second via conductor 23 penetrates, opposite to the core substrate 100.

[0028] The core substrate included in the wiring substrate manufactured by the manufacturing method of the embodiment can be a glass substrate. The core substrate 100 of the wiring substrate 1 shown in the figure is formed using a glass substrate. The glass material used as the glass substrate constituting the core substrate 100 can be, for example, soda lime glass, borosilicate glass, or alkali-free glass. These glasses can contain elements such as magnesium, calcium, manganese, aluminum, lead, iron, chromium, potassium, sulfur, antimony, and boron as additives. In addition, the core substrate included in the wiring substrate is sometimes also a substrate containing materials other than glass, such as a silicon substrate, a ceramic substrate, or a resin substrate.

[0029] The first insulating layer 11 and the second insulating layer 21 are formed using any insulating resin. Examples of insulating resins include thermosetting resins such as epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin, as well as thermoplastic resins such as fluoropolymers, liquid crystal polymers (LCP), fluorinated vinyl ester (PTFE) resin, polyester (PE) resin, and modified polyimide (MPI) resin. The first insulating layer 11 and the second insulating layer 21 may contain inorganic fillers (not shown) such as silica or alumina. The first insulating layer 11 and the second insulating layer 21 may also contain reinforcing materials (core materials) such as glass fiber or aramid fiber.

[0030] Examples of conductors constituting the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, and the through conductor 101 include copper and nickel, with copper being preferred. Figure 1 In the example shown, the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, and the through conductor 101 are each shown as a single layer, but they can be constructed in a multilayer structure. For example, the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, and the through conductor 101 can have a multilayer structure including any one of a metal foil layer (preferably copper foil), a metal film layer (preferably a copper film formed by chemical plating or sputtering), and a plating film layer (preferably an electroplated copper film). For example, the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, and the through conductor 101 can have a two-layer structure including a metal film layer and a plating film layer.

[0031] Each conductor layer (first conductor layer 12, second conductor layer 22) constituting the wiring substrate 1 is patterned with a predetermined conductor pattern. The first conductor layer 12 constituting the first surface 1F of the wiring substrate 1 is formed with a pattern having a plurality of conductor pads 12fp. The second conductor layer 22 constituting the second surface 1S of the wiring substrate 1 is formed with a pattern having a plurality of conductor pads 22sp.

[0032] The first laminate portion 10 constituting the wiring substrate 1 has a solder resist layer 10Rf formed, for example, using a photosensitive polyimide resin or epoxy resin, on its outermost side. An opening 10Rfa is formed in the solder resist layer 10Rf, through which a conductor pad 12fp is exposed. That is, the first surface 1F of the wiring substrate 1 includes the surface of the solder resist layer 10Rf and the surface of the conductor pad 12fp exposed from the opening 10Rfa. The second laminate portion 20 constituting the wiring substrate 1 has a solder resist layer 20Rs formed, for example, using a photosensitive polyimide resin or epoxy resin, on its outermost side. An opening 20Rsa is formed in the solder resist layer 20Rs, through which a conductor pad 22sp is exposed. That is, the second surface 1S of the wiring substrate 1 includes the surface of the solder resist layer 20Rs and the surface of the conductor pad 22sp exposed from the opening 20Rsa.

[0033] For example, a plating layer containing nickel and tin layers can be formed on the surfaces of the conductor pad 12fp exposed from the opening 10Rfa of the solder resist layer 10Rf and the conductor pad 22sp exposed from the opening 20Rsa of the solder resist layer 20Rs. Additionally, as shown in the figure, sometimes a conductor bump 10BP, indicated by a double-dotted line in the figure, connected to the conductor pad 12fp, is formed within the opening 10Rfa of the solder resist layer 10Rf. Sometimes a conductor bump 20BP, indicated by a double-dotted line in the figure, connected to the conductor pad 22sp, is formed within the opening 120Rsa of the solder resist layer 20Rs. The conductor bumps 10BP and 20BP can be, for example, solder bumps containing tin, copper, or nickel. Therefore, when the wiring substrate 1 includes conductor bumps 10BP and 20BP, the conductors exposed on the first surface 1F and the second surface 1S of the wiring substrate 1 can be, for example, copper, nickel, tin, or silver.

[0034] In the illustrated example, the first surface 1F of the wiring substrate 1 is configured as a component mounting surface for connecting external electronic components. The conductor pads 12fp (in the case of formation, conductor protrusions 10BP) constituting the first surface 1F can connect with the connection pads of external electronic components during the use of the wiring substrate 1. The second surface 1S of the wiring substrate 1 can be a connection surface for connecting with external substrates, for example, when the wiring substrate 1 is mounted on an external substrate that serves as the motherboard of any electrical device. During the use of the wiring substrate 1, the conductor pads 22sp (in the case of formation, conductor protrusions 20BP) constituting the second surface 1S can connect with the connection pads of external substrates.

[0035] As will be described in detail later, the single wiring substrate 1 in the illustrated example is formed by dividing and monolithizing a laminate containing multiple wiring substrates 1 into individual wiring substrates 1. The side extending in the thickness direction of the wiring substrate 1 is the surface exposed by monolithizing the laminate into individual wiring substrates 1. Furthermore, in top view, each wiring substrate 1 has a rectangular shape, and in the aforementioned laminate, the multiple wiring substrates 1 are connected in a lattice pattern. Here, "top view" refers to viewing the object from a line of sight parallel to the thickness direction of the wiring substrate 1.

[0036] As detailed below, in the process of dividing a laminate containing multiple wiring substrates 1 into individual wiring substrates 1, a groove is formed along the dividing line that passes through the first stacking portion 10 in the thickness direction and exposes a metal layer on one surface 100f at the bottom, and a groove is formed that passes through the second stacking portion 20 in the thickness direction and exposes a metal layer on another surface 100s at the bottom. The metal layer exposed at the bottom of the formed groove is removed by etching, and the exposed surface 100f and the other surface 100s are cut off along the dividing line. The metal layer is formed of a different metal than the conductors (conductor pads 12fp, 22sp or conductor protrusions 10BP, 20BP) exposed on the surface of the laminate (i.e., the surface of the wiring substrate 1). Therefore, the etching process for removing the metal layer has little impact on the conductors exposed on the surface of the laminate. Thus, the wiring substrate 1 is manufactured as a high-quality wiring substrate that suppresses the degradation of the surface quality of the exposed conductors. Furthermore, in the illustration, the metal portion ML located above one surface 100f and another surface 100s and exposed on the side of the wiring substrate 1 is the portion of the aforementioned metal layer that is not exposed at the bottom of the trench (i.e., the portion that was not removed by etching).

[0037] Next, refer to Figures 2A to 2D , Figures 3A to 3D , Figures 4A-4B as well as Figures 5A-5B This section describes a method for manufacturing a wiring substrate according to an embodiment. First, referring to... Figures 2A to 2D as well as Figures 3A to 3D This indicates the manufacturing process. Figure 1 The example shown is of the wiring substrate 1. Furthermore, the structural elements formed in the wiring substrate manufacturing method described below can be used in [the following text is incomplete and requires further context]. Figure 1 The material used as the material for the corresponding structural element in the description of the wiring substrate 1 is formed. Furthermore, in the following, the referenced... Figures 2A to 5B The text does not depict the metal film layer and the coated film layer, which are structural elements of each conductor layer. Figure 1 Similarly, each conductor layer is depicted as a single layer.

[0038] The method for manufacturing a wiring substrate according to the embodiment includes the following steps: preparing a core substrate having one side and another side; forming a first laminate portion on one side; forming a second laminate portion on the other side; and dividing a laminate containing the core substrate, the first laminate portion, and the second laminate portion into a plurality of wiring substrates along a dividing line. Here, "laminate" refers to a laminate in which a plurality of wiring substrates, which are to be monolithically connected by division, are joined together. First, refer to... Figures 2A to 2D The formation of the layered structure is explained.

[0039] like Figure 2A As shown, a core substrate 100 is prepared. For example, a core substrate 100 is prepared on a glass substrate 100P containing soda lime glass, borosilicate glass or alkali-free glass, etc., on which a through conductor 101 is formed.

[0040] The core substrate 100 includes multiple wiring substrate forming regions BA corresponding to the multiple wiring substrates 1 to be manufactured. In addition, an example is shown in which the core substrate 100 includes a glass substrate 100P, but in the preparation of the core substrate 100, a silicon substrate, a ceramic substrate, or a resin substrate may be used instead of the glass substrate 100P.

[0041] Next, as Figure 2B As shown, a first metal layer ML1 is formed that contacts one side 100f of the core substrate 100, and a second metal layer ML2 is formed that contacts the other side 100s of the core substrate 100. The first metal layer ML1 and the second metal layer ML2 are formed at the boundary with the wiring substrate forming region BA when viewed from above (i.e., referring to...). Figures 3A to 3D The overlapping position of the dividing lines (BD) in the process of dividing the laminated body described later. The first metal layer ML1 and the second metal layer ML2 are formed covering the entire periphery of the rectangular wiring substrate forming area BA when viewed from above. The first metal layer ML1 and the second metal layer ML2 are formed by referring to the implementation reference. Figure 3B The process described later (etch-based removal of the first metal layer ML1 and the second metal layer ML2) exposes different metallic materials on the surfaces (first and second surfaces) of the laminate.

[0042] The first metal layer ML1 and the second metal layer ML2 formed are not conducive to the transmission of electrical signals in the use of the manufactured wiring substrate, and also do not function as power or ground layers. In the described example, the first conductor layer 12 constituting the first stacked portion 10 is not formed on one surface 100f of the core substrate 100, and no conductors other than the first metal layer ML1 are formed. Furthermore, the second conductor layer 22 constituting the second stacked portion 20 is not formed on the other surface 100s, and no conductors other than the second metal layer ML2 are formed (see reference). Figure 1 ).

[0043] Specifically, the first metal layer ML1 extends across a surface 100f, and is consistent with the reference surface. Figure 3A The region corresponding to the area GBA1 where the groove GB1 is formed in the process of dividing the laminated body described later is formed. The second metal layer ML2 is formed throughout the region corresponding to the area GBA2 where the groove GB2 is formed on the other side 100s. The first metal layer ML1 and the second metal layer ML2 can be formed by forming a resist with an opening on the surface of the core substrate 100, forming a metal layer in the opening by chemical vapor deposition (e.g., CVD) or physical vapor deposition (e.g., sputtering), and then removing the resist. The first metal layer ML1 and the second metal layer ML2 can be formed, for example, as a single layer of aluminum or titanium, or as a multilayer composed of two or more different metal layers or alloy layers such as titanium and copper. The first metal layer ML1 and the second metal layer ML2 can be formed, for example, with a thickness of 10 nm or more and 10 μm or less, preferably with a thickness of 50 nm or more and 100 nm or less.

[0044] Next, as Figure 2C As shown, a first insulating layer 11 is stacked covering one surface 100f of the core substrate 100, and then an innermost first conductor layer 12 is formed on the first insulating layer 11. A first via conductor 13 is integrally formed with the first conductor layer 12 while the first conductor layer 12 is being formed. The first insulating layer 11 is stacked across multiple wiring substrate forming regions BA, and the first conductor layer 12 and the first via conductor 13 are formed in the multiple wiring substrate forming regions BA. A second insulating layer 21 is formed covering the other surface 100s of the core substrate 100, and then an innermost second conductor layer 22 is formed on the second insulating layer 21. A second via conductor 23 is integrally formed with the second conductor layer 22 while the second conductor layer 22 is being formed. The second insulating layer 21 is stacked across multiple wiring substrate forming regions BA, and the second conductor layer 22 and the second via conductor 23 are formed in the multiple wiring substrate forming regions BA.

[0045] In the illustrated example, the first conductor layer 12 is formed without contact with one surface 100f, and the second conductor layer 22 is formed without contact with another surface 100s. Specifically, the innermost first conductor layer 12 is formed with a first insulating layer 11 spaced apart from one surface 100f (i.e., away from one surface 100f), and the innermost second conductor layer 22 is formed with a second insulating layer 21 spaced apart from another surface 100s (i.e., away from another surface 100s). The first conductor layer 12 can be formed to have a thickness greater than that of the first metal layer ML1. The second conductor layer 22 can be formed to have a thickness greater than that of the second metal layer ML2. The thicknesses of the formed first conductor layer 12 and second conductor layer 22 are, for example, 1 μm or more and 30 μm or less. Furthermore, as described above, when the first conductor layer 12 and the second conductor layer 22 have a two-layer structure comprising a metal film layer and a plating film layer, the metal film layer can function as a power supply layer for the plating film layer. In this case, the thickness of the power supply layer (metal film layer) is, for example, 150 nm to 400 nm. The first metal layer ML1 and the second metal layer ML2 can be formed to have a thickness smaller than the thickness of the metal film layer contained in the first conductor layer 12 and the thickness of the metal film layer contained in the second conductor layer 22.

[0046] The first insulating layer 11 and the second insulating layer 21 can be formed by thermally bonding a film-like insulating resin (e.g., epoxy resin) to the surface (one side 100f and the other side 100s) of the core substrate 100. A through-hole 13a is formed at the location in the first insulating layer 11 where the first via conductor 13 is to be formed, for example, by irradiation with a carbon dioxide laser. A first conductor layer 12 and the first via conductor 13 are formed by forming a metal film (not shown) on the inner surface of the through-hole 13a and the upper surface of the first insulating layer 11 using chemical plating or sputtering, and by forming a plating film (not shown) using an anti-plating agent with appropriate openings and by electroplating using the metal film as a power supply layer. A through-hole 23a is formed at the location in the second insulating layer 21 where the second via conductor 23 is to be formed, for example, by irradiation with a carbon dioxide laser. The second conductor layer 22 and the second via conductor 23 are formed by forming a metal film layer (not shown) on the inner surface of the through hole 23a and the upper surface of the second insulating layer 21 using chemical plating or sputtering, and by forming a plating film (not shown) using an anti-plating agent with appropriate openings and by using the metal film layer as a power supply layer.

[0047] Next, as Figure 2DAs shown, on the upper side of one surface 100f of the core substrate 100, the same process as the formation of the first insulating layer 11 and the integral formation of the first via conductor 13 and the first conductor layer 12 described above is repeated a desired number of times to form the first insulating layer 11 and the first conductor layer 12 of the desired number of layers. Additionally, on the upper side of the other surface 100s, the same process as the formation of the second insulating layer 21 and the integral formation of the second via conductor 23 and the second conductor layer 22 described above is repeated a desired number of times to form the second insulating layer 21 and the second conductor layer 22 of the desired number of layers. The outermost first conductor layer 12 is formed with a pattern including conductor pads 12fp. The outermost second conductor layer 22 is formed with a pattern including conductor pads 22sp. Furthermore, in the formation of the first conductor layer 12 and the second conductor layer 22, the first trench GB1 (refer to...) is formed... Figure 3A In the region GBA1, the first conductor layer 12 is not patterned, while in the region where the second trench GB2 is formed (see reference...), the pattern of the first conductor layer 12 is not formed. Figure 3A The region GBA2 does not form the pattern of the second conductor layer 22.

[0048] Furthermore, a solder resist layer 10Rf with an opening 10Rfa exposing a conductor pad 12fp is formed on the outermost first conductor layer 12 and first insulating layer 11 on one side 100f of the core substrate 100, covering multiple wiring substrate formation regions BA. On the side of the core substrate 100 opposite to one side 100f, a first laminate portion 10 having a first surface 1F formed by the surface of the solder resist layer 10Rf and the upper surface of the conductor pad 12fp is formed. On the outermost second conductor layer 22 and second insulating layer 21 on the other side 100s of the core substrate 100, a solder resist layer 20Rs with an opening 20Rsa exposing a conductor pad 22sp is formed covering multiple wiring substrate formation regions BA. On the side of the core substrate 100 opposite to one side 100s, a second laminate portion 20 having a second surface 1S formed by the surface of the solder resist layer 20Rs and the upper surface of the conductor pad 22sp is formed.

[0049] The above is based on reference. Figures 2A to 2D The described process completes the formation of a laminate 1P in which multiple wiring substrates 1 are connected. Additionally, in the formed laminate IP, conductor bumps 10BP and 20BP (shown by double-dotted lines in the figure) can be formed on the conductor pads 12fp and 22sp as conductive connection elements. The conductor bumps 10BP and 20BP can be formed by printing, for example, tin-copper solder paste onto the conductor pads 12fp and 22sp and reflowing the paste.

[0050] Next, refer to Figures 3A to 3DThis describes the process of dividing the formed laminate 1P into individual wiring substrates 1. In the wiring substrate manufacturing method of the embodiment, the step of dividing the laminate includes the following steps: forming a first groove GB1 that passes through the first stacked portion 10 along the thickness direction from the first surface 1F and a second groove GB2 that passes through the second stacked portion 20 along the thickness direction from the second surface 1S; and cutting between the bottom of the first groove GB1 and the bottom of the second groove GB2 along the dividing line BD.

[0051] First, such as Figure 3A As shown, along the dividing line BD, which serves as the boundary between the plurality of wiring substrates 1 constituting the laminate 1P, a first groove GB1 passing through the first stacking portion 10 in the thickness direction and a second groove GB2 passing through the second stacking portion 20 in the thickness direction are formed. The first groove GB1 can be formed, for example, by irradiating the laminate 1P with a laser such as a carbon dioxide laser from the outside of the first stacking portion 10. The second groove GB2 can be formed, for example, by irradiating the laminate 1P with a laser such as a carbon dioxide laser from the outside of the second stacking portion 20. The first groove GB1 and the second groove GB2 can also be formed using a cutting blade capable of general cutting.

[0052] The first trench GB1 and the second trench GB2 are formed to cover the entire periphery of the rectangle when viewed from above on each wiring substrate 1. When the first trench GB1 and the second trench GB2 are formed by laser, the first metal layer ML1 and the second metal layer ML2 function as laser blocking layers. In the illustrated example, the first trench GB1 penetrates the innermost first insulating layer 11 of the first stacked portion 10, exposing the first metal layer ML1 at its bottom. The second trench GB2 penetrates the innermost second insulating layer 21 of the second stacked portion 20, exposing the second metal layer ML2 at its bottom.

[0053] Next, the first metal layer ML1 exposed at the bottom of the first trench GB1 is removed by etching, and the second metal layer ML2 exposed at the bottom of the second trench GB2 is removed by etching. In the process of removing the first metal layer ML1 and the second metal layer ML2 by etching, a solution suitable for removing the metal material constituting the first metal layer ML1 and the second metal layer ML2 is used. The first metal layer ML1 and the second metal layer ML2 are made of a different material than the metal material constituting the conductors exposed on the surface of the laminate 1P (the metal material constituting the upper surface of the conductor pads 12fp and 22sp, or the metal material constituting the conductor protrusions 10BP and 20BP). Therefore, the degree to which etching affects the surface of the conductors exposed on the first surface 1F and the second surface 1S of the laminate 1P can be suppressed. Figure 3BAs shown, by removing the first metal layer ML1, one side 100f of the core substrate 100 is exposed at the bottom of the first groove GB1. By removing the second metal layer ML2, the other side 100s of the core substrate 100 is exposed at the bottom of the second groove GB2.

[0054] Next, as Figure 3C As shown, the bottom of the first groove GB1 and the bottom of the second groove GB2 are cut along the dividing line BD. For example, as shown, by completely cutting the core substrate 100 using the cutting blade DB, the multiple connected wiring substrates 1 are completely separated and monolithically divided into individual wiring substrates 1. In cutting the core substrate 100, the core substrate 100 can be cut using a dicing device, or it can be cut by applying external force after forming a modified portion or crack (micro-crack) on the core substrate 100 using a laser. Figure 3D As shown, the fabrication of the monolithic wiring substrate 1 is complete. As described above, in reference... Figure 3B In the described process, the effect of etching on the surface of the conductor exposed on the surface of the laminate 1P is minimized, so the conductors exposed on the first surface 1F and the second surface 1S of the manufactured wiring substrate 1 have a high-quality surface.

[0055] Furthermore, as a reference Figures 3A to 3D The examples described are different from other examples of processes that monolithize a laminate into individual wiring substrates; sometimes, the reference is not implemented. Figure 3B The removal of the first metal layer ML1 and the second metal layer ML2 is described. In this case, as... Figure 4A As shown, the first metal layer ML1, the core substrate 100, and the second metal layer ML2 are cut off together using a cutting blade DB or a dicing blade. During the cutting of the first metal layer ML1 and the second metal layer ML2 using the cutting blade DB, cutting powder of the metal material constituting the first metal layer ML1 and the second metal layer ML2 is generated. The cutting powder can be removed from the surface of the laminate 1P by washing. However, when a conductor made of the same metal material as the cutting powder is exposed on the surface of the laminate 1P, the cutting powder adheres firmly to the conductor surface and is sometimes difficult to remove easily. In the wiring substrate manufacturing method of the embodiment, the first metal layer ML1 and the second metal layer ML2 are formed of a different metal material than the conductors exposed on the first surface 1F and the second surface 1S. Therefore, it is believed that such firm adhesion of the cutting powder to the conductor surface is suppressed, and the cutting powder is easily removed. Figure 4A The results of the process shown are as follows: Figure 4B As shown, a monolithic wiring substrate 1a is obtained by exposing the upper surfaces of the first metal layer ML1 and the second metal layer ML2.

[0056] Furthermore, as a reference Figures 3A to 3D The example illustrates a different approach from other examples, as shown in the reference. Figure 3A In the described process, sometimes the first groove GB1 is formed as a groove extending to a position outside the first metal layer ML1, and the second groove GB2 is formed as a groove extending to a position outside the second metal layer ML2. In this case, the bottom of the first groove GB1 is formed by the first insulating layer 11, and the bottom of the second groove GB2 is formed by the second insulating layer 21, as shown. Figure 5A As shown, the first insulating layer 11, the first metal layer ML1, the core substrate 100, the second metal layer ML2, and the second insulating layer 21 are cut together using the cutting blade DB. In this case, it is also possible to suppress the strong adhesion of the cutting powder of the first metal layer ML1 and the second metal layer ML2 to the surface of the conductor exposed on the surface of the laminate 1P.

[0057] As shown in the figure, when the bottom of the first groove GB1 is formed by a first insulating layer 11, the surface of the first insulating layer 11 exposed at the bottom after the first groove GB1 is formed can be roughened. When the bottom of the second groove GB2 is formed by a second insulating layer 21, the surface of the second insulating layer 21 exposed at the bottom after the second groove GB2 is formed can be roughened. At this time, the surfaces of the first insulating layer 11 constituting the bottom of the first groove GB1 and the surfaces of the second insulating layer 21 constituting the bottom of the second groove GB2 can be formed, for example, to have a roughness of 0.5 μm or more and 5 μm or less in terms of arithmetic mean roughness Ra.

[0058] Figure 5A The results of the process shown are as follows: Figure 5B As shown, a monolithic wiring substrate 1b is obtained by exposing the upper surfaces of the first insulating layer 11 and the second insulating layer 21, which are roughened near the sides. Since the upper surfaces of the roughened first insulating layer 11 and the roughened second insulating layer 21 are exposed near the sides, over-wetting and expansion of the underfill are suppressed when an underfill is applied during the mounting of external electronic components in use of the wiring substrate 1b.

[0059] Furthermore, from the viewpoint of suppressing the coarsening of wiring substrates 1, 1a, and 1b, when viewed from above, the shortest distance DS1 between the side of the core substrate 100 constituting the periphery of wiring substrates 1, 1a, and 1b and the side of the first stacking portion 10, and the shortest distance DS2 between the side of the core substrate 100 and the side of the second stacking portion 20, are preferably 60 μm or less.

Claims

1. A method for manufacturing a wiring substrate, comprising the following steps: Prepare a core substrate having one side and another side opposite to the one side; A first laminate portion is formed on one of the surfaces, the first laminate portion comprising a first insulating layer and a first conductor layer, the first laminate portion having a first surface opposite to the core substrate; A second laminate portion is formed on the other surface, the second laminate portion comprising a second insulating layer and a second conductor layer, the second laminate portion having a second surface opposite to the core substrate; as well as The laminate containing the core substrate, the first laminate portion, and the second laminate portion is divided into multiple wiring substrates along the dividing line. in, The method for manufacturing the wiring substrate further includes the following steps: forming a first metal layer that contacts one surface and a second metal layer that contacts the other surface at a position that overlaps with the dividing line when viewed from above. The step of dividing the laminate includes the following steps: A first groove extending from the first surface through the first laminate portion and a second groove extending from the second surface through the second laminate portion are formed at the position where they overlap with the dividing line when viewed from above. as well as Cut along the dividing line between the bottom of the first groove and the bottom of the second groove. The first metal layer and the second metal layer are formed of a metal different from the material of the conductor exposed on the first surface and the conductor exposed on the second surface.

2. The method for manufacturing a wiring substrate according to claim 1, wherein, The step of forming the first stacked portion includes the following steps: forming the innermost first conductor layer away from the surface. The step of forming the second stacked portion includes the following steps: forming the innermost second conductor layer away from the other side.

3. The method for manufacturing a wiring substrate according to claim 1, wherein, The step of forming the first groove includes the following steps: exposing the first metal layer at the bottom. The step of forming the second groove includes the following step: exposing the second metal layer at the bottom.

4. The method for manufacturing a wiring substrate according to claim 3, wherein, The step of forming the first groove includes the following steps: removing the exposed first metal layer to expose one surface at the bottom. The step of forming the second groove includes the following steps: removing the exposed second metal layer to expose the other side at the bottom.

5. The method for manufacturing a wiring substrate according to claim 1, wherein, The step of forming the first groove includes the following steps: exposing the first insulating layer at the bottom. The step of forming the second groove includes the following step: exposing the second insulating layer at the bottom.

6. The method for manufacturing a wiring substrate according to claim 5, wherein, The step of forming the first groove includes the following steps: forming the bottom surface of the first groove to have an arithmetic mean roughness of 0.5 μm or more. The step of forming the second groove includes the following steps: forming the bottom surface of the second groove to have an arithmetic mean roughness of 0.5 μm or more.

7. The method for manufacturing a wiring substrate according to claim 5, wherein, When viewed from above, the shortest distance between the side of the first groove and the side of the core substrate formed by the cutting is less than 60 μm. The shortest distance between the side of the second groove and the side of the core substrate formed by the cutting is less than 60 μm.

8. The method for manufacturing a wiring substrate according to claim 1, wherein, The first metal layer is formed to have a thickness smaller than that of the first conductor layer. The second metal layer is formed to have a thickness smaller than that of the second conductor layer.

9. The method for manufacturing a wiring substrate according to claim 1, wherein, The first metal layer and the second metal layer are formed to have a thickness of 50 nm or more and 100 nm or less.

10. The method for manufacturing a wiring substrate according to claim 1, wherein, Before the laminate is divided, conductive connection elements are formed that are exposed on the first and second surfaces.

11. The method for manufacturing a wiring substrate according to claim 1, wherein, The core substrate includes a glass substrate.

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