A triode package structure

Abstract

This application discloses a transistor packaging structure. This solution integrates two independent transistors into the same plastic package, replacing two discrete single transistor devices, which significantly reduces the PCB board area occupied, shortens the signal transmission trace length, and improves the signal transmission speed. In addition, the two lead frames adopt a mirror-symmetrical stacked layout, which structurally avoids the collapse defects caused by the mutual compression and stacking of leads during molding packaging. Furthermore, the chip carrier area is provided with a stepped structure composed of an inner arc step and an outer edge ring. The two form an overflow guide gap, allowing the die bonding adhesive to flow smoothly into the gap along the arc structure, avoiding adhesive overflow and contamination of the chip, which could cause device failure.

Description

Technical Field

[0001] This application relates to the field of semiconductor power device packaging and manufacturing technology, and in particular to a transistor packaging structure. Background Technology

[0002] Transistors are one of the most fundamental and core semiconductor devices in modern electronic circuits. Essentially, they are current-controlled components that use a small base current to control a larger current between the collector and emitter, making them extremely widely used in circuits.

[0003] Currently, existing transistors are usually single devices packaged in a plastic package. With the increasing density and miniaturization of electronic devices, the use of multiple independent devices will seriously increase the PCB board area, the difficulty of wiring, and the signal transmission path, causing the circuit to face multiple effects such as parasitic capacitance and signal transmission delay.

[0004] Therefore, how to develop a new type of transistor packaging structure is an urgent problem to be solved. Summary of the Invention

[0005] This application aims to at least solve the technical problems existing in the prior art. To this end, the first aspect of this application proposes a transistor packaging structure, including: a molding compound and two lead frames, wherein the two lead frames are symmetrically stacked and encapsulated together inside the molding compound; wherein: Both lead frames include lead frame carriers, and each lead frame carrier has a reserved chip placement area. The chip placement area has a stepped structure inside, which includes an inner arc step and an outer angular ring. The inner arc step and the outer angular ring form an overflow guide gap. The lead frame carrier is integrally connected to the lead frame via horizontal ribs.

[0006] In one possible implementation, the inner arc step is an arc structure, the outer angular ring is an angular structure, and the die-bonding adhesive is guided along the arc structure to the gap between the inner arc step and the outer angular ring.

[0007] In one possible implementation, the lead frame carrier has angular structures and rounded bevels on its side to increase the bonding strength between the carrier and the encapsulation.

[0008] In one possible implementation, the side end of the lead frame carrier has an angular structure, and the sidewall extends outward to form a continuous arc slope.

[0009] In one possible implementation, the angular structure and the rounded bevel are integrally formed.

[0010] In one possible implementation, the sides of the lead frame carrier have a roughened structure.

[0011] In one possible implementation, each of the two lead frames is equipped with an independent transistor chip, and the two transistor chips are fabricated from the same batch of wafers.

[0012] In one possible implementation, the two lead frames have identical structures and dimensions.

[0013] In one possible implementation, the lead frame carrier and the lead frame as a whole are rigidly connected by at least two transverse ribs.

[0014] The embodiments of this application have the following beneficial effects: This application provides a transistor packaging structure, including: a molding compound and two lead frames. The two lead frames are symmetrically stacked and encapsulated together inside the molding compound. Each lead frame includes a lead frame carrier, and each lead frame carrier has a pre-reserved chip placement area. The chip placement area has a stepped structure inside, which includes an inner arc step and an outer corner ring. The inner arc step and the outer corner ring form an overflow drainage gap. The lead frame carrier is integrally connected to the lead frame through a cross rib. This solution integrates two independent transistors into a single plastic package, replacing two discrete single-transistor devices. This significantly reduces the PCB board area, shortens the signal transmission trace length, and improves signal transmission speed. In addition, the two lead frames adopt a mirror-symmetrical stacked layout, structurally avoiding the collapse defects caused by the mutual compression and stacking of leads during molding. Furthermore, the chip carrier area features a stepped structure composed of an inner arc step and an outer angular ring, which together form an overflow guide gap. The die bonding adhesive can flow smoothly into the gap along the arc structure, preventing adhesive overflow from contaminating the chip and causing device failure. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall appearance of a transistor packaging structure product provided in an embodiment of this application; Figure 2 A top view of the internal structure of a lead frame provided in an embodiment of this application; Figure 3 This application provides a partially enlarged three-dimensional schematic diagram of a stepped structure at the chip placement location of a lead frame; Figure 4 A schematic plan view of two symmetrically arranged lead frames provided in an embodiment of this application; Figure 5 This is a partially enlarged structural diagram of the side of a lead frame carrier provided in an embodiment of this application.

[0016] Explanation of reference numerals in the attached figures: 1 ~ Chip placement area; 2 ~ Connecting rib; 3 ~ Side of lead frame carrier; 4 ~ First horizontal rib; 5 ~ Second horizontal rib; 6 ~ First lead frame; 7 ~ Second lead frame; 8 ~ Inner arc step; 9 ~ Outer corner ring; 10 ~ Right angle corner structure. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] Currently, the industry standard for transistor packaging is a single-chip independent package structure, meaning a single transistor chip is packaged in an independent plastic casing, enabling only single-channel signal control. With the trend towards high-density, miniaturized, and integrated electronic product designs, scenarios such as differential amplifier circuits, symmetrical switch drive circuits, and dual-channel signal sampling circuits often require two transistors with matching performance. If the existing discrete single-transistor solution is used, two independently packaged transistor devices need to be soldered onto the PCB circuit board.

[0019] This traditional approach has several inherent drawbacks: First, the two independent components occupy separate PCB pad areas, significantly increasing the overall board area, which contradicts the design requirements for thinner and smaller devices; second, the discrete layout of the two components lengthens the signal transmission traces between the chips, significantly increasing the complexity of the wiring layout, and easily leading to problems such as trace crossing and insufficient wiring space in high-density PCBs; third, longer metal transmission traces introduce additional parasitic capacitance and inductance, which can cause signal transmission delay, waveform distortion, and crosstalk interference in high-speed signal circuits, severely reducing circuit signal integrity.

[0020] In addition, traditional single-tube packaging lead frames lack targeted anti-overflow adhesive, reinforcement, and anti-delamination structures. During the production process, there are also risks of process defects such as die bonding adhesive spillage contaminating the chip, lead bonding carrier shaking and poor soldering, delamination between the frame and the adhesive after molding, tombstoning during surface mount reflow, and lead collapse during molding. These factors limit the device production yield and long-term reliability.

[0021] Therefore, the industry urgently needs to design a new packaging structure that integrates dual transistors to simultaneously address multiple technical pain points from the packaging architecture level, such as large PCB footprint, poor high-speed signal transmission performance, low device parameter matching, and numerous defects in packaging manufacturing processes.

[0022] In view of this, this application integrates two independent transistors into the same plastic package, replacing two discrete single-transistor devices, which significantly reduces the PCB board area occupied, shortens the signal transmission trace length, effectively reduces parasitic capacitance and signal transmission delay in high-speed circuits, and improves signal transmission speed. In addition, the two lead frames adopt a mirror-symmetrical stacked layout, which structurally avoids the collapse defects caused by the mutual compression and stacking of leads during molding packaging. Furthermore, the chip carrier area is provided with a stepped structure composed of an inner arc step and an outer angular ring, which forms an overflow guide gap. The die bonding adhesive can flow smoothly into the gap along the arc structure, avoiding adhesive overflow and contamination of the chip, which may cause device failure.

[0023] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more conditions or values ​​may in practice be based on additional conditions or exceeding values.

[0024] The following combination Figures 1-5 This application provides a detailed description of a transistor packaging structure. Figure 1 This is a schematic diagram of the overall appearance of a transistor packaging structure product provided in an embodiment of this application; Figure 2 A top view of the internal structure of a lead frame provided in an embodiment of this application; Figure 3 This application provides a partially enlarged three-dimensional schematic diagram of a stepped structure at the chip placement location of a lead frame; Figure 4 A schematic plan view of two symmetrically arranged lead frames provided in an embodiment of this application; Figure 5 This is a partially enlarged structural diagram of the side of a lead frame carrier provided in an embodiment of this application.

[0025] This application provides a transistor packaging structure, including: a molding compound and two lead frames, the two lead frames being symmetrically stacked and encapsulated together inside the molding compound; wherein: each lead frame includes a lead frame carrier, each lead frame carrier having a reserved chip placement area (1), the chip placement area (1) having a stepped structure inside, the stepped structure including an inner arc step (8) and an outer corner ring (9), the inner arc step (8) and the outer corner ring (9) forming an overflow guide gap; the lead frame carrier is integrally connected to the lead frame through a cross rib.

[0026] Specifically, the transistor package structure comprises a plastic encapsulation body and two lead frames with identical structural dimensions, which are stacked in a mirror-symmetrical arrangement, such as... Figure 4 As shown, the two lead frames are the first lead frame (6) and the second lead frame (7), which are encapsulated and fixed inside the plastic package. Each of the two lead frames is equipped with an independent transistor chip. The two transistor chips are prepared by wafer cutting from the same batch and have highly consistent electrical performance.

[0027] In this embodiment, the dual lead frame is equipped with wafer chips from the same batch, resulting in high consistency of device electrical parameters and perfect suitability for circuit scenarios with high matching requirements. Furthermore, the two lead frames have completely identical structural dimensions, allowing for unified mold processing and simplifying the packaging production process.

[0028] In some optional embodiments, the lead frame carrier and the lead frame as a whole are rigidly connected by at least two transverse ribs. The rigid connection between the lead frame carrier and the frame body via at least two transverse ribs prevents the carrier from shaking during bonding, ensuring the accuracy of the lead bonding points and the bonding strength, reducing wire breakage and poor soldering, and adapting to various bonding processes such as fine leads and thick metal wires.

[0029] For example, such as Figure 2 As shown, both lead frames are integrally formed with lead frame carriers. The lead frame carriers and the overall exterior of the lead frames are rigidly connected by two transverse ribs, namely the first transverse rib (4) and the second transverse rib (5). During the bonding process, the two transverse ribs can provide stable support for the lead frame carrier, effectively suppressing carrier shaking, ensuring the accuracy of the lead bonding points, and improving bonding strength and product yield. In addition, individual frame structures can be placed in a whole frame through connecting ribs (2).

[0030] Please continue to refer to this. Figure 2 and Figure 3 The lead frame carrier has a chip placement area (1) in the middle. The chip placement area (1) has a stepped structure integrally processed on the inner side. The stepped structure consists of two parts: an inner arc step (8) and an outer corner ring (9). The inner arc step (8) is a smooth arc shape, and the outer corner ring (9) is a right-angled edge. An annular overflow guide gap is formed between the inner arc step (8) and the outer corner ring (9). When the die bonding process is used to place the chip, the glue will flow smoothly along the inner arc step (8) into the guide gap, avoiding the glue from overflowing into the effective area of ​​the chip and causing device failure. At the same time, the stepped layer structure forms a visual distinction and realizes process error prevention.

[0031] like Figure 5As shown, the side surface (3) of the lead frame carrier is a composite structure, with a right-angled angular structure (10) formed at its end. The carrier sidewall behind the angular structure extends outward to form a continuous arc-shaped slope, and the angular structure and the arc-shaped slope are integrally formed. In addition, the side surface (3) of the lead frame carrier can be chemically roughened.

[0032] During the molding stage, the molten molding compound can fill the gaps formed by the right-angled edges and corners, while closely fitting the roughened rounded bevels. This significantly increases the contact area between the lead frame carrier and the molding resin, reducing the risk of delamination and peeling after encapsulation from both mechanical snap-fit ​​and microscopic bonding perspectives.

[0033] The overall assembly and workflow based on the above transistor package structure is as follows: 1. First, place the transistor chips of two wafers from the same batch at the chip placement positions (1) of the two lead frames respectively, apply die bond adhesive to complete the bonding, and let the adhesive flow into the overflow gap along the inner arc step (8). 2. Then, the lead frame carrier is stabilized and supported by two horizontal ribs to complete the metal wire bonding between the chip electrode and the lead pin; 3. Two lead frames with identical structures are mirror-symmetrically stacked. The symmetrical layout can avoid the lead wires from collapsing due to mutual squeezing during molding. At the same time, the symmetrical structure can balance the stress during surface mount reflow soldering and greatly reduce the tombstoning effect of the device. 4. Inject molten encapsulant, which fills the gaps and edges of the carrier and wets the roughened rounded bevels. After cooling, a complete encapsulated body is formed. 5. After cutting, shaping, and testing, a single-package device with integrated dual transistors is obtained.

[0034] In this embodiment, compared to two independent single-transistor devices, this solution shortens the signal transmission traces, reduces parasitic capacitance and transmission delay, and significantly improves the signal transmission performance of high-speed circuits by occupying only the PCB pad area of ​​a single device.

[0035] In some alternative embodiments, the lead frame carrier and the lead frame as a whole are connected by three or more horizontal ribs to further strengthen the carrier support and adapt to the bonding process of ultra-fine leads and high-current thick metal wires.

[0036] In addition, the inner arc step (8) of the chip placement area (1) can increase the arc curvature, thereby widening the overflow adhesive guide gap, adapting to the die bonding large adhesive amount process, and is suitable for high power transistor chip packaging.

[0037] This application provides a transistor packaging structure, including: a molding compound and two lead frames. The two lead frames are symmetrically stacked and encapsulated together inside the molding compound. Each lead frame includes a lead frame carrier, and each lead frame carrier has a pre-reserved chip placement area. The chip placement area has a stepped structure inside, which includes an inner arc step and an outer corner ring. The inner arc step and the outer corner ring form an overflow drainage gap. The lead frame carrier is integrally connected to the lead frame through a cross rib. This solution integrates two independent transistors into a single plastic package, replacing two discrete single-transistor devices. This significantly reduces the PCB board area, shortens the signal transmission trace length, and improves signal transmission speed. In addition, the two lead frames adopt a mirror-symmetrical stacked layout, structurally avoiding the collapse defects caused by the mutual compression and stacking of leads during molding. Furthermore, the chip carrier area features a stepped structure composed of an inner arc step and an outer angular ring, which together form an overflow guide gap. The die bonding adhesive can flow smoothly into the gap along the arc structure, preventing adhesive overflow from contaminating the chip and causing device failure.

[0038] It is readily understood that, based on the several embodiments provided in this application, those skilled in the art can combine, split, or reorganize the embodiments of this application to obtain other embodiments, none of which exceed the protection scope of this application.

[0039] The above detailed embodiments further illustrate the purpose, technical solution, and beneficial effects of the embodiments of this application. It should be understood that the above are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solutions of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A transistor packaging structure, characterized in that, include: The package includes a molding compound and two lead frames, which are symmetrically stacked and encapsulated together inside the molding compound; wherein: Both lead frames include lead frame carriers, and each lead frame carrier has a reserved chip placement area. The chip placement area has a stepped structure inside, and the stepped structure includes an inner arc step and an outer angular ring. The inner arc step and the outer angular ring form an overflow guide gap. The lead frame carrier is integrally connected to the lead frame via horizontal ribs.

2. The transistor packaging structure according to claim 1, characterized in that, The inner arc step has an arc structure, and the outer angular ring has an angular structure. The die-bonding adhesive is guided along the arc structure to the gap between the inner arc step and the outer angular ring.

3. The transistor packaging structure according to claim 1 or 2, characterized in that, The lead frame carrier has angular structures and rounded bevels on its side to increase the bonding strength between the carrier and the encapsulation.

4. The transistor packaging structure according to claim 3, characterized in that, The side end of the lead frame carrier has an angular structure, and the side wall extends outward to form a continuous arc slope.

5. The transistor packaging structure according to claim 4, characterized in that, The angular structure and the curved surface are integrally formed.

6. The transistor packaging structure according to claim 1 or 2, characterized in that, The sides of the lead frame carrier have a roughened structure.

7. The transistor packaging structure according to claim 1 or 2, characterized in that, The two lead frames each correspond to an independent transistor chip, and the two transistor chips are made from the same batch of wafers.

8. The transistor packaging structure according to claim 1 or 2, characterized in that, The two lead frames have identical structures and dimensions.

9. The transistor packaging structure according to claim 1 or 2, characterized in that, The lead frame carrier and the lead frame as a whole are rigidly connected by at least two horizontal ribs.

Images