Electronic package structure and method of manufacturing the same

Abstract

This invention relates to an electronic packaging structure comprising an encapsulation, interconnect elements, a first metal material, and a second metal material. The interconnect elements are disposed within the encapsulation. The upper surface of the interconnect elements is not flush with the upper surface of the encapsulation. The first metal material is disposed on the upper surface of the interconnect elements. The second metal material is conformally disposed on the first metal material.

Description

Technical Field

[0001] This disclosure relates to an electronic packaging structure and a manufacturing method, and specifically to an electronic packaging structure including interconnecting elements and a method for manufacturing the electronic packaging structure. Background Technology

[0002] During operation of an electronic package structure, the heat generated by the semiconductor die or chip within the package can adversely affect its performance. However, the semiconductor die or chip can be encapsulated in a molding compound, such as a molding compound with relatively low thermal conductivity. Therefore, heat dissipation is a critical issue. Furthermore, the encapsulated semiconductor die or chip becomes thicker, making the electrical paths extending around it a significant concern. Summary of the Invention

[0003] In some embodiments, an electronic package structure includes an encapsulation, interconnect elements, a first metal material, and a second metal material. The interconnect elements are disposed within the encapsulation. The upper surface of the interconnect elements is not flush with the upper surface of the encapsulation. The first metal material is disposed on the upper surface of the interconnect elements. The second metal material is conformally disposed on the first metal material.

[0004] In some embodiments, an electronic package structure includes an encapsulation, interconnect elements, a first metal material, a second metal material, and a soldering material. The interconnect elements are disposed within the encapsulation and are bent. The first metal material is disposed on an upper portion of the interconnect elements. The second metal material is conformally disposed on the first metal material. The soldering material is disposed on the second metal material.

[0005] In some embodiments, an electronic package structure includes an encapsulation, interconnect elements, and a top substrate. The interconnect elements are disposed within the encapsulation. The top substrate is disposed above the interconnect elements and includes an external bonding pad. The center of the external bonding pad is not aligned with the center of the upper surface of the interconnect elements in a direction perpendicular to the upper surface of the encapsulation. Attached Figure Description

[0006] Various aspects of some embodiments of this disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view illustrating an electronic packaging structure according to some embodiments of the present disclosure.

[0008] Figure 2 illustrate Figure 1A magnified view of area "A".

[0009] Figure 3 A cross-sectional view illustrating an electronic packaging structure according to some embodiments of the present disclosure.

[0010] Figure 4 illustrate Figure 3 A magnified view of area "B".

[0011] Figure 5 A cross-sectional view illustrating an electronic packaging structure according to some embodiments of the present disclosure.

[0012] Figure 6 illustrate Figure 5 A magnified view of area "C".

[0013] Figure 7 A cross-sectional view illustrating an electronic packaging structure according to some embodiments of the present disclosure.

[0014] Figure 8 illustrate Figure 7 A magnified view of area "D".

[0015] Figure 9 A cross-sectional view illustrating an electronic packaging structure according to some embodiments of the present disclosure.

[0016] Figure 10 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0017] Figure 11 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0018] Figure 12 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0019] Figure 13 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0020] Figure 14 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0021] Figure 15 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0022] Figure 16This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0023] Figure 17 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0024] Figure 18 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0025] Figure 19 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0026] Figure 20 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0027] Figure 21 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0028] Figure 22 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0029] Figure 23 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0030] Figure 24 illustrate Figure 23 A magnified view of area "E".

[0031] Figure 25 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0032] Figure 26 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0033] Figure 27 illustrate Figure 26 A magnified view of the area "F".

[0034] Figure 28 This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure.

[0035] Figure 29This describes one or more stages of an example of a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure. Detailed Implementation

[0036] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0037] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0038] Figure 1 A cross-sectional view of an electronic packaging structure 1 according to some embodiments of the present disclosure is shown. Figure 2 illustrate Figure 1 An enlarged view of region "A". The electronic package structure 1 may include a lower substrate 2, a first electronic component 11, at least one interconnection element 4, an encapsulant 13, a first metal material 51, a second metal material 52, an upper substrate 3, a heat dissipation structure 14, at least one soldering material 15, a protective material 16, a second electronic component 17, at least one connecting element 18, and at least one external connector 19.

[0039] The lower substrate 2 may be a first substrate, a circuit pattern structure, a redistribution layer (RDL) structure, a wiring structure, or a substrate structure, and may be disposed on the lower surface 131 of the encapsulation 13. The lower substrate 2 may have a first surface 21 (e.g., a lower surface or bottom surface) and a second surface 22 opposite to the first surface 21 (e.g., an upper surface or top surface). The lower substrate structure 2 may include at least one dielectric layer 23, at least one circuit layer 24 (or redistribution layer), and at least one inner via 25. Figure 1As shown, the lower substrate 2 may include three dielectric layers 23, three circuit layers 24, and a plurality of internal vias 25. However, in this disclosure, the amount of dielectric layers 23 and the amount of circuit layers 24 are not limited.

[0040] The dielectric layer 23 may be made of a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) containing a photoinitiator. The dielectric layer 23 may cover the circuit layer 24 and may be stacked one on top of the other. Internal vias 25 may connect to the circuit layer 24. The internal vias 25 may taper upwards. The internal vias 25 may taper towards the first electronic component 11. Therefore, the width of the internal vias 25 may decrease upwards. The taper direction of the internal vias 25 in the lower substrate 2 may be the same as the taper direction of the internal vias 35 in the upper substrate 3. The circuit layer 24 may include a seed layer and a conductive layer disposed on the seed layer. In some embodiments, the seed layer may be omitted.

[0041] The topmost circuit layer 24 may include at least one outer pad 241 and at least one inner pad 242 exposed by the topmost dielectric layer in the dielectric layer 23. The upper surfaces of the outer pad 241 and the inner pad 242 may be substantially coplanar or aligned with the upper surface of the topmost dielectric layer 23 (i.e., the second surface 22 (upper surface or top surface) of the lower substrate 2). Additionally, the bottommost circuit layer 24 may include at least one bottom pad 243 exposed by the bottommost dielectric layer in the dielectric layer 23. The lower surface of the bottom pad 243 may be substantially coplanar or aligned with the lower surface of the bottommost dielectric layer 23 (i.e., the first surface 21 (lower surface or bottom surface) of the lower substrate 2). In some embodiments, the lower substrate 2 may have a first thickness T1. For example, the first thickness T1 may be about 110 μm to 120 μm.

[0042] A first electronic component 11 may be disposed above a second surface 22 of a lower substrate 2. The first electronic component 11 may be bonded to the lower substrate 2 and electrically connected to a circuit layer 24 of the lower substrate 2. The first electronic component 11 may be encapsulated by an encapsulant 13. The first electronic component 11 may be a semiconductor device such as an application-specific integrated circuit (ASIC) die or a high-bandwidth memory (HBM) die. The first electronic component 11 may have a lower surface 111 (e.g., an active surface), an upper surface 112 (e.g., a back surface) opposite the lower surface 111, and a side surface extending between the upper surface 112 and the lower surface 111. The first electronic component 11 may include a plurality of electrical contacts 114. The electrical contacts 114 may be disposed adjacent to the lower surface 111 (e.g., the active surface) of the first electronic component 11. The electrical contacts 114 may be exposed or protrude from the lower surface 111 (e.g., the active surface) for electrical connection. Electrical contacts 114 may be pads, bumps, studs, pillars, or posts. In some embodiments, the electrical contacts 114 of the first electronic component 11 may be electrically connected to and physically connected to the inner pads 242 of the lower substrate 2 via a plurality of solder materials 115. In other words, the first electronic component 11 may be electrically connected to the lower substrate 2 via flip-chip bonding.

[0043] like Figure 1 As shown, the first electronic component 11 may be disposed between the upper substrate 3 and the lower substrate 2. It may further include an underfill 12, which may be disposed in the space between the first electronic component 11 and the lower substrate 2 to cover and protect the joint structure formed by the electrical contact 114, the inner pad 242, and the solder material 115. In some embodiments, the underfill 12 may be omitted. In some embodiments, the first electronic component 11 may have a second thickness T2. For example, the second thickness T2 may be about 320 μm to 350 μm. The second thickness T2 of the first electronic component 11 may be greater than 2 times, 2.5 times, 3 times, or 3.5 times the first thickness T1 of the lower substrate 2.

[0044] At least one interconnect element 4 may comprise a plurality of interconnect elements 4 disposed around the first electronic component 11. The interconnect elements 4 may be disposed within an encapsulation 13. Each of the interconnect elements 4 may be a conductive wire or a bonding wire. In some embodiments, the interconnect elements 4 may physically connect, electrically connect, and / or thermally connect the upper substrate 3 and the lower substrate 2, and may be configured to conduct heat and / or transmit signals. Thus, the interconnect elements 4 may have the function of transmitting signals (e.g., digital signals). The interconnect elements 4 may be configured to transfer heat between the upper substrate 3 and the lower substrate 2.

[0045] In some embodiments, interconnect elements 4 may be electrically connected to and physically connected to an outer pad 241 of a lower substrate 2 via a wire bonding process. Interconnect elements 4 may be nanowires. The material of interconnect elements 4 may include copper (Cu), gold (Au), aluminum (Al), or other suitable metallic materials. Interconnect elements 4 may include a main portion 42 and a connecting portion 41. The connecting portion 41 may be generally circular and may directly contact the outer pad 241 of the lower substrate 2. The width of the connecting portion 41 may be greater than the width of the main portion 42. The width of the main portion 42 of interconnect elements 4 may be less than 100 nm, less than 80 nm, less than 50 nm, or less than 40 nm. The spacing of interconnect elements 4 may be less than 250 nm, less than 200 nm, less than 150 nm, or less than 120 nm.

[0046] The main portion 42 and the connecting portion 41 can be integrally formed as a single structure. The main portion 42 of the interconnecting element 4 can have a generally uniform width and can be bent. That is, in a cross-sectional view, the main portion 42 of the interconnecting element 4 can have a first segment and a second segment that intersect each other at an angle greater than 90 degrees. Both the first segment and the second segment can be generally straight. The entire side of the main portion 42 of the interconnecting element 4 may not be straight or a straight line in a cross-sectional view. In some embodiments, all interconnecting elements 4 can be bent in the same direction.

[0047] Encapsulation 13 may be disposed above the lower substrate 2. Encapsulation 13 may be disposed between the upper substrate 3 and the lower substrate 2 to encapsulate the first electronic component 11, the underfill 12, and the interconnect element 4. The material of encapsulation 13 may be a molding compound with or without filler. Encapsulation 13 may have a lower surface 131 (e.g., a first surface), an upper surface 132 (e.g., a second surface) opposite to the lower surface 131, and a side surface extending between the upper surface 132 and the lower surface 131. The lower surface 131 of encapsulation 13 may contact the second surface 22 (e.g., the upper surface or top surface) of the lower substrate 2. The upper surface 112 (e.g., the back surface) of the first electronic component 11 may be substantially aligned or coplanar with the upper surface 132 of encapsulation 13. Therefore, the upper surface 112 (e.g., the back surface) of the first electronic component 11 may be exposed by encapsulation 13.

[0048] like Figure 2 As shown, the main portion 42 of the interconnect element 4 may have an upper surface (top surface) 421 and a side surface 423. The upper surface 421 of the main portion 42 of the interconnect element 4 may not be flush with or aligned with the upper surface 132 of the encapsulation 13. In some embodiments, the upper surface 421 of the main portion 42 of the interconnect element 4 may be lower than the upper surface 132 of the encapsulation 13 to define a recessed portion 134. The upper surface 421 of the main portion 42 of the interconnect element 4 may be substantially parallel to the upper surface 132 of the encapsulation 13. The side surface 423 of the main portion 42 of the interconnect element 4 may not be perpendicular to the upper surface 132 of the encapsulation 13. The side surface 423 of the main portion 42 of the interconnect element 4 may not be perpendicular to the upper surface 421 of the main portion 42 of the interconnect element 4. The surface roughness of the side surface 423 of the main portion 42 of the interconnect element 4 may be less than the surface roughness of the upper surface 421 of the main portion 42 of the interconnect element 4.

[0049] The first metal material 51 and the second metal material 52 can together form a cap structure or an intermediate structure. The first metal material 51 can be disposed on the upper surface 421 of the main portion 42 of the interconnect element 4 and can extend beyond the upper surface 132 of the encapsulation 13. The first metal material 51 can be disposed on the upper portion of the interconnect element 4. Therefore, the first metal material 51 can extend from the upper surface 421 of the main portion 42 of the interconnect element 4 to above the upper surface 132 of the encapsulation 13. The upper surface 132 of the encapsulation 13 can horizontally overlap with the first metal material 51.

[0050] The first metallic material 51 may include an upper portion 512 and a lower portion 511. The lower portion 511 may be disposed in the recessed portion 134 and may be lower than the upper surface 132 of the encapsulation 13. The lower portion 511 may have a generally uniform thickness and width. The upper portion 512 may be disposed on the lower portion 511 and may be higher than the upper surface 132 of the encapsulation 13. The maximum width W1 of the upper portion 512 of the first metallic material 51 may be greater than the maximum width W2 of the lower portion 511 of the first metallic material 51. The maximum width W2 of the lower portion 511 of the first metallic material 51 may be generally equal to the width W2 of the main portion 42 of the interconnect element 4. The upper portion 512 of the first metallic material 51 may taper away from the upper surface 132 of the encapsulation 13 or may taper away from the lower substrate 2.

[0051] The upper portion 512 of the first metal material 51 may include a central portion 5121 and a peripheral portion 5122 surrounding the central portion 5121. The central portion 5121 may have a generally uniform thickness and may have a generally flat upper surface (or top surface) 5123. The peripheral portion 5122 may taper away from the central portion 5121. The peripheral portion 5122 may contact the upper surface 132 of the encapsulation 13. In addition, the width W3 of the generally flat upper surface 5123 of the central portion 5121 of the upper portion 512 of the first metal material 51 may be generally equal to the width W2 of the main portion 42 of the interconnecting element 4.

[0052] The upper portion 512 and the lower portion 511 can be integrally formed into a single structure. Therefore, the first metal material 51 can be generally mushroom-shaped or "T"-shaped. There may be no interface between the upper portion 512 and the lower portion 511. The first metal material 51 may contain nickel (Ni) and can be formed by a deposition process, such as an electroless nickel immersion gold (ENIG) process or an electroless nickel / electroless palladium / immersion gold (ENEPIG) process. In addition, the surface roughness of the generally flat upper surface (or top surface) 5123 of the central portion 5121 of the upper portion 512 of the first metal material 51 can be less than the surface roughness of the upper surface (or top surface) 421 of the main portion 42 of the interconnecting element 4.

[0053] The second metal material 52 may be conformally formed or disposed on the first metal material 51. The second metal material 52 may be a metal layer having a generally uniform thickness. The second metal material 52 may be formed or disposed on the entire upper surface (or top surface) of the first metal material 51 and may contact the upper surface 132 of the encapsulation 13. The thickness of the second metal material 52 may be less than the thickness of the central portion 5121 of the upper portion 512 of the first metal material 51 or the thickness of the lower portion 511 of the first metal material 51. The second metal material 52 may contain gold (Au) and may be formed by a deposition process, such as electroless nickel immersion gold (ENIG) or electroless nickel / electroless palladium / immersion gold (ENEPIG).

[0054] like Figure 1 As shown, the heat dissipation structure 14 may be formed or disposed on the upper surface 112 (e.g., the back or top surface) of the first electronic component 11. Therefore, the heat dissipation structure 14 can directly contact the upper surface 112 (e.g., the back or top surface) of the first electronic component 11. In some embodiments, the heat dissipation structure 14 may extend to the upper surface 132 of the encapsulation 13. Therefore, the heat dissipation structure 14 can directly contact the upper surface 132 of the encapsulation 13. Figure 1 As shown, the heat dissipation structure 14 may be disposed between the upper substrate 3 and the first electronic component 11. Therefore, the heat dissipation structure 14 may physically, electrically, and / or thermally connect the upper substrate 3 and the first electronic component 11, and may be configured to conduct heat and / or transmit signals. Thus, the heat dissipation structure 14 may or may not have the function of transmitting signals (e.g., digital signals). The heat dissipation structure 14 may be configured to transfer heat between the first electronic component 11 and the upper substrate 3. For example, the heat dissipation structure 14 may be configured to dissipate heat from the first electronic component 11 to the upper substrate 3. In some embodiments, the heat dissipation structure 14 may include a thermally conductive film, such as a die attach film (DAF), thermal interface material (TIM), thermally conductive adhesive, or a metal heat sink. Alternatively, the heat dissipation structure 14 may include multiple lines.

[0055] An upper substrate 3 (e.g., a thermally conductive structure) may be disposed above the lower substrate 2 and the first electronic component 11. A gap may exist between the first electronic component 11 and the upper substrate 3. The upper substrate 3 may be physically connected to and electrically connected to the lower substrate 2 via interconnecting elements 4 and at least one solder material 15. The upper substrate 3 may be a second substrate, a circuit pattern structure, a redistribution layer (RDL) structure, a wiring structure, or a substrate structure, and may be disposed on the upper surface of the heat dissipation structure 14. The upper substrate 3 may have a first surface 31 (e.g., a lower surface or bottom surface) and a second surface 32 (e.g., an upper surface or top surface) opposite the first surface 31. The upper substrate 3 may include at least one dielectric layer 33, at least one circuit layer 34 (e.g., a patterned circuit layer or redistribution layer), and at least one internal via 35.

[0056] like Figure 1 As shown, the upper substrate 3 may include three dielectric layers 33, three circuit layers 34, and a plurality of internal vias 35. However, in this disclosure, the number of dielectric layers 33 and the number of circuit layers 34 are not limited. The dielectric layers 33 may be made of a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) containing a photoinitiator. The dielectric layers 33 may cover the circuit layers 34 and may be stacked one on top of the other. The internal vias 35 may connect to the circuit layers 34. The internal vias 35 may taper upwards. Therefore, the width of the internal vias 35 may decrease upwards. The circuit layers 34 may include a seed layer and a conductive layer disposed on the seed layer. In some embodiments, the seed layer may be omitted.

[0057] The bottommost circuit layer in circuit layer 34 may include at least one external bonding pad 341 and at least one first inner thermal pad 342 exposed from the bottommost dielectric layer in dielectric layer 33. The lower surfaces of the external bonding pad 341 and the first inner thermal pad 342 may be substantially coplanar or aligned with the lower surface of the bottommost dielectric layer 33 (i.e., the first surface 31 (lower surface) of the upper substrate 3). The intermediate circuit layers in circuit layer 34 may include at least one second inner thermal pad 343. Additionally, the topmost circuit layer 34 may include at least one top pad 345 and at least one third inner thermal pad 344 exposed from the topmost dielectric layer in dielectric layer 33. The upper surfaces of the top pad 345 and the third inner thermal pad 344 may be substantially coplanar or aligned with the upper surface of the topmost dielectric layer 33 (i.e., the second surface 32 (upper surface) of the upper substrate 3).

[0058] The first internal thermal pad 342, the second internal thermal pad 343, and the third internal thermal pad 344 may have a large area and may be physically, electrically, and / or thermally connected to each other via internal through-holes 35. The first internal thermal pad 342 may contact the upper surface of the heat dissipation structure 14. Therefore, the first surface 31 (lower surface or bottom surface) of the upper substrate 3 may directly contact the heat dissipation structure 14. The widths of the first internal thermal pad 342, the second internal thermal pad 343, the third internal thermal pad 344, the width of the heat dissipation structure 14, and the width of the first electronic component 11 may be substantially equal to or different from each other. In some embodiments, the upper substrate 3 may have a third thickness T3. For example, the third thickness T3 may be about 60 μm to 80 μm. The third thickness T3 of the upper substrate 3 may be less than the first thickness T1 of the lower substrate 2. The second thickness T2 of the first electronic component 11 may be greater than the sum of the first thickness T1 of the lower substrate 2 and the third thickness T3 of the upper substrate 3.

[0059] In some embodiments, the upper substrate 3 may also be referred to as a "stacked structure," a "high-density electronic structure," or a "high-density stacked structure." The circuit layer 34 of the upper substrate 3 may also be referred to as a "high-density redistribution layer." The lower substrate 2 may also be referred to as a "stacked structure," a "low-density electronic structure," or a "low-density stacked structure." The circuit layer 24 of the lower substrate 2 may also be referred to as a "low-density redistribution layer." However, in some embodiments, the upper substrate 3 may also be referred to as a "low-density electronic structure" or a "low-density stacked structure." The circuit layer 34 of the upper substrate 3 may also be referred to as a "low-density redistribution layer." The lower substrate 2 may also be referred to as a "high-density electronic structure" or a "high-density stacked structure." The circuit layer 24 of the lower substrate 2 may also be referred to as a "high-density redistribution layer." It should be noted that the density of the circuit lines (including, for example, traces or pads) in the high-density redistribution layer is greater than the density of the circuit lines in the low-density redistribution layer. In other words, the number of circuit lines (including, for example, traces or pads) per unit area in a high-density redistribution layer is greater than the number of circuit lines per unit area in a low-density redistribution layer, for example, about 1.2 times or more, about 1.5 times or more, or about 2 times or more, or about 5 times or more. Alternatively or in combination, the line width / line space (L / S) of the high-density redistribution layer is smaller than the L / S of the low-density redistribution layer, for example, about 90% or less, about 50% or less, or about 20% or less.

[0060] At least one solder material 15 may comprise multiple solder materials 15. Solder materials 15 may comprise reflowable solderable materials, such as SnAg alloys. Solder materials 15 may electrically and physically connect the external bonding pad 341 of the upper substrate 3 to the second metal material 52. Solder materials 15 may be disposed on the second metal material 52 and may cover and contact the entire upper surface (or top surface) of the second metal material 52. Solder materials 15 may or may not contact the upper surface 132 of the encapsulation 13. The sides of solder materials 15 may include curved surfaces.

[0061] Protective material 16 (e.g., bottom filler) may be placed in the gap between the upper surface 132 of the encapsulation 13 and the first surface 31 (lower surface) of the upper substrate 3 to cover and contact the welding material 15.

[0062] The second electronic component 17 may be disposed above the upper substrate 3. The second electronic component 17 may be electrically connected and physically connected to the top pad 345 of the upper substrate 3 via at least one connecting element 18. The connecting element 18 may comprise solderable or reflowable materials, such as SnAg alloy. The second electronic component 17 may be a semiconductor device, such as an application-specific integrated circuit (ASIC) die or a high-bandwidth memory (HBM) die. The function of the second electronic component 17 may differ from that of the first electronic component 11. The thickness of the second electronic component 17 may be less than the second thickness T2 of the first electronic component 11.

[0063] At least one external connector 19 may include a plurality of external connectors 19 for external connection. The external connector 19 may contain a reflowable solderable material, such as a SnAg alloy. The external connector 19 may be formed or disposed on a bottom pad 243 of the bottommost circuit layer 24 of the lower substrate 2, the bottom pad 243 being exposed by the lower surface of the bottommost dielectric layer 23 (i.e., the first surface 21 (lower surface) of the lower substrate 2).

[0064] exist Figure 1 and Figure 2 In the embodiments described herein, the second thickness T2 of the first electronic component 11 may be greater than the sum of the first thickness T1 of the lower substrate 2 and the third thickness T3 of the upper substrate 3. Therefore, there may be a relatively long distance or a large gap between the lower substrate 2 and the upper substrate 3, which will increase the difficulty of manufacturing the electronic package structure 1. Metal wires can achieve long-distance connections, so when the interconnecting element 4 is a metal wire, the difficulty of manufacturing the electronic package structure 1 can be improved.

[0065] Furthermore, the heat generated by the first electronic component 11 is efficiently dissipated to the second surface 32 (upper surface) of the upper substrate 3 via the heat dissipation structure 14, the first internal thermal pad 342, the second internal thermal pad 343, and the third internal thermal pad 344. Therefore, the heat dissipation efficiency of the electronic packaging structure 1 can be improved.

[0066] Furthermore, the welding material 15 can be electrically connected to the interconnecting element 4 via the first metal material 51 and the second metal material 52. Since the maximum width W1 of the upper portion 512 of the first metal material 51 can be greater than the width W2 of the main portion 42 of the interconnecting element 4, the contact area between the welding material 15 and the second metal material 52 can be increased. Therefore, the reliability of the bonding between the welding material 15 and the second metal material 52 can be improved. In addition, the second metal material 52, exemplified by gold, can enhance the bonding between the welding material 15 and the first metal material 51, exemplified by nickel.

[0067] Figure 3 A cross-sectional view of an electronic packaging structure 1a according to some embodiments of the present disclosure is shown. Figure 4 illustrate Figure 3 A magnified view of area "B". Figure 3 and Figure 4 The electronic packaging structure 1a is similar to Figure 1 and Figure 2 The electronic package structure 1a has the following differences. In a cross-sectional view of the electronic package structure 1a, the main portion 42 of the interconnect element 4a may have a warped or bent profile. The entire side of the main portion 42 of the interconnect element 4a may not be flat or straight in the cross-sectional view. In some embodiments, all interconnect elements 4a may be bent in the same direction. In addition, the center of the outer bonding pad 341 may be misaligned or misaligned with the center of the upper surface 421 of the interconnect element 4a in a direction perpendicular to the upper surface 132 of the package 13. In addition, the first metal material 51 and the second metal material 52 may be misaligned with the solder material 15. Due to the materials and structures of the first metal material 51 and the second metal material 52, the solder material 15 may be disposed on the second metal material 52 and may be connected to the outer bonding pad 341. Therefore, the bonding between the second metal material 52 and the solder material 15 and the outer bonding pad 341 can still be ensured.

[0068] Figure 5 A cross-sectional view of an electronic packaging structure 1b according to some embodiments of the present disclosure is shown. Figure 6 illustrate Figure 5 A magnified view of area "C". Figure 5 and Figure 6 The electronic packaging structure 1b is similar to Figure 1 and Figure 2The electronic package structure 1b has the following differences. The interconnect element 4b of the electronic package structure 1b is electrically connected and physically connected to the outer pad 241 of the lower substrate 2 via wire bonding. The interconnect element 4b can be a nanowire. The material of the interconnect element 4b can include copper (Cu), gold (Au), aluminum (Al), or other suitable metals. The interconnect element 4b can include a main portion 42, a connecting portion 41, and an upper portion 43. The connecting portion 41 can be generally circular and can directly contact the outer pad 241 of the lower substrate 2. The width of the connecting portion 41 can be greater than the width of the main portion 42.

[0069] The main portion 42, the connecting portion 41, and the upper portion 43 can be integrally formed into a single structure. The main portion 42 of the interconnect element 4b can have a generally uniform width and can be bent. That is, in a cross-sectional view, the main portion 42 of the interconnect element 4b can have a first segment and a second segment that intersect each other at an angle greater than 90 degrees. The entire side of the main portion 42 of the interconnect element 4b may not be straight or a straight line in a cross-sectional view. The main portion 42 and the connecting portion 41 of the interconnect element 4b can be disposed in the encapsulation 13. The main portion 42 of the interconnect element 4b can have a warped or curved profile. The upper portion 43 of the interconnect element 4b can extend beyond the upper surface 132 of the encapsulation 13. Therefore, the upper surface 132 of the encapsulation 13 can horizontally overlap with the interconnect element 4b. In addition, the upper portion 43 of the interconnect element 4b can taper away from the upper surface 132 of the encapsulation 13 or taper away from the lower substrate 2.

[0070] A first metal material 51a may be conformally disposed on the upper portion 43 of the interconnect element 4b. A second metal material 52a may be conformally disposed on the first metal material 51a. The first metal material 51a may have a substantially uniform thickness. The second metal material 52a may have a substantially uniform thickness. The thickness of the first metal material 51a may be greater than the thickness of the second metal material 52a. Both the first metal material 51a and the second metal material 52a may contact the upper surface 132 of the encapsulation 13.

[0071] Figure 7 A cross-sectional view of an electronic packaging structure 1c according to some embodiments of the present disclosure is shown. Figure 8 illustrate Figure 7 A magnified view of area "D". Figure 7 and Figure 8 The electronic packaging structure 1c is similar to Figure 5 and Figure 6The electronic package structure 1b has the following differences. The interconnect element 4c of the electronic package structure 1c may have a turning point 44 formed between the upper portion 43 of the interconnect element 4c and the main portion 42 of the interconnect element 4c. The extending direction of the upper portion 43 of the interconnect element 4c may differ from the extending direction of the main portion 42 of the interconnect element 4c. The upper portion 43 of the interconnect element 4c and the main portion 42 of the interconnect element 4c may intersect each other at an angle greater than 90 degrees.

[0072] Figure 9 A cross-sectional view of an electronic packaging structure 1d according to some embodiments of the present disclosure is shown. Figure 9 The electronic packaging structure 1d is similar to Figure 1 and Figure 2 The electronic packaging structure 1 has the following differences. Figure 1 and Figure 2 Interconnecting element 4 can be made by Figure 9 The interposer 6 is replaced. The interposer 6 may include a main portion 60 and at least one through-via 61. The main portion 60 may contain silicon (Si), glass, or a dielectric material. The through-via 61 may contain a metallic material and may extend through the main portion 60. The upper surface of the main portion 60 may be substantially aligned or coplanar with the upper surface 112 (e.g., the back side) of the first electronic component 11 and the upper surface 132 of the encapsulation 13. Solder material 15 may be electrically connected and physically attached to the top end of the through-via 61. The bottom end of the through-via 61 may be electrically connected and physically attached to the outer pad 241 of the lower substrate 2 via solder material 62.

[0073] Figures 10 to 21 This invention describes a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture... Figure 1 and Figure 2 The electronic packaging structure 1 shown is illustrated.

[0074] refer to Figure 10 A lower substrate 2 can be provided. Figure 10 The lower substrate 2 can be with Figure 1 The lower substrate 2 is the same.

[0075] refer to Figure 11The first electronic component 11 may be attached or bonded to the lower substrate 2 and electrically connected to the circuit layer 24 of the lower substrate 2. The first electronic component 11 may have a lower surface 111 (e.g., an active surface), an upper surface 112 (e.g., a back surface) opposite the lower surface 111, and a side surface extending between the upper surface 112 and the lower surface 111. The first electronic component 11 may include a plurality of electrical contacts 114. The electrical contacts 114 may be disposed adjacent to the lower surface 111 (e.g., the active surface) of the first electronic component 11. The electrical contacts 114 may be exposed or protruding from the lower surface 111 (e.g., the active surface) for electrical connection. In some embodiments, the electrical contacts 114 of the first electronic component 11 may be electrically connected to and physically connected to an inner pad 242 of the lower substrate 2 via a plurality of solder materials 115. In other words, the first electronic component 11 may be electrically connected to the lower substrate 2 via flip-chip bonding.

[0076] refer to Figure 12 The bottom filler 12 may be formed or disposed in the space between the first electronic component 11 and the lower substrate 2 to cover and protect the joint structure formed by the electrical contact 114, the inner pad 242 and the solder material 115.

[0077] refer to Figure 13 At least one interconnect element 4b may be formed or disposed on the lower substrate 2. The at least one interconnect element 4b may comprise a plurality of interconnect elements 4b disposed around the first electronic component 11. Each of the interconnect elements 4b may be a conductive wire or a bonding wire. In some embodiments, the interconnect element 4b may be electrically connected to and physically connected to an outer pad 241 of the lower substrate 2 via a wire bonding process. The interconnect element 4b may be a nanowire. The interconnect element 4b may include a main portion 42, a connecting portion 41, and an upper portion 43. The connecting portion 41 may be generally circular plate-shaped and may directly contact the outer pad 241 of the lower substrate 2. The width of the connecting portion 41 may be greater than the width of the main portion 42.

[0078] The main portion 42, connecting portion 41, and upper portion 43 may be integrally formed as a single structure. The main portion 42 of the interconnecting element 4 may have a generally uniform width and may be flexible. That is, in a cross-sectional view, the main portion 42 of the interconnecting element 4 may have a first segment and a second segment intersecting each other at an angle greater than 90 degrees. Both the first segment and the second segment may be generally straight. The entire side of the main portion 42 of the interconnecting element 4 may not be straight or a straight line in a cross-sectional view. In some embodiments, all interconnecting elements 4 may be bent in the same direction. The upper portion 43 of the interconnecting element 4b may be higher than the upper surface 112 (e.g., the back side) of the first electronic assembly 11.

[0079] refer to Figure 14Encapsulation 13 may be formed or disposed above the lower substrate 2. Encapsulation 13 may encapsulate the first electronic component 11, the underfill 12, and the interconnect element 4b. Encapsulation 13 may have a lower surface 131 (e.g., a first surface) and an upper surface 132 (e.g., a second surface) opposite to the lower surface 131. The lower surface 131 of encapsulation 13 may contact the second surface 22 (e.g., the upper surface) of the lower substrate 2. The upper surface 112 (e.g., the back surface) of the first electronic component 11 may be lower than the upper surface 132 of encapsulation 13.

[0080] refer to Figure 15 A polishing process can be performed to polish the upper surface 132 of the encapsulation 13 to expose the upper surface 112 (e.g., the back side) of the first electronic component 11 and the interconnect element 4b. The upper portion 43 of the interconnect element 4b and a portion of the encapsulation 13 can be removed. Figure 15 As shown, the main portion 42 of the interconnect element 4 may have an upper surface 421 and a side surface 423. The upper surface 421 of the main portion 42 of the interconnect element 4 may be substantially coplanar or aligned with the upper surface 132 of the encapsulation 13. The side surface 423 of the main portion 42 of the interconnect element 4 may not be perpendicular to the upper surface 132 of the encapsulation 13. The side surface 423 of the main portion 42 of the interconnect element 4 may not be perpendicular to the upper surface 421 of the main portion 42 of the interconnect element 4.

[0081] refer to Figure 16 For example, a portion of the main portion 42 of the interconnect element 4b can be removed by an etching process. Simultaneously, the interconnect element 4b can be transformed into the interconnect element 4. The upper surface 421 of the main portion 42 of the interconnect element 4 may be lower than the upper surface 132 of the encapsulation 13 to define the recessed portion 134. The upper surface 421 of the main portion 42 of the interconnect element 4 may be substantially parallel to the upper surface 132 of the encapsulation 13. The surface roughness of the side surface 423 of the main portion 42 of the interconnect element 4 may be less than the surface roughness of the upper surface 421 of the main portion 42 of the interconnect element 4.

[0082] refer to Figure 17A first metal material 51 may be formed or disposed on the upper surface 421 of the main portion 42 of the interconnect element 4. The first metal material 51 may extend beyond the upper surface 132 of the encapsulation 13. Therefore, the first metal material 51 may extend from the upper surface 421 of the main portion 42 of the interconnect element 4 to above the upper surface 132 of the encapsulation 13. The upper surface 132 of the encapsulation 13 may horizontally overlap with the first metal material 51. The first metal material 51 may include an upper portion 512 and a lower portion 511. The lower portion 511 may be disposed in a recessed portion 134 and may be below the upper surface 132 of the encapsulation 13. The lower portion 511 may have a generally uniform thickness and width. The upper portion 512 may be disposed on the lower portion 511 and may be above the upper surface 132 of the encapsulation 13.

[0083] The upper portion 512 of the first metallic material 51 may taper away from the lower substrate 2. The upper portion 512 of the first metallic material 51 may include a central portion 5121 and a peripheral portion 5122 surrounding the central portion 5121. The central portion 5121 may have a generally uniform thickness and may have a generally flat upper surface 5123. The peripheral portion 5122 may taper away from the central portion 5121. The peripheral portion 5122 may contact the upper surface 132 of the encapsulation 13.

[0084] The upper portion 512 and the lower portion 511 can be integrally formed into a single structure. Therefore, the first metal material 51 can be generally mushroom-shaped or "T"-shaped. There may be no interface between the upper portion 512 and the lower portion 511. The first metal material 51 may contain nickel (Ni) and can be formed by a deposition process, such as electroless nickel immersion gold (ENIG) or electroless nickel / electroless palladium / immersion gold (ENEPIG). In addition, the surface roughness of the generally flat upper surface 5123 of the central portion 5121 of the upper portion 512 of the first metal material 51 may be less than the surface roughness of the upper surface 421 of the main portion 42 of the interconnecting element 4.

[0085] Next, a second metal material 52 may be conformally formed or disposed on the first metal material 51. The second metal material 52 may be a metal layer having a generally uniform thickness. The second metal material 52 may be formed or disposed on the entire upper surface of the first metal material 51 and may contact the upper surface 132 of the encapsulation 13. The thickness of the second metal material 52 may be less than the thickness of the central portion 5121 of the upper portion 512 of the first metal material 51 or the thickness of the lower portion 511 of the first metal material 51. The second metal material 52 may contain gold (Au) and may be formed by a deposition process, such as electroless nickel immersion gold (ENIG) or electroless nickel / electroless palladium / immersion gold (ENEPIG).

[0086] refer to Figure 18The heat dissipation structure 14 may be formed or disposed on the upper surface 112 (e.g., the back side) of the first electronic component 11. The heat dissipation structure 14 may directly contact the upper surface 112 (e.g., the back side) of the first electronic component 11. In some embodiments, the heat dissipation structure 14 may extend to the upper surface 132 of the encapsulation 13. Therefore, the heat dissipation structure 14 may directly contact the upper surface 132 of the encapsulation 13. The heat dissipation structure 14 may be physically, electrically, and / or thermally connected to the first electronic component 11, and may be configured to conduct heat and / or transmit signals. In some embodiments, the heat dissipation structure 14 may include a thermally conductive film, such as a die-attach film (DAF), a thermal interface material (TIM), a thermally conductive adhesive, or a metal heat sink. Alternatively, the heat dissipation structure 14 may include multiple lines.

[0087] refer to Figure 19 The upper substrate 3 can be placed above the lower substrate 2 and the first electronic component 11. Figure 19 The upper substrate 3 can be with Figure 1 The upper substrate 3 is identical to the lower substrate 2. A gap may exist between the upper substrate 3 and the upper surface 132 of the encapsulation 13. The upper substrate 3 may be physically connected and electrically connected to the lower substrate 2 via interconnecting elements 4 and at least one solder material 15. The solder material 15 may comprise a reflowable solderable material, such as a SnAg alloy. The solder material 15 may electrically and physically connect the outer bonding pad 341 of the upper substrate 3 to the second metal material 52. The solder material 15 may cover and contact the entire upper surface of the second metal material 52. The solder material 15 may or may not contact the upper surface 132 of the encapsulation 13. The sides of the solder material 15 may include curved surfaces. Meanwhile, the first surface 31 (lower surface) of the upper substrate 3 may directly contact the heat dissipation structure 14.

[0088] refer to Figure 20 Protective material 16 (e.g., bottom filler) may be formed or disposed in the gap between the upper surface 132 of the encapsulation 13 and the first surface 31 (lower surface) of the upper substrate 3 to cover and contact the welding material 15.

[0089] refer to Figure 21 At least one external connector 19 may be formed or disposed on a bottom pad 243 of the bottommost circuit layer 24 of the lower substrate 2, the bottom pad 243 being exposed by the lower surface of the bottommost dielectric layer 23 (i.e., the first surface 21 (lower surface) of the lower substrate 2). At least one external connector 19 may comprise a plurality of external connectors 19 for external connectivity. The external connector 19 may comprise a reflowable solderable material, such as a SnAg alloy.

[0090] Next, a second electronic component 17 may be disposed above the upper substrate 3. The second electronic component 17 may be electrically connected and physically connected to the top pad 345 of the upper substrate 3 via at least one connecting element 18. The connecting element 18 may comprise solderable or reflowable materials, such as SnAg alloy. The function of the second electronic component 17 may differ from that of the first electronic component 11.

[0091] Next, a single-cut process can be performed to obtain... Figure 1 and Figure 2 Multiple electronic packaging structures 1.

[0092] Figures 22 to 29 This invention describes a method for manufacturing an electronic packaging structure according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture... Figure 5 and Figure 6 The electronic packaging structure 1b shown is illustrated. The initial stage of the process described is related to... Figures 10 to 13 The stages described are the same or similar. Figure 22 Depicting Figure 13 The stage following the stage described in the text.

[0093] refer to Figure 22 Encapsulation 13 may be formed or disposed above the lower substrate 2. Encapsulation 13 may encapsulate the first electronic component 11, the underfill 12, and the interconnect element 4b. Encapsulation 13 may have a lower surface 131 (e.g., a first surface) and an upper surface 132 (e.g., a second surface) opposite to the lower surface 131. The lower surface 131 of encapsulation 13 may contact the second surface 22 (e.g., the upper surface) of the lower substrate 2. The main portion 42 and the connection portion 41 of the interconnect element 4b may be disposed in the encapsulation 13. The upper portion 43 of the interconnect element 4b may extend beyond the upper surface 132 of the encapsulation 13. Therefore, the upper surface 132 of the encapsulation 13 may horizontally overlap with the interconnect element 4b. In addition, the upper portion 43 of the interconnect element 4b may taper away from the lower substrate 2. The upper surface 112 (e.g., the back surface) of the first electronic component 11 may be substantially coplanar or aligned with the upper surface 132 of the encapsulation 13.

[0094] refer to Figure 23 and Figure 24 ,in Figure 24 illustrate Figure 23In an enlarged view of region "E", a first metal material 51a may be conformally formed or disposed on the upper portion 43 of the interconnect element 4b. Next, a second metal material 52a may be conformally disposed on the first metal material 51a. The first metal material 51a may have a substantially uniform thickness. The second metal material 52a may have a substantially uniform thickness. The thickness of the first metal material 51a may be greater than the thickness of the second metal material 52a. Both the first metal material 51a and the second metal material 52a may contact the upper surface 132 of the encapsulation 13.

[0095] Therefore, the first metallic material 51a and the second metallic material 52a can be generally triangular in shape. The first metallic material 51a may contain nickel (Ni) and can be formed by a deposition process, such as electroless nickel immersion gold (ENIG) or electroless nickel / electroless palladium / electroless gold immersion (ENEPIG). The second metallic material 52a may contain gold (Au) and can be formed by a deposition process, such as electroless nickel immersion gold (ENIG) or electroless nickel / electroless palladium / electroless gold immersion (ENEPIG).

[0096] refer to Figure 25 The heat dissipation structure 14 may be formed or disposed on the upper surface 112 (e.g., the back side) of the first electronic component 11. The heat dissipation structure 14 may directly contact the upper surface 112 (e.g., the back side) of the first electronic component 11.

[0097] refer to Figure 26 and Figure 27 ,in Figure 27 illustrate Figure 26 An enlarged view of region “F”, showing that the upper substrate 3 can be placed above the lower substrate 2 and the first electronic component 11. Figure 26 The upper substrate 3 can be with Figure 5 The upper substrate 3 is identical to the lower substrate 2. The upper substrate 3 may be physically connected and electrically connected to the lower substrate 2 via interconnecting elements 4b and at least one solder material 15. The solder material 15 may comprise a reflowable solderable material, such as a SnAg alloy. The solder material 15 may electrically and physically connect the outer bonding pad 341 of the upper substrate 3 to the second metal material 52. The solder material 15 may cover and contact the entire upper surface of the second metal material 52. The solder material 15 may or may not contact the upper surface 132 of the encapsulation 13.

[0098] refer to Figure 28 Protective material 16 (e.g., bottom filler) may be formed or disposed in the gap between the upper surface 132 of the encapsulation 13 and the first surface 31 (lower surface) of the upper substrate 3 to cover and contact the welding material 15.

[0099] refer to Figure 29At least one external connector 19 may be formed or disposed on a bottom pad 243 of the bottommost circuit layer 24 of the lower substrate 2, the bottom pad 243 being exposed by the lower surface of the bottommost dielectric layer 23 (i.e., the first surface 21 (lower surface) of the lower substrate 2). At least one external connector 19 may comprise a plurality of external connectors 19 for external connectivity. The external connector 19 may comprise a reflowable solderable material, such as a SnAg alloy.

[0100] Next, a second electronic component 17 may be disposed above the upper substrate 3. The second electronic component 17 may be electrically connected and physically connected to the top pad 345 of the upper substrate 3 via at least one connecting element 18. The connecting element 18 may comprise solderable or reflowable materials, such as SnAg alloy. The function of the second electronic component 17 may differ from that of the first electronic component 11.

[0101] Next, a single-cutting process can be performed to obtain... Figure 5 and Figure 6 Multiple electronic packaging structures 1b.

[0102] Unless otherwise specified, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” and “below” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not compromised by such arrangement.

[0103] As used herein, the terms “approximately,” “generally,” “roughly,” “about,” and “approximately” are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first value is within a range of variation less than or equal to ±10% of a second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value may be considered “generally” the same as or equal to the second value.

[0104] If the displacement between two surfaces is no greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the two surfaces are considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the surface is considered substantially flat.

[0105] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may contain a plural or multiple indicators.

[0106] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are those that offer little or no resistance to the flow of electric current. A unit of measurement for conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m, for example, at least 10 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0107] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted as including not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0108] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and alternative equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments may exist that are not specifically described in this disclosure. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are considered to be included within the scope of the appended claims. Although the disclosed methods have been described herein with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. An electronic packaging structure, comprising: Packaging material; Interconnecting elements disposed within the encapsulation, wherein the upper surface of the interconnecting elements is not flush with the upper surface of the encapsulation; A first metallic material is disposed on the upper surface of the interconnecting element; as well as A second metallic material is conformally disposed on the first metallic material.

2. The electronic packaging structure of claim 1, wherein the upper surface of the interconnecting element is lower than the upper surface of the encapsulation, and the first metal material extends beyond the upper surface of the encapsulation.

3. The electronic packaging structure according to claim 2, wherein the interconnecting element comprises conductive lines.

4. The electronic packaging structure according to claim 3, wherein the interconnecting elements have a generally uniform width and are curved.

5. The electronic packaging structure according to claim 2, wherein the second metal material contacts the upper surface of the encapsulation.

6. The electronic packaging structure of claim 2, wherein the first metal material comprises an upper portion and a lower portion, wherein the maximum width of the upper portion of the first metal material is greater than the maximum width of the lower portion of the first metal material, the maximum width of the lower portion of the first metal material is substantially equal to the width of the interconnect element, and the upper portion of the first metal material tapers away from the upper surface of the encapsulation.

7. The electronic packaging structure of claim 6, wherein the upper portion of the first metal material comprises a central portion and a peripheral portion surrounding the central portion, wherein the central portion has a substantially uniform thickness and a substantially flat upper surface, and wherein the peripheral portion tapers away from the central portion.

8. The electronic packaging structure of claim 7, wherein the width of the generally flat upper surface of the central portion of the upper portion of the first metal material is generally equal to the width of the interconnect element.

9. The electronic packaging structure according to claim 2, further comprising: Upper substrate; as well as A welding material that electrically connects the upper substrate to the second metal material.

10. The electronic packaging structure according to claim 9, further comprising: An electronic component electrically connected to a lower substrate and encapsulated by the encapsulation, wherein the upper surface of the electronic component is exposed by the encapsulation.

11. The electronic packaging structure according to claim 10, further comprising: A heat dissipation structure is disposed on the upper surface of the electronic component.

12. The electronic packaging structure according to claim 11, wherein the lower surface of the upper substrate directly contacts the heat dissipation structure.

13. The electronic packaging structure of claim 1, wherein the upper portion of the interconnecting element extends beyond the upper surface of the encapsulation.

14. The electronic packaging structure of claim 13, wherein both the first metal material and the second metal material are in contact with the upper surface of the encapsulation.

15. The electronic packaging structure of claim 14, wherein the upper portion of the interconnecting element tapers away from the upper surface of the encapsulation.

16. The electronic packaging structure of claim 15, wherein the interconnecting element further comprises a main portion disposed within the encapsulation, wherein a turning point is formed between the upper portion of the interconnecting element and the main portion of the interconnecting element.

17. An electronic packaging structure, comprising: Packaging material; Interconnecting elements, which are disposed within the encapsulation and are bent; A first metallic material is disposed on the upper portion of the interconnecting element; A second metallic material is conformally disposed on the first metallic material; as well as Welding material, which is placed on the second metal material.

18. The electronic packaging structure of claim 17, wherein the upper surface of the interconnecting element is lower than the upper surface of the encapsulation, and the first metal material extends beyond the upper surface of the encapsulation.

19. An electronic packaging structure, comprising: Packaging material; Interconnecting elements disposed within the encapsulation; as well as An upper substrate, disposed above the interconnect element, includes an external bonding pad, wherein the center of the external bonding pad is not aligned with the center of the upper surface of the interconnect element in a direction perpendicular to the upper surface of the encapsulation.

20. The electronic packaging structure of claim 19, further comprising a soldering material disposed on the second metal material and connected to the external bonding pad.

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