Chip package structure, manufacturing method and electronic device

Abstract

This invention discloses a chip packaging structure, fabrication method, and electronic device, belonging to the field of chip packaging technology. The chip packaging structure includes multiple chips, each receiving a first electrical signal, processing the first electrical signal, and outputting a second electrical signal; multiple through-holes electrically connected to the chips, receiving the second electrical signal, and outputting the second electrical signal to a first wiring layer; the first wiring layer is electrically connected to the multiple through-holes for transmitting the second electrical signal. This invention is compatible with the integration of heterogeneous chips of various thicknesses and specifications, avoids the failure problem of grinding bump interconnects, has high packaging reliability, and is relatively easy to implement.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a chip packaging structure, manufacturing method, and electronic device. Background Technology

[0002] With the continuous development of advanced semiconductor packaging technologies such as heterogeneous integration and system-in-package (SiP), there is a growing demand for integrating more and more chips and passive devices within the package. Multi-chip packaging technologies commonly employ microbumps for chip interconnection. However, during assembly, variations in chip thickness and bump height lead to processing tolerances, making localized interconnect failures common and significantly reducing packaging yield. Furthermore, differences in chip thickness make coplanar placement difficult, limiting heterogeneous chip integration. Traditional bump fabrication requires multiple processes such as photolithography and electroplating, resulting in a complex and costly process. Current technologies lack interconnection solutions that are compatible with chips of varying thicknesses and eliminate bump height tolerances, making it difficult to meet the mass production demands of high-density heterogeneous packaging.

[0003] Current multi-chip packaging technology first prefabricates a substrate, then mounts several chips on the substrate, prefabricates the chip surfaces with bumps, and exposes all the bumps on the chip surfaces through a mechanical polishing process. Interconnection is then achieved through wiring layers on the chips. Current multi-chip packaging technology is based on panel manufacturing processes, and all chip signals are led out through the top bumps. It requires a mechanical polishing stage to expose all the chip bumps and keep them at the same level. The bump height of discrete devices is typically only 50μm, but the warpage of the resulting encapsulated plastic package can easily reach millimeter levels, and is also limited by chip thickness tolerances, adhesive thickness tolerances, and bump height tolerances.

[0004] Therefore, existing multi-chip packaging technologies still suffer from the lack of compatibility with chips of various thicknesses and the inability to eliminate bump height tolerances. Summary of the Invention

[0005] The present invention aims to provide a chip packaging structure, a manufacturing method and an electronic device, which establishes electrical connections between multiple chips and wiring layers through multiple through holes, enabling the integration of heterogeneous chips of various thicknesses and specifications, and eliminating the problem of bump height tolerance.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows: A chip packaging structure, comprising, Multiple chips, wherein each chip receives a first electrical signal, processes the first electrical signal, and outputs a second electrical signal; Multiple vias are electrically connected to the chip, receive the second electrical signal, and output the second electrical signal to the first wiring layer; The first wiring layer is electrically connected to the plurality of vias for transmitting the second electrical signal.

[0007] Furthermore, by adjusting the thickness of the via, the end of the via that is electrically connected to the first wiring layer is placed on the same horizontal plane.

[0008] Furthermore, the chip packaging structure further includes a wiring unit, which is electrically connected to the chip via a second adhesive material. The wiring unit receives a first electrical signal and transmits the first electrical signal to the chip. The wiring unit is electrically connected to the via and transmits a second electrical signal.

[0009] Furthermore, the chip packaging structure further includes a plurality of first copper pillars, the first copper pillars being electrically connected to the first wiring layer, the first copper pillars receiving the second electrical signal and transmitting the second electrical signal to the second wiring layer; The second wiring layer is electrically connected to the plurality of first copper pillars for transmitting the second electrical signal.

[0010] Furthermore, the chip packaging structure further includes at least one surface mount device, which is electrically connected to a plurality of through-holes, or the surface mount device is electrically connected to the second wiring layer through a first adhesive material, wherein the first adhesive material receives the second electrical signal and transmits the second electrical signal to the plurality of surface mount devices; the surface mount device receives the second electrical signal or outputs a third electrical signal.

[0011] Furthermore, the first surface of the chip is on the same horizontal plane, and the second surface of the chip is electrically connected to the through hole.

[0012] A chip packaging fabrication method, used to fabricate a chip packaging structure as described in any one of the above claims, includes the following steps: Step S1: Apply a temporary adhesive film to the surface of the carrier board, and attach the first side of multiple chips to the temporary adhesive film on the surface of the carrier board to form a first package. Step S2: Encapsulate the first package with a dielectric material to form a second package; Step S3: Drill holes in the upper surface of the second package using a laser to form multiple through holes; Step S4: Metallize the hole walls of the plurality of through holes and the upper surface of the second package body. Step S5: Encapsulate the second package with a dielectric material to form a third package; Step S6: Flip the third package over, remove the carrier plate and temporary adhesive film, and drill multiple through holes in the third package using a laser. Step S7: Metallize the walls of the multiple through holes and the upper surface of the third package body. Step S8: Encapsulate the third package with a dielectric material to obtain a fourth package.

[0013] Furthermore, step S1 also includes: placing the first side of at least one surface-mount device on a temporary adhesive film on the surface of the carrier board.

[0014] Furthermore, in step S3, the through-hole is disposed on the plurality of chips, the through-hole is disposed on at least one surface mount device, and the through-hole is provided with a preset distance from the upper surface of the carrier board; When the via is disposed on multiple chips, the bottom of the via exposes the metal pads on the second surface of the multiple chips; when the via is disposed on at least one surface mount device, the bottom of the via exposes the metal pads on the second surface mount device; the preset distance between the via and the upper surface of the carrier board is not equal to zero.

[0015] Furthermore, in step S4, the metallization wiring process specifically includes: Step S41: Deposit a first metal on the inner wall of the multiple through holes; Step S42 involves sequentially fabricating a first wiring layer and multiple first copper pillars on the multiple through holes through a series of processes including exposure, development, and electroplating.

[0016] Furthermore, step S6 specifically includes the following steps: Step S61: Flip the third package over, remove the carrier board and temporary adhesive film, and expose the first side of multiple chips and at least one surface mount device. Step S62: Drill multiple through holes at a preset interval between the through holes and the upper surface of the carrier plate using a laser.

[0017] Furthermore, the chip packaging fabrication method further includes: Step S9: Flip the fourth package over and expose the multiple first copper pillars through a mechanical grinding process; Step S10: A second wiring layer is fabricated on the plurality of first copper pillars through a series of processes including exposure, development, and electroplating. Step S11: Use the first adhesive material to fix multiple surface-mount devices onto the second wiring layer; Step S12: Through reflow soldering process, the plurality of surface mount devices are electrically connected to the second wiring layer; Step S13: Encapsulate the fourth package using a dielectric material to obtain a chip package structure.

[0018] An electronic device includes a circuit board and a chip package structure as described in any of the above, soldered onto the circuit board.

[0019] Beneficial effects: This invention establishes electrical connections between the active surfaces of multiple chips and the wiring layer through multiple vias; the passive surfaces of multiple chips are electrically exposed on one side of the substrate using a conductive adhesive material, allowing the chips to be conductive on both sides; this invention mounts the passive surfaces of multiple chips on the same horizontal plane, drills holes in the chips using a laser, and performs electroplating processes, establishing electrical connections between the multiple chips and the wiring layer through multiple vias, replacing the exposed bump interconnection caused by grinding. This avoids problems such as bump damage, over-grinding, and debris contamination caused by grinding, eliminates bump height tolerances, and improves packaging reliability; this invention drills multiple vias on multiple chips using a laser, and the opening thickness of the vias can be adaptively set according to the chip thickness, enabling the integration of heterogeneous chips of various thicknesses and specifications, significantly improving production yield while further reducing costs and meeting the needs of mass production.

[0020] To make the above-mentioned features and advantages of the invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a chip packaging structure provided in one embodiment of the present invention.

[0023] Figure 2 This is a flowchart of a chip packaging fabrication method provided in one embodiment of the present invention.

[0024] Figure 3 This is a schematic cross-sectional view of the chip packaging process in step S1 of a chip packaging fabrication method provided in one embodiment of the present invention. Figure 4 This is a schematic cross-sectional view of the chip packaging process in step S2 of a chip packaging fabrication method provided in one embodiment of the present invention.

[0025] Figure 5 This is a schematic cross-sectional view of the chip packaging process in step S3 of a chip packaging fabrication method provided in one embodiment of the present invention.

[0026] Figure 6 This is a schematic cross-sectional view of the chip packaging process in steps S4 and S5 of a chip packaging fabrication method provided in one embodiment of the present invention.

[0027] Figure 7 This is a schematic cross-sectional view of the chip packaging process in steps S6, S7, and S8 of a chip packaging fabrication method provided in one embodiment of the present invention.

[0028] Figure 8 This is a schematic cross-sectional view of a chip packaging process provided in one embodiment of the present invention.

[0029] Figure 9 This is a schematic diagram of the structure of an electronic device provided in one embodiment of the present invention. Detailed Implementation

[0030] To make the objectives and technical solutions of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0031] In one embodiment, see Figure 1 The present invention provides a chip packaging structure, wherein the chip packaging structure 1 includes: Wiring unit 101; The wiring unit 101 includes: a first metal layer 1011, a plurality of second copper pillars 1012, a third wiring layer 1013, and a fourth wiring layer 1014. The first metal layer 1011 is electrically connected to the plurality of second copper pillars 1012, the second copper pillars 1012 are electrically connected to the third wiring layer 1013, and the third wiring layer 1013 is electrically connected to the fourth wiring layer. The first metal layer 1011 receives a first electrical signal Vin, and the first electrical signal Vin is transmitted to the chip 103 via the plurality of second copper pillars 1012, the third wiring layer 1013, and the fourth wiring layer 1014.

[0032] Multiple chips 103 are electrically connected to the wiring unit 101 via a second adhesive material 104. Each chip 103 is used to receive a first electrical signal Vin input from the outside of the package, process the first electrical signal Vin, and output a second electrical signal Vout. The first surfaces of the multiple chips are on the same horizontal plane.

[0033] As an example, the multiple chips 103 include a first chip 1031, a second chip 1032, ..., an Nth chip 103N.

[0034] Multiple vias 105 are electrically connected to the chip 103, receive the second electrical signal Vout, and output the second electrical signal Vout to the first wiring layer 106.

[0035] The plurality of through holes 105 are electrically connected to the wiring unit 101, transmitting the second electrical signal Vout to the wiring unit 101; The fourth wiring layer 1014 receives the second electrical signal Vout and transmits the second electrical signal Vout to the third wiring layer 1013. The third wiring layer 1013 receives the second electrical signal Vout and transmits the second electrical signal Vout to the second copper pillar 1012. The second copper pillar 1012 receives the second electrical signal Vout and transmits the second electrical signal Vout to the first metal layer 1011.

[0036] The first wiring layer 106 is electrically connected to the through-hole 105 and is used to transmit the second electrical signal Vout.

[0037] At least one surface-mount device 102 is electrically connected to the via 105 and receives the second electrical signal Vout or outputs a third electrical signal.

[0038] Multiple first copper pillars 107 are electrically connected to the first wiring layer 106. The first copper pillars 107 receive the second electrical signal Vout and transmit the second electrical signal Vout to the second wiring layer 108.

[0039] The second wiring layer 108 is electrically connected to the first copper pillar 107 and is used to transmit the second electrical signal Vout.

[0040] Multiple surface mount devices 102 are electrically connected to the second wiring layer 108 via a first adhesive material 109; the first adhesive material 109 receives the second electrical signal Vout and transmits the second electrical signal Vout to the surface mount device 102, and the surface mount device 102 receives the second electrical signal Vout or outputs a third electrical signal.

[0041] Dielectric material 110 is used to fill the gaps between the plurality of surface-mount devices 102 and the first metal layer 1011 and to cover the surface of the plurality of surface-mount devices 102.

[0042] As an example, the sizes of the multiple surface-mount devices 102 can be the same or different.

[0043] Furthermore, the first side of the multiple chips 103 is the back side, which is a passive side; the second side of the multiple chips 103 is the front side, which is an active side.

[0044] As an example, the thickness of the multiple chips 103 may be the same or different.

[0045] As an example, the opening size of the plurality of through holes 105 can be one or more. The thickness of the through holes 105 can be adjusted according to the thickness of the plurality of chips 103 or surface mount devices 102, so that the end of the through hole 105 electrically connected to the first wiring layer 106 is at the same horizontal plane.

[0046] As an example, the first adhesive material 109 and the second adhesive material 104 may be conductive adhesive materials.

[0047] As an example, the dielectric material 110 may be a molding compound.

[0048] As an example, the fourth wiring layer 1014 can serve as a base island for multiple chips 103.

[0049] As an example, the plurality of surface-mount devices 102 may be passive devices.

[0050] This invention provides a chip packaging structure in which the active surfaces of multiple chips are electrically connected to a wiring layer through multiple vias; and the passive surfaces of multiple chips are electrically exposed to the substrate on one side of the passive surface using a conductive adhesive material, allowing the chip to be conductive on both sides. This invention mounts the passive surfaces of multiple chips on the same horizontal plane, and the multiple chips are electrically connected to the wiring layer through multiple vias, replacing the grinding of exposed bump interconnects. This can eliminate bump height tolerances and is compatible with the integration of heterogeneous chips of various thicknesses and specifications.

[0051] In one embodiment, see Figure 2 This invention provides a chip packaging fabrication method for manufacturing the aforementioned chip packaging structure, comprising the following steps: Step S1: Apply a temporary adhesive film to the surface of the carrier board, and attach the first side of multiple chips to the temporary adhesive film on the surface of the carrier board to form a first package. Step S2: Encapsulate the first package with a dielectric material to form a second package; Step S3: Drill holes in the upper surface of the second package using a laser to form multiple through holes; Step S4: Metallize the hole walls of the plurality of through holes and the upper surface of the second package body. Step S5: Encapsulate the second package with a dielectric material to form a third package; Step S6: Flip the third package over, remove the carrier plate and temporary adhesive film, and drill multiple through holes in the third package using a laser. Step S7: Metallize the walls of the multiple through holes and the upper surface of the third package body. Step S8: Encapsulate the third package with a dielectric material to obtain a fourth package.

[0052] This invention provides a chip packaging fabrication method in which the passive surfaces of multiple chips are mounted on the same horizontal plane. Holes are drilled on the multiple chips using a laser and electroplating is performed. The multiple chips are electrically connected to the wiring layer through multiple through-holes, which replaces the exposed bump interconnection caused by grinding. This avoids problems such as bump damage, over-grinding, and debris contamination caused by grinding, and solves the problem of electrical interconnection failure caused by grinding bumps. By drilling multiple through-holes with a laser, the opening thickness of the through-holes can be adaptively set according to the thickness of the chip, which can be compatible with the integration of heterogeneous chips of various thicknesses and specifications. This significantly improves the production yield while further reducing costs and meeting the needs of mass production.

[0053] In one example, taking two chips as an example, a chip packaging preparation method of the present invention is introduced. In this embodiment, the multiple chips 103 include a first chip 1031 and a second chip 1032.

[0054] Specifically, please refer to Figure 3 In step S1, a temporary adhesive film 112 is attached to the surface of the carrier board 111, and the first side of multiple chips 103 is attached to the temporary adhesive film 112 on the surface of the carrier board 111 by the second adhesive material 104.

[0055] Step S1 further includes: mounting the first side of at least one surface mount device 102 onto a temporary adhesive film 112 on the surface of a carrier plate 111 to form a first package 11.

[0056] As an example, when mounting the first side of the multiple chips 103 and at least one surface mount device 102 onto the temporary adhesive film 112 on the surface of the carrier board 111, the mounting area can be set according to the planar dimensions of the chips to be assembled, the planar dimensions of the at least one surface mount device 102, the device layout, and the required insulation spacing between the devices.

[0057] As an example, the first side of the chip 103 is the back side, which is a passive side; the second side of the chip 103 is the front side, which is an active side.

[0058] As an example, the surface mount device 102 can be the same or different in size.

[0059] As an example, the surface mount device 102 can be a passive device. The first side of the surface mount device 102 is the back side, which is used for device mounting and contact with the carrier substrate. The second side of the at least one surface mount device 102 is the front side, which is a terminal surface with conductive terminals, and the conductive terminals of the terminal surface are metal pads.

[0060] As an example, the chip thickness of the chip 103 can be the same or different.

[0061] Furthermore, the first surface of the chip 103 is mounted on the same horizontal plane.

[0062] As an example, the second side of the chip 103 has several windowed areas. To prevent laser damage to the chip, the surface of the windowed areas has metal pads. The material of the stacked metal layers in the metal pads is usually titanium-nickel-silver (TiNiAg), nickel-palladium-gold (NiPdAu), or nickel-gold (NiAu). When the stacked metal layers in the metal pads include a nickel layer, the thickness of the nickel layer is usually greater than or equal to 3μm. If the stacked metal layers in the metal pads are made of copper, the thickness of the copper layer is usually greater than or equal to 5μm.

[0063] As an example, the terminal surface material of the second side of the surface mount device 102 is generally copper.

[0064] Further, please refer to Figure 4 In step S2, the first package 11 is encapsulated with dielectric material 110 to fill the gaps in the first package 11 and cover the second side of the chip 103 and at least one surface mount device 102, forming a second package 12.

[0065] As an example, the dielectric material 110 may be a molding compound.

[0066] Further, please refer to Figure 5 In step S3, the through hole 105 is disposed on the plurality of chips, the through hole 105 is disposed on at least one surface mount device 102, and the through hole 105 is separated from the upper surface of the carrier board 111 by a preset distance H.

[0067] As an example, when drilling with a laser to obtain multiple through holes 105, the drilling position can be set according to the position of the metal pads on the second surface of the chip 103 and the second surface of the surface mount device 102, the wiring path layout, the safety distance between adjacent through holes, and the process allowance of laser processing.

[0068] Specifically, when the through hole 105 is disposed on multiple chips 103, the bottom of the through hole exposes the metal pads on the second surface of the multiple chips 103; when the through hole 105 is disposed on at least one surface mount device 102, the bottom of the through hole exposes the metal pads on the second surface of at least one surface mount device 102; the preset distance H between the through hole 105 and the upper surface of the carrier board 111 is not equal to zero.

[0069] As an example, the opening size of the multiple through holes 105 can be one or more, and the opening thickness of the through holes 105 can be adaptively set according to the thickness of the multiple chips 103 and at least one surface mount device 102. The through holes 105 cannot be drilled to the surface of the carrier board.

[0070] Further, please refer to Figure 6 In step S4, the walls of the plurality of through holes 105 and the upper surface of the second package 12 are subjected to metallization wiring treatment. The metallization wiring treatment may include the following steps: Step S41: Deposit a first metal on the inner wall of the through hole 105 and the exposed surface of the molding compound; In step S42, a first wiring layer 106 and a plurality of first copper pillars 107 are sequentially fabricated on the through hole 105 through a series of processes including exposure, development and electroplating.

[0071] As an example, the thickness of the first metal needs to be adapted to the inner diameter of the through hole 105 and the electroplating processing conditions.

[0072] Preferably, in step S41, a copper plating process can be used to deposit the first metal, which can be metallic copper.

[0073] Further, in step S5, the second package 12 is encapsulated with dielectric material 110 to fill the gaps in the second package 12 and cover the upper surface of the plurality of first copper pillars 107 to form a third package 13.

[0074] Further, please refer to Figure 7 In step S6, the third package 13 is flipped over, the carrier plate 111 and the temporary adhesive film 112 are removed, and multiple through holes 105 are drilled into the third package 13 using a laser; specifically, the following steps are included: Step S61: Flip the third package 13 over, remove the carrier plate 111 and temporary adhesive film 112, and expose the first side of multiple chips 103 and at least one surface mount device 102. Step S62: Drill multiple through holes 105 at a predetermined interval H between the through hole and the upper surface of the carrier plate using a laser. As an example, when multiple through holes are drilled at preset intervals using a laser, the hole thickness is the preset interval H.

[0075] Further, in step S7, the walls of the plurality of through holes 105 and the upper surface of the third package 13 are subjected to metallization wiring treatment, which may include the following steps: Step S71: Deposit a second metal on the walls of the multiple vias 105 and on the first surface of the multiple chips 103; Step S72: The wiring unit 101 is fabricated through a series of processes including exposure, development, and electroplating.

[0076] Preferably, in step S71, a copper plating process can be used to deposit a second metal, which can be metallic copper, and the metallic copper can be an electroplating seed layer.

[0077] Specifically, in step S72, the wiring unit 101 includes a fourth wiring layer 1014, a third wiring layer 1013, a plurality of second copper pillars 1012, and a first metal layer 1011. That is, when fabricating the wiring unit 101, the fourth wiring layer 1014, the third wiring layer 1013, the plurality of second copper pillars 1012, and the first metal layer 1011 are sequentially fabricated on the first side of the plurality of chips 103.

[0078] As an example, the fourth wiring layer 1014 can serve as a base island for multiple chips 103.

[0079] As an example, the first metal layer 1011 can serve as an external pin of the package.

[0080] Furthermore, in step S8, the third package 13 is encapsulated using dielectric material 110 to obtain the fourth package 14.

[0081] Specifically, when encapsulating the third package 13, the first metal layer 1011 needs to be exposed.

[0082] Further, please refer to Figure 8 The chip packaging fabrication method further includes: Step S9: The fourth package 14 is flipped upside down and the multiple second copper pillars 1012 are exposed by mechanical grinding. Step S10: A second wiring layer 108 is fabricated on the plurality of second copper pillars 1012 through a series of processes including exposure, development and electroplating. Step S11: Use the first adhesive material 109 to fix the plurality of surface-mount devices 102 onto the second wiring layer 108; Step S12: Through reflow soldering process, the plurality of surface mount devices 102 are electrically connected to the second wiring layer 108; Step S13: Encapsulate the fourth package 14 with dielectric material 110 to obtain the final chip package structure 1.

[0083] As an example, in step S9, the dielectric material 110 can be planarized by a mechanical polishing process.

[0084] As an example, in step S11, the mounting positions of multiple surface-mount devices 102 can be determined based on the pad layout positions of the second wiring layer 108, the shape specifications of multiple surface-mount devices 102, the insulation safety distance between adjacent devices, and the process allowance required for encapsulation and filling.

[0085] As an example, the first adhesive material 109 and the second adhesive material 104 can be conductive adhesive materials, generally titanium-nickel-silver (TiNiAg), titanium-nickel-gold (TiNiAu), or cured silver paste.

[0086] As an example, encapsulation with dielectric material 110 can provide structural support and protect components from external damage.

[0087] In one embodiment, see Figure 9 The present invention also provides an electronic device, including a circuit board 2, wherein a chip package structure 1 is soldered to the circuit board 2 by solder balls 3, and the chip package structure 1 adopts a chip package structure as described above.

[0088] In summary, this invention establishes electrical connections between the active surfaces of multiple chips and the wiring layer through multiple vias; it also uses conductive adhesive materials to expose the electrical properties of the substrate on one side of the passive surfaces of multiple chips, enabling double-sided conductivity. Furthermore, this invention mounts the passive surfaces of multiple chips on the same horizontal plane, drills holes in the chips using a laser, and performs electroplating. The multiple chips are then electrically connected to the wiring layer through multiple vias, replacing the exposed bump interconnection caused by grinding. This avoids problems such as bump damage, over-grinding, and debris contamination caused by grinding, eliminates bump height tolerances, and improves packaging reliability. Finally, this invention uses a laser to drill multiple vias on multiple chips, and the opening thickness of the vias can be adaptively set according to the chip thickness, enabling the integration of heterogeneous chips of various thicknesses and specifications. This significantly improves production yield while further reducing costs, meeting the needs of mass production.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention.

Claims

1. A chip packaging structure, characterized in that, include, Multiple chips, wherein each chip receives a first electrical signal, processes the first electrical signal, and outputs a second electrical signal; Multiple vias are electrically connected to the chip, receive the second electrical signal, and output the second electrical signal to the first wiring layer; The first wiring layer is electrically connected to the plurality of vias for transmitting the second electrical signal.

2. The chip packaging structure according to claim 1, characterized in that, By adjusting the thickness of the via, the end of the via that is electrically connected to the first wiring layer is placed on the same horizontal plane.

3. The chip packaging structure according to claim 1, characterized in that, It also includes a wiring unit, which is electrically connected to the chip via a second adhesive material. The wiring unit receives a first electrical signal and transmits the first electrical signal to the chip. The wiring unit is electrically connected to the via and transmits a second electrical signal.

4. The chip packaging structure according to claim 1, characterized in that, It also includes a plurality of first copper pillars, the first copper pillars being electrically connected to the first wiring layer, the first copper pillars receiving the second electrical signal and transmitting the second electrical signal to the second wiring layer; The second wiring layer is electrically connected to the plurality of first copper pillars for transmitting the second electrical signal.

5. A chip packaging structure according to claim 4, characterized in that, It also includes at least one surface-mount device, which is electrically connected to a plurality of vias, or the surface-mount device is electrically connected to the second wiring layer through a first adhesive material, wherein the first adhesive material receives the second electrical signal and transmits the second electrical signal to the plurality of surface-mount devices; the surface-mount device receives the second electrical signal or outputs a third electrical signal.

6. A chip packaging structure according to claim 1, characterized in that, The first side of the chip is on the same horizontal plane, and the second side of the chip is electrically connected to the through hole.

7. A chip packaging fabrication method, used to fabricate a chip packaging structure as described in any one of claims 1 to 6, characterized in that, Includes the following steps: Step S1: Apply a temporary adhesive film to the surface of the carrier board, and attach the first side of multiple chips to the temporary adhesive film on the surface of the carrier board to form a first package. Step S2: Encapsulate the first package with a dielectric material to form a second package; Step S3: Drill holes in the upper surface of the second package using a laser to form multiple through holes; Step S4: Metallize the hole walls of the plurality of through holes and the upper surface of the second package body. Step S5: Encapsulate the second package with a dielectric material to form a third package; Step S6: Flip the third package over, remove the carrier plate and temporary adhesive film, and drill multiple through holes in the third package using a laser. Step S7: Metallize the walls of the multiple through holes and the upper surface of the third package body. Step S8: Encapsulate the third package with a dielectric material to obtain a fourth package.

8. The chip packaging fabrication method according to claim 7, characterized in that, Step S1 further includes: placing the first side of at least one surface-mount device on a temporary adhesive film on the surface of a carrier board.

9. A chip packaging fabrication method according to claim 7, characterized in that, In step S3, the through-hole is disposed on the plurality of chips, the through-hole is disposed on at least one surface mount device, and the through-hole is separated from the upper surface of the carrier board by a preset distance. When the via is disposed on multiple chips, the bottom of the via exposes the metal pads on the second surface of the multiple chips; when the via is disposed on at least one surface mount device, the bottom of the via exposes the metal pads on the second surface mount device; the preset distance between the via and the upper surface of the carrier board is not equal to zero.

10. A chip packaging fabrication method according to claim 7, characterized in that, In step S4, the metallization wiring process specifically includes: Step S41: Deposit a first metal on the inner wall of the multiple through holes; Step S42: Through a series of processes including exposure, development, and electroplating, a first wiring layer and multiple first copper pillars are sequentially fabricated on the multiple through holes.

11. A chip packaging fabrication method according to claim 7, characterized in that, Step S6 specifically includes the following steps: Step S61: Flip the third package over, remove the carrier board and temporary adhesive film, and expose the first side of multiple chips and at least one surface mount device. Step S62: Drill multiple through holes at a preset interval between the through holes and the upper surface of the carrier plate using a laser.

12. The chip packaging fabrication method according to claim 7, characterized in that, The chip packaging fabrication method further includes: Step S9: Flip the fourth package over and expose the multiple first copper pillars through a mechanical grinding process; Step S10: A second wiring layer is fabricated on the plurality of first copper pillars through a series of processes including exposure, development, and electroplating. Step S11: Use the first adhesive material to fix multiple surface-mount devices onto the second wiring layer; Step S12: Through reflow soldering process, the plurality of surface mount devices are electrically connected to the second wiring layer; Step S13: Encapsulate the fourth package using a dielectric material to obtain a chip package structure.

13. An electronic device, characterized in that, Includes a circuit board and a chip packaging structure soldered onto the circuit board as described in any one of claims 1 to 6.

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