Packaging structure, packaging substrate and its fabrication method

Abstract

This invention discloses a packaging structure, a packaging substrate, and a method for fabricating the same. The packaging structure includes a packaging substrate, a chip, and multiple solder balls. The packaging substrate includes a silicon-containing substrate, multiple silicon-integrated passive components, multiple metal frame walls, multiple conductive via structures, multiple blind via structures, and a first and a second circuit structure layer. The silicon-integrated passive components are respectively bonded to multiple recesses in the silicon-containing substrate. The metal frame walls are respectively disposed within the recesses of the silicon-containing substrate and contact the surrounding surface of the silicon-integrated passive components and the inner wall of the recesses. The blind via structures extend from a second surface of the silicon-containing substrate towards and connect to the metal frame walls. The first and second circuit structure layers are respectively disposed on a first and a second surface of the silicon-containing substrate. The chip and solder balls are respectively disposed on the first and second circuit structure layers of the packaging substrate.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and its fabrication method, and particularly to a packaging structure and packaging substrate and its fabrication method. Background Technology

[0002] Existing flip-chip ball grid array (FCBGA) packages typically use an organic substrate as the core layer, and cavities are drilled through the core layer using laser or mechanical drilling to embed passive components (such as integrated passive devices (IPDs) or multi-layer ceramic capacitors (MLCCs)). When the core layer thickness exceeds 800 micrometers, mechanical drilling is the only option for forming the cavities, but this method has poor alignment accuracy, affecting the precision of passive component embedding. Furthermore, after placing the passive components in the cavities, resin needs to be filled into the cavities to fix / position the passive components. However, the mismatch in the coefficients of thermal expansion (CTE) between the various heterogeneous materials such as passive components, resin, and metal layers within the organic substrate leads to significant stress under thermal cycling, thus affecting the overall structural reliability of the package.

[0003] Furthermore, since the cavity edges (especially corners) of the organic substrate are stress concentration zones, copper rings are needed to buffer and release this stress, with resin positioned between the passive components and the copper rings. Additionally, the copper rings are disposed on the surface of the organic substrate to enhance its rigidity. However, design limitations exist regarding the width of the copper rings (typically 60 micrometers or more), the distance between the passive components and the copper rings (typically 125 micrometers or more), and the minimum spacing between adjacent passive components (typically 900 micrometers or more). These limitations result in low passive component density, and signal transmission paths must bypass these restricted areas, leading to longer signal transmission paths. This not only increases signal delay, loss, and crosstalk but also severely impacts high-frequency signal integrity and power integrity, thus limiting the overall system performance of the package structure. Summary of the Invention

[0004] This invention provides a packaging structure that has better structural reliability.

[0005] The present invention also provides a packaging substrate that has better heat dissipation and can improve electrical performance.

[0006] The present invention also provides a method for manufacturing a packaging substrate, for manufacturing the above-mentioned packaging substrate.

[0007] The packaging structure of the present invention includes a packaging substrate, a chip, and a plurality of solder balls. The packaging substrate includes a silicon-containing substrate, a plurality of silicon-integrated passive components, a plurality of metal frame walls, a plurality of conductive via structures, a plurality of blind via structures, a first wiring layer, and a second wiring layer. The silicon-containing substrate has a first surface and a second surface opposite to each other, and a plurality of grooves extending from the first surface to the second surface. The silicon-integrated passive components are respectively bonded within the grooves of the silicon-containing substrate. The metal frame walls are respectively disposed within the grooves of the silicon-containing substrate and contact the surrounding surfaces of the silicon-integrated passive components and the inner walls of the grooves. The conductive via structures penetrate the silicon-containing substrate and extend to the first surface and the second surface. The blind via structures extend from the second surface of the silicon-containing substrate to the metal frame walls and connect to the metal frame walls. The first wiring layer is disposed on the first surface of the silicon-containing substrate and electrically connects the conductive via structures to the silicon-integrated passive components. The second wiring layer is disposed on the second surface of the silicon-containing substrate and electrically connects the conductive via structures to the blind via structures. The chip is disposed on and electrically connected to the first circuit structure layer of the packaging substrate. The solder balls are disposed on and electrically connected to the second circuit structure layer of the packaging substrate.

[0008] The packaging substrate of the present invention includes a silicon-containing substrate, a plurality of silicon-containing integrated passive components, a plurality of metal frame walls, a plurality of conductive via structures, a plurality of blind via structures, a first wiring layer, and a second wiring layer. The silicon-containing substrate has a first surface and a second surface opposite to each other, and a plurality of grooves extending from the first surface to the second surface. The silicon-containing integrated passive components are respectively bonded within the grooves of the silicon-containing substrate. The metal frame walls are respectively disposed within the grooves of the silicon-containing substrate and contact the peripheral surfaces of the silicon-containing integrated passive components and the inner walls of the grooves. The conductive via structures penetrate the silicon-containing substrate and extend to the first surface and the second surface. The blind via structures extend from the second surface of the silicon-containing substrate to the metal frame walls and are connected to the metal frame walls. The first wiring layer is disposed on the first surface of the silicon-containing substrate and electrically connects the conductive via structures to the silicon-containing integrated passive components. The second wiring layer is disposed on the second surface of the silicon-containing substrate and electrically connects the conductive via structures to the blind via structures.

[0009] The present invention provides a method for fabricating a packaging substrate, comprising the following steps: Providing a silicon-containing substrate having a first surface and a second surface opposite to each other. Forming a plurality of grooves extending from the first surface of the silicon-containing substrate to the second surface. Bonding a plurality of silicon-integrated passive components into the grooves of the silicon-containing substrate. Forming a plurality of metal frame walls into the grooves of the silicon-containing substrate, wherein the metal frame walls contact the peripheral surfaces of the silicon-integrated passive components and the inner walls of the grooves. Forming a plurality of conductive via structures and a plurality of blind via structures. The conductive via structures penetrate the silicon-containing substrate and extend to the first surface and the second surface. The blind via structures extend from the second surface of the silicon-containing substrate to the metal frame walls and connect to the metal frame walls. Forming a first wiring structure layer on the first surface of the silicon-containing substrate. The first wiring structure layer electrically connects the conductive via structures and the silicon-integrated passive components. Forming a second wiring structure layer on the second surface of the silicon-containing substrate. The second wiring structure layer electrically connects the conductive via structures and connects the blind via structures.

[0010] Based on the above, in the design of the packaging substrate of the present invention, by bonding the silicon-integrated passive component into the groove of the silicon-integrated substrate, wherein the coefficients of thermal expansion of the two are the same or similar, the core of the packaging substrate can be made more homogeneous, effectively reducing the impact of thermal stress. Furthermore, the present invention utilizes a metal frame wall contacting the surrounding surface of the silicon-integrated passive component and a blind via structure contacting the metal frame wall, thereby effectively increasing the heat dissipation path and improving performance and reliability in high-frequency, high-current, and high-power applications. In addition, the packaging structure using the packaging substrate of the present invention has better structural reliability.

[0011] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0012] Figure 1A This is a cross-sectional schematic diagram of a packaging structure according to an embodiment of the present invention;

[0013] Figure 1B yes Figure 1A A top view of the silicon-integrated passive components and conductive via structures in the diagram.

[0014] Figure 1C This is a top view schematic diagram of a silicon-integrated passive component and conductive via structure according to another embodiment of the present invention;

[0015] Figure 2 This is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention;

[0016] Figures 3A to 3M This is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate according to an embodiment of the present invention.

[0017] Symbol Explanation

[0018] 10a, 10b: Package structure

[0019] 100, 100a, 100b: Packaging substrate

[0020] 110: Silicon-containing substrate

[0021] 111: First Surface

[0022] 112: Groove

[0023] 113: Second Surface

[0024] 114: Bottom surface

[0025] 120: Silicon-integrated passive components

[0026] 122:Contact

[0027] 130: Metal frame wall

[0028] 131: Top surface

[0029] 140: Conductive through-hole structure

[0030] 142: First conductive via structure

[0031] 144: Second conductive via structure

[0032] 150a, 150b: Blind hole structure

[0033] 160: First line structure layer

[0034] 162, 172: Insulation layer

[0035] 164, 174: Conductive layer

[0036] 170: Second line structure layer

[0037] 180: First solder resist layer

[0038] 182: First weld guard opening

[0039] 185: Connector

[0040] 190, 190a, 190b: Second solder resist layer

[0041] 192, 192a, 192b: Second weld guard opening

[0042] 200: Chip

[0043] 300: Welding ball

[0044] 400: Base Rubber

[0045] A: Gap

[0046] B: Blind hole

[0047] D: Aperture

[0048] G: Spacing

[0049] H, H': Horizontal spacing

[0050] P1: First bonding pad

[0051] P2: Second bonding pad

[0052] PR: Photoresist layer

[0053] M1, M2: Metallic materials

[0054] S1, S2: Signal paths

[0055] S3: Power / Ground Path

[0056] T: Through hole

[0057] W: Width Detailed Implementation

[0058] The embodiments of the present invention can be understood in conjunction with the accompanying drawings, which are also considered part of the disclosure. It should be understood that the drawings are not drawn to scale; in fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly illustrate the features of the invention.

[0059] Figure 1A This is a cross-sectional schematic diagram of a packaging structure according to an embodiment of the present invention. Figure 1B yes Figure 1A A top view of the silicon-integrated passive components and conductive via structures. Figure 1C This is a top view schematic diagram of a silicon-integrated passive component and conductive via structure according to another embodiment of the present invention.

[0060] Please refer to this first. Figure 1AIn this embodiment, the package structure 10a includes a package substrate 100a, a chip 200, and a plurality of solder balls 300. The package substrate 100a includes a silicon-containing substrate 110, a plurality of silicon-integrated passive components 120, a plurality of metal frame walls 130, a plurality of conductive via structures 140, a plurality of blind via structures 150a, a first circuit structure layer 160, and a second circuit structure layer 170. The silicon-containing substrate 110 has a first surface 111 and a second surface 113 opposite to each other, and a plurality of grooves 112 extending from the first surface 111 to the second surface 113. The silicon-integrated passive components 120 are respectively bonded within these grooves 112 of the silicon-containing substrate 110. The metal frame walls 130 are respectively disposed within these grooves 112 of the silicon-containing substrate 110 and contact the surrounding surfaces of the silicon-integrated passive components 120 and the inner walls of the grooves 112. In other words, the metal frame walls 130 surround the silicon-integrated passive components 120. In one embodiment, the top view of the metal frame 130 is a rectangular metal frame surrounding the silicon-integrated passive component 120, such as... Figure 1B or Figure 1C The diagram is shown, but is not intended to limit the invention. In other embodiments not shown, the top view of the metal frame 130 may be a polygonal metal frame, or it may be a circular or elliptical metal frame, the shape of which depends on the requirements. The conductive via structures 140 penetrate the silicon-containing substrate 110 and extend to the first surface 111 and the second surface 113, respectively. The blind via structures 150a extend from the second surface 113 of the silicon-containing substrate 110 to the metal frame walls 130 and connect to them. A first wiring layer 160 is disposed on the first surface 111 of the silicon-containing substrate 110 and electrically connects the conductive via structures 140 to the silicon-containing integrated passive components 120. A second wiring layer 170 is disposed on the second surface 113 of the silicon-containing substrate 110 and electrically connects the conductive via structures 140 to the blind via structures 150a. Chip 200 is disposed on and electrically connected to the first circuit structure layer 160 of the packaging substrate 100a. Solder balls 300 are disposed on and electrically connected to the second circuit structure layer 170 of the packaging substrate 100a.

[0061] In one embodiment, the silicon-containing substrate 110 is, for example, a glass substrate, a ceramic substrate, or a glass-ceramic substrate. Compared to the organic substrates used in the prior art, the silicon-containing substrate 110 in this embodiment can have better mechanical strength, dimensional stability, and thermal stability. The silicon-integrated passive components 120 are directly bonded to the grooves 112 of the silicon-containing substrate 110, meaning that there are no other component layers (such as adhesive layers) between the silicon-integrated passive components 120 and the grooves 112. In one embodiment, each silicon-integrated passive component 120 is, for example, a silicon-based integrated passive component or a glass-based integrated passive component. Here, the integrated passive component is, for example, an integrated capacitor, resistor, inductor, or other passive component to provide electrical functionality. Since the packaging substrate 100a uses a silicon-containing substrate 110 and silicon-integrated passive components 120 with the same or similar coefficients of thermal expansion, the core of the packaging substrate 100a can be more homogeneous, effectively reducing the impact of thermal stress. It should be noted that if the silicon-containing material is glass, the cost can be reduced and it has lower dielectric loss, making it more suitable for high-frequency artificial intelligence (AI) applications.

[0062] These metal frame walls 130 are respectively disposed within the recesses 112 of the silicon-containing substrate 110 and contact the surrounding surfaces of the silicon-integrated passive components 120 and the inner walls of the recesses 112. That is, the recesses 112 only contain the silicon-integrated passive components 120 and the metal frame walls 130 that directly contact the surrounding surfaces of the silicon-integrated passive components 120. The metal frame walls 130 are in direct contact with the corresponding silicon-integrated passive components 120, meaning there are no other component layers (such as resin layers) between the metal frame walls 130 and the silicon-integrated passive components 120. In one embodiment, the material of the metal frame walls 130 is, for example, copper, but is not limited thereto.

[0063] These conductive via structures 140 may include a plurality of first conductive via structures 142, wherein each first conductive via structure 142 may be located between two adjacent silicon-integrated passive components 120. Additionally, these conductive via structures 140 may also include a plurality of second conductive via structures 144, wherein these second conductive via structures 144 are located around the first conductive via structures 142. That is, these second conductive via structures 144 surround the first conductive via structures 142. Here, the orthographic projection of the chip 200 on the packaging substrate 100a overlaps these first conductive via structures 142 and these silicon-integrated passive components 120. In other words, these first conductive via structures 142 and these silicon-integrated passive components 120 are located within the orthographic projection range of the chip 200. Since these silicon-integrated passive components 120 are located within the recesses 112 of the silicon-containing substrate 110, the shortest connection path between these silicon-integrated passive components 120 and the chip 200 can be achieved, optimizing electrical performance.

[0064] Please also refer to Figure 1A and Figure 1B A first conductive via structure 142 is located between two silicon-integrated passive components 120, wherein the first conductive via structure 142 has an aperture D. In one embodiment, the aperture D is, for example, 25 micrometers. In one embodiment, a metal frame wall 130 has a width W, wherein the width W is, for example, 20 micrometers. In one embodiment, a spacing G is provided between the metal frame wall 130 and the first conductive via structure 142, wherein the spacing G is, for example, 15 micrometers. In one embodiment, a horizontal spacing H is provided between adjacent silicon-integrated passive components 120, wherein the horizontal spacing H is, for example, 95 micrometers. In another embodiment, please refer to... Figure 1C If no first conductive via structure 142 is provided between the two silicon-integrated passive components 120, the horizontal spacing H' between the two silicon-integrated passive components 120 is, for example, 55 micrometers. Compared to the prior art, where passive components are disposed in the cavity of an organic substrate and the minimum distance between adjacent passive components is typically at least 900 micrometers, this embodiment effectively reduces the horizontal spacing H, H' between the two silicon-integrated passive components 120 by using a silicon-integrated substrate 110 with grooves 112 and without requiring additional resin filling.

[0065] Please refer to this again. Figure 1A These blind via structures 150a extend from the second surface 113 of the silicon substrate 110 toward and connect to the metal frame walls 130. In other words, these blind via structures 150a are directly connected to their corresponding metal frame walls 130. Here, these blind via structures 150a are, for example, multiple non-conductive blind via structures, meaning they do not have electrical conduction functions and are only used for heat dissipation; they can also be called thermally conductive blind via structures. Therefore, the blind via structures 150a and their corresponding metal frame walls 130 form a heat dissipation path, enabling the corresponding silicon-integrated passive component 120 to have lower thermal stress and better power integrity, thereby generating lower voltage ripple. In other words, the combination of multiple blind via structures 150a and metal frame walls 130 can reduce the thermal stress caused by the mismatch in the coefficient of thermal expansion within the package substrate 100a, improving performance and reliability in high-frequency, high-current, and high-power applications.

[0066] A first wiring structure layer 160 disposed on a first surface 111 of a silicon-containing substrate 110 may include an insulating layer 162 and a conductive layer 164. The conductive layer 164 may have conductive and / or signal transmission functions, and may be, for example, a circuit, a conductive via, a conductive blind via, a connecting pad, or a combination thereof. The layout design of the circuit can be adjusted as needed and is not limited thereto. For example, in the wiring of the first wiring structure layer 160, portions not connected in the figures may be electrically connected through other unshown areas and / or other conductive elements. In one embodiment, the first wiring structure layer 160 may be, for example, a fan-out overlay circuit layer, but is not limited thereto.

[0067] The second wiring structure layer 170 disposed on the second surface 113 of the silicon-containing substrate 110 may include an insulating layer 172 and a conductive layer 174. The conductive layer 174 may have conductive and / or signal transmission functions, and may be, for example, a circuit, a conductive via, a conductive blind via, a connecting pad, or a combination thereof. The wiring design of the circuit can be adjusted as needed and is not limited thereto. For example, in the wiring of the second wiring structure layer 170, portions not connected in the figures may be electrically connected through other unshown areas and / or other conductive elements. In one embodiment, the second wiring structure layer 170 may be, for example, a fan-out overlay wiring layer, but is not limited thereto. In one embodiment, the line width / space (L / S) of the first wiring structure layer 160 may be the same as or different from the line width / space of the second wiring structure layer 170.

[0068] Furthermore, the packaging substrate 100a of this embodiment also includes a first solder resist layer 180 and a second solder resist layer 190a. The first solder resist layer 180 is disposed on the first circuit structure layer 160, and the first solder resist opening 182 of the first solder resist layer 180 exposes a portion of the conductive layer 164 of the first circuit structure layer 160, thereby defining a plurality of first pads P1. Here, the first pads P1 are specifically defined as solder mask defined (SMD) pads. The second solder resist layer 190a is disposed on the second circuit structure layer 170, and the second solder resist opening 192a of the second solder resist layer 190a exposes a portion of the conductive layer 174 of the second circuit structure layer 170, thereby defining a plurality of second pads P2. Here, the second pads P2 are specifically defined as solder mask defined (SMD) pads.

[0069] Furthermore, the packaging substrate 100a of this embodiment also includes a plurality of connectors 185 disposed on the first circuit structure layer 160 and located on the first pad P1, wherein the chip 200 is electrically connected to the first circuit structure layer 160 through these connectors 185. In one embodiment, the connectors 185 may be, for example, solder ball bumps or copper-containing solder ball bumps. These solder balls 300 are disposed on the second pad P2 and electrically connected to the second circuit structure layer 170, wherein these solder balls 300 can be electrically connected to external circuitry. In addition, in this embodiment, the packaging structure 10a also includes a primer 400 disposed between the chip 200 and the first circuit structure layer 160, wherein the primer 400 covers these connectors 185 to protect them.

[0070] Because the overall structure formed by using a silicon-containing substrate 110 and silicon-integrated passive components 120 in this embodiment has better rigidity, a first conductive via structure 142 can be configured between the two silicon-integrated passive components 120, and the orthographic projection of the chip 200 on the packaging substrate 100a overlaps these first conductive via structures 142 and these silicon-integrated passive components 120. Therefore, a signal path S1 can be formed from the connector 185 directly below the chip 200, through the conductive layer 164 of the first circuit structure layer 160, the first conductive via structure 142, the conductive layer 174 of the second circuit structure layer 170 to the solder ball 300. Here, the signal path S1 is also within the range of the orthographic projection on the chip 200 and the packaging substrate 100a. Therefore, compared with the signal transmission path in the prior art that needs to bypass the setting of the restriction area, the signal path S1 of this embodiment is shorter, which can effectively reduce / avoid the problems of signal delay, loss and crosstalk, and can have better high-frequency signal integrity.

[0071] In short, by using the same or similar materials, this embodiment can achieve a better match in the coefficient of thermal expansion (CTE) between the silicon-containing substrate 110 and the silicon-containing integrated passive component 120, making the core of the packaging substrate 100a more homogeneous and thus reducing thermal stress. Furthermore, by bonding the silicon-containing integrated passive component 120 within the recess 112 of the silicon-containing substrate 110 and utilizing the metal frame wall 130 and multiple blind via structures 150, this embodiment effectively increases the heat dissipation path, thereby reducing thermal stress caused by the mismatch in coefficient of thermal expansion and improving performance and reliability in high-frequency, high-current, and high-power applications. In addition, the packaging structure 10a of the packaging substrate 100a in this embodiment significantly shortens the spacing between the chip 200 and the silicon-containing integrated passive component 120, the horizontal spacing H between adjacent silicon-containing integrated passive components 120, and the signal transmission path, making it more suitable for advanced packaging applications involving high frequency, high current, and high power.

[0072] It should be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals used to represent the same or similar components, and descriptions of the same technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0073] Figure 2 This is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Please also refer to... Figure 1A and Figure 2 The packaging structure 10b in this embodiment is similar to the packaging structure 10a described above, except that the main difference is that in this embodiment, the blind via structures 150b of the packaging substrate 100b are specifically implemented as multiple conductive blind via structures, which have the function of conducting electricity, or have the functions of conducting electricity and heat simultaneously. In addition, the position of the second solder mask opening 192b of the second solder mask layer 190b of the packaging substrate 100b is different from the position of the second solder mask opening 192a of the second solder mask layer 190a of the packaging substrate 100a, so that the shortest signal path S2 can be formed from the connector 185 directly below the chip 200, through the conductive layer 164 of the first circuit structure layer 160, the first conductive via structure 142, the conductive layer 174 of the second circuit structure layer 170 to the solder ball 300. On the other hand, a shortest power / ground path S3 can be formed from the connector 185 directly below the chip 200, through the conductive layer 164 of the first circuit structure layer 160, the metal frame wall 130, the blind via structure 150b, the conductive layer 174 of the second circuit structure layer 170, to the solder ball 300, which can significantly improve power integrity and signal integrity. In short, the metal frame wall 130 and the blind via structure 150b in this embodiment not only provide heat dissipation but also serve as power lines or ground paths.

[0074] Figures 3A to 3M This is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate according to an embodiment of the present invention. According to the method for manufacturing the packaging substrate of this embodiment, firstly, please refer to... Figure 3A A silicon-containing substrate 110 is provided, wherein the silicon-containing substrate 110 has a first surface 111 and a second surface 113 opposite to each other. In one embodiment, the silicon-containing substrate 110 is, for example, a glass substrate, a ceramic substrate, or a glass-ceramic substrate.

[0075] Next, please refer to Figure 3BA plurality of grooves 112 are formed extending from the first surface 111 of the silicon-containing substrate 110 to the second surface 113. Here, the grooves 112 do not penetrate the silicon-containing substrate 110, but are grooves 112 with a bottom surface 114, wherein there is a height difference between the bottom surface 114 and the second surface 113. In one embodiment, the method for forming the grooves 112 extending from the first surface 111 to the second surface 113 of the silicon-containing substrate 110 is, for example, laser-induced depth etching, in which the laser depth is controlled by computer calculation, achieving extremely high precision, a high aspect ratio (greater than 10:1), no cracks or heat-affected zones, and precise control over the dimensions of the grooves 112.

[0076] Next, please refer to Figure 3C Multiple silicon-integrated passive components 120 are respectively bonded within the grooves 112 of the silicon-integrated substrate 110, wherein the contacts 122 of each silicon-integrated passive component 120 face upwards and away from the grooves 112, so as to facilitate the subsequent formation of the first circuit structure layer 160 (see reference). Figure 3L Electrical connection. In one embodiment, the method for bonding these silicon-integrated passive components 120 to the grooves 112 of the silicon-integrated substrate 110 is, for example, laser welding. Since the silicon-integrated passive components 120 and the silicon-integrated substrate 110 are made of the same or similar materials, when the silicon-integrated passive components 120 are bonded to the bottom surface 114 of the grooves 112 of the silicon-integrated substrate 110 by laser welding, the silicon-integrated passive components 120 and the silicon-integrated substrate 110 can be directly bonded without the need for an adhesive layer, ensuring a tight and homogeneous bond and eliminating the problem of thermal expansion coefficient mismatch that may be caused by adhesive layers in the prior art. In one embodiment, each silicon-integrated passive component 120 is, for example, a silicon-based integrated passive component or a glass-based integrated passive component. Here, each silicon-integrated passive component 120 is spaced apart from the inner wall of the corresponding groove 112, with an air gap between them.

[0077] Next, please refer to Figure 3D A photoresist layer PR is formed on the first surface 111 of the silicon-containing substrate 110, wherein the photoresist layer PR covers the first surface 111, the grooves 112, and the contacts 122 of the silicon-containing integrated passive components 120.

[0078] Next, please refer to Figure 3E A patterned photoresist layer PR' is formed by photolithography, wherein the patterned photoresist layer PR' exposes the gap A between the groove 112 and the silicon-integrated passive element 120.

[0079] Next, please refer to Figure 3FAn electroplating seed layer (not shown) is formed by sputtering or chemical deposition, and a metal material M1 is electroplated onto the patterned photoresist layer PR' and into the gap A between the groove 112 and the silicon-integrated passive element 120 using this electroplating seed layer.

[0080] Next, please refer to the following: Figure 3F as well as Figure 3G The metal material M1 located on the patterned photoresist layer PR' is removed, leaving only the metal material M1 within the gap A between the groove 112 and the silicon-integrated passive element 120, thus defining a metal frame wall 130. The shape of this metal frame wall 130 is related to the shape of the gap A. At this point, multiple metal frame walls 130 have been formed within the grooves 112 of the silicon-integrated substrate 110, wherein these metal frame walls 130 contact the surrounding surfaces of the silicon-integrated passive elements 120 and the inner walls of the grooves 112. That is, these metal frame walls 130 directly contact the corresponding silicon-integrated passive elements 120, without any other element layers (such as resin layers) between them. In one embodiment, the method for removing part of the metal material M1 is, for example, etching.

[0081] Next, please refer to Figure 3H The patterned photoresist layer PR' is removed, for example, by peeling, exposing the first surface 111 of the silicon-containing substrate 110 and the contacts 122 of the silicon-containing integrated passive components 120. In one embodiment, the top surface 131 of the metal frame wall 130 may be flush with the first surface 111 of the silicon-containing substrate 110, that is, the top surface 131 of the metal frame wall 130 is coplanar with the first surface 111. In another embodiment, the top surface 131 of the metal frame wall 130 may be slightly lower than the first surface 111 of the silicon-containing substrate 110, that is, the top surface 131 of the metal frame wall 130 is not coplanar with the first surface 111.

[0082] It should be noted that the depth of the groove 112 can be matched with the thickness / height of the silicon-integrated passive component 120. For example, if the thickness of the silicon-integrated passive component 120 is 500 micrometers, the depth of the groove 112 can be controlled between approximately 500 and 510 micrometers, ensuring that the silicon-integrated passive component 120 is nearly flush with the first surface 111 of the silicon-integrated substrate 110. On the other hand, the width of the groove 112 is approximately equal to the width of the silicon-integrated passive component 120 plus the width of the metal frame wall 130. That is, only the silicon-integrated passive component 120 and the metal frame wall 130 that directly contacts the surrounding surface of the silicon-integrated passive component 120 are disposed in the groove 112, meaning that there are no other component layers (such as resin layers) between the metal frame wall 130 and the silicon-integrated passive component 120.

[0083] Next, please refer to Figure 3I A laser-induced deep etching process is performed on the silicon substrate 110 to form a plurality of through holes T penetrating the silicon substrate 110 and a plurality of blind holes B extending from the second surface 113 of the silicon substrate 110 toward these metal frame walls 130.

[0084] Next, please refer to the following: Figure 3I and Figure 3J An electroplating seed layer (not shown) is formed by sputtering or chemical deposition, and a metal material M2 is electroplated onto the through-holes T, the blind vias B, and the first surface 111 and the second surface 113 of the silicon substrate 110 using this seed layer. Next, the metal material M2 is patterned to form the conductive via structures 140 and the blind via structures 150. Here, the conductive via structures 140 penetrate the silicon substrate 110 and extend to the first surface 111 and the second surface 113, respectively. These conductive via structures 140 include a plurality of first conductive via structures 142, wherein each first conductive via structure 142 is located between two adjacent silicon-integrated passive components 120. These conductive via structures 140 also include a plurality of second conductive via structures 144, wherein these second conductive via structures 144 are located around the first conductive via structures 142. These blind via structures 150 extend from the second surface 113 of the silicon substrate 110 toward and connect to the metal frame walls 130. These blind via structures 150 can be configured as multiple non-conductive blind via structures (e.g., ...) as needed. Figure 1A Blind hole structure 150a) or multiple conductive blind hole structures (such as Figure 2 Blind hole structure 150b). Figure 1A The blind hole structure 150a is, for example, a thermally conductive blind hole structure.

[0085] Next, please refer to Figure 3K A patterned insulating layer 162 is formed on the first surface 111 of the silicon-containing substrate 110, and a patterned insulating layer 172 is formed on the second surface 113 of the silicon-containing substrate 110. At this time, the patterned insulating layer 162 and the patterned insulating layer 172 expose the first conductive via structures 142, the second conductive via structures 144, and the blind via structures 150.

[0086] Next, please refer to Figure 3LA first circuit structure layer 160 is formed on the first surface 111 of the silicon-containing substrate 110 through a build-up fabrication process, and a second circuit structure layer 170 is formed on the second surface 113 of the silicon-containing substrate 110. The first circuit structure layer 160 may include an insulating layer 162 and a conductive layer 164. The conductive layer 164 may have conductive and / or signal transmission functions, such as circuits, conductive vias, conductive blind vias, connecting pads, or combinations thereof, wherein the wiring design of the circuits can be adjusted as needed and is not limited thereto. The first circuit structure layer 160 electrically connects these conductive via structures 140 to these silicon-integrated passive components 120. The second circuit structure layer 170 may include an insulating layer 172 and a conductive layer 174. The conductive layer 174 may have conductive and / or signal transmission functions, such as circuits, conductive vias, conductive blind vias, connecting pads, or combinations thereof, wherein the wiring design of the circuits can be adjusted as needed and is not limited thereto. The second circuit structure layer 170 electrically connects these conductive via structures 140 to these blind via structures 150.

[0087] Next, please refer to Figure 3L A first solder resist layer 180 is formed on the first circuit structure layer 160, and a second solder resist layer 190 is formed on the second circuit structure layer 170. Here, a first solder resist opening 182 of the first solder resist layer 180 exposes a portion of the conductive layer 164 of the first circuit structure layer 160, defining a plurality of first pads P1. A second solder resist opening 192 of the second solder resist layer 190 exposes a portion of the conductive layer 174 of the second circuit structure layer 170, defining a plurality of second pads P2. Here, the first pads P1 and the second pads P2 are respectively embodied as solder mask defined (SMD) pads.

[0088] Finally, please refer to Figure 3M Multiple connectors 185 are formed on the first circuit structure layer 160 and located on the first pad P1. In one embodiment, the connectors 185 may be, for example, solder ball bumps or copper-containing solder ball bumps. At this point, the fabrication of the package substrate 100 is complete.

[0089] Structurally, please refer to [the relevant documentation / reference]. Figure 3MIn this embodiment, the packaging substrate 100 includes a silicon-containing substrate 110, a plurality of silicon-integrated passive components 120, a plurality of metal frame walls 130, a plurality of conductive via structures 140, a plurality of blind via structures 150, a first wiring layer 160, and a second wiring layer 170. The silicon-containing substrate 110 has a first surface 111 and a second surface 113 opposite to each other, and a plurality of grooves 112 extending from the first surface 111 to the second surface 113. The silicon-integrated passive components 120 are respectively bonded within the grooves 112 of the silicon-containing substrate 110. The metal frame walls 130 are respectively disposed within the grooves 112 of the silicon-containing substrate 110 and contact the surrounding surfaces of the silicon-integrated passive components 120 and the inner walls of the grooves 112. The conductive via structures 140 penetrate the silicon-containing substrate 110 and extend to the first surface 111 and the second surface 113. These conductive via structures 140 include a plurality of first conductive via structures 142, each first conductive via structure 142 being located between adjacent silicon-integrated passive components 120. These conductive via structures 140 also include a plurality of second conductive via structures 144, which are located around the first conductive via structures 142. These blind via structures 150 extend from the second surface 113 of the silicon-integrated substrate 110 toward and connect to the metal frame walls 130. A first wiring layer 160 is disposed on the first surface 111 of the silicon-integrated substrate 110 and electrically connects the conductive via structures 140 to the silicon-integrated passive components 120. A second wiring layer 170 is disposed on the second surface 113 of the silicon-integrated substrate 110 and electrically connects the conductive via structures 140 to the blind via structures 150.

[0090] Furthermore, the packaging substrate 100 of this embodiment also includes a first solder resist layer 180 and a second solder resist layer 190. The first solder resist layer 180 is disposed on the first circuit structure layer 160 and exposes a portion of the first circuit structure layer 160, defining a plurality of first pads P1. The second solder resist layer 190 is disposed on the second circuit structure layer 170 and exposes a portion of the second circuit structure layer 170, defining a plurality of second pads P2. In addition, the packaging substrate 100 of this embodiment also includes a plurality of connectors 185 disposed on the first circuit structure layer 160 and located on the first pads P1.

[0091] In applications, the packaging substrate 100 is suitable for connecting at least one chip (such as...). Figure 1A and Figure 2The chip 200 in the package substrate 100 has its orthographic projection superimposed on the first conductive via structures 142 and the silicon-integrated passive components 120. Since the contacts 122 of the silicon-integrated passive components 120 in this embodiment are electrically connected to the first circuit structure layer 160 with their contacts facing upwards, the connection length between them and the chip 200 can be shortened.

[0092] In summary, in the fabrication of the packaging substrate 100 in this embodiment, since there is no need to form a cavity penetrating the silicon-containing substrate 110 to accommodate the silicon-integrated passive components 120, fabrication process steps can be saved and cycle time shortened. Furthermore, silicon-integrated passive components 120 of different thicknesses can be selected more flexibly. Moreover, compared to the design of flip-chip ball grid array (FCBGA) packages in the prior art, this embodiment does not require the fabrication of copper rings to buffer cavity edge stress, saving fabrication process steps, wiring space, and reducing costs. In addition, the fabrication of the packaging substrate 100 in this embodiment can minimize component spacing, achieving maximum density of silicon-integrated passive components 120, and the conductive via structures 140 provided between the silicon-integrated passive components 120 can increase the flexibility of wiring arrangements.

[0093] In summary, in the design of the packaging substrate of this invention, by bonding the silicon-integrated passive component into the recess of the silicon-integrated substrate, where the coefficients of thermal expansion of both are the same or similar, the core of the packaging substrate can be made more homogeneous, effectively reducing the impact of thermal stress. Furthermore, this invention utilizes a metal frame wall contacting the surrounding surface of the silicon-integrated passive component and a multiple blind via structure contacting the metal frame wall, thereby effectively increasing the heat dissipation path and improving performance and reliability in high-frequency, high-current, and high-power applications. In addition, the packaging structure using the packaging substrate of this invention offers superior structural reliability.

[0094] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A packaging structure, comprising: Packaging substrate, including: A silicon-containing substrate having a first surface and a second surface opposite to each other, and a plurality of grooves extending from the first surface to the second surface; Multiple silicon-integrated passive components are respectively bonded to the grooves of the silicon-integrated substrate; Multiple metal frame walls are respectively disposed in the grooves of the silicon-containing substrate and contact the surrounding surface of the silicon-containing integrated passive components and the inner wall of the grooves; Multiple conductive via structures penetrate the silicon-containing substrate and extend to the first surface and the second surface, respectively; Multiple blind via structures extend from the second surface of the silicon-containing substrate toward and connect to the metal frame walls; A first circuit structure layer is disposed on the first surface of the silicon-containing substrate and electrically connects the conductive via structures to the silicon-containing integrated passive components; and The second circuit structure layer is disposed on the second surface of the silicon-containing substrate and electrically connects the conductive via structures and the blind via structures. A chip is disposed on the first circuit structure layer of the packaging substrate and electrically connected to the first circuit structure layer; and Multiple solder balls are disposed on the second circuit structure layer of the packaging substrate and are electrically connected to the second circuit structure layer.

2. The packaging structure of claim 1, wherein the conductive via structures include a plurality of first conductive via structures, and each of the first conductive via structures is located between two adjacent silicon-integrated passive components.

3. The packaging structure as described in claim 2, wherein the conductive via structures further include a plurality of second conductive via structures, and the second conductive via structures are located around the first conductive via structures.

4. The packaging structure of claim 2, wherein the orthographic projection of the chip onto the packaging substrate overlaps the first conductive via structures and the silicon-integrated passive components.

5. The packaging structure as claimed in claim 1, wherein the packaging substrate further includes a plurality of connectors disposed on the first circuit structure layer, wherein the chip is electrically connected to the first circuit structure layer through the connectors.

6. The packaging structure of claim 1, wherein the silicon-containing substrate comprises a glass substrate, a ceramic substrate, or a glass-ceramic substrate.

7. The packaging structure of claim 1, wherein each of the silicon-integrated passive components comprises a silicon-based integrated passive component or a glass-based integrated passive component.

8. A packaging substrate, comprising: A silicon-containing substrate having a first surface and a second surface opposite to each other, and a plurality of grooves extending from the first surface to the second surface; Multiple silicon-integrated passive components are respectively bonded to the grooves of the silicon-integrated substrate; Multiple metal frame walls are respectively disposed in the grooves of the silicon-containing substrate and contact the surrounding surface of the silicon-containing integrated passive components and the inner wall of the grooves; Multiple conductive via structures penetrate the silicon-containing substrate and extend to the first surface and the second surface, respectively; Multiple blind via structures extend from the second surface of the silicon-containing substrate toward and connect to the metal frame walls; A first circuit structure layer is disposed on the first surface of the silicon-containing substrate and electrically connects the conductive via structures to the silicon-containing integrated passive components; and A second circuit structure layer is disposed on the second surface of the silicon-containing substrate and electrically connects the conductive via structures to the blind via structures.

9. The packaging substrate of claim 8, wherein the conductive via structures include a plurality of first conductive via structures, and each of the first conductive via structures is located between two adjacent silicon-integrated passive components.

10. The packaging substrate of claim 9, wherein the conductive via structures further include a plurality of second conductive via structures, and the second conductive via structures are located around the first conductive via structures.

11. The packaging substrate of claim 9, wherein the packaging substrate is adapted to connect at least one chip, the orthographic projection of the chip on the packaging substrate overlapping the first conductive via structures and the silicon-integrated passive components.

12. The packaging substrate of claim 8, wherein the silicon-containing substrate comprises a glass substrate, a ceramic substrate, or a glass-ceramic substrate.

13. The packaging substrate of claim 8, wherein each of the silicon-integrated passive components comprises a silicon-based integrated passive component or a glass-based integrated passive component.

14. The packaging substrate of claim 8, further comprising: A first solder resist layer is disposed on the first circuit structure layer and exposes a portion of the first circuit structure layer, thereby defining a plurality of first pads; as well as A second solder resist layer is disposed on the second circuit structure layer and exposes a portion of the second circuit structure layer, thereby defining a plurality of second pads.

15. The packaging substrate of claim 8, wherein the blind via structures include a plurality of thermally conductive blind via structures or a plurality of electrically conductive blind via structures.

16. A method for manufacturing a packaging substrate, comprising: A silicon-containing substrate is provided, the silicon-containing substrate having a first surface and a second surface opposite to each other; A plurality of grooves are formed extending from the first surface of the silicon-containing substrate to the second surface; Multiple silicon-integrated passive components are respectively bonded within the grooves of the silicon-integrated substrate; Multiple metal frame walls are formed in the grooves of the silicon-containing substrate, wherein the metal frame walls contact the surrounding surface of the silicon-containing integrated passive components and the inner wall of the grooves; Multiple conductive via structures and multiple blind via structures are formed. The conductive via structures penetrate the silicon-containing substrate and extend to the first surface and the second surface, respectively. The blind via structures extend from the second surface of the silicon-containing substrate to the metal frame walls and connect to the metal frame walls. A first circuit structure layer is formed on the first surface of the silicon-containing substrate, the first circuit structure layer electrically connecting the conductive via structures and the silicon-containing integrated passive components; and A second circuit structure layer is formed on the second surface of the silicon-containing substrate, and the second circuit structure layer electrically connects the conductive via structures and the blind via structures.

17. The method for manufacturing a packaging substrate as described in claim 16, further comprising: Multiple connectors are formed on the first line structure layer.

18. The method of fabricating a package substrate as claimed in claim 16, wherein the method of forming the grooves extending from the first surface of the silicon-containing substrate to the second surface includes laser-induced depth etching.

19. The method of manufacturing a packaging substrate as claimed in claim 16, wherein the method of bonding the silicon-containing integrated passive components to the grooves in the silicon-containing substrate includes laser welding.

20. The method for manufacturing a packaging substrate as claimed in claim 16, wherein the step of forming the conductive via structures and the blind via structures comprises: A laser-induced deep etching process is performed on the silicon-containing substrate to form a plurality of through holes penetrating the silicon-containing substrate and a plurality of blind holes extending from the second surface of the silicon-containing substrate toward the metal frame walls; Electroplated metal material is applied within the through holes, the blind holes, and on the first and second surfaces of the silicon-containing substrate; and The metal material is patterned to form conductive via structures and blind via structures.

21. The method of fabricating a packaging substrate as claimed in claim 16, wherein the conductive via structures include a plurality of first conductive via structures, and each of the first conductive via structures is located between two adjacent silicon-integrated passive components.

22. The method for manufacturing a packaging substrate as claimed in claim 21, wherein the conductive via structures further include a plurality of second conductive via structures, and the second conductive via structures are located around the first conductive via structures.

23. The method of manufacturing a packaging substrate as claimed in claim 21, wherein the packaging substrate is adapted to connect at least one chip, the orthographic projection of the chip on the packaging substrate overlapping the first conductive via structures and the silicon-integrated passive components.

24. The method for manufacturing a packaging substrate as described in claim 16, wherein the silicon-containing substrate comprises a glass substrate, a ceramic substrate, or a glass-ceramic substrate.

25. The method for manufacturing a packaging substrate as claimed in claim 16, wherein each of the silicon-integrated passive components comprises a silicon-based integrated passive component or a glass-based integrated passive component.

Images