Packaging structure and preparation method thereof, circuit board, motor controller, and vehicle

Abstract

This application relates to a packaging structure and its fabrication method, a circuit board, a motor controller, and a vehicle. The packaging structure includes a packaging substrate, a chip, and a first super-wiring layer. The packaging substrate includes a receiving groove, within which the chip is located. At least one blind via is provided on the chip, and the first super-wiring layer is electrically connected to the chip through the at least one blind via. By providing a receiving groove on the packaging substrate to embed the chip within the groove, and providing a blind via on top of the chip, the blind via can be directly filled with metal paste subsequently. The first super-wiring layer can be directly electrically connected to the chip through the blind via, resulting in a simpler process, lower cost, and easier process control.

Description

Technical Field

[0001] This application relates to the field of chip packaging, and more particularly to a packaging structure and its preparation method, a circuit board, a motor controller, and a vehicle. Background Technology

[0002] With the development of new energy vehicles, the importance of motor controllers, as the core component of electric drive, is constantly increasing. Traditional motor controller design ideas can no longer meet the growing demand, and the trend of miniaturization of motor controllers is becoming increasingly obvious.

[0003] Related technologies typically achieve electrical connections by adding solder balls after chip-level packaging and then performing array reflow soldering, or by exposing chip electrodes through laser windowing and then filling blind vias with electroplating. However, both of these methods suffer from complex manufacturing processes. Summary of the Invention

[0004] This application provides a packaging structure and its manufacturing method, a circuit board, a motor controller, and a vehicle, which can simplify the process and at least partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, a packaging structure is provided, comprising:

[0006] Packaging substrate, including receiving groove;

[0007] A chip, located within the receiving slot, having at least one blind via on its surface; and

[0008] A first wiring layer is disposed on the packaging substrate;

[0009] The first redistribution layer is electrically connected to the chip through at least one of the blind vias.

[0010] Optionally, the packaging structure further includes a conductive dielectric layer, which at least fills the blind vias, and the first redistribution layer is electrically connected to the chip through the conductive dielectric layer.

[0011] Optionally, the packaging structure further includes an insulating dielectric layer located within the receiving groove and covering the chip.

[0012] Optionally, the insulating dielectric layer includes the at least one blind via.

[0013] Optionally, the packaging structure further includes a heat dissipation substrate located within the receiving groove, the chip located on the heat dissipation substrate, and the insulating dielectric layer covering the chip and the heat dissipation substrate.

[0014] Optionally, the at least one blind via includes a first blind via corresponding to the first electrode of the chip, and the conductive dielectric layer includes a first conductive dielectric layer that at least fills the first blind via, and the first conductive dielectric layer is electrically connected to the first electrode.

[0015] Optionally, the at least one blind via further includes a second blind via corresponding to the second electrode of the chip, and the conductive dielectric layer further includes a second conductive dielectric layer that at least fills the second blind via, and the second conductive dielectric layer is electrically connected to the second electrode.

[0016] Optionally, the at least one blind hole further includes a third blind hole that exposes a portion of the surface of the heat dissipation substrate, and the conductive dielectric layer includes a third conductive dielectric layer that at least fills the third blind hole, and the third conductive dielectric layer is electrically connected to the heat dissipation substrate through the third blind hole.

[0017] Optionally, the insulating dielectric layer includes a first surface adjacent to the first redistribution layer, and the packaging substrate includes a second surface adjacent to the first redistribution layer, wherein the first surface and the second surface are flush.

[0018] Optionally, the roughness of the first surface is greater than or equal to 0.6.

[0019] Optionally, it further includes a first adhesive layer disposed between the first redistribution layer and the packaging substrate.

[0020] Optionally, the first adhesive layer includes a clearance hole corresponding to the at least one blind hole.

[0021] Optionally, the conductive dielectric layer protrudes from the first surface.

[0022] Optionally, the distance by which the conductive medium protrudes from the first surface is 0.2 mm to 0.4 mm.

[0023] Optionally, the horizontal distance between the center of the heat dissipation substrate and the center of the receiving groove is less than or equal to 50 micrometers.

[0024] Optionally, the chip is soldered to the heat dissipation substrate.

[0025] Optionally, the thickness of the packaging substrate is greater than the sum of the thicknesses of the chip and the heat dissipation substrate.

[0026] Optionally, the insulating dielectric layer includes at least one of polyurethane, polycarbonate, epoxy resin, and thermally conductive silicone.

[0027] Optionally, the conductive medium comprises a metal paste in which a binder is doped.

[0028] Optionally, the packaging substrate includes one of FR4 board, FR5 board, ceramic substrate, aluminum substrate and BT board.

[0029] Optionally, the packaging structure further includes a second wiring layer, which is disposed on the side of the heat dissipation substrate opposite to the first wiring layer.

[0030] Optionally, the packaging structure further includes a second adhesive layer disposed between the second redistribution layer and the heat dissipation substrate.

[0031] Optionally, the second adhesive layer is thermally fused to or riveted to the encapsulation substrate.

[0032] According to a second aspect of this application, a method for fabricating a package structure is provided, comprising: providing a package substrate having a receiving groove; placing a chip in the receiving groove; forming at least one blind via on the package substrate, wherein the at least one blind via corresponds to the chip; and forming a first redistribution layer on the package substrate, wherein the first redistribution layer is electrically connected to the chip through the blind via.

[0033] Optionally, the step of placing the chip in the receiving groove includes: soldering the chip to the surface of the heat dissipation substrate; and placing the soldered chip and the heat dissipation substrate in the receiving groove.

[0034] Optionally, the step of forming at least one blind via on the substrate includes: filling the receiving groove with insulating material to cover the chip and the heat dissipation substrate; curing the insulating material; polishing the insulating material until the insulating material is flush with the surface of the packaging substrate to form an insulating dielectric layer; and making an opening in the insulating dielectric layer to form the at least one blind via.

[0035] Optionally, before making openings in the insulating dielectric layer, the process further includes annealing the packaging substrate on which the insulating dielectric layer is formed.

[0036] Optionally, before forming the first redistribution layer on the substrate, the method further includes: filling the at least one blind via with a metal paste; and drying the metal paste to form a conductive dielectric layer.

[0037] Optionally, the metal slurry is doped with a binder.

[0038] Optionally, the conductive dielectric layer protrudes from the surface of the packaging substrate, and the distance by which the conductive dielectric layer protrudes from the surface of the packaging substrate is 0.2 mm to 0.4 mm.

[0039] Optionally, the step of forming a first redistribution layer on the substrate includes: forming a first adhesive layer on the surface of the packaging substrate, wherein the first adhesive layer includes clearance holes corresponding to the blind vias; and forming a first redistribution layer on the first adhesive layer, wherein the first redistribution layer is electrically connected to the chip through the conductive dielectric layer.

[0040] Optionally, the preparation method further includes: forming a second adhesive layer on the side of the packaging substrate opposite to the first redistribution layer; and forming a second redistribution layer on the side of the second adhesive layer opposite to the packaging substrate.

[0041] Optionally, the fabrication method further includes: hot-pressing the first redistribution layer, the conductive dielectric layer, and the chip.

[0042] According to a third aspect of this application, a circuit board is also provided, comprising the above-described packaging structure or the packaging structure prepared by the above-described preparation method.

[0043] According to a third aspect of this application, a motor controller is also provided, including the aforementioned circuit board.

[0044] According to a third aspect of this application, a vehicle is also provided, including the aforementioned motor controller.

[0045] In summary, the embodiments of this application provide a receiving groove on the packaging substrate so that the chip is buried in the receiving groove, and a blind hole is provided above the chip so that the blind hole can be directly filled with metal paste in the future. The first wiring layer can be directly electrically connected to the chip through the blind hole. The process is simpler, the cost is lower, and the process control is also simpler.

[0046] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0049] Figure 1 This is a schematic diagram of the packaging structure provided in an exemplary embodiment of this disclosure;

[0050] Figure 2This is a top view of the receiving groove and heat dissipation substrate provided in an exemplary embodiment of this disclosure;

[0051] Figure 3 This is a top view of the first adhesive layer provided in an exemplary embodiment of this disclosure;

[0052] Figure 4 This is a flowchart of the steps of the method for preparing the packaging structure provided in the exemplary embodiments of this disclosure;

[0053] Figure 5 This is a schematic diagram of a circuit board module provided in an exemplary embodiment of this disclosure.

[0054] Explanation of reference numerals in the attached figures:

[0055] 1000, Circuit board; 100, Packaging structure; 10, Packaging substrate; 101, Center of receiving groove; 102, Second surface; 11, Receiving groove; 20, Chip; 30, Heat dissipation substrate; 301, Center of heat dissipation substrate; 31, First metal layer; 32, Ceramic layer; 33, Second metal layer; 40, Insulating dielectric layer; 401, First surface; 41, Blind via; 411, First blind via; 412, Second blind via; 413, Third blind via; 50, Conductive dielectric layer; 51, First conductive dielectric layer; 52, Second conductive dielectric layer; 53, Third conductive dielectric layer; 60, First adhesive layer; 61, Clearance hole; 70, First redistribution layer; 80, Second adhesive layer; 90, Second redistribution layer. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0057] Based on the problems mentioned in the background, some related technologies involve a connection layer above the power chip, an insulating ceramic substrate above the connection layer, and soldering the power chip to the insulating ceramic substrate via the connection layer. Below the power chip, a ball grid array (BGA) serves as the chip connection medium, and below the BGA, a low-temperature co-fired ceramic layer serves as the lower signal connection layer. However, this method requires reflow soldering, adding an extra step compared to wafer-level packaging and board-level packaging. Furthermore, the electrical conductivity, thermal conductivity, and high-temperature reliability of the solder balls limit the functionality of the packaged module, hindering the mass production of automotive-grade modules.

[0058] In other related technologies, the back side of the chip is thinned, applied to the substrate of a printed circuit board (PCB), and then covered with another PCB to embed the chip within the PCB. Grooves are created in the PCB, extending to the conductive structure of the PCB substrate and the connection surface of the chip. Contact is established through a contact conductor structure that extends to the connection surface of the chip and the conductive structure of the PCB substrate. The difference in height between the chip and the substrate results in two depths of blind vias. The electroplating requirements for blind vias with different aperture ratios differ, complicating subsequent electroplating processes. Furthermore, for blind vias of varying depths, using electroplating for electrode extraction may make it difficult to fill large blind vias, resulting in excessively long electroplating times and a risk of short-circuit failure due to residual plating solutions. Additionally, the difference in height between the chip and the substrate can lead to voids during subsequent lamination.

[0059] Based on this, this application provides a packaging structure 100, please refer to... Figure 1 The packaging structure 100 provided in this application embodiment includes a packaging substrate 10, a chip 20, and a first redistribution layer 70. The packaging substrate 10 includes a receiving groove 11, and the chip 20 is located in the receiving groove 11. At least one blind via 41 is provided on the chip 20, and the first redistribution layer 70 is electrically connected to the chip 20 through the at least one blind via 41.

[0060] In this embodiment, by providing a receiving groove 11 on the packaging substrate 10, the chip 20 is buried in the receiving groove 11, and a blind hole 41 is provided above the chip 20 so that the blind hole 41 can be directly filled with metal paste in the future. The first redistribution layer 70 can be directly electrically connected to the chip 20 through the blind hole 41. The process is simpler, the cost is lower, and the process control is also simpler.

[0061] Specifically, the packaging structure 100 provided in this application embodiment, compared to the related art scheme of first completing the chip 20-level packaging and then adding solder balls to achieve electrical connection, can support the filling of blind vias 41 with metal paste to achieve electrode output, without the need for an additional reflow soldering process, and its structure and process are simpler. Compared to the related art scheme of electroplating electrode output, the process is simpler, can support the filling of blind vias 41 with metal paste to achieve electrode output, and can avoid the problems of chemical residue and complex deep and shallow hole electroplating processes that may occur in the electroplating process.

[0062] The packaging substrate 10 in this application embodiment may include one of the following: FR4 board (Flame-Retardant 4 Epoxy Glass Cloth Laminate), FR5 board (Flame-Retardant-5 Epoxy Glass Cloth Laminate or EPGC-204 Epoxy Glass Fiber Reinforced Laminate), ceramic substrate, aluminum substrate, and BT board (Bismaleimide Triazine resin-based board). Compared to existing solutions that directly use the heat dissipation substrate 30 as the packaging substrate 10 or place the chip 20 between PP sheets (generally composed of resin and reinforcing materials such as glass fiber, carbon fiber, etc.) and press them together to form the packaging substrate 10, this application embodiment uses the above-mentioned directly molded general-purpose board material as the packaging substrate 10. This can more effectively control the problem of substrate warping after heat treatment, and avoids defects such as voids caused by the height difference between the chip 20 and the substrate during subsequent lamination or potting.

[0063] The first wiring layer 70 in this embodiment includes a metallic material, specifically copper foil. The first wiring layer 70 can be formed on the packaging substrate 10 by direct attachment. The first wiring layer 70 can be patterned into circuitry through chemical etching in subsequent processes.

[0064] In some embodiments, the packaging structure 100 further includes a conductive dielectric layer 50, which at least fills the blind vias 41. The first redistribution layer 70 is electrically connected to the chip 20 through the conductive dielectric layer 50. The packaging structure 100 provided in this application embodiment can directly fill the blind vias 41 with the conductive dielectric layer 50 by stencil printing or dispensing, without the need for reflow soldering or electroplating processes, making the process relatively simple.

[0065] The conductive dielectric layer 50 may include a metal paste. Optionally, a binder may be doped into the metal paste. The addition of the binder facilitates the sintering of the metal paste, reduces the temperature and pressure required during the sintering process, and reduces power consumption. In some embodiments, the binder may include, but is not limited to, at least one of fumed silica, castor oil, hydrogenated castor oil, polyamide wax, polyacrylamide, and polyvinyl alcohol.

[0066] In some embodiments, the packaging structure 100 further includes an insulating dielectric layer 40 located within the receiving groove 11. The insulating dielectric layer 40 covers the chip 20 to serve as an insulating package and to fix the chip 20. The insulating dielectric layer 40 may include the aforementioned blind via 41, that is, the blind via 41 is formed in the insulating dielectric layer 40.

[0067] Optionally, the insulating dielectric layer 40 includes at least one of polyurethane, polycarbonate, epoxy resin, and thermally conductive silicone.

[0068] In some embodiments, the packaging structure 100 further includes a heat dissipation substrate 30 located within the receiving groove 11, with the chip 20 situated on the heat dissipation substrate 30, and an insulating dielectric layer 40 covering the chip 20 and the heat dissipation substrate 30. The heat dissipation substrate 30 serves to conduct heat to the chip 20 and extend the back electrode of the chip 20. Furthermore, while increasing the integration level of the packaging structure 100, it also elevates the chip 20 to reduce the depth of the blind via 41 and lower the difficulty of opening the via.

[0069] It is understandable that the thickness of the packaging substrate 10 may be slightly greater than the sum of the thicknesses of the chip 20 and the heat dissipation substrate 30, in order to provide space for the packaging of the insulating medium.

[0070] Optionally, such as Figure 1 As shown, the heat dissipation substrate 30 may include a first metal layer 31, a ceramic layer 32, and a second metal layer 33 stacked together. The chip 20 is located on the first metal layer 31, specifically on the side of the first metal layer 31 away from the second metal layer 33. The first redistribution layer 70 may also be electrically connected to the first metal layer 31 through at least one corresponding blind via 41. The first metal layer 31 can serve as an electrode extension layer for the electrodes of the chip 20. The heat generated by the device on the first metal layer 31 during operation is rapidly conducted to the second metal layer 33 through the ceramic layer 32, and the second metal layer 33 conducts the heat away, thereby achieving heat dissipation of the device.

[0071] Optionally, the first metal layer 31 and the second metal layer 33 may be copper foil.

[0072] In some embodiments, the chip 20 can be fixedly connected to the heat dissipation substrate 30 by welding.

[0073] Ideally, when placing the heat dissipation substrate 30 carrying the chip 20 into the receiving groove 11, the heat dissipation substrate 30 should be placed in the center of the receiving groove 11. However, considering positioning deviations, the positioning tolerance of the heat dissipation substrate 30 in this embodiment needs to be maintained within 50 micrometers, that is, the horizontal distance between the center 301 of the heat dissipation substrate and the center 101 of the receiving groove is less than or equal to 50 micrometers. Figure 2As shown. Since the positioning of the heat dissipation substrate 30 and the subsequent blind hole 41 both rely on the positioning marks / positioning holes on the packaging substrate 10, after the heat dissipation substrate 30 is positioned and placed in the receiving groove 11, even if there is a positioning deviation in the heat dissipation substrate 30, in order to save process flow, the position of the heat dissipation substrate 30 will not be recalculated when the blind hole 41 is subsequently formed by laser engraving. That is, the blind hole 41 will not be repositioned. Therefore, by controlling the positioning tolerance within this range, it can be ensured that when the blind hole 41 is formed, the final position of the blind hole 41 will not be too far off from the ideal position, thus affecting the subsequent electrical connection. In the embodiments of this application, "the distance in the horizontal direction" can be understood as the distance on the plane where the orthographic projection in the thickness direction of the packaging substrate 10 is located, and "horizontal direction" can be understood as the direction parallel to the plane where the packaging substrate 10 is located.

[0074] Please see Figure 1 The insulating dielectric layer 40 includes a first surface 401 adjacent to the first redistribution layer 70, and the encapsulation substrate 10 includes a second surface 102 adjacent to the first redistribution layer 70. The first surface 401 and the second surface 102 are flush. By aligning the first surface 401 and the second surface 102, a flat surface can be provided for subsequently formed components or films.

[0075] In some embodiments, the roughness of the first surface 401 of the insulating dielectric layer 40 is greater than or equal to 0.6. By controlling the roughness of the first surface 401 of the insulating dielectric layer 40 within this range, the adhesion between the insulating dielectric layer 40 and other film layers can be effectively enhanced.

[0076] In some embodiments, the blind via 41 may include a first blind via 411 corresponding to the first electrode of the chip 20. Accordingly, the conductive dielectric layer 50 includes a first conductive dielectric layer 51 that at least fills the first blind via 411, and the first conductive dielectric layer 51 is electrically connected to the first electrode. It is understood that the first conductive dielectric layer 51 is also electrically connected to the first redistribution layer 70.

[0077] The blind via 41 may also include a second blind via 412 corresponding to the second electrode of the chip 20. Accordingly, the conductive dielectric layer 50 further includes a second conductive dielectric layer 52 that at least fills the second blind via 412, and the second conductive dielectric layer 52 is electrically connected to the second electrode. It is understood that the second conductive layer is also electrically connected to the first redistribution layer 70.

[0078] It is understandable that the first electrode can be one of the positive and negative electrodes of the chip 20, and the second electrode can be the other of the positive and negative electrodes of the chip 20.

[0079] Optionally, the diameters of the first blind hole 411 and the second blind hole 412 may be smaller than the diameter of the third blind hole 413.

[0080] In some embodiments, the blind via 41 further includes a third blind via 413 exposing a portion of the surface of the heat dissipation substrate 30. Accordingly, the conductive dielectric layer 50 includes a third conductive dielectric layer 53 that at least fills the third blind via 413, and the third conductive dielectric layer 53 is electrically connected to the heat dissipation substrate 30. It is understood that the third conductive dielectric layer 53 is electrically connected to the heat dissipation substrate 30.

[0081] Please see Figure 1 and Figure 3 In some embodiments, the encapsulation structure 100 further includes a first adhesive layer 60, which is disposed between the first redistribution layer 70 and the encapsulation substrate 10. The first adhesive layer 60 serves to bond the first redistribution layer 70 to the encapsulation substrate 10 and the insulating dielectric layer 40, and also serves to fill the gaps between the film layers.

[0082] In some embodiments, please refer to Figure 3 The first adhesive layer 60 includes clearance holes 61 corresponding to the blind vias 41, to ensure that the upper first redistribution layer 70 can be electrically connected to the chip 20 or the heat sink substrate 30 through the corresponding conductive dielectric layer 50. It is understood that the number of clearance holes 61 can be consistent with the number of blind vias 41, and the aperture of the clearance holes 61 can also be the same as the aperture of the corresponding blind vias 41.

[0083] Optionally, the first adhesive layer 60 may be a PP sheet, which may be a sheet material composed of resin and reinforcing materials (such as glass fiber, carbon fiber, etc.). The aforementioned clearance holes 61 can be formed by cutting the PP sheet at specific positions corresponding to the electrodes of the chip 20 and the heat dissipation substrate 30. The thickness of the first adhesive layer 60 is generally about 0.2 mm.

[0084] In some embodiments, please refer to Figure 1 The conductive dielectric layer 50 protrudes from the first surface 401 of the insulating dielectric layer 40. Further, the distance by which the conductive dielectric layer 50 protrudes from the first surface 401 is 0.2 mm to 0.4 mm. Optionally, it is 0.25 mm to 0.35 mm. During the fabrication of the package structure 100, lamination and sintering processes are involved. During lamination and sintering, the nanoparticles of the metal paste in the conductive dielectric layer 50 fuse together, reducing its volume. If the protrusion distance is less than this range, it may cause the metal paste to detach from the first redistribution layer 70; if it is greater than this range, it may cause unevenness after lamination, affecting the reliability of the package structure 100.

[0085] It is understood that the first conductive dielectric layer 51, the second conductive dielectric layer 52, and the third conductive dielectric layer 53 all protrude from the first surface 401 of the insulating layer. The distances between the first conductive dielectric layer 51, the second conductive dielectric layer 52, and the third conductive dielectric layer 53 protruding from the first surface 401 are kept as consistent as possible to ensure the flatness of the film interface.

[0086] Please see Figure 1 In some embodiments, the package structure 100 further includes a second wiring layer 90, which is disposed on the side of the heat sink substrate 30 opposite to the first wiring layer. That is, the second wiring layer 90 is located below the heat sink substrate 30 (in the illustrated direction). In this way, a more complex multilayer interconnect structure can be formed, improving the degree of integration.

[0087] It is understood that in some embodiments, the second wiring layer 90 is also located on the side of the packaging substrate 10 away from the first wiring layer, that is, below the packaging substrate 10. However, it is not excluded that in other embodiments, the second wiring layer 90 is not completely located below the packaging substrate 10.

[0088] Optionally, the second wiring layer 90 can be made of the same material as the first wiring layer 70, which can both be copper foil. The second wiring layer 90 can be directly attached to the heat sink substrate 30.

[0089] Similarly, the packaging structure 100 may also include a second adhesive layer 80, which is disposed between the second redistribution layer 90 and the heat dissipation substrate 30. Optionally, the second adhesive layer 80 may also be a PP sheet. The second adhesive layer 80 serves to bond the upper and lower film layers and also provides support. The chip 20 located between the first adhesive layer 60 and the second adhesive layer 80 is protected and supported by these two adhesive layers.

[0090] The second adhesive layer 80 and the encapsulation substrate 10 can be fixed together by means of hot-melt connection or riveting.

[0091] Based on the above-described encapsulation structure 100, this application provides a method for fabricating the encapsulation structure 100. Please refer to [link to relevant documentation]. Figure 1 and Figure 4 The preparation method includes the following steps S10 to S40.

[0092] S10, a packaging substrate 10 having a receiving groove 11 is provided.

[0093] Specifically, a packaging substrate 10 is provided, with a thickness slightly greater than the sum of the thicknesses of the chip 20 and the heat dissipation substrate 30. The packaging substrate 10 includes, but is not limited to, one of FR4, FR5, ceramic, aluminum, and BT substrates. A slot is formed in the packaging substrate 10 by mechanical or laser cutting to create a receiving slot 11. The dimensions of the receiving slot 11 must be greater than the dimensions of the heat dissipation substrate 30. These dimensions include the slot width, slot length, and slot depth.

[0094] S20, place the chip 20 into the receiving slot 11.

[0095] Specifically, S20 may include: S21, soldering the chip 20 to the surface of the heat dissipation substrate 30; and placing the soldered chip 20 and the heat dissipation substrate 30 in the receiving groove 11.

[0096] Specifically, the heat dissipation substrate 30, on which the chip 20 is soldered / carried, is positioned and embedded in the receiving groove 11, preferably at the center 101 of the receiving groove. However, due to the influence of process precision, positioning tolerances are unavoidable. The positioning tolerance of the heat dissipation substrate 30 is controlled within 50 micrometers. The significance of positioning tolerance has been mentioned above and will not be repeated here.

[0097] S30, at least one blind hole 41 is formed on the packaging substrate 10, wherein at least one of the blind holes 41 corresponds to the chip 20.

[0098] Specifically, S30 may include: S31, filling the receiving groove 11 with insulating material to cover the chip 20 and the heat dissipation substrate 30; S32, curing the insulating material; S33, polishing the insulating material until the insulating material is flush with the surface of the packaging substrate 10 to form an insulating dielectric layer 40; S34, making openings in the insulating dielectric layer 40 to form the at least one blind hole 41.

[0099] The insulating material may include at least one of polyurethane, polycarbonate, epoxy resin, and thermally conductive silicone. The insulating material is mechanically ground until the surface roughness is greater than or equal to 0.6. A blind via 41 perpendicular to the electrodes of the chip 20 can be formed by laser engraving in the insulating dielectric layer 40.

[0100] In some embodiments, before creating openings in the insulating dielectric layer 40, the preparation method may further include annealing the encapsulation substrate 10 on which the insulating dielectric layer 40 is formed. By performing pressurized thermal annealing on the insulating layer, the internal stress generated during the curing process of the insulating material can be further released.

[0101] S40, a first redistribution layer 70 is formed on the packaging substrate 10, wherein the first redistribution layer 70 is electrically connected to the chip 20 through the blind via 41.

[0102] In some embodiments, before forming the first redistribution layer 70, the preparation method may further include filling at least one blind via 41 with a metal paste; and drying the metal paste to form a conductive dielectric layer 50.

[0103] Specifically, the metal paste can be applied to fill the blind holes 41 to a point slightly above the surface of the insulating dielectric layer 40 by means of stencil printing or dispensing with a dispensing machine. Optionally, the distance by which the metal paste protrudes from the surface of the insulating dielectric layer 40 is 0.2 to 0.4 mm.

[0104] The drying temperature of the metal paste can be 50-150℃. Drying can be carried out under vacuum conditions to remove the solvent from the metal paste inside the blind hole 41.

[0105] Metal slurries can be doped with binders to reduce the temperature and pressure required for subsequent sintering processes.

[0106] Specifically, S40 includes: S41, forming a first adhesive layer 60 on the surface of the packaging substrate 10, wherein the first adhesive layer 60 includes a clearance hole 61 corresponding to the blind via 41; S42, forming a first redistribution layer 70 on the first adhesive layer 60, wherein the first redistribution layer 70 is electrically connected to the chip 20 through the conductive dielectric layer 50.

[0107] The first adhesive layer 60 can be a PP sheet, and the first redistribution layer 70 can be a copper foil. The PP sheet has clearance holes 61 corresponding to the blind vias 41. The PP sheet and the copper foil are sequentially attached to the packaging substrate 10.

[0108] In some embodiments, the fabrication method further includes: forming a second adhesive layer 80 on the side of the packaging substrate 10 opposite to the first redistribution layer 70; and forming a second redistribution layer 90 on the side of the second adhesive layer 80 opposite to the packaging substrate 10.

[0109] The second adhesive layer 80 can be a PP sheet, and the second redistribution layer 90 can be a copper foil. The PP sheet and the copper foil are sequentially attached to the underside of the encapsulation substrate 10, and the second adhesive layer 80 and the second redistribution layer 90 are fixed by hot-melt positioning or riveting.

[0110] In some embodiments, the fabrication method further includes hot-pressing the first redistribution layer 70, the conductive dielectric layer 50, and the chip 20.

[0111] Specifically, the above structures are pressed into a single unit, namely the package structure 100, by high-temperature hot pressing. Under hot pressing conditions, the metal paste simultaneously undergoes sintering with the electrodes of the chip 20 and the first redistribution layer 70.

[0112] The pressing temperature can be 150℃~250℃, and the pressure can be 15bar~20bar.

[0113] Optionally, the above structure can be pre-pressed before hot pressing. The pre-pressing temperature can be 100℃~150℃ and the pressure can be 5bar~10bar.

[0114] Based on the above-described encapsulation structure 100 and its fabrication method, this application also provides a circuit board 1000, including the above-described encapsulation structure 100 or the encapsulation structure 100 fabricated by the above-described fabrication method. This circuit board 1000 possesses all the beneficial effects of the above-described encapsulation structure 100 and its fabrication method, which will not be elaborated upon further herein.

[0115] This application also provides a motor controller, including the aforementioned circuit board 1000. This motor controller possesses all the beneficial effects of the aforementioned circuit board 1000, which will not be elaborated upon here.

[0116] This application also provides a vehicle including the aforementioned motor controller. This vehicle possesses all the beneficial effects of the aforementioned motor controller, which will not be elaborated further herein.

[0117] In some examples, the vehicle may be a gasoline-powered vehicle, a plug-in hybrid electric vehicle, or a new energy vehicle, etc., and this disclosure does not specifically limit it.

[0118] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0119] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0120] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0121] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A packaging structure, characterized in that, include: Packaging substrate, including receiving groove; A chip is located within the receiving slot, and at least one blind via is provided on the chip. as well as A first wiring layer is disposed on the packaging substrate; The first redistribution layer is electrically connected to the chip through at least one of the blind vias.

2. The packaging structure according to claim 1, characterized in that, It also includes a conductive dielectric layer, which at least fills the blind vias, and the first redistribution layer is electrically connected to the chip through the conductive dielectric layer.

3. The packaging structure according to claim 2, characterized in that, It also includes an insulating dielectric layer, which is located within the receiving groove and covers the chip.

4. The packaging structure according to claim 3, characterized in that, The insulating dielectric layer includes at least one blind via.

5. The packaging structure according to claim 4, characterized in that, It also includes a heat dissipation substrate, which is located in the receiving groove, and the chip is located on the heat dissipation substrate. The insulating dielectric layer covers the chip and the heat dissipation substrate.

6. The packaging structure according to claim 5, characterized in that, The at least one blind via includes a first blind via corresponding to the first electrode of the chip, and the conductive dielectric layer includes a first conductive dielectric layer that at least fills the first blind via, and the first conductive dielectric layer is electrically connected to the first electrode.

7. The packaging structure according to claim 6, characterized in that, The at least one blind via further includes a second blind via corresponding to the second electrode of the chip, and the conductive dielectric layer further includes a second conductive dielectric layer that at least fills the second blind via, and the second conductive dielectric layer is electrically connected to the second electrode.

8. The packaging structure according to claim 5, characterized in that, The at least one blind via further includes a third blind via exposing a portion of the surface of the heat dissipation substrate, and the conductive dielectric layer includes a third conductive dielectric layer that at least fills the third blind via, and the third conductive dielectric layer is electrically connected to the heat dissipation substrate.

9. The packaging structure according to any one of claims 3 to 8, characterized in that, The insulating dielectric layer includes a first surface adjacent to the first redistribution layer, and the packaging substrate includes a second surface adjacent to the first redistribution layer, with the first surface and the second surface being flush.

10. The packaging structure according to claim 9, characterized in that, The roughness of the first surface is greater than or equal to 0.

6.

11. The packaging structure according to claim 9, characterized in that, It also includes a first adhesive layer disposed between the first redistribution layer and the packaging substrate.

12. The packaging structure according to claim 11, characterized in that, The first adhesive layer includes clearance holes corresponding to the at least one blind hole.

13. The packaging structure according to claim 11, characterized in that, The conductive dielectric layer protrudes from the first surface.

14. The packaging structure according to claim 13, characterized in that, The conductive medium protrudes from the first surface by a distance of 0.2 mm to 0.4 mm.

15. The packaging structure according to claim 5, characterized in that, The horizontal distance between the center of the heat dissipation substrate and the center of the receiving groove is less than or equal to 50 micrometers.

16. The packaging structure according to claim 5, characterized in that, The chip is soldered to the heat dissipation substrate.

17. The packaging structure according to claim 5, characterized in that, The thickness of the packaging substrate is greater than the sum of the thicknesses of the chip and the heat dissipation substrate.

18. The packaging structure according to claim 3, characterized in that, The insulating dielectric layer includes at least one of polyurethane, polycarbonate, epoxy resin, and thermally conductive silicone.

19. The packaging structure according to claim 2, characterized in that, The conductive medium includes a metal paste, wherein a binder is doped into the metal paste.

20. The packaging structure according to claim 1, characterized in that, The packaging substrate includes one of FR4 board, FR5 board, ceramic substrate, aluminum substrate and BT board.

21. The packaging structure according to claim 1, characterized in that, It also includes a second wiring layer, which is disposed on the side of the heat dissipation substrate away from the first wiring layer.

22. The packaging structure according to claim 21, characterized in that, It also includes a second adhesive layer, which is disposed between the second redistribution layer and the heat dissipation substrate.

23. The packaging structure according to claim 22, characterized in that, The second adhesive layer is thermally fused to or riveted to the encapsulation substrate.

24. A method for preparing a packaging structure, characterized in that, include: Provide a packaging substrate with a receiving groove; Place the chip in the receiving slot; At least one blind via is formed on the packaging substrate, wherein the at least one blind via corresponds to the chip; and A first wiring layer is formed on the packaging substrate, wherein the first wiring layer is electrically connected to the chip through the blind via.

25. The preparation method according to claim 24, characterized in that, The step of placing the chip in the receiving slot includes: The chip is soldered to the surface of the heat dissipation substrate; and The soldered chip and the heat dissipation substrate are placed in the receiving groove.

26. The preparation method according to claim 25, characterized in that, The step of forming at least one blind hole on the substrate includes: Insulating material is poured into the receiving groove to cover the chip and the heat dissipation substrate; Curing the insulating material; Polishing the insulating material until it is flush with the surface of the encapsulation substrate to form an insulating dielectric layer; and An opening is made in the insulating dielectric layer to form the at least one blind via.

27. The preparation method according to claim 26, characterized in that, Before making openings in the insulating dielectric layer, the process further includes annealing the packaging substrate on which the insulating dielectric layer is formed.

28. The preparation method according to claim 26, characterized in that, Before forming the first redistribution layer on the substrate, the method further includes: The at least one blind hole is filled with metal slurry; and The metal slurry is dried to form a conductive dielectric layer.

29. The preparation method according to claim 28, characterized in that, The metal slurry contains a binder.

30. The preparation method according to claim 28, characterized in that, The conductive dielectric layer protrudes from the surface of the packaging substrate, and the distance by which the conductive dielectric layer protrudes from the surface of the packaging substrate is 0.2 mm to 0.4 mm.

31. The preparation method according to claim 28, characterized in that, The step of forming a first redistribution layer on the substrate includes: A first adhesive layer is formed on the surface of the packaging substrate, wherein the first adhesive layer includes clearance holes corresponding to the blind vias; and A first redistribution layer is formed on the first adhesive layer, and the first redistribution layer is electrically connected to the chip through the conductive dielectric layer.

32. The preparation method according to claim 28, characterized in that, Also includes: A second adhesive layer is formed on the side of the packaging substrate opposite to the first redistribution layer; as well as A second rewiring layer is formed on the side of the second adhesive layer opposite to the packaging substrate.

33. The preparation method according to any one of claims 28 to 32, characterized in that, Also includes: The first redistribution layer, the conductive dielectric layer, and the chip are subjected to thermal pressing.

34. A circuit board, characterized in that, This includes the packaging structure as described in any one of claims 1 to 23 or the packaging structure prepared by the preparation method according to any one of claims 24 to 33.

35. A motor controller, characterized in that, Includes the circuit board as described in claim 34.

36. A vehicle, characterized in that, Includes the motor controller as described in claim 35.

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