Substrate and method of manufacturing the same

Abstract

This invention provides a substrate and a method for manufacturing the same. The substrate includes a glass core circuit structure, a first capping layer, and a first add-on structure. The glass core circuit structure includes a glass block and vertical conductive connectors. The first capping layer is embedded in the glass core circuit structure. The first add-on structure is disposed on the glass core circuit structure and electrically connected to it. The first add-on structure includes a first insulating layer, and the Young's modulus of the first capping layer is smaller than that of the first insulating layer. A method for manufacturing the substrate is also provided. This invention can improve the reliability of the substrate.

Description

Technical Field

[0001] This invention relates to a substrate and a method for manufacturing the same. Background Technology

[0002] Currently, glass core substrates are widely used in high-end substrate applications due to their advantages such as tunable modulus, a coefficient of thermal expansion (CTE) closer to that of silicon, dimensional stability, high via density, ultra-low loss dielectric, smooth copper layer, and higher temperature capability. However, due to the brittleness of glass, the stress generated in traditional substrate manufacturing processes can easily lead to cracking (SeWaRe) problems, potentially reducing the reliability of glass core substrates. Summary of the Invention

[0003] A substrate includes a glass core circuit structure, a first capping layer, and a first add-on structure. The glass core circuit structure includes a glass block and vertical conductive connectors. The first capping layer is embedded in the glass core circuit structure. The first add-on structure is disposed on the glass core circuit structure and electrically connected to the glass core circuit structure. The first add-on structure includes a first insulating layer, and the Young's modulus of the first capping layer is smaller than the Young's modulus of the first insulating layer.

[0004] A method of manufacturing a substrate includes: providing a plurality of glass core circuit structures, wherein a diced region is formed by glass bulk portions located between adjacent glass core circuit structures; removing a portion of the glass bulk portions to form a trench; forming a capping layer in the trench; forming an add-on structure on the plurality of glass core circuit structures, wherein the add-on structure is electrically connected to the glass core circuit structures, and the Young's modulus of the capping layer is less than the Young's modulus of the insulating layer of the add-on structure; and performing a dicing process on the diced regions to form a substrate, the substrate including one of the plurality of glass core circuit structures, a portion of the capping layer, and a portion of the add-on structure.

[0005] Based on the above, by designing the Young's modulus and position of the introduced cover layer, the stress generated during the manufacturing process can be effectively alleviated, thereby improving the cracking problem of the glass block material in the glass core circuit structure.

[0006] To make the above content easier to understand, several embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0007] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0008] Figure 1 This is a schematic cross-sectional view of a substrate according to some embodiments of the present disclosure;

[0009] Figures 2 to 8 for Figure 1 A partial cross-sectional schematic diagram of the substrate during different stages of the manufacturing process;

[0010] Figures 9 to 10 This is a partial cross-sectional schematic diagram of an alternative embodiment during an intermediate stage of the manufacturing process.

[0011] Figure 11 This is a schematic cross-sectional view of a substrate according to some embodiments of the present disclosure;

[0012] Figures 12 to 18 for Figure 11 A partial cross-sectional schematic diagram of the substrate during different stages of the manufacturing process;

[0013] Figure 19 This is a schematic cross-sectional view of a substrate according to some embodiments of the present disclosure;

[0014] Figures 20 to 23 for Figure 19 A partial cross-sectional schematic diagram of the substrate during different stages of the manufacturing process. Detailed Implementation

[0015] In the detailed description of the embodiments, terms such as "first," "second," and "third" may be used to describe different elements. These terms are used only to distinguish elements, but the elements should not be structurally limited by these terms. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. Furthermore, in the manufacturing method, the order in which elements or components are formed should not be limited by these terms, except for specific manufacturing processes. For example, a first element may be formed before a second element, or a first element may be formed after a second element, or the first and second elements may be formed in the same process or step.

[0016] Furthermore, the thickness of the membranes and regions in the accompanying drawings may be magnified for clarity. The same or similar reference numerals are used to denote the same or similar components, and details will not be repeated below.

[0017] Please refer to Figure 1The substrate 100 includes a glass core circuit structure 110, a capping layer 120, and an add-on structure 130, wherein the capping layer 120 is embedded in the glass core circuit structure 110, and the add-on structure 130 is disposed on and electrically connected to the glass core circuit structure 110. For example, the glass core circuit structure 110 includes a glass block 111 and a vertical conductive connector 112 penetrating the glass block 111, the add-on structure 130 includes an insulating layer 131 and a conductive layer 132 embedded in the insulating layer 131, and the Young's modulus of the capping layer 120 is smaller than that of the insulating layer 131. Accordingly, by designing the Young's modulus and position of the capping layer 120, stress generated during the manufacturing process can be effectively alleviated, thereby improving the cracking problem (e.g., horizontal crack propagation) of the glass block 111 of the glass core circuit structure 110. Here, the vertical conductive connector 112 can be a TGV (Transient Voltage Variation). Furthermore, the vertical conductive connector 112 can be either fully filled or conformal, depending on design requirements.

[0018] exist Figure 1 In this configuration, the glass block 111 comprises two parts (separated by dashed lines 10L), such as glass block portion 111a and glass block portion 111b, wherein the thickness T1 of glass block portion 111a is greater than the thickness T2 of glass block portion 111b. For example, glass block portion 111b has a tapered profile in a direction away from glass block portion 111a, meaning that the thickness T2 of glass block portion 111b is the minimum thickness of glass block portion 111b. In this configuration, the glass core circuit structure 110 may include a trench 20. In this embodiment, the trench 20 is filled by a cover layer 120, such that the cover layer 120 can directly contact the insulating layer 131 and the glass core circuit structure 110. Furthermore, the cover layer 120 may be disposed only in the trench 20, and the insulating layer 131 may extend into the remaining space of the trench 20.

[0019] In some embodiments, the substrate 100 is a single-element component after dicing, such that the sidewalls 120s of the cover layer 120 can be aligned with the sidewalls 110s of the glass core circuit structure 110 (e.g., the sidewalls of the glass block portion 111b), that is, the sidewalls 120s of the cover layer 120 and the sidewalls 110s of the glass core circuit structure 110 can be located at substantially the same position in the vertical direction.

[0020] exist Figure 1In this process, the substrate 100 may also include a conductive pattern 101 that lands on the glass block 111 and the vertical conductive connector 112. That is, the conductive pattern 101 is in direct contact with the glass block 111 and the vertical conductive connector 112, and the conductive pattern 101 can be directly electrically connected to the vertical conductive connector 112 (without using additional conductive vias).

[0021] In addition, the substrate 100 may also include a barrier layer 140 and bumps 150. Specifically, the barrier layer 140 includes an opening 140a to expose the topmost conductive layer 132 of the build-up structure 130, such that the bumps 150 can be disposed in the opening 140a to contact the topmost conductive layer 132, thereby forming a conductive path.

[0022] In an alternative embodiment, the substrate 100 may further include a capping layer 160 disposed on the sidewalls 110s of the glass core circuit structure 110, the sidewalls 120s of the capping layer 120, the sidewalls 130s of the build-up structure 130, and the sidewalls 140s of the barrier layer 140, wherein the Young's modulus of the capping layer 160 is greater than or equal to the Young's modulus of the capping layer 120, to further provide protection. In another alternative embodiment, the capping layer 160 may be replaced by a capping layer 160A, which is disposed only on the sidewalls 120s of the capping layer 120 and the sidewalls 110s of the glass core circuit structure 110 (as shown by another dashed line), while the capping layer 160A may expose the sidewalls 130s of the build-up structure 130 and the sidewalls 140s of the barrier layer 140.

[0023] exist Figure 1 In this structure, the substrate 100 has an approximately symmetrical structure, which allows the substrate 100 to further include trenches 20A, conductive patterns 101A, a capping layer 120A, a build-up structure 130A (including an insulating layer 131A and a conductive layer 132A), and a barrier layer 140A, such as... Figure 1 As shown in the lower part, the implementation details of the trench 20A, conductive pattern 101A, cover layer 120A, add-on structure 130A (including insulating layer 131A and conductive layer 132A), and barrier layer 140A can be referred to the above description of the trench 20, conductive pattern 101A, cover layer 120, add-on structure 130 (including insulating layer 131A and conductive layer 132A), and barrier layer 140, respectively. For example, the trench 20A, conductive pattern 101A, cover layer 120A, add-on structure 130A (including insulating layer 131A and conductive layer 132A), and barrier layer 140A can be the same as or similar to the trench 20, conductive pattern 101, cover layer 120, add-on structure 130 (including insulating layer 131 and conductive layer 132A), and barrier layer 140, respectively. Here, the bump 150 can be formed only on one side.

[0024] In this approximately symmetrical structure, the add-on structure 130A is disposed on the surface of the glass core circuit structure 110 opposite to the add-on structure 130. The add-on structure 130 is electrically connected to the add-on structure 130A via the glass core circuit structure 110 (e.g., via conductive pattern 101, vertical conductive connector 112, and conductive pattern 101A). The add-on structure 130A includes an insulating layer 131A and a conductive layer 132A embedded in the insulating layer 131A, and the Young's modulus of the capping layer 120A is smaller than the Young's modulus of the insulating layer 131A. The above description is applicable here and will not be repeated.

[0025] It should be noted that, Figure 1 The approximate symmetrical structure in the illustration is for illustrative purposes only, and this disclosure is not limited thereto. As long as the substrate includes at least one cover layer embedded in the glass core circuit structure, and the cover layer and the insulating layer of the added-layer structure have corresponding design rules, it falls within the protection scope of this disclosure.

[0026] The manufacturing process of the aforementioned substrate 100 will be... Figures 2 to 8 The description in the text is as follows: Figures 7 to 8 In alternative embodiments, it may be by Figures 9 to 10 The alternative is described in detail below. It must be noted that the following embodiments continue to use the component reference numerals and some content from the above embodiments, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. The omitted descriptions can be referred to the above embodiments, and will not be repeated in the following embodiments.

[0027] Please refer to Figure 2The present invention provides a plurality of glass core circuit structures 110, wherein one of the glass core circuit structures 110 includes a glass bulk 111 and a vertical conductive connector 112. In some embodiments, the glass bulk 111 includes alkali glass, alkali-free glass, borosilicate glass, boro-aluminosilicate glass, lead glass, soda-lime glass, or the like. At this stage, the glass core circuit structure 110 includes chamfered edges on both outermost sides, but the present disclosure is not limited thereto. In some embodiments, the vertical conductive connector 112 may be formed by laser-induced deep etching (LIDE) process, metallization process, or other suitable process. For example, metallic materials (such as copper (Cu), titanium / copper (Ti / Cu), silver (Ag), gold (Au), nickel / gold (Ni / Au), nickel / palladium (Ni / Pd), nickel / palladium / gold (Ni / Pd / Au) or similar materials) may be used in the above process, but this disclosure is not limited thereto.

[0028] exist Figure 2 In this embodiment, conductive pattern 101 is formed on the top surface 120t of the vertical conductive connector 112, and conductive pattern 101A is formed on the bottom surface 120b of the vertical conductive connector 112. In some embodiments, conductive pattern 101 and conductive pattern 101A are formed by electroplating or similar processes, and metallic materials (e.g., copper (Cu), titanium / copper (Ti / Cu), silver (Ag), gold (Au), nickel / gold (Ni / Au), nickel / palladium (Ni / Pd), nickel / palladium / gold (Ni / Pd / Au) or similar materials) are used in the above processes, but this disclosure is not limited thereto.

[0029] Please refer to Figure 3 A mask layer 10 is formed on the top surface 110t of the glass core circuit structure 110, and a mask layer 10A is formed on the bottom surface 110b of the glass core circuit structure 110. For example, the mask layer 10 may have an opening 11 to expose the top surface 110t of the glass core circuit structure 110, and the mask layer 10A may have an opening 11A to expose the bottom surface 110b of the glass core circuit structure 110. Furthermore, the cutting region DR is formed by a portion of a glass block 111 located between adjacent glass core circuit structures 110, and this portion of the glass block 111 is exposed by both openings 11 and 11A.

[0030] On the other hand, the conductive pattern 101 can be protected by the mask layer 10 in a subsequent stage, and the conductive pattern 101A can be protected by the mask layer 10A in a subsequent stage. In some embodiments, the width W1 of the cut region DR is greater than or equal to 100 micrometers (µm), but this disclosure is not limited thereto.

[0031] In some embodiments, mask layer 10 and mask layer 10A are formed by a suitable process, such as laser direct imaging, photolithography and etching or a combination thereof, and a photosensitive material (e.g., photoresist or photosensitive dielectric layer (PID)) is used in the above processes.

[0032] Please refer to Figure 4 A portion of the glass block 111 is removed from the top surface 110t of the glass core circuit structure 110 through mask layer 10 to form trench 20, and another portion of the glass block 111 is removed from the bottom surface 110b of the glass core circuit structure 110 through mask layer 10A to form trench 20A. Neither trench 20 nor trench 20A penetrates the glass block 111, leaving a residual portion of the glass block 111 sandwiched between trench 20 and trench 20A. Please refer to... Figure 5 After trenches 20 and 20A are formed, mask layers 10 and 10A can be removed by a suitable process.

[0033] In some embodiments, a wet etching process (e.g., etching with an acidic etchant or an alkaline etchant) is performed to form trenches 20 and 20A. For example, etchants include hydrofluoric acid (HF), ammonium fluoride (NH4F), or sodium hydroxide (NaOH), but this disclosure is not limited thereto. In some embodiments, the shapes of trenches 20 and 20A in a cross-sectional schematic diagram may include arcuate, stepped, gradient, or similar shapes.

[0034] In some embodiments, the maximum thickness T of the glass block 111 is multiplied by 100% (t / T) by the thickness t of the residual glass block 111 sandwiched between the groove 20 and the groove 20A. The ratio of 100% to 20% is greater than or equal to 20%. Furthermore, the depth D of the trench (e.g., trench 20 or trench 20A) divided by the maximum thickness T and then multiplied by 100% (D / T) The ratio of 100% to 40% is less than or equal to 40%. This specific range can improve the reliability problems of glass blocks 111 caused by being too thin or too thick.

[0035] Please refer to Figure 6A capping layer 120 is formed in trench 20, and a capping layer 120A is formed in trench 20A. For example, the materials of capping layer 120 and capping layer 120A may include resin materials, such as Ajinomoto additive film (ABF), photosensitive dielectric layer (PID), epoxy-based materials (epoxy adhesives), silicon-based materials (silicone adhesives), or combinations thereof. Furthermore, capping layer 120 and capping layer 120A can be dispensed into trench 20 and trench 20A respectively via a pneumatic valve, a screw-down valve, or a piezoelectric valve, and then vacuum degassing, pre-curing, and post-curing processes are sequentially performed using a vacuum chamber.

[0036] In some embodiments, the filling depth d1 of the cover layer (e.g., cover layer 120 or cover layer 120A) may be less than the trench depth D, such as Figure 6 As shown, but not limited thereto, the filling depth d1 of the cover layer can be greater than or equal to the trench depth D (not shown). In some embodiments, the filling depth d1 of the cover layer is divided by the trench depth D and then multiplied by 100% (d1 / D). The ratio of 100% to 15% is greater than or equal to 15%.

[0037] Please refer to Figure 7 Addendum structure 130 is formed on the top surface 110t of glass core circuit structure 110, and addendum structure 130A is formed on the bottom surface 110b of glass core circuit structure 110. Addendum structure 130 and addendum structure 130A can have independent conductive structures at this stage, and there is a set of independent conductive structures between adjacent cut regions DR.

[0038] In this embodiment, trench 20 is filled with insulating layer 131 of add-on structure 130, and trench 20A is filled with insulating layer 131A of add-on structure 130A. Here, add-on structures 130 and 130A may use suitable add-on techniques (e.g., materials and processes), and this disclosure is not limited thereto. Figure 7 In the above, the insulating layer 131 of the add-on structure 130 and the insulating layer 131A of the add-on structure 130A may further extend to and surround the outermost glass core circuit structure 110 on both sides. In an embodiment not shown, the insulating layer 131 of the add-on structure 130 and the insulating layer 131A of the add-on structure 130A may not further extend to and surround the outermost glass core circuit structure 110 on both sides.

[0039] Next, barrier layer 140 is formed on add-on structure 130 using a suitable deposition process, and barrier layer 140A is formed on add-on structure 130A using a suitable deposition process. Then, bump 150 is formed in the opening 140a of barrier layer 140 using a suitable ball-mounting process. In some embodiments, bump 150 may be solder bumps or the like, and thus barrier layer 140 and barrier layer 140A may be solder resist or the like. In some embodiments, a coin process is performed on bump 150 such that the top surface 150t of bump 150 may be flat, such as... Figure 7 As shown, but this disclosure is not limited thereto, when the pressing process is omitted, the top surface of the bump is arc-shaped (not shown).

[0040] Please refer to Figure 8 ,exist Figure 3 A dicing process is performed on the dicing region DR to form a substrate 100. The substrate 100 includes: one of the glass core circuit structures 110, a portion of capping layer 120 and capping layer 120A, and a portion of add-on structure 130 and add-on structure 130A, such as... Figure 1 As shown in the diagram. Optionally, a cover layer 160 or a cover layer 160A may be formed, wherein the material of cover layer 160 or cover layer 160A includes a suitable resin material. In some embodiments, prior to the formation of the single substrate 100, another dicing process may be performed structurally to form a medium-sized panel type (not shown). In some embodiments, after the formation of the single substrate 100, automated optical inspection (AOI) testing, encapsulation processes, or other suitable processes may be performed.

[0041] In some embodiments, the dicing process includes wafer dicing saw process, laser ablation process, or laser grooving and modification process, but this disclosure is not limited thereto. In some embodiments, the width W1 of the dicing region DR is equal to 2. The residual width W2 + width W3 of the cutting area DR after the single-cutting process (e.g., the width of the cutting saw or the width of the laser beam).

[0042] exist Figures 7 to 8 In this process, bump 150 is formed before the dicing process is performed, but this disclosure is not limited thereto. Figures 9 to 10 In this process, bump 150 is not formed before the dicing process is performed; that is, bump 150 is formed after the dicing process is performed. For example, bump 150 is formed in a situation where... Figure 1 On a single substrate as shown.

[0043] Please refer to Figure 11 Similar to Figure 1 , Figure 11 substrate 200 and Figure 1The substrate 100 differs as follows. Specifically, the substrate 200 further includes a cover layer 220 covering the cover layer 120, and the Young's modulus of the cover layer 220 is less than that of the insulating layer 131. Accordingly, through the design of the Young's modulus and position of the cover layers 120 and 220, stress generated during the manufacturing process can be effectively alleviated, thereby improving the cracking problem of the glass core circuit structure 110. Furthermore, the Young's modulus of the cover layer 160 is greater than or equal to that of the cover layer 220 to further provide protective functionality.

[0044] In this embodiment, the capping layer 220 may extend on the surface of the glass core circuit structure 110 and the surface of the capping layer 120. Furthermore, the conductive pattern 201 is spaced apart from the glass block 111 by the capping layer 220. For example, the substrate 200 also includes a conductive via 270 penetrating the capping layer 220, and the conductive pattern 201 is electrically connected to the glass core circuit structure 110 through the conductive via 270. Additionally, the build-up structure 130 of the substrate 200 is in direct contact with the capping layer 220 and does not extend into the trench 20.

[0045] exist Figure 11 In this structure, substrate 200 has an approximately symmetrical structure, which allows substrate 200 to include, for example, Figure 11 The conductive pattern 201A, cover layer 220A, and conductive via 270A shown in the lower part are implemented in such a way that the implementation details of the conductive pattern 201A, cover layer 220A, and conductive via 270A can be referred to the descriptions of the conductive pattern 201, cover layer 220, and conductive via 270 above. For example, the conductive pattern 201A, cover layer 220A, and conductive via 270A may be the same as or similar to the conductive pattern 201, cover layer 220, and conductive via 270, respectively.

[0046] The manufacturing process of the aforementioned substrate 200 will be... Figures 12 to 18 The following is a detailed description. It must be noted that the following embodiments continue to use the component reference numerals and some content from the above embodiments, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. The omitted descriptions can be referred to in the above embodiments, and will not be repeated in the following embodiments. It should be noted that... Figure 9 and Figure 10 The description can also be applied to this embodiment.

[0047] Please refer to Figure 12 , Figure 13 and Figure 14 Similar to Figure 1 , Figure 5 and Figure 6 , Figure 12 , Figure 13 and Figure 14 Structure and Figure 1 , Figure 5 and Figure 6 The structural differences are as follows. Specifically, conductive patterns 101 and 101A can be omitted in this stage of the embodiment, so that conductive patterns 101 and 101A are not formed on the glass core circuit structure 110 before the formation of cover layer 120 and cover layer 120A, or conductive patterns 101 and 101A can be formed first and then removed by chemical mechanical planarization (CMP) process.

[0048] Please refer to Figure 15 Cover layer 220 is formed on the top surface 120t of cover layer 120 and the top surface 110t of glass core circuit structure 110, and cover layer 220A is formed on the top surface 120At of cover layer 120A and the bottom surface 110b of glass core circuit structure 110. In this embodiment, cover layer 220 and cover layer 220A completely cover glass core circuit structure 110. Furthermore, the thickness d2 of the cover layer (e.g., cover layer 220 or cover layer 220A) on glass core circuit structure 110 is greater than 1 μm. In some embodiments, the thickness d3 of the cover layer (e.g., cover layer 220 or cover layer 220A) on cover layer (e.g., cover layer 120 or cover layer 120A) is greater than or equal to the thickness d2.

[0049] Please refer to Figure 16 Conductive vias 270 are formed in the capping layer 220 by electroplating or a similar process, and conductive vias 270A are formed in the capping layer 220A by electroplating or a similar process. Next, conductive patterns 201 and 201A are formed on conductive vias 270 and 270A, respectively, by electroplating or a similar process. In some embodiments, metallic materials (e.g., copper (Cu), titanium / copper (Ti / Cu), silver (Ag), gold (Au), nickel / gold (Ni / Au), nickel / palladium (Ni / Pd), nickel / palladium / gold (Ni / Pd / Au), or the like) are used in the above processes, but this disclosure is not limited thereto.

[0050] Please refer to Figures 17 to 18 ,and Figures 7 to 8 similar, Figures 17 to 18 Structure and Figures 7 to 8 The structural differences are as follows. Specifically, cover layer 220 and cover layer 220A are introduced, so that the configuration relationship of add-on structure 130 and add-on structure 130A changes with the previously introduced layers (cover layer 220 and cover layer 220A).

[0051] Substrate 300 is shown in Figure 19In the middle, and the manufacturing process of substrate 300 will be Figures 20 to 23 The following description is provided. It must be noted that the following embodiments continue to use the component reference numerals and parts of the above embodiments, wherein the same or similar reference numerals are used to denote the same or similar components, and descriptions of the same technical content are omitted. The omitted descriptions can be referred to in the above embodiments, and will not be repeated in the following embodiments. It should be noted that... Figure 9 and Figure 10 The description can also be applied to this embodiment.

[0052] Please refer to Figures 19 to 23 Substrate 300 is similar to substrate 200, but differs from substrate 200 as follows. Specifically, capping layer 120 and capping layer 120A are omitted in this embodiment, while capping layer 220 and capping layer 220A are directly conformally disposed on the surfaces of trench 20 and trench 20A. In this embodiment, the sidewalls of capping layer 220 and capping layer 220A have concave contours. For example, Figure 14 The description can be omitted in this embodiment.

[0053] For those skilled in the art, various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the following claims and their equivalents.

Claims

1. A substrate, comprising: The glass core circuit structure includes glass blocks and vertical conductive connectors; The first cover layer is embedded in the glass core circuit structure; as well as A first add-on structure is disposed on the glass core circuit structure and electrically connected to the glass core circuit structure, wherein the first add-on structure includes a first insulating layer, and the Young's modulus of the first cover layer is smaller than the Young's modulus of the first insulating layer.

2. The substrate according to claim 1, further comprising: The second add-in structure, wherein the first add-in structure and the second add-in structure are respectively disposed on opposite surfaces of the glass core circuit structure, the first add-in structure is electrically connected to the second add-in structure through the glass core circuit structure, the second add-in structure includes a second insulating layer, and the Young's modulus of the first cover layer is smaller than the Young's modulus of the second insulating layer.

3. The substrate according to claim 1, wherein the glass block comprises a first glass block portion and a second glass block portion, the thickness of the first glass block portion being greater than the thickness of the second glass block portion.

4. The substrate of claim 3, wherein the second glass block portion has a tapered profile in a direction away from the first glass block portion.

5. The substrate according to claim 1, wherein the glass core circuit structure includes a trench, and the trench is filled by the first cover layer.

6. The substrate according to claim 5, wherein the first cover layer is in direct contact with the first insulating layer and the glass core circuit structure.

7. The substrate according to claim 5, further comprising: Conductive patterns are applied to the glass block and the vertical conductive connector.

8. The substrate according to claim 5, further comprising: A second cover layer covers the first cover layer, and the Young's modulus of the second cover layer is less than that of the first insulating layer.

9. The substrate of claim 8, wherein the second cover layer extends between the surface of the glass core circuit structure and the surface of the first cover layer.

10. The substrate according to claim 8, further comprising: A conductive pattern, wherein the conductive pattern is spaced apart from the glass block by the second cover layer.

11. The substrate according to claim 8, further comprising: A third cover layer is disposed on the sidewall of the first cover layer and the sidewall of the glass core circuit structure, and the Young's modulus of the third cover layer is greater than or equal to the Young's modulus of the first cover layer and / or the second cover layer.

12. The substrate of claim 1, wherein the glass core circuit structure includes a trench, and the first cover layer is conformally disposed on the surface of the trench.

13. The substrate of claim 12, wherein the sidewalls of the first cover layer have a concave profile.

14. The substrate of claim 1, wherein the sidewalls of the first cover layer are aligned with the sidewalls of the glass core circuit structure.

15. The substrate according to claim 1, wherein the material of the first capping layer comprises an Ajinomoto layer, a photosensitive dielectric layer, an epoxy-based material, a silicon-based material, or a combination thereof.

16. A method for manufacturing a substrate, comprising: Multiple glass core circuit structures are provided, wherein the cut area is formed by glass block portions located between adjacent glass core circuit structures; Remove a portion of the glass block to form a groove; A covering layer is formed in the trench; An add-in structure is formed on the plurality of glass core circuit structures, wherein the add-in structure is electrically connected to the plurality of glass core circuit structures, and the Young's modulus of the cover layer is less than the Young's modulus of the insulating layer of the add-in structure. as well as A dicing process is performed on the dicing area to form the substrate comprising one of the glass core circuit structures, a portion of the cover layer, and a portion of the add-on structure.

17. The method for manufacturing a substrate according to claim 16, further comprising: Before performing the cutting process, multiple bumps are formed on the layered structure.

18. The method for manufacturing a substrate according to claim 16, further comprising: After the cutting process is performed, multiple bumps are formed on the layered structure.

19. The method for manufacturing a substrate according to claim 16, further comprising: Prior to forming the trench, multiple conductive patterns are formed on the multiple glass core circuit structures.

20. The method for manufacturing a substrate according to claim 16, further comprising: After the cover layer is formed, multiple conductive patterns are formed on the multiple glass core circuit structures.

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