Low parasitic inductance vdmos package structure

Abstract

This invention provides a low parasitic inductance VDMOS package structure, relating to the field of semiconductor packaging technology. It includes a substrate, a VDMOS chip, flat gate leads, source leads, drain leads, and a package body. It uses flat copper strips instead of circular leads, shortening the equivalent length of the current path while maintaining the same conductive cross-sectional area, thereby reducing the self-inductance coefficient.

Description

Technical Field

[0001] This invention relates to semiconductor packaging technology, and more particularly to a low parasitic inductance VDMOS packaging structure. Background Technology

[0002] Traditional VDMOS packaging structures use circular gold or aluminum wires with a diameter of 0.2-0.3mm as gate leads, which are connected to the chip gate pads and external pins through wire bonding. This circular lead structure has a parasitic inductance problem under high-frequency operating conditions, with a typical parasitic inductance value of 2.1-2.5nH.

[0003] Existing technologies have included improvements such as using flat strip wire bonding technology, but these mainly focus on mechanical connection strength and do not optimize for high-frequency parasitic parameters. They also reduce inductance using multilayer lead structures, but this involves complex manufacturing processes and significantly increases costs. They also use special lead layouts to reduce mutual inductance, but this has limited effect on reducing self-inductance.

[0004] Therefore, how to shorten the equivalent length of the current path and reduce the self-inductance under the same conductive cross-sectional area has become an urgent problem to be solved. Summary of the Invention

[0005] This invention provides a low parasitic inductance VDMOS package structure that uses flat copper strips instead of circular leads, thereby shortening the equivalent length of the current path while maintaining the same conductive cross-sectional area, thus reducing the self-inductance coefficient.

[0006] A first aspect of the present invention provides a low parasitic inductance VDMOS package structure, comprising: Substrate 50, VDMOS chip 10 disposed on substrate 50, VDMOS chip 10 having gate pad 11 and source pad 12; The flat gate lead 20 is electrically connected to the gate pad 11 and the gate pin 60; Source lead 40 is electrically connected to the source pad 12 and the source pin 61; The drain lead is electrically connected to the drain of the VDMOS chip 10 and the drain pin 62. And a package 70, which covers the substrate 50, the drain lead, the VDMOS chip 10, the flat gate lead 20 and the source lead 40.

[0007] Optionally, in one possible implementation of the first aspect, the VDMOS chip 10 disposed on the substrate 50 includes: The substrate 50 has a first surface 51 and a second surface 52; The VDMOS chip 10 is reflow soldered onto the first surface 51 of the substrate 50 based on conductive silver paste 80.

[0008] Optionally, in one possible implementation of the first aspect, the flat gate lead 20 includes: The flat gate lead 20 is a flat copper strip structure with a rectangular cross-section, a thickness of 0.35-0.4 mm, a width of 2.5-3.0 mm, and a width-to-thickness ratio of 6.25-8.57.

[0009] The surface of the flat gate lead 20 is provided with a micro-trench structure 21.

[0010] Optionally, in one possible implementation of the first aspect, the microgroove structure 21 includes: The trench depth of the microgroove structure 21 is 5μm to 10μm, the trench spacing is 20μm to 30μm, and the extension direction of the microgroove structure 21 is parallel to the current flow direction.

[0011] Optionally, in one possible implementation of the first aspect, the flat copper strip structure includes: The flat copper strip structure is made of oxygen-free copper material, and the purity of the oxygen-free copper material is greater than or equal to 99.95%. The surface of the flat copper strip structure is sequentially plated with a nickel layer and a gold layer, wherein the thickness of the nickel layer is 2 μm to 5 μm and the thickness of the gold layer is 0.1 μm to 0.3 μm.

[0012] Optionally, in one possible implementation of the first aspect, the encapsulation structure further includes: A silicon nitride ceramic shielding sheet 30 is disposed between the flat gate lead 20 and the source lead 40.

[0013] Optionally, in one possible implementation of the first aspect, the silicon nitride ceramic shield 30 is disposed between the flat gate lead 20 and the source lead 40, comprising: The silicon nitride ceramic shield 30 is bonded and fixed to the VDMOS chip 10 between the flat gate lead 20 and the source lead 40 using high-temperature resistant insulating adhesive and preset spacing conditions.

[0014] Optionally, in one possible implementation of the first aspect, the preset spacing condition includes: The vertical spacing between the silicon nitride ceramic shield 30 and the flat gate lead 20 is 0.1 mm to 0.2 mm, and the vertical spacing between the silicon nitride ceramic shield 30 and the source lead 40 is 0.15 mm to 0.25 mm.

[0015] Optionally, in one possible implementation of the first aspect, the flat gate lead 20 electrically connects the gate pad 11 and the gate pin 60, including: Based on the bonding process, the flat gate lead 20 is sequentially connected to the gate pad 11, and the flat gate lead 20 is sequentially connected to the gate pin 60.

[0016] Optionally, one possible implementation of the first aspect includes: The EMC material was encapsulated at 175°C and 80 kg / cm² pressure for 90 seconds to obtain the encapsulated body.

[0017] The beneficial effects of this invention are as follows: 1. This structure uses flat copper strips instead of round leads, which shortens the equivalent length of the current path while maintaining the same conductive cross-sectional area, thereby reducing the self-inductance coefficient.

[0018] 2. This structure introduces a silicon nitride ceramic shielding sheet, which utilizes its high dielectric constant and high thermal conductivity to provide electric field shielding without affecting heat dissipation. The gate-source mutual inductance is reduced by more than 60%, which facilitates the suppression of crosstalk noise. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a low parasitic inductance VDMOS package structure provided by the present invention; Figure 2 This is a partially enlarged schematic diagram of a gate lead region provided by the present invention. Figure 3 This is a longitudinal cross-sectional view of a packaging structure provided by the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein.

[0022] It should be understood that in the various embodiments of the present invention, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0023] It should be understood that in this invention, "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0024] It should be understood that in this invention, "multiple" refers to two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "Contains A, B, and C", "Contains A, B, and C" means that all three A, B, and C are contained; "Contains A, B, or C" means that one of A, B, and C is contained; "Contains A, B, and / or C" means that any one, two, or three of A, B, and C are contained.

[0025] It should be understood that in this invention, "B corresponding to A", "B corresponding to A", "A and B correspond", or "B and A correspond" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information. Matching A and B is defined as a similarity between A and B that is greater than or equal to a preset threshold.

[0026] Depending on the context, "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection."

[0027] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0028] like Figure 1 As shown, this invention provides a three-dimensional schematic diagram of a low parasitic inductance VDMOS package structure, which includes: S1, substrate 50, VDMOS chip 10 disposed on the substrate 50, the VDMOS chip 10 having a gate pad 11 and a source pad 12.

[0029] S11, the substrate 50 has a first surface 51 and a second surface 52.

[0030] S12, the VDMOS chip 10 is reflow soldered onto the first surface 51 of the substrate 50 based on conductive silver paste 80.

[0031] Understandably, the process involves preparing a DBC substrate and performing surface cleaning, screen printing conductive silver paste, placing a VDMOS chip, and reflow soldering to fix the VDMOS chip onto the first surface of the substrate.

[0032] The first surface is the surface of the substrate facing upwards, and the second surface is the surface facing downwards relative to the first surface.

[0033] S2, the flat gate lead 20 is electrically connected to the gate pad 11 and the gate pin 60.

[0034] S21, the flat gate lead 20 is a flat copper strip structure with a rectangular cross-section, a thickness of 0.35-0.4mm, a width of 2.5-3.0mm, and a width-to-thickness ratio of 6.25-8.57.

[0035] Understandably, replacing round leads with flat copper strips can shorten the equivalent length of the current path while maintaining the same conductive cross-sectional area, thereby reducing the self-inductance.

[0036] S211, the flat copper strip structure is made of oxygen-free copper material, and the purity of the oxygen-free copper material is greater than or equal to 99.95%.

[0037] S212, the surface of the flat copper strip structure is sequentially plated with a nickel layer and a gold layer, wherein the thickness of the nickel layer is 2μm to 5μm and the thickness of the gold layer is 0.1μm to 0.3μm.

[0038] S22, a micro-trench structure 21 is provided on the surface of the flat gate lead 20.

[0039] S221, the trench depth of the microtrench structure 21 is 5μm to 10μm, the trench spacing is 20μm to 30μm, and the extension direction of the microtrench structure 21 is parallel to the current flow direction.

[0040] It is understandable that, such as Figure 2 The diagram shows a partially enlarged schematic of the gate lead area, with a nickel and gold layer plated on the surface. The flat gate lead has a thickness of 0.35-0.4 mm and a width of 2.5-3.0 mm. A micro-trench structure 21 is set on the surface of the flat lead, with a trench depth of 5-10 μm and a spacing of 20-30 μm. The micro-trench structure is arranged along the current direction, which can increase the equivalent path length of the high-frequency current and destroy the continuous current layer under the skin effect, thereby reducing the equivalent inductance and AC resistance.

[0041] S23, based on the bonding process, the flat gate lead 20 is sequentially connected to the gate pad 11, and the flat gate lead 20 is connected to the gate pin 60.

[0042] Understandably, a special fixture is used to position the flat copper strip for wire bonding, where the bonding process can be ultrasonic bonding or thermo-press bonding, so that the two ends of the flat gate lead are connected to the gate pad and the gate pin, respectively.

[0043] S3, source lead 40, electrically connects the source pad 12 and the source pin 61.

[0044] It is understood that the way the source lead electrically connects the source pad and the source pin is the same as the connection method of the existing package structure, and will not be described in detail here.

[0045] S4, drain lead, electrically connects the drain of the VDMOS chip 10 to the drain pin 62.

[0046] It is understandable that the way the drain leads connect to the drain of the VDMOS chip is the same as the connection method of the existing package structure, and will not be described in detail here.

[0047] S5, and package 70, which covers the substrate 50, the drain lead, the VDMOS chip 10, the flat gate lead 20 and the source lead 40.

[0048] The package includes: S51, the EMC material is encapsulated at 175°C and 80 kg / cm² pressure for 90 seconds to obtain the encapsulated body.

[0049] It is understandable that the material of the package is EMC material.

[0050] The packaging structure further includes: A1, silicon nitride ceramic shielding sheet 30, wherein the silicon nitride ceramic shielding sheet 30 is disposed between the flat gate lead 20 and the source lead 40.

[0051] It is understandable that, such as Figure 3 The diagram shows a longitudinal cross-sectional view of the package structure. In this package structure, a silicon nitride ceramic shield is introduced. A silicon nitride ceramic shield 30 with a thickness of 0.04-0.06 mm is placed between the flat gate lead and the source lead. Utilizing its high dielectric constant of 7.5-8.0 and high thermal conductivity of 80-90 W / m·K, it provides electric field shielding without affecting heat dissipation.

[0052] A11, based on high-temperature resistant insulating adhesive and preset spacing conditions, the silicon nitride ceramic shield 30 is bonded and fixed between the flat gate lead 20 and the source lead 40 on the VDMOS chip 10.

[0053] It is understandable that when fixing the silicon nitride ceramic shield between the flat gate lead and the source lead, it is necessary to maintain a certain distance from both the flat gate lead and the source lead. The high-temperature resistant insulating adhesive can be epoxy resin.

[0054] The preset spacing conditions are as follows: the vertical spacing between the silicon nitride ceramic shield 30 and the flat gate lead 20 is 0.1 mm to 0.2 mm, and the vertical spacing between the silicon nitride ceramic shield 30 and the source lead 40 is 0.15 mm to 0.25 mm.

[0055] It is easy to understand that not only can high-temperature resistant insulating adhesive be used to fix the silicon nitride ceramic shield, but the encapsulating material of the package can also be used to fix the silicon nitride ceramic shield between the flat gate lead and the source lead.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low parasitic inductance VDMOS package structure, characterized in that, include: A substrate (50) and a VDMOS chip (10) disposed on the substrate (50), wherein the VDMOS chip (10) is provided with a gate pad (11) and a source pad (12). The flat gate lead (20) electrically connects the gate pad (11) to the gate pin (60). Source lead (40) electrically connects the source pad (12) to the source pin (61). The drain lead is electrically connected to the drain of the VDMOS chip (10) and the drain pin (62). And a package (70) covering the substrate (50), the drain lead, the VDMOS chip (10), the flat gate lead (20) and the source lead (40).

2. The structure according to claim 1, characterized in that, The VDMOS chip (10) disposed on the substrate (50) includes: The substrate (50) has a first surface (51) and a second surface (52); The VDMOS chip (10) is reflow soldered onto the first surface (51) of the substrate (50) based on conductive silver paste (80).

3. The structure according to claim 1, characterized in that, The flat gate lead (20) includes: The flat gate lead (20) is a flat copper strip structure with a rectangular cross-section, a thickness of 0.35-0.4 mm, a width of 2.5-3.0 mm, and a width-to-thickness ratio of 6.25-8.

57. The surface of the flat gate lead (20) is provided with a micro trench structure (21).

4. The structure according to claim 3, characterized in that, The microgroove structure (21) includes: The trench depth of the microgroove structure (21) is 5μm to 10μm, the trench spacing is 20μm to 30μm, and the extension direction of the microgroove structure (21) is parallel to the current flow direction.

5. The structure according to claim 3, characterized in that, The flat copper strip structure includes: The flat copper strip structure is made of oxygen-free copper material, and the purity of the oxygen-free copper material is greater than or equal to 99.95%. The surface of the flat copper strip structure is sequentially plated with a nickel layer and a gold layer, wherein the thickness of the nickel layer is 2 μm to 5 μm and the thickness of the gold layer is 0.1 μm to 0.3 μm.

6. The structure according to claim 1, characterized in that, The packaging structure further includes: A silicon nitride ceramic shield (30) is disposed between the flat gate lead (20) and the source lead (40).

7. The structure according to claim 6, characterized in that, The silicon nitride ceramic shield (30) is disposed between the flat gate lead (20) and the source lead (40), and includes: Based on the high-temperature resistant insulating adhesive and the preset spacing conditions, the silicon nitride ceramic shield (30) is bonded and fixed between the flat gate lead (20) and the source lead (40) on the VDMOS chip (10).

8. The structure according to claim 7, characterized in that, The preset spacing conditions include: The vertical spacing between the silicon nitride ceramic shield (30) and the flat gate lead (20) is 0.1 mm to 0.2 mm, and the vertical spacing between the silicon nitride ceramic shield (30) and the source lead (40) is 0.15 mm to 0.25 mm.

9. The structure according to claim 1, characterized in that, The flat gate lead (20) electrically connects the gate pad (11) and the gate pin (60), including: Based on the bonding process, the flat gate lead (20) is sequentially connected to the gate pad (11), and the flat gate lead (20) is connected to the gate pin (60).

10. The structure according to claim 1, characterized in that, The package includes: The EMC material was encapsulated at 175°C and 80 kg / cm² pressure for 90 seconds to obtain the encapsulated body.

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