Multi-core sealing structure and preparation method thereof

Abstract

This application relates to the field of packaging technology and discloses a multi-core encapsulation structure and its fabrication method. The multi-core encapsulation structure includes: a substrate, an irregularly shaped metal conductive component, an embedded chip, a first electroplated copper layer, a second electroplated copper layer, a surface-mount chip, and an encapsulation structure. The encapsulation structure is partially embedded in the irregular structure of the irregularly shaped metal conductive component and forms a mechanically interlocking interface. The irregularly shaped metal conductive component used in this application can form a mechanically interlocking interface with the encapsulation structure, increasing the effective contact area between the irregularly shaped metal conductive component and the encapsulation material, improving the bonding strength between the metal and the encapsulation material, and reducing the risk of interface dragging, delamination, or cracking of the package under thermal cycling, power cycling, or mechanical stress. Simultaneously, it can also perform current transmission and heat dissipation functions. Combined with the three-dimensional copper interconnect path formed by electroplated copper, low-resistance, low-parasitic, and high-current-carrying interconnection between the embedded chip and the surface-mount chip is achieved.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a multi-chip encapsulation structure and its fabrication method. Background Technology

[0002] In recent years, embedded chip packaging and panel-level packaging technologies have been increasingly applied to the field of power semiconductor packaging. Embedding power semiconductor chips in printed circuit boards or resin packages helps to shorten current loops, reduce interconnect resistance and parasitic inductance, and improve heat dissipation through thick copper structures. Furthermore, embedded PCB packaging of power semiconductors can reduce converter size, shorten current loops, reduce interconnect resistance and parasitic inductance, and improve heat dissipation through thick copper substrates. Moreover, chip embedding technology can achieve new interconnection methods without the use of bonding wires, and improve thermal performance, electrical performance, and chip stacking capabilities.

[0003] In wafer-level fan-out packaging or embedded semiconductor packaging, chips are typically embedded within epoxy molding compounds or resin packages, and copper redistribution layers are used to connect the chip's input / output terminals to external circuitry or printed circuit boards. For example, existing embedded semiconductor packaging solutions disclose structures that embed chips within epoxy molding compounds and form copper redistribution layers within or on the surface of the molding compound. However, such structures also suffer from problems such as chip misalignment and warpage caused by the molding compound, as well as mismatches in the coefficients of thermal expansion between the chip and the molding compound. While this technology can achieve chip embedding and redistribution interconnection, for multi-chip power semiconductor packaging, relying solely on ordinary redistribution layers often makes it difficult to simultaneously achieve high current carrying capacity, low parasitic interconnection, thick copper heat dissipation, and long-term interface reliability between the metal and resin within the package.

[0004] Furthermore, in power packaging and molded semiconductor devices, the reliability of the interfacial bonding between metal components and epoxy resin or molding compound is also a crucial factor affecting package lifespan. Due to differences in thermal expansion coefficients, elastic moduli, and surface chemical properties between metals such as copper and aluminum and epoxy resins, the metal-resin interface is prone to debonding, delamination, or crack propagation under thermal cycling, power cycling, humid and hot environments, or mechanical stress.

[0005] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of this application is to provide a multi-core encapsulation structure and its preparation method to solve the problem of poor interfacial bonding reliability between metal parts and epoxy resin in power packaging.

[0007] The technical solution of this application is as follows: In a first aspect, this application provides a multi-core encapsulation structure, which includes: substrate; An irregularly shaped metal conductive component is disposed on the substrate; the side of the irregularly shaped metal conductive component has an irregular structure. An embedded chip is disposed on the irregularly shaped metal conductive component; A first electroplated copper and a second electroplated copper, wherein the first electroplated copper is connected to the embedded chip and the second electroplated copper is connected to the irregularly shaped metal conductive component; Surface chips are respectively disposed on the first electroplated copper and the second electroplated copper; Chip electrodes are disposed on the surface chip; An encapsulation structure is located on the substrate and covers the irregularly shaped metal conductive component, the embedded chip, the surface chip, the first electroplated copper, the second electroplated copper, and the chip electrode; wherein, the chip electrode portion is exposed outside the encapsulation structure; the encapsulation structure portion is embedded in the irregular structure of the irregularly shaped metal conductive component and forms a mechanical locking interface.

[0008] In a further embodiment of this application, the irregular structure includes a stepped structure, a notched structure, a protruding structure, or a non-straight sidewall structure.

[0009] In a further provision of this application, at least one second electroplated copper is provided.

[0010] In a further embodiment of this application, the encapsulation structure is made of epoxy resin material.

[0011] In a further embodiment of this application, the chip electrode has a Z-shaped structure; the chip electrode is a copper electrode.

[0012] In a further embodiment of this application, the surface chip is fixed to the first electroplated copper and the second electroplated copper by a conductive connecting material; the embedded chip is fixed to the irregularly shaped metal conductive component by a conductive connecting material.

[0013] In a further embodiment of this application, the irregularly shaped metal conductive component is an irregularly shaped copper component.

[0014] Secondly, this application also provides a method for preparing a multi-core encapsulation structure as described above, comprising the following steps: Provide a substrate; An irregularly shaped metal conductive component is disposed on the substrate; wherein, the side of the irregularly shaped metal conductive component has an irregular structure. The embedded chip is fixed onto the irregularly shaped metal conductive component using a conductive connecting material; The embedded chip and the irregularly shaped metal conductive component are encapsulated with epoxy resin, so that the epoxy resin fills around the irregularly shaped metal conductive component and enters the region of the irregular structure to form a mechanical locking interface. Windows or grooves are formed in the epoxy resin to expose local areas of the embedded chip and / or the irregularly shaped metal conductive component; Electroplated copper is formed on the surface of epoxy resin and in the windowed area, and the electroplated copper is connected to the embedded chip and the irregular metal conductive component to form a continuous copper interconnect path. A surface chip is set in a predetermined area of ​​electroplated copper; Chip electrodes are formed or connected on the surface chip; The surface chip, the chip electrodes, and the electroplated copper interconnect area are encapsulated a second time.

[0015] In a further embodiment of this application, the chip electrode is a copper electrode; the chip electrode is formed by electroplating, sputtering, vapor deposition, welding, bonding, or prefabrication.

[0016] In a further provision of this application, when performing secondary encapsulation on the surface chip, the chip electrode, and the electroplated copper interconnect area, the encapsulation material includes epoxy resin and epoxy film plastic.

[0017] This application provides a multi-core encapsulation structure and its fabrication method. The multi-core encapsulation structure includes: a substrate; a shaped metal conductive element disposed on the substrate; the shaped metal conductive element has an irregular structure on its side; an embedded chip disposed on the shaped metal conductive element; a first electroplated copper and a second electroplated copper, the first electroplated copper being connected to the embedded chip and the second electroplated copper being connected to the shaped metal conductive element; a surface chip disposed on the first electroplated copper and the second electroplated copper; a chip electrode disposed on the surface chip; and an encapsulation structure located on the substrate and covering the shaped metal conductive element, the embedded chip, the surface chip, the first electroplated copper, the second electroplated copper, and the chip electrode; wherein the chip electrode portion is exposed outside the encapsulation structure; and the encapsulation structure portion is embedded in the irregular structure of the shaped metal conductive element and forms a mechanical locking interface. The irregularly shaped conductive metal structure used in this application can form a mechanically interlocking interface with the encapsulation structure, increasing the effective contact area between the irregularly shaped conductive metal component and the encapsulation material, improving the bonding strength between the metal and the encapsulation material, and reducing the risk of interface dragging, delamination, or cracking of the package under thermal cycling, power cycling, or mechanical stress. Simultaneously, the irregularly shaped conductive metal component not only serves as a chip carrier or connection structure but also undertakes current transmission and heat dissipation functions. Furthermore, combined with the three-dimensional copper interconnect path formed by electroplated copper, low-resistance, low-parasitic, and high-current-carrying interconnects between embedded chips and surface-mount chips are achieved, thereby improving the electrical performance, heat dissipation capacity, and interface reliability of the multi-chip structure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a multi-core encapsulation structure in one embodiment of this application.

[0020] Figure 2 This is a schematic diagram of the preparation method of a multi-core encapsulation structure in one embodiment of this application.

[0021] Figure 3 This is a flowchart of a method for preparing a multi-core encapsulation structure in one embodiment of this application.

[0022] The following are the markings in the attached figures: 1. Substrate; 2. Irregularly shaped metal conductive component; 21. Irregular structure; 3. Embedded chip; 4. First copper plating; 5. Second copper plating; 6. Surface chip; 7. Chip electrode; 8. Encapsulation structure. Detailed Implementation

[0023] This application provides a multi-core encapsulation structure and its preparation method. To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description is provided with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit the scope of this application.

[0024] In the implementation methods and scope of the claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of this application involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0025] It should be further understood that the term "comprising" as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any units and all combinations thereof of one or more associatedly listed items.

[0026] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0027] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0028] As power semiconductor devices evolve towards higher power density, higher switching frequencies, and miniaturization, the chip interconnect structure within power modules has an increasingly significant impact on the electrical, thermal, and reliability performance of the package. In traditional power semiconductor packaging, chips are typically mounted on a substrate or lead frame, and electrical connections between chip electrodes and external terminals are achieved through aluminum wire bonding, copper wire bonding, copper clips, metal strips, or redistribution layers. For multi-chip co-package structures, interconnect paths with low resistance, low parasitic inductance, and high current carrying capacity need to be formed between the multiple chips; otherwise, problems such as voltage overshoot, oscillation, localized heating, and uneven current distribution during switching can easily occur.

[0029] In existing power device packaging, using metal strips or copper clips to replace traditional bonding wires is a common approach. For example, in existing high-power semiconductor device packaging solutions, conductive metal strips are used to electrically and thermally connect the semiconductor chip to the metal lead frame to improve connection reliability and mitigate shear stress issues caused by temperature changes. This type of solution can improve current carrying capacity and reduce parasitic parameters to some extent. However, metal strips or copper clips typically require pre-forming, positioning, and soldering, limiting structural freedom and making it difficult to flexibly form complex three-dimensional interconnect paths in multi-chip, multi-layer, or embedded packaging structures.

[0030] Embedded chip packaging and panel-level packaging technologies are increasingly being applied to the field of power semiconductor packaging. Embedding power semiconductor chips into printed circuit boards or resin packages helps shorten current loops, reduce interconnect resistance and parasitic inductance, and improves heat dissipation through thick copper structures. Furthermore, embedded PCB packaging of power semiconductors can reduce converter size, shorten current loops, reduce interconnect resistance and parasitic inductance, and improve heat dissipation through thick copper substrates. Moreover, chip embedding technology can achieve new interconnection methods without using bonding wires and improve thermal performance, electrical performance, and chip stacking capabilities. In wafer-level fan-out packaging or embedded semiconductor packaging, chips are typically embedded in epoxy molding compounds or resin packages, and copper redistribution layers are used to connect the chip's input / output terminals to external circuitry or printed circuit boards. For example, existing embedded semiconductor packaging solutions disclose structures that embed chips in epoxy molding compounds and form copper redistribution layers within or on the surface of the molding compound; however, such structures also suffer from problems such as chip misalignment and warpage caused by the molding compound, and mismatch in thermal expansion coefficients between the chip and the molding compound. While this type of technology can achieve chip embedding and redistribution interconnection, for multi-chip packages of power semiconductors, relying solely on ordinary redistribution layers often makes it difficult to simultaneously ensure high current carrying capacity, low parasitic interconnection, thick copper heat dissipation, and long-term interface reliability between the metal and resin inside the package.

[0031] Furthermore, in power packaged and molded semiconductor devices, the reliability of the interfacial bonding between the metal components and the epoxy resin or molding compound is also a crucial factor affecting package lifespan. Due to differences in thermal expansion coefficients, elastic moduli, and surface chemical properties between metals such as copper and aluminum and epoxy resins, the metal-resin interface is prone to debonding, delamination, or crack propagation under thermal cycling, power cycling, humid environments, or mechanical stress. Existing technologies typically improve the bonding strength between the leadframe and the molding compound by increasing the surface area and providing mechanical interlocking through structures such as holes, grooves, or hemispherical recesses on the leadframe surface. Other publicly available solutions for power semiconductor chips propose forming interlocking structures on structured metallized surfaces to create a more reliable bonding interface with the copper interconnect layer or epoxy-based packaging material, thereby reducing adhesion failure under shear stress conditions.

[0032] The existing technologies still have the following shortcomings: First, traditional bonding wire, metal strip, or copper clip interconnection methods are easily limited by the interconnection path length, spatial layout, and shape of pre-formed metal parts in multi-chip package structures, making it difficult to flexibly form three-dimensional copper interconnection structures suitable for staggered chips or embedded chips; Second, although ordinary embedded chip packages can achieve electrical connections through copper redistribution layers, the redistribution layers usually mainly serve the function of electrical signal or current extraction, and are still insufficient for the high current carrying capacity, heat diffusion, and structural reinforcement capabilities required by power devices; Third, after thick copper parts or large-size metal parts are embedded in epoxy resin packages, the interface is prone to debonding and delamination during thermal cycling and power cycling due to the mismatch in the thermal expansion coefficients between the metal and the resin; Fourth, existing metal surface roughening, trenching, or coating enhancement schemes mostly focus on improving the adhesion performance between a single metal surface and the resin, and have not fully combined the process requirements of high current interconnection, chip embedding, resin encapsulation, windowing, and electroplated copper three-dimensional interconnection in multi-chip power packaging.

[0033] To address the aforementioned technical problems, this application proposes a multi-chip encapsulation structure and its fabrication method. This structure enables the placement of irregularly shaped metal conductive components with mechanical anchoring capabilities within the package. The contact area between the irregularly shaped metal conductive components and the encapsulation material is increased through steps, grooves, notches, protrusions, or non-straight sidewall structures, forming a mechanical interlocking interface after the encapsulation material cures. Simultaneously, continuous three-dimensional copper interconnect paths are formed through windowing in the encapsulation material and copper electroplating processes, achieving low-resistance, low-parasitic, and high-current interconnection between embedded chips and surface-mount chips. This improves the electrical performance, heat dissipation capacity, and interface reliability of the multi-chip package structure.

[0034] Please also refer to Figure 1 This application provides a preferred embodiment of a multi-core encapsulation structure.

[0035] In some embodiments, such as Figure 1As shown, this application provides a multi-core encapsulation structure, comprising: a substrate 1; a shaped metal conductive element 2 disposed on the substrate 1; the shaped metal conductive element 2 having an irregular structure 21 on its side; an embedded chip 3 disposed on the shaped metal conductive element 2; a first electroplated copper 4 and a second electroplated copper 5, the first electroplated copper 4 being connected to the embedded chip 3, and the second electroplated copper 5 being connected to the shaped metal conductive element 2; a surface chip 6 disposed on the first electroplated copper 4 and the second electroplated copper 5 respectively; a chip electrode 7 disposed on the surface chip 6; and an encapsulation structure 8 located on the substrate 1 and covering the shaped metal conductive element 2, the embedded chip 3, the surface chip 6, the first electroplated copper 4, the second electroplated copper 5, and the chip electrode 7; wherein, the chip electrode 7 is partially exposed outside the encapsulation structure 8; and the encapsulation structure 8 is partially embedded in the irregular structure 21 of the shaped metal conductive element 2 to form a mechanical locking interface.

[0036] In this embodiment, the multi-core encapsulation structure refers to a structure in which an embedded chip 3 and a surface-mount chip 6 are encapsulated together. The substrate 1 serves as the carrier of the entire encapsulation structure. The encapsulation structure 8 covers the substrate 1 and can encapsulate the irregularly shaped metal conductive component 2, the embedded chip 3, the surface-mount chip 6, the first electroplated copper 4, the second electroplated copper 5, and the chip electrode 7. The chip electrode 7 is partially exposed outside the encapsulation structure 8 and can be used to connect to external terminals, metal connectors, heat dissipation structures, or subsequent encapsulation structures.

[0037] The irregularly shaped metal conductive component 2, the first electroplated copper 4, and the second electroplated copper 5 form a continuous copper interconnect path, realizing the three-dimensional interconnection between the embedded chip 3 and the surface chip 6. During the process of the encapsulation structure 8 covering the irregularly shaped metal conductive component 2 and the embedded chip 3, the material of the encapsulation structure 8 is embedded in the irregular structure 21 of the irregularly shaped metal conductive component 2, and forms a mechanically locking interface with the irregularly shaped metal conductive structure after curing.

[0038] In the above technical solution, this application adopts an irregularly shaped metal conductive structure with an irregular structure 21. During the encapsulation process (the encapsulation material is fluid during encapsulation), the encapsulation structure 8 can enter the irregular structure 21 region of the irregularly shaped metal conductive component 2 and form a mechanical interlocking structure with the irregularly shaped metal conductive component 2 after curing. Compared with traditional flat copper sheets or regular copper components, this increases the effective contact area between the irregularly shaped metal conductive component 2 and the encapsulation material, improves the bonding strength between the metal and the encapsulation material, and reduces the risk of interface dragging, delamination, or cracking of the package under thermal cycling, power cycling, or mechanical stress. In addition, it should be understood that in existing multi-chip packages, after thick copper components or large-size metal connectors are embedded in resin, stress concentration is easily generated at the interface due to the mismatch of the thermal expansion coefficients of copper and epoxy resin. This application utilizes the mechanical anchoring effect between the irregularly shaped metal conductive component 2 and the encapsulation material to achieve a more stable structural constraint for the irregularly shaped metal conductive component 2 within the package. This helps to suppress interface peeling and positional displacement of the thick copper component during temperature changes or power loading, thereby improving the overall stability of the package structure.

[0039] The copper interconnect path formed by the irregularly shaped metal conductive element 2 and electroplated copper, compared with traditional bonding wires, metal strips, or copper clip interconnects, can form a shorter and more direct electrical connection path within the package. Therefore, it helps reduce inter-chip interconnect resistance and parasitic inductance, improves current transmission consistency in multi-chip package structures, and reduces the risk of voltage overshoot and oscillation caused by interconnect paths under high-frequency switching conditions. Furthermore, traditional copper clips or metal strips typically require pre-forming and precise alignment, and their interconnect paths are significantly limited by chip position, package height, and connector shape. Traditional pre-fabricated metal connectors are insufficiently adaptable to embedded chips, staggered chips, or multi-chip compact layout structures. This application forms a continuous copper interconnect layer, allowing the electroplated copper layer to cover the resin surface, windowed sidewalls, and exposed areas of the chip electrodes 7 or irregularly shaped metal conductive element 2, thereby achieving three-dimensional interconnection between the embedded chip 3 and the surface chip 6. This method improves the flexibility of interconnect path design within multi-chip packages.

[0040] Furthermore, after the chip is encapsulated by the encapsulation material, the lead-out of the chip electrode 7 typically requires windowing, metallization, or redistribution processes. Existing conventional redistribution layers have certain limitations in terms of current carrying capacity and co-connection with the internal thick copper structure. This application forms a continuous conductive path with the chip electrode 7, the irregularly shaped metal conductive component 2, and the surface chip 6 through electroplated copper (first electroplated copper and second electroplated copper). This structure facilitates large-area metal connection of the embedded chip 3 electrode, improving the reliability and current carrying capacity of the electrode lead-out.

[0041] In this application, the irregularly shaped metal conductive element 2 not only serves as a chip carrier or connection structure but also simultaneously undertakes current transmission and heat dissipation functions. The electroplated copper layer is used to achieve surface wiring and three-dimensional connections between chips. Therefore, compared to single bonding wires, single copper clips, or ordinary redistribution structures, this application can simultaneously achieve low-resistance interconnection, heat dissipation, and metal / resin interface enhancement within the same package structure, which is beneficial for improving the overall reliability of multi-chip co-package structures. Furthermore, by embedding some chips into the package and utilizing electroplated copper and the irregularly shaped metal conductive element 2 to achieve short-path connections between multiple chips, this application can reduce the space required for traditional wire bonding, copper clips, or external connectors. Therefore, this structure is beneficial for improving the utilization rate of internal package space and is suitable for compact packaging designs in multi-chip parallel, series, bridge arm structures, or power modules.

[0042] In some embodiments, the encapsulation structure 8 is an epoxy resin material.

[0043] In this embodiment, the multi-core encapsulation structure undergoes two encapsulation processes. The first encapsulation involves encapsulating the irregularly shaped metal conductive component 2 and the embedded chip 3, with epoxy resin as the encapsulation material. The second encapsulation involves encapsulating the interconnection areas of the electroplated copper, the surface chip 6, and the chip electrode 7, with epoxy resin, epoxy film plastic, or other insulating encapsulation materials suitable for semiconductor packaging as the encapsulation material.

[0044] In some embodiments, the irregularly shaped metal conductive component 2 is an irregularly shaped copper component.

[0045] In this embodiment, the irregularly shaped metal conductive component 2 is made of a material with conductive function, for example, copper material is used in this embodiment.

[0046] In some embodiments, the irregular structure 21 includes a stepped structure, a notched structure, a grooved structure, a protruding structure, or a non-straight sidewall structure.

[0047] In this embodiment, the irregular structure 21 is generally located on the side of the irregularly shaped metal conductive component 2, for example, the front, rear, left, or right side. The irregular structure 21 can be, but is not limited to, one or more of a stepped structure, a groove structure, a notch structure, a protrusion structure, or a non-planar straight wall structure, such as a combination of a stepped structure and a notch structure. When encapsulating the embedded chip 3 and the irregularly shaped metal conductive component 2 with epoxy resin, the epoxy resin fills the area around the irregularly shaped metal conductive component 2 and enters the stepped structure, notch structure, and other areas, forming a mechanically locking interface after the epoxy resin cures.

[0048] In some embodiments, at least one of the second electroplated copper 5 is provided.

[0049] In this embodiment, the second electroplated copper 5 is formed on the irregularly shaped metal conductive component 2. The second electroplated copper 5 is used to support the surface chip 6, realizing the connection between the surface chip 6 and the irregularly shaped metal conductive component 2, thereby realizing the connection between the embedded chip 3 and the surface chip 6. Multiple second electroplated copper 5s can be provided, and their number is determined according to the number of surface chips 6 to be packaged.

[0050] In some embodiments, the chip electrode 7 has a Z-shaped structure; the chip electrode 7 is a copper electrode.

[0051] In this embodiment, the chip electrode 7 is a copper electrode. The copper electrode can be formed on the surface chip 6 by electroplating, sputtering, evaporation, welding, or bonding. In another implementation, the copper electrode can be pre-prepared and connected to the surface chip 6 via mounting. The function of the chip electrode 7 is to enable external lead-out of the chip electrode 7 of the surface chip 6, further facilitating the connection between the surface chip 6 and external terminals, metal connectors, heat dissipation structures, or subsequent packaging structures.

[0052] In this embodiment, the chip electrode 7 is Z-shaped, which increases the contact area between the chip electrode 7 and the encapsulation material during encapsulation, thereby increasing the encapsulation stability of the chip electrode 7.

[0053] In some embodiments, the surface chip 6 is fixed to the first electroplated copper 4 and the second electroplated copper 5 by a conductive connecting material; the embedded chip 3 is fixed to the irregularly shaped metal conductive component 2 by a conductive connecting material.

[0054] In this embodiment, the surface chip 6 is connected to the first electroplated copper 4 and the second electroplated copper 5 using a conductive material. This conductive material can be, but is not limited to, solder, sintered silver, sintered copper, or conductive adhesive. Similarly, the embedded chip 3 is connected to the irregularly shaped metal conductive component 2 using a conductive material. This conductive material can be, but is not limited to, solder, sintered silver, sintered copper, or conductive adhesive.

[0055] In some embodiments, such as Figure 2 As shown, this application also provides a method for fabricating a multi-core encapsulation structure as described above, which includes the following steps: S1. Provide a substrate; Specifically, please combine Figure 3 As shown in Figure a, the substrate serves as a carrier structure for fabricating subsequent irregularly shaped metal conductive components, embedded chips, surface-mount chips, and encapsulation structures. The irregularly shaped metal conductive components can be irregularly shaped copper parts, and the encapsulation structure can be made of epoxy resin material.

[0056] S2. An irregularly shaped metal conductive component is disposed on the substrate; wherein, the side of the irregularly shaped metal conductive component is provided with an irregular structure; Specifically, please combine Figure 3 As shown in b, irregularly shaped metal conductive parts with irregular structures such as steps, grooves, notches, protrusions, and non-straight sidewall structures are placed on the substrate.

[0057] S3. The embedded chip is fixed onto the irregularly shaped metal conductive component using a conductive connecting material; Specifically, please combine Figure 3 As shown in c, an embedded chip is disposed in a local area or adjacent area of ​​the irregularly shaped conductive metal component and fixed using a conductive connecting material, so that the embedded chip and the irregularly shaped conductive metal component form a compact electrical and thermal connection structure. The conductive connecting material may be, but is not limited to, solder, sintered silver, sintered copper, or conductive adhesive.

[0058] S4. The embedded chip and the irregular metal conductive component are encapsulated with epoxy resin, so that the epoxy resin fills around the irregular metal conductive component and enters the area of ​​the irregular structure to form a mechanical locking interface. Specifically, please combine Figure 3 As shown in d, epoxy resin is used to encapsulate embedded chips and irregularly shaped metal conductive components. The epoxy resin fills the area around the irregularly shaped metal conductive component and enters its grooves, notches, or stepped areas, forming a mechanically interlocking interface after curing.

[0059] S5. Forming windows or grooves in epoxy resin to expose local areas of the embedded chip and / or the irregularly shaped metal conductive component; Specifically, please combine Figure 3 As shown in 'e', ​​a window or groove structure is formed on the epoxy resin to expose the embedded chip connection area and / or a local area of ​​the irregularly shaped metal conductive part, providing connection positions for subsequent electroplated copper interconnects.

[0060] S6. Electroplated copper is formed on the surface of epoxy resin and in the windowed area, and the electroplated copper is connected to the embedded chip and the irregular metal conductive part to form a continuous copper interconnect path. Specifically, please combine Figure 3 In the f section, electroplated copper (i.e., first electroplated copper and second electroplated copper) is formed on the epoxy resin surface and in the window area, so that the electroplated copper is connected to the embedded chip or irregular metal conductive parts, and a continuous copper interconnect path is formed in the package.

[0061] S7. Set a surface chip in a predetermined area of ​​electroplated copper; Specifically, please combine Figure 3As shown in g, the surface chip can be fixed to the electroplated copper using solder, sintered silver, sintered copper, conductive adhesive, or other conductive connecting materials. Through this step, the embedded chip inside the epoxy resin and the surface chip on the surface of the package can be electrically connected through electroplated copper and irregular copper parts, thereby forming a multi-core encapsulation structure.

[0062] S8. Form or connect chip electrodes on the surface chip; Specifically, please combine Figure 3 As shown in h, the chip electrode can be a copper electrode. Copper electrodes can be used for external lead-out of the chip's electrodes, or for connection to external terminals, metal connectors, heat dissipation structures, or subsequent packaging structures. Copper electrodes can be formed by electroplating, sputtering, evaporation, soldering, bonding, or through pre-fabrication and mounting methods.

[0063] S9. Perform secondary encapsulation on the surface chip, the chip electrode, and the electroplated copper interconnect area.

[0064] Specifically, please combine Figure 3 As shown in 'i', when performing secondary encapsulation on the surface chip, the chip electrodes, and the electroplated copper interconnect area, the secondary encapsulation material can be epoxy resin, epoxy molding compound, or other insulating encapsulation materials suitable for semiconductor packaging. After secondary encapsulation, the chip, electroplated copper, and irregular copper parts are fixed and protected by the encapsulation material, and the copper electrodes can be partially exposed or connected to external terminals as needed.

[0065] In the above technical solution, a substrate is first provided as the packaging carrier structure; then, an irregular copper component is placed on the substrate, and a chip is placed in a local area or adjacent area of ​​the irregular copper component; subsequently, epoxy resin is used to encapsulate the chip and the irregular copper component, so that the epoxy resin fills the area around the irregular copper component and forms a mechanical interlocking structure with it; then, windows or grooves are formed on the epoxy resin to expose the chip connection area and / or a local area of ​​the irregular copper component; then, electroplated copper is formed on the epoxy resin surface and the window area, so that the electroplated copper is connected to the chip or the irregular copper component, and a continuous copper interconnect path is formed in the package; then, other chips are placed in the predetermined area of ​​the electroplated copper, and electrode copper is formed or connected; finally, the surface chip, electrode copper and electroplated copper interconnect area are encapsulated a second time to obtain the final multi-core encapsulated structure.

[0066] Through the above technical solution, the irregular copper component not only serves as a conductive and thermally conductive structure within the package, but also leverages its irregular shape to form a mechanical interlocking interface with epoxy resin, improving the reliability of the metal / resin interface bonding. Electroplated copper is used to form continuous interconnect paths between the embedded chip, the irregular copper component, and the surface-mount chip, thereby achieving short-path, low-impedance copper interconnects between multiple chips. This solution is suitable for power semiconductor devices, multi-chip power modules, bridge arm structures, parallel chip structures, or other packaging structures requiring high integration and high-reliability interconnects.

[0067] In summary, the multi-core encapsulation structure and its preparation method provided in this application have the following beneficial effects: This application utilizes irregularly shaped metal conductive components not only as conductive and thermally conductive structures within the package, but also to form a mechanical interlocking interface with epoxy resin, thereby improving the reliability of the metal / resin interface bonding. Electroplated copper is used to form continuous interconnect paths between embedded chips, irregularly shaped metal conductive components, and surface-mount chips, thus achieving short-path, low-impedance copper interconnects between multiple chips. This application is applicable to power semiconductor devices, multi-chip power modules, bridge arm structures, parallel chip structures, or other packaging structures requiring high integration and high-reliability interconnects.

[0068] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A multi-core encapsulation structure, characterized in that, include: substrate; An irregularly shaped metal conductive component is disposed on the substrate; The side of the irregularly shaped metal conductive component has an irregular structure; An embedded chip is disposed on the irregularly shaped metal conductive component; A first electroplated copper and a second electroplated copper, wherein the first electroplated copper is connected to the embedded chip and the second electroplated copper is connected to the irregularly shaped metal conductive component; Surface chips are respectively disposed on the first electroplated copper and the second electroplated copper; Chip electrodes are disposed on the surface chip; An encapsulation structure is located on the substrate and covers the irregularly shaped metal conductive component, the embedded chip, the surface chip, the first electroplated copper, the second electroplated copper, and the chip electrode; wherein the chip electrode portion is exposed outside the encapsulation structure; The encapsulation structure is partially embedded in the irregular structure of the irregularly shaped metal conductive component and forms a mechanical locking interface.

2. The multi-core encapsulation structure according to claim 1, characterized in that, The irregular structure includes stepped structure, groove structure, notched structure, protruding structure or non-straight sidewall structure.

3. The multi-core encapsulation structure according to claim 1, characterized in that, At least one second electroplated copper is provided.

4. The multi-core encapsulation structure according to claim 1, characterized in that, The encapsulation structure is made of epoxy resin material.

5. The multi-core encapsulation structure according to claim 1, characterized in that, The chip electrode has a Z-shaped structure; the chip electrode is a copper electrode.

6. The multi-core encapsulation structure according to claim 1, characterized in that, The surface chip is fixed to the first electroplated copper and the second electroplated copper by conductive connecting material; the embedded chip is fixed to the irregular metal conductive component by conductive connecting material.

7. The multi-core encapsulation structure according to claim 1, characterized in that, The irregularly shaped metal conductive component is an irregularly shaped copper component.

8. A method for preparing a multi-core encapsulation structure based on any one of claims 1-7, characterized in that, Including the following steps: Provide a substrate; An irregularly shaped metal conductive component is disposed on the substrate; wherein, the side of the irregularly shaped metal conductive component has an irregular structure. The embedded chip is fixed onto the irregularly shaped metal conductive component using a conductive connecting material; The embedded chip and the irregularly shaped metal conductive component are encapsulated with epoxy resin, so that the epoxy resin fills around the irregularly shaped metal conductive component and enters the region of the irregular structure to form a mechanical locking interface. Windows or grooves are formed in the epoxy resin to expose local areas of the embedded chip and / or the irregularly shaped metal conductive component; Electroplated copper is formed on the surface of epoxy resin and in the windowed area, and the electroplated copper is connected to the embedded chip and the irregular metal conductive component to form a continuous copper interconnect path. A surface chip is set in a predetermined area of ​​electroplated copper; Chip electrodes are formed or connected on the surface chip; The surface chip, the chip electrodes, and the electroplated copper interconnect area are encapsulated a second time.

9. The preparation method according to claim 8, characterized in that, The chip electrode is a copper electrode; the chip electrode is formed by electroplating, sputtering, vapor deposition, welding, bonding or pre-mounting.

10. The preparation method according to claim 8, characterized in that, When performing secondary encapsulation on the surface chip, the chip electrode, and the electroplated copper interconnect area, the encapsulation material includes epoxy resin and epoxy film plastic.

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