Rdl re-routed electroplated metal layer

Abstract

This invention discloses an electroplated metal layer for RDL redistribution, belonging to the field of semiconductor packaging. It includes an RDL layer comprising a top layer, an intermediate layer, and a bottom layer. A substrate is disposed below the RDL layer, and metal bumps are disposed above the RDL layer, positioned above the chip. A solder layer is disposed above the metal bumps, and the metal bumps are connected to the RDL layer via the solder layer. This invention employs a copper-nickel-copper structure in the redistribution layer solder layer, achieving atomic-level diffusion barrier and controllable interface reaction with a 3-5 micrometer thick nickel layer. This ensures solder strength while suppressing copper diffusion and preventing plating stress cracking, effectively improving the reliability and lifespan of high-reliability products and SiP products.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically referring to an RDL redistribution electroplated metal layer. Background Technology

[0002] In existing fan-out packaging processes, multiple reflow soldering is a necessary step to achieve chip interconnection and package formation. However, this process is prone to a series of technical challenges. Under multiple reflow soldering conditions, an excessively thick intermetallic compound (IMC) layer is formed at the solder-metal interface. As the IMC layer thickness increases, the copper layer of the redistribution layer (RDL) undergoes a significant displacement reaction, leading to noticeable deformation of the copper layer. This, in turn, causes abnormal bonding between the edge dielectric layer and the RDL copper layer, such as PI layer lifting and delamination. These structural defects not only compromise the integrity of the RDL layer and the stability of electrical connections but also significantly reduce the long-term reliability of the packaged product. Especially for products with high reliability requirements and system-in-package (SiP) products, these problems severely restrict product lifespan and application scenarios, becoming a key pain point hindering the further development of fan-out packaging technology. Summary of the Invention

[0003] In view of the above situation and to overcome the defects of the prior art, the present invention provides an RDL redistribution electroplated metal layer, which effectively solves the problems of excessively thick IMC layer, large-scale replacement of RDL copper layer and obvious deformation faced by Fan-out DSM / SIP and other packaging structures in the market during multiple reflow processes.

[0004] The technical solution adopted by the present invention is as follows: The present invention proposes an RDL redistribution electroplated metal layer, including an RDL layer, the RDL layer including a top layer, an intermediate layer and a bottom layer, a base material is disposed below the RDL layer, a metal bump is disposed above the RDL layer, the metal bump is disposed above the chip, a solder layer is disposed above the metal bump, and the metal bump is connected to the RDL layer through the solder layer.

[0005] Preferably, the intermediate layer is a nickel layer.

[0006] Preferably, the thickness of the intermediate layer is in the range of 2-6 micrometers.

[0007] Preferably, the thickness of the intermediate layer is in the range of 3-5 micrometers.

[0008] Preferably, the top and bottom layers are copper layers.

[0009] Preferably, a dielectric layer is disposed around the RDL layer.

[0010] Preferably, the dielectric layer below the RDL layer is the base material.

[0011] Preferably, the dielectric layer comprises a polyimide layer, an Ajinomoto multilayer film, a polypropylene layer, a benzocyclobutene layer, and a polybenzoxazole layer.

[0012] Preferably, the metal bumps form a conductive connection structure with the help of a solder layer, and the metal bumps are connected to the RDL layer through the solder layer to bring out signals inside the chip.

[0013] Preferably, an intermediate layer is provided below the top layer, a bottom layer is provided below the intermediate layer, and a bottom layer material is provided below the bottom layer.

[0014] The beneficial effects of the present invention using the above structure are as follows: This solution proposes an RDL redistribution electroplated metal layer, including a top layer, an intermediate layer, and a bottom layer, wherein the intermediate layer can be a nickel layer as a barrier layer, and the top and bottom layers can be copper layers. This method sets a nickel solder resist layer of a certain thickness between the top and bottom layers of the redistribution layer, and utilizes the characteristics of dense atomic packing, high melting point, chemical stability, and strong corrosion resistance of the nickel layer to achieve atomic-level diffusion barrier and controllable interface reaction, effectively suppressing solder diffusion and copper layer replacement, avoiding problems such as excessively thick IMC, copper layer deformation of the redistribution layer, and abnormal edge PI bonding during multiple reflow soldering. While ensuring soldering strength, it significantly improves the reliability and service life of packaged products, including fan-out double-sided packages or system-in-package (FO DSM / SIP), while avoiding defects such as copper diffusion caused by excessively thin nickel layers and large plating stress and easy cracking caused by excessively thick nickel layers, taking into account both structural stability and process adaptability. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of an electroplated metal layer for RDL redistribution proposed in this invention;

[0016] Figure 2 This is a schematic diagram of an RDL layer with an electroplated metal layer for RDL redistribution proposed in this invention.

[0017] Figure 3 This is a schematic diagram of the substrate of the RDL redistribution electroplated metal layer proposed in this invention.

[0018] Among them, 1. Chip; 2. Metal bump; 3. Solder layer; 4. RDL layer; 41. Top layer; 42. Middle layer; 43. Bottom layer; 5. Base material.

[0019] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0022] like Figures 1-3 As shown, this invention proposes an electroplated metal layer for RDL redistribution, such as... Figure 1 As shown, the structure includes an RDL layer 4, which may comprise a top layer 41, an intermediate layer 42, and a bottom layer 43. This three-layer structure can be manufactured using electroplating to replace the traditional single-layer electroplated copper RDL structure. By adding a solder resist barrier layer between the copper layers in the RDL layer 4, the copper layer loss problem under multiple reflow processes is solved. The top layer 41, intermediate layer 42, and bottom layer 43 are arranged sequentially from top to bottom. The intermediate layer 42 is located below the top layer 41, the bottom layer 43 is located below the intermediate layer 42, and a base material 5 is bonded to the bottom layer 43. The three layers are stacked in a fixed order to avoid diffusion protection failure caused by reversing the layer order.

[0023] Dielectric layers are provided around RDL layer 4. The dielectric layers can be polyimide (PI) layer, Ajinomoto laminate (ABF) layer, polypropylene (PP) layer, benzocyclobutene (BCB) layer, polybenzoxazole (PBO) layer, and the dielectric layer below RDL layer 4 is the base material 5.

[0024] The dielectric layer can be placed below the RDL layer 4 as the core dielectric material. It can provide interlayer insulation for different levels of RDL layer 4 lines, and can also play a stress buffering role, improve the bonding state between the dielectric layer and the RDL layer 4 at the edge position during the manufacturing process, and avoid bonding defects.

[0025] like Figure 2As shown, it should be noted that the top layer 41 and the bottom layer 43 can be electroplated copper layers. Copper material has low resistivity, good conductivity, and ductility. The interface bonding strength between the bottom copper layer 43 and the underlying material 5 is high, which can ensure the adhesion stability of the RDL layer 4 circuitry and the dielectric layer. The top copper layer 41 can form an electrical connection with the metal bump 2 through the solder layer 3, providing a low-loss conduction path for chip signals. The solder layer 3 can be tin solder or tin alloy solder, but is not limited to these, or can be other solders that can achieve soldering functions. In traditional single-layer copper RDL structures, the RDL copper layer is easily eroded by solder during multiple reflow processes. However, this structure, through the design of two copper layers and an intermediate barrier layer, improves the overall protection capability of the RDL layer 4 while ensuring conductivity.

[0026] It should be noted that the intermediate layer 42 is an electroplated nickel barrier layer sandwiched between the top and bottom copper layers. It is the core solder mask layer of this structure, specifically addressing the reliability defects exposed in existing fan-out double-sided packages or fan-out system-in-packages (FODSM, FO SIP) during multiple reflow soldering processes. In conventional packaging processes, an intermetallic compound (IMC) forms at the interface between the solder and the RDL copper layer. After multiple reflows, the IMC layer overgrows and its thickness increases significantly. The RDL copper layer is largely replaced and consumed by the solder, resulting in significant structural deformation. This leads to abnormal bonding between the edge dielectric layer and the RDL layer 4, causing warping and ultimately reducing solder strength and overall product reliability.

[0027] In this structure, the nickel layer essentially serves as an atomic-level diffusion barrier and a controllable interface reaction: nickel itself has dense atomic packing, a high melting point, strong chemical stability and corrosion resistance, and can form a stable interface bond when in contact with solders such as tin. This ensures the mechanical welding strength of the solder joints without causing excessive reaction with the solder, effectively inhibiting the diffusion of tin atoms into the copper layer. This reduces the replacement consumption and deformation damage of the copper layer during multiple reflows, controls the thickness of the intermetallic compound layer, and protects the structural integrity of the RDL copper layer. It is the preferred solder resist layer solution in the industry.

[0028] It should be noted that the nickel interlayer 42 has clearly defined two-level thickness control ranges. The optimal thickness for conventional mass production is controlled between 3 and 5 micrometers, while a general safe processing range of 2 to 6 micrometers is defined. When the nickel layer thickness is less than 2 micrometers, the nickel layer cannot form a complete and dense barrier, resulting in diffusion barrier failure. Copper atoms can still undergo displacement reactions with the solder, failing to protect the copper layer. When the nickel layer thickness exceeds 6 micrometers, significant internal stress accumulates within the plating, making the plating itself prone to microcracks. Simultaneously, the interfacial bonding between the nickel and copper layers decreases, leading to delamination defects and affecting the structural stability of the RDL circuit.

[0029] It should be noted that a metal bump 2 is disposed above the RDL layer 4, and a solder layer 3 is disposed above the metal bump 2. The metal bump 2 is disposed above the chip 1, and the solder layer 3 is disposed above the metal bump 2. The metal bump 2 and the RDL layer 4 are stably connected through the solder layer 3. The metal bump 2 is used to lead out the electrical signals inside the chip 1, and form a conductive connection with the RDL layer 4 through the solder layer 3, thus forming a complete signal transmission path and realizing the stable transmission of signals from inside the chip 1 to the external rewiring lines.

[0030] It should be noted that the present invention provides an RDL redistribution electroplated metal layer, which is mainly suitable for packaged products that require multiple reflow processes, covering package types such as 2.5D / 3DIC, PIP / PoP, FODSM, and FOSIP, and can effectively improve the soldering reliability and long service life of the product.

[0031] It should be noted that this three-layer metal structure is not suitable for radio frequency, high frequency and high speed packaging scenarios. This is because nickel has a higher resistivity than copper and is a magnetic metal. In high frequency operating environments, nickel will cause the line impedance to increase and the return loss to deteriorate, which will negatively affect the transmission performance of high frequency signals.

[0032] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0033] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0034] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. An electroplated metal layer for RDL redistribution, characterized in that: include: RDL layer (4), the RDL layer (4) includes a top layer (41), an intermediate layer (42) and a bottom layer (43), a base material (5) is disposed below the RDL layer (4), a metal bump (2) is disposed above the RDL layer (4), the metal bump (2) is disposed above the chip (1), a solder layer (3) is disposed above the metal bump (2), and the metal bump (2) is connected to the RDL layer (4) through the solder layer (3).

2. The RDL redistribution electroplated metal layer according to claim 1, characterized in that: The intermediate layer (42) is a nickel layer.

3. The RDL redistribution electroplated metal layer according to claim 2, characterized in that: The thickness of the intermediate layer (42) ranges from 2 to 6 micrometers.

4. The RDL redistribution electroplated metal layer according to claim 3, characterized in that: The thickness of the intermediate layer (42) ranges from 3 to 5 micrometers.

5. The RDL redistribution electroplated metal layer according to claim 1, characterized in that: The top layer (41) and the bottom layer (43) are copper layers.

6. The RDL redistribution electroplated metal layer according to claim 1, characterized in that: A dielectric layer is provided around the RDL layer (4).

7. The RDL redistribution electroplated metal layer according to claim 6, characterized in that: The dielectric layer below the RDL layer (4) is the base material (5).

8. The RDL redistribution electroplated metal layer according to claim 6, characterized in that: The dielectric layer includes a polyimide layer, an Ajinomoto multilayer film, a polypropylene layer, a benzocyclobutene layer, and a polybenzoxazole layer.

9. The RDL redistribution electroplated metal layer according to claim 1, characterized in that: The metal bump (2) forms a conductive connection structure with the help of the solder layer (3). The metal bump (2) is connected to the RDL layer (4) through the solder layer (3) to bring out the internal signals of the chip (1).

10. The RDL redistribution electroplated metal layer according to claim 5, characterized in that: A middle layer (42) is provided below the top layer (41), a bottom layer (43) is provided below the middle layer (42), and a bottom layer material (5) is provided below the bottom layer (43).

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