Semiconductor device, semiconductor device design method, and electronic device

Abstract

A semiconductor device, a semiconductor device design method, an electronic packaging device, and an electronic device are disclosed. The semiconductor device includes: a package containing at least one chip; and a circuit board connected to the package via a solder ball array. The solder ball array includes multiple regions, including a first region and a second region. At least one warpage compensation characteristic of the first region differs from that of the second region. The warpage compensation characteristic represents the ability of the solder ball array to suppress deformation after the package and circuit board are connected. Embodiments of this disclosure can compensate for warpage mismatch between the package and the circuit board, improve the uniformity of solder contact, and enhance the reliability of package interconnects.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and more particularly to a semiconductor device, a semiconductor device design method, an electronic packaging device, and an electronic device. Background Technology

[0002] The packaging substrate and the circuit board are connected by a solder ball array. Due to differences in material systems, coefficient of thermal expansion (CTE), thickness, and copper distribution between the packaging substrate and the circuit board, warping deformations of different directions or degrees may occur during the soldering process and temperature changes during operation. This results in variations in the gap between the two in different areas, placing higher demands on the reliability of package interconnects under these conditions within the industry. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device, a semiconductor device design method, an electronic packaging device, and an electronic device to improve the reliability of package interconnects.

[0004] In a first aspect, a semiconductor device is provided, comprising: A package, the package comprising at least one chip; The circuit board is connected to the package via an array of solder balls. The solder ball array includes multiple regions, including a first region and a second region. At least one warpage compensation characteristic of the first region is different from that of the second region. The warpage compensation characteristic represents the ability of the solder ball array to suppress deformation after the package and the circuit board are connected.

[0005] In one possible implementation, the warp compensation characteristics include at least one of the following: solder ball density, solder ball spacing, solder ball size, solder ball support height, solder ball material, solder joint structure, and solder joint equivalent stiffness.

[0006] In one possible implementation, the solder ball density in the first region is different from that in the second region.

[0007] In one possible implementation, the center-to-center distance of the solder balls in the first region is different from that in the second region.

[0008] In one possible implementation, the solder ball size in the first region is different from the solder ball size in the second region.

[0009] In one possible implementation, the solder balls in the first region and the solder balls in the second region have different solder joint connection structures.

[0010] In one possible implementation, the pad opening size in the first region is different from the pad opening size in the second region.

[0011] In one possible implementation, a first region is located in the central region between the package and the circuit board, and a second region is located in the edge region between the package and the circuit board; the package and the circuit board have the same warp direction in the second region, and the gap between the package and the circuit board in the first region is smaller than the gap between the second regions; the warp compensation characteristics of the solder ball array in the first region are lower than the warp compensation characteristics of the solder ball array in the second region.

[0012] In one possible implementation, a first region is located in the central region between the package and the circuit board, and a second region is located in the edge region between the package and the circuit board; the package and the circuit board have opposite warp directions in the second region, and the gap between the package and the circuit board in the first region is greater than the gap between the second regions; the warp compensation characteristics of the solder ball array in the first region are higher than the warp compensation characteristics of the solder ball array in the second region.

[0013] In one possible implementation, the edge region of the connection area between the package and the circuit board includes a first diagonal region and a second diagonal region, the first diagonal region being warped along a first direction and the second diagonal region being warped along a second direction opposite to the first direction; the first region is located in the first diagonal region and the second region is located in the second diagonal region; the warp compensation characteristics of the solder ball array in the first region are higher than those of the solder ball array in the second region.

[0014] In one possible implementation, the multiple regions further include a third region located between the first and second regions, wherein the warpage compensation characteristics of the solder ball array in the third region are between those of the solder ball array in the first region and the solder ball array in the second region.

[0015] In one possible implementation, solder balls in multiple regions form an interconnect layer with regional warp compensation characteristics.

[0016] In one possible implementation, the package includes a chip and a package substrate, the package substrate having a first surface and a second surface opposite to each other; a solder ball array is disposed between the second surface and a circuit board; the circuit board is connected to the package substrate via the solder ball array.

[0017] In one possible implementation, the package includes a chip having a third surface and a fourth surface opposite to each other; an array of solder balls is disposed between the fourth surface and a circuit board; the circuit board is connected to the chip via the array of solder balls.

[0018] Secondly, a semiconductor device design method is provided, comprising: acquiring warpage deformation information of a package and a circuit board during the soldering process and / or operation, and determining warpage mismatch parameters for different regions between the package and the circuit board; dividing the area on the package where a solder ball array is configured according to the warpage mismatch parameters of different regions, and determining multiple regions, including a first region and a second region; determining corresponding warpage compensation characteristic parameters for the multiple regions, the warpage compensation characteristic parameters including at least one of solder ball spacing, solder ball density, solder ball size, solder ball support height, solder joint material, solder joint structure, and solder joint equivalent stiffness, wherein at least one warpage compensation characteristic of the first region is different from that of the second region; and forming a regionalized solder ball array according to the warpage compensation characteristic parameters corresponding to the multiple regions to compensate for the warpage mismatch between the package and the circuit board.

[0019] In one possible implementation, warp compensation characteristic parameters are determined for multiple regions, including: determining warp compensation characteristic parameters based on the local gaps and / or the degree of local warp mismatch in multiple regions, wherein the solder ball density in regions with larger local gaps is higher than that in regions with smaller local gaps, and the solder ball spacing in regions with stronger local constraints is greater than that in regions with weaker local constraints.

[0020] In one possible implementation, corresponding warp compensation characteristic parameters are determined for multiple regions, including: determining different solder joint structures and / or different solder volumes for multiple regions, so that the solder ball array forms regionalized warp compensation characteristics.

[0021] In one possible implementation, the packaging structure design method further includes: acquiring warpage deformation information of the package and circuit board after forming a regionalized solder ball array, and updating the warpage compensation characteristic parameters corresponding to multiple regions based on the warpage deformation information.

[0022] Thirdly, an electronic packaging device is provided, comprising a semiconductor device of the first aspect or any possible implementation thereof.

[0023] Fourthly, an electronic device is provided, including the electronic packaging device of the third aspect.

[0024] The semiconductor device provided in this disclosure divides a solder ball array disposed between a package and a circuit board into multiple regions. At least one warpage compensation characteristic of the first region is different from that of the second region, so that the solder ball array exhibits different deformation and support capabilities in different regions, which are adapted to the degree of warpage deformation of the package and the circuit board in the corresponding regions. During the soldering process and operation, the warpage mismatch between the package and the circuit board is compensated, the uniformity of the soldering contact is improved, the probability of local stress concentration, solder joint bridging and cold solder joints is reduced, and the reliability of package interconnection is improved. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an electronic device provided in some embodiments of this disclosure; Figure 2 This is a cross-sectional view of a packaging structure in related technologies; Figure 3A This is a cross-sectional view of a semiconductor device provided in some embodiments of this disclosure; Figure 3B This is a cross-sectional view of a semiconductor device provided in some embodiments of this disclosure; Figure 3C This is a cross-sectional view of a semiconductor device provided in some embodiments of this disclosure; Figure 4 This is a top view of a solder ball array provided in some embodiments of this disclosure; Figure 5 This is a partial cross-sectional view of a solder ball array provided in some embodiments of this disclosure; Figure 6 This is a cross-sectional view of yet another semiconductor device provided in some embodiments of this disclosure; Figure 7 This is a cross-sectional view of yet another semiconductor device provided in some embodiments of this disclosure; Figure 8 This is a top view of yet another solder ball array provided in some embodiments of this disclosure; Figure 9 This is a cross-sectional view of a solder joint connection structure provided in some embodiments of this disclosure; Figure 10 This is a schematic flowchart of a semiconductor device design method provided in some embodiments of this disclosure; Figure 11 This is a schematic diagram of the structure of an electronic device provided in some embodiments of this disclosure. Detailed Implementation

[0026] The specific embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0027] To keep the drawings simple, the following figures only schematically show the parts relevant to the corresponding descriptions, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, some figures only schematically show partial structures or components; in reality, there may be more or fewer identical or similar structures or components.

[0028] Unless otherwise explicitly stated and defined: "Connection" includes direct or indirect connection between objects: connected objects can be directly connected through a medium (e.g., wires, wiring, etc.), or indirectly connected through other components, or can be an internal connection. "Coupling" includes signal connection between objects, which can be achieved directly through a medium (e.g., wires, wiring, etc.), or through other components, etc.

[0029] Unless otherwise explicitly stated and limited: ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe relationships between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, " / " is used to indicate an "or" relationship between preceding and following objects. "One or more of A and B" or "at least one of A and B" has the same meaning as "A and / or B" or "A or B" above; more objects are similarly represented.

[0030] Figure 1 This is a schematic diagram of a semiconductor device provided in some embodiments of this disclosure. The semiconductor device includes a packaging substrate 100 and a chip 200 disposed on the packaging substrate 100. The packaging substrate 100 is mounted on a circuit board 400 via a solder ball array 300, thereby forming an electrical connection with other devices on the circuit board 400. During the assembly process of the semiconductor device, the packaging substrate 100 with the chip 200 and the circuit board 400 are connected by a reflow soldering process. The solder balls in the solder ball array 300 melt at high temperature and form solder joints between the pads of the packaging substrate 100 and the pads of the circuit board 400. During the operation of the semiconductor device, the power consumption of the chip 200 causes the packaging substrate 100 and the circuit board 400 to undergo repeated temperature changes. As the integration density of the chip 200 and the planar size of the packaging substrate 100 increase, the connection reliability between the packaging substrate 100 and the circuit board 400 has a greater impact on the overall reliability of the electronic device 500.

[0031] For example, Figure 2This is a cross-sectional view of a packaging structure in related technologies. A chip 200' is disposed on one side of a packaging substrate 100', and the other side is connected to a circuit board 400' via a solder ball array 300'. The package substrate 100' and the circuit board 400' have different CTEs (Chip-to-Earth Transformation). Under the high-temperature conditions of the soldering process, both undergo different degrees of warping deformation, resulting in varying gaps between the package substrate 100' and the circuit board 400' in different areas. The solder balls in the solder ball array 300' have the same solder ball density, solder ball spacing, and solder ball size in all areas. Therefore, in areas with smaller gaps, the solder balls undergo greater lateral deformation under the pressure of both, posing a risk of bridging between adjacent solder balls. In areas with larger gaps, the wetting between the solder balls and the pads is insufficient, posing a risk of poor contact or cold solder joints. The solder joints in these areas will also experience significant thermomechanical stress during subsequent temperature cycling.

[0032] In some embodiments, the solder ball array disposed between the package substrate and the circuit board is regionalized, so that the solder ball array has different warp compensation characteristics in different regions, thereby compensating for warp mismatch between the package substrate and the circuit board and improving the reliability of package interconnection. Warp compensation characteristics represent the ability of the solder ball array to suppress deformation after the package and circuit board are connected. Warp compensation characteristics may include at least one of: solder ball density, solder ball spacing, solder ball size, solder ball support height, solder ball material, solder joint structure, and solder joint equivalent stiffness.

[0033] Figure 3A This is a cross-sectional view of a semiconductor device provided in some embodiments of the present disclosure. The semiconductor device includes a package 10, a solder ball array 300, and a circuit board 400. The package 10 includes at least one chip 200. The solder ball array 300 includes multiple regions, including a first region 310 and a second region 320. At least one warpage compensation characteristic of the first region 310 is different from that of the second region 320. The warpage compensation characteristic represents the ability of the solder ball array to suppress deformation after the package and the circuit board are connected.

[0034] By using a regionalized design of the solder ball array positioned between the package and the circuit board, the solder ball array can have different warp compensation characteristics in different regions, thereby compensating for the warp mismatch between the package and the circuit board and improving the reliability of the package interconnect.

[0035] Figure 3BThis is a schematic diagram of one embodiment of the semiconductor package provided in this application. In this embodiment, the package 10 may further include a package substrate 100 and at least one chip 200. The package substrate 100 has a first surface 101 and a second surface 102 opposite to the first surface 101. The chip 200 is disposed on the first surface 101 of the package substrate 100. This disclosure does not limit the number, type, or arrangement of chips. For example, the chip 200 may include one or more of logic chips, memory chips, and chiplets. This disclosure also does not limit the implementation of the package substrate 100. For example, the package substrate 100 may include a substrate, or it may include a substrate and an interposer disposed on the substrate.

[0036] The solder ball array 300 can be disposed on the second surface 102 of the packaging substrate 100. The circuit board 400 is connected to the second surface 102 of the packaging substrate 100 through the solder ball array 300, that is, one end of the solder ball in the solder ball array 300 is connected to the pad on the second surface 102, and the other end is connected to the pad on the side surface of the circuit board 400 facing the packaging substrate 100.

[0037] The solder ball array 300 includes multiple regions, including a first region 310 and a second region 320. The first region 310 has at least one warp compensation characteristic different from that of the second region 320. The warp compensation characteristic represents the ability of the solder ball array 300 to suppress deformation after the package substrate 100 and the circuit board 400 are connected. A higher value indicates a stronger ability of the solder ball array in the corresponding region to constrain the relative deformation between the package substrate 100 and the circuit board 400 and maintain the flatness of the connection interface between them during the soldering and operational processes.

[0038] Figure 3C This is a schematic diagram of one embodiment of the semiconductor package provided in this application. In this embodiment, the package 10 includes only a chip 200. The chip 200 has a third surface 201 and a fourth surface 202 opposite to the third surface 201. At least one chip 200 is connected to a circuit board 400 via a solder ball array 300. This disclosure does not limit the number, type, or arrangement of chips. For example, at least one chip 200 may include one or more of logic chips, memory chips, and chiplets.

[0039] The solder ball array 300 can be disposed on the fourth surface 202 of the chip 200. The circuit board 400 is connected to the fourth surface 202 of the chip 200 through the solder ball array 300, that is, one end of the solder ball in the solder ball array 300 is connected to the pad on the fourth surface 202, and the other end is connected to the pad on the side surface of the circuit board 400 facing the chip 200.

[0040] The solder ball array 300 may include multiple regions, including a first region 310 and a second region 320. The first region 310 has at least one warp compensation characteristic different from that of the second region 320. The warp compensation characteristic represents the ability of the solder ball array 300 to suppress deformation after the chip 200 and the circuit board 400 are connected. A higher value indicates a stronger ability of the solder ball array within the corresponding region to constrain the relative deformation between the chip 200 and the circuit board 400 and maintain the flatness of the connection interface between them during the soldering and operational processes.

[0041] Similarly, in another possible implementation, the solder ball array 300 may also be disposed on the side of the circuit board 400 facing the fourth surface 202 of the chip 200, which will not be described in detail here.

[0042] In embodiments of this disclosure, the solder paste printing area, printing volume, and pad opening size can be differentiated based on the local structural parameters of the solder ball array and the local gap between the package substrate and the circuit board. When a larger solder ball is used in a local area, the size of the circuit board side pad and the solder paste printing volume can be increased accordingly to form a solder joint with a larger solder volume and higher support capacity; when a smaller solder ball is used in a local area, the pad size and solder paste printing volume can be reduced accordingly to reduce the local solder joint volume and structural constraints.

[0043] When the solder ball density or solder ball pitch is small in a local area, a corresponding high-density solder paste printing area can be set according to the solder ball array layout. By reducing the amount of solder paste printed between adjacent pads, solder bridging can be prevented and the overall equivalent stiffness of the area can be improved. When the solder ball density or pitch is small in a local area, the spacing between adjacent solder paste printing areas can be increased accordingly to reduce the local equivalent stiffness and provide greater deformation space for the relative thermomechanical displacement between the package and the circuit board.

[0044] Furthermore, for areas with large gaps, one or more combinations of larger solder balls, larger pad openings, larger solder paste printing volume, or higher solder ball density can be used to improve local support and soldering contact; for areas with small gaps or stress concentrations, one or more combinations of smaller solder balls, smaller solder paste printing volume, lower solder ball density, larger pitch, or lower local interconnect stiffness can be used to reduce the equivalent strength of solder balls and release the relative displacement caused by thermomechanical mismatch.

[0045] This disclosure does not limit the specific form of the warp compensation characteristics. In some embodiments, the warp compensation characteristics include at least one of solder ball density, solder ball spacing, solder ball size, solder ball support height, solder ball material, and solder joint equivalent stiffness. Solder ball density refers to the number of solder balls per unit area; solder ball spacing refers to the center-to-center distance between two adjacent solder balls; solder ball size refers to the maximum dimension of the solder ball in the direction parallel to the fourth surface 202; solder ball support height refers to the dimension of the solder ball in the direction perpendicular to the fourth surface 202; solder joint equivalent stiffness refers to the ability of the solder joint to resist deformation under a unit load, which is related to the solder ball material, solder joint structure, and solder volume. Differences in any one or more of the above characteristics between different regions can enable the solder ball array 300 to form regionalized warp compensation characteristics.

[0046] Figure 4 This is a top view of a solder ball array provided in some embodiments of the present disclosure, illustrating one implementation of a package comprising a chip and a package substrate 100. As shown in the figure, the arrangement of the solder ball array 300 is viewed from one side of the second surface 102 of the package substrate 100. In some embodiments, a first region 310 is located in the central region between the package substrate 100 and the circuit board 400, and a second region 320 is located in the edge region between the package substrate 100 and the circuit board 400, the second region 320 being disposed around the first region 310. The solder ball density in the second region 320 is higher than that in the first region 310, and the solder ball spacing in the second region 320 is smaller than that in the first region 310.

[0047] In some embodiments, the solder ball array 300 may further include a third region located between the first region 310 and the second region 320. The warpage compensation characteristics of the solder ball array in the third region are between the warpage compensation characteristics of the solder ball array in the first region 310 and the warpage compensation characteristics of the solder ball array in the second region 320, so that the solder ball array 300 as a whole presents a gradient distribution that gradually changes from the center to the edge, avoiding abrupt changes in the warpage compensation characteristics between adjacent regions and introducing new stress concentrations.

[0048] In some embodiments, passive devices, such as capacitors, can be placed in areas with low solder ball density, and these passive devices are electrically connected to the circuit board 400. In this way, without increasing the planar dimensions of the package substrate 100, the local decoupling capability can be improved by utilizing areas with low solder ball density, thereby improving the power supply integrity and signal integrity of the chip 200.

[0049] Although this embodiment is described using a packaging substrate 100 as an example, it can also be applied to embodiments where the package includes a chip, and will not be elaborated further.

[0050] Figure 5This is a partial cross-sectional view of a solder ball array provided in some embodiments of this disclosure. The package includes a chip and a package substrate 100, as can be seen from the figure. Figure 5 (a) shows the first region 310. Figure 5 (b) shows the second region 320. The first solder ball 311 in the first region 310 has a solder ball spacing of p1, a solder ball support height of h1, and a solder ball size of d1; the second solder ball 321 in the second region 320 has a solder ball spacing of p2, a solder ball support height of h2, and a solder ball size of d2.

[0051] In some embodiments, the solder ball density in the first region 310 is different from that in the second region 320. This difference in solder ball density can be achieved through a difference in solder ball spacing, specifically, the center-to-center distance p1 between the solder balls in the first region 310 and the center-to-center distance p2 between the solder balls in the second region 320. For example, p1 is greater than p2, resulting in a greater number of solder balls distributed per unit area in the second region 320 than in the first region 310. This increases the number of connection interfaces carried per unit area by the solder ball array in the second region 320, providing stronger constraint on the relative deformation between the package substrate 100 and the circuit board 400.

[0052] In some embodiments, the solder ball size d1 in the first region 310 is different from the solder ball size d2 in the second region 320. The difference in solder ball size can be achieved through differences in the pad opening size on the second surface 102 of the packaging substrate 100, or through differences in the solder volume during ball placement. In regions with larger solder ball sizes, the resulting solder joints have a larger solder volume and effective load-bearing cross-sectional area, exhibiting higher local support capacity under similar structural parameters, and can provide a larger solder filling volume in the molten state to accommodate larger local gaps between the packaging substrate and the PCB. In regions with smaller solder ball sizes, by controlling the solder volume, solder joint position, and solder joint height, the solder joints can form a relatively large height-to-diameter ratio or a larger spacing, thereby reducing the equivalent stiffness of the solder joints. During temperature cycling, these solder joints can absorb the relative displacement caused by thermal expansion mismatch between the packaging substrate and the PCB through their own shear deformation, thereby reducing local thermomechanical stress and solder joint fatigue damage.

[0053] In some embodiments, the solder ball support height h1 in the first region 310 is different from the solder ball support height h2 in the second region 320. The difference in solder ball support height can be achieved through differences in solder volume or by introducing support structures such as copper pillars into the solder joint. Regions with larger support heights can bridge larger gaps, thereby maintaining a reliable connection interface in areas with larger gaps between the package substrate 100 and the circuit board 400.

[0054] There are various forms of warpage mismatch between the packaging substrate 100 and the circuit board 400. The region division method of the solder ball array 300 and the warpage compensation characteristics of each region can be determined according to the form of warpage mismatch.

[0055] Although this embodiment is described using a packaging substrate 100 as an example, it can also be applied to embodiments where the package includes a chip, and will not be elaborated further.

[0056] Figure 6 This is a cross-sectional view of another semiconductor device provided in some embodiments of this disclosure. The package includes a chip and a packaging substrate 100, as shown in the figure. It illustrates a situation where the packaging substrate 100 and the circuit board 400 have the same warp direction in the edge regions. Figure 6 (a) shows a case where the edge regions of both objects warp away from each other. Figure 6 (b) shows a case where the central regions of both protrude away from each other. In this case, the first region 310 is located in the central region between the package substrate 100 and the circuit board 400, and the second region 320 is located in the edge region between the package substrate 100 and the circuit board 400. Since the degree of warpage of the package substrate 100 is different from that of the circuit board 400, the gap G2 between the package substrate 100 and the circuit board 400 in the first region 310 is smaller than the gap G1 between the two in the second region 320.

[0057] To address the aforementioned situation, the warpage compensation characteristics of the solder ball array in the first region 310 are lower than those in the second region 320. For example, the solder ball density in the second region 320 can be increased while the solder ball spacing can be decreased, while the solder ball density in the first region 310 can be decreased while the solder ball spacing can be increased. Thus, the second region 320 with a larger gap G1 obtains more connection interfaces and stronger support capabilities, improving the wetting state between the solder balls and pads in this region and reducing the probability of poor contact or cold solder joints in edge and corner areas. The solder balls in the first region 310 with a smaller gap G2 have more space for arrangement, making it less likely for lateral deformation of the solder balls under compression to cause bridging between adjacent solder balls. Simultaneously, the structural rigidity constraint in this region is reduced, allowing local thermomechanical stress to be released.

[0058] Although this embodiment is described using a packaging substrate 100 as an example, it can also be applied to embodiments where the package includes a chip, and will not be elaborated further.

[0059] Figure 7This is a cross-sectional view of another semiconductor device provided in some embodiments of the present disclosure. The package includes a chip and a package substrate 100. As shown in the figure, the package substrate 100 and the circuit board 400 have opposite warping directions in their edge regions. In this case, a first region 310 is located in the central region between the package substrate 100 and the circuit board 400, and a second region 320 is located in the edge region between the package substrate 100 and the circuit board 400. The central region of the package substrate 100 bulges away from the circuit board 400, while the edge region of the circuit board 400 warps away from the package substrate 100, such that the gap G1 between the package substrate 100 and the circuit board 400 in the first region 310 is greater than the gap G2 between them in the second region 320.

[0060] To address the aforementioned situation, the warpage compensation characteristics of the solder ball array in the first region 310 are higher than those in the second region 320. For example, the solder ball density in the first region 310 can be increased, the solder ball spacing in the first region 310 can be decreased, or the solder ball support height in the first region 310 can be increased, while simultaneously decreasing the solder ball density in the second region 320. In this way, the central region with a larger gap G1 gains enhanced contact and support capabilities, preventing solder joints in this region from experiencing cold solder joints due to excessive gaps; the edge region with a smaller gap G2 gains greater deformation margin by reducing the solder ball density, reducing the risk of bridging, ultimately enabling the package substrate 100 and the circuit board 400 to achieve a state of curvature compatibility after board-level assembly.

[0061] Although this embodiment is described using a packaging substrate 100 as an example, it can also be applied to embodiments where the package includes a chip, and will not be elaborated further.

[0062] Figure 8 This is a top view of another solder ball array provided in some embodiments of this disclosure. The package includes a chip and a package substrate 100, as shown in the figure, which illustrates a non-axisymmetric warped shape of the package substrate 100. When multiple chips 200 are integrated on the package substrate 100, due to factors such as uneven chip distribution, uneven local copper density, and differences in material systems, the package substrate 100 may exhibit saddle-shaped, torsional, or locally wavy deformation patterns during the soldering process.

[0063] Taking the saddle-shaped deformation mode as an example, the edge region of the connection area between the packaging substrate 100 and the circuit board 400 includes a first diagonal region and a second diagonal region. The first diagonal region warps along a first direction, and the second diagonal region warps along a second direction opposite to the first direction. That is, the first diagonal region warps away from the circuit board 400, while the second diagonal region sinks towards the circuit board 400. At this time, the first region 310 is located in the first diagonal region, and the second region 320 is located in the second diagonal region. The gap between the packaging substrate 100 and the circuit board 400 in the first region 310 is greater than the gap between them in the second region 320.

[0064] To address the aforementioned situation, the warpage compensation characteristics of the solder ball array in the first region 310 are higher than those in the second region 320. For example, the solder ball density is increased in the raised first diagonal region and decreased in the sunken second diagonal region; a solder ball density between the two is used in the third region 330, located between the first and second regions 310. In this way, the solder ball array 300 forms a non-uniform distribution in the plane that matches the non-axisymmetric deformation of the packaging substrate 100, making the deformation experienced by the solder joints in each region tend to be more balanced.

[0065] The division of the first and second regions and the corresponding warp compensation characteristics can be adopted individually or in combination, depending on the actual warp shape of the packaging substrate 100 and the circuit board 400.

[0066] In some embodiments, the solder balls in the first region 310 and the solder balls in the second region 320 have different solder joint connection structures, thereby giving the solder joints in different regions different equivalent stiffness and deformation capacity.

[0067] Although this embodiment is described using a packaging substrate 100 as an example, it can also be applied to embodiments where the package includes a chip, and will not be elaborated further. Figure 9 This is a cross-sectional view of a solder joint connection structure provided in some embodiments of this disclosure. One embodiment of the package includes a chip and a package substrate 100, as shown in the figure. Figure 9 (a) shows a solder ball solder joint 351, which is formed by solder melting and spreading between the pads 340 of the package substrate 100 and the pads 340 of the circuit board 400, and has moderate equivalent stiffness and deformability. Figure 9 (b) shows a copper pillar composite solder joint 352, which includes a copper pillar and a solder layer located at the end of the copper pillar. The elastic modulus of the copper pillar is higher than that of the solder, so the solder joint has higher equivalent stiffness and larger support height. Figure 9(c) shows a high solder volume solder joint 353, whose solder volume is greater than that of the solder ball solder joint 351, thus the solder joint has a stronger deformation capacity during temperature cycling.

[0068] In some embodiments, in areas with large local gaps, a risk of insufficient contact, or a need for strong support, copper pillar composite solder joints 352 or high-modulus metal interconnect structures are used to improve the equivalent stiffness and load-bearing capacity of the solder joints in these areas. In areas with small local gaps, concentrated thermomechanical stress, or large relative displacement, high-solder-volume solder joints 353 are used to improve the deformation capacity of the solder joints in these areas. This disclosure does not limit the specific implementation of the solder joint connection structure. For example, by using solder ball materials with different melting points or different elastic moduli in different areas, the solder ball array 300 can form regionalized warp compensation characteristics.

[0069] Although this embodiment is described using a packaging substrate 100 as an example, it can also be applied to embodiments where the package includes a chip, and will not be elaborated further.

[0070] By dividing the solder ball array 300 disposed between the packaging substrate 100 and the circuit board 400 into multiple regions, and making at least one warpage compensation characteristic of the first region 310 different from that of the second region 320, the solder balls in the multiple regions form an interconnect layer with regional warpage compensation characteristics. This interconnect layer provides strong contact and support capabilities in regions with larger gaps and provides a larger deformation margin in regions with smaller gaps, thereby actively compensating for the warpage mismatch between the packaging substrate 100 and the circuit board 400. Compared with solutions that reduce warpage by increasing the height of the reinforcing member, adjusting the thickness of the circuit board, or filling the bottom filler, the above solution does not require changing the material system and overall structure of the packaging substrate 100 and the circuit board 400. It can improve the uniformity of solder contact, reduce the probability of corner solder ball bridging, cold solder joints, and local stress concentration, and improve the life of the solder joints in temperature cycling and the reliability of the package interconnect. At the same time, the regional design of the solder ball array 300 can be achieved by adjusting the pad pattern and the ball placement process parameters without adding additional structural components and assembly processes, thus reducing the structural complexity and cost required to achieve the above-mentioned reliability improvement.

[0071] Similar to the above embodiments, in embodiments where the package 10 contains only the chip 200, the fourth surface 202 of the chip 200 can also be provided with a solder ball array, which is directly connected to the circuit board. The arrangement of the solder ball array can refer to the previous embodiments for connecting the package substrate to the circuit board, and will not be elaborated further here. It has the same or similar advantages as the previous embodiments, and will not be elaborated further here. Some embodiments of this disclosure also provide a package structure design method, see [link to relevant documentation]. Figure 10 , Figure 10This is a schematic flowchart illustrating a semiconductor device design method provided in some embodiments of this disclosure. Figure 10 As shown, the method includes: Step S110: Obtain warpage deformation information of the package and circuit board during the soldering process and / or operation process, and determine the warpage mismatch parameters of different areas between the package and circuit board.

[0072] Step S120: Based on the warpage mismatch parameters of different regions, the area on the package where the solder ball array is configured is divided into regions, and multiple regions are determined, including the first region and the second region.

[0073] Step S130: Determine the corresponding warp compensation characteristic parameters for multiple regions. The warp compensation characteristic parameters include at least one of the following: solder ball spacing, solder ball density, solder ball size, solder ball support height, solder joint material, and solder joint structure. At least one warp compensation characteristic of the first region is different from that of the second region.

[0074] Step S140: A regionalized solder ball array is formed based on the warp compensation characteristic parameters corresponding to multiple regions to compensate for the warp mismatch between the package and the circuit board.

[0075] In step S110, the warpage curvature of the package and circuit board under different temperature conditions can be obtained through deformation measurement methods such as shadow moiré, forming a deformation distribution map of the package and circuit board; alternatively, the above warpage deformation information can be obtained through finite element simulation. Based on the difference between the deformation distribution of the package and the deformation distribution of the circuit board, the gap between the two at various locations is obtained, and the deviation of this gap from the preset gap is used as a parameter of the degree of warpage mismatch in the region where that location is located.

[0076] In step S120, locations where the warp mismatch parameter falls within the same numerical range can be grouped into the same region, resulting in a first region, a second region, and an optional third region. The region division result is related to the warp morphology of the package. For example, in an axisymmetric warp morphology, the regions are distributed sequentially from the center to the edge, such as... Figure 4 As shown; in a non-axisymmetric warped shape, the regions exhibit a diagonal distribution, such as... Figure 8 As shown.

[0077] In step S130, warp compensation characteristic parameters are determined based on the local gaps and / or the degree of local warp mismatch in multiple regions. Specifically, the solder ball density in regions with larger local gaps is higher than that in regions with smaller local gaps, and the solder ball spacing in regions with stronger local constraints is greater than that in regions with weaker local constraints. In some embodiments, different solder joint structures and / or different solder volumes can be determined for multiple regions to create regionalized warp compensation characteristics in the solder ball array. For example, copper pillar composite solder joints can be used in regions requiring stronger support capabilities, while high-solder-volume solder joints can be used in regions requiring greater deformation margins.

[0078] In step S140, the pad pattern and ball-mounting process parameters of the package are generated according to the warp compensation characteristic parameters corresponding to each region, and a ball array is formed on the second surface of the package according to the pad pattern and ball-mounting process parameters, resulting in... Figures 3A to 9 The semiconductor device shown in any of the above.

[0079] In some embodiments, the semiconductor device design method further includes: acquiring warpage deformation information of the package and circuit board after forming a regionalized solder ball array, and updating warpage compensation characteristic parameters corresponding to multiple regions based on the warpage deformation information. In this way, the design parameters of the solder ball array can be iteratively adjusted for products of different sizes and different material combinations to form a solder ball arrangement rule with process adaptability.

[0080] It is understood that the package in this method embodiment can be any of the forms in the preceding embodiments. For example, the package may include a chip and a packaging substrate, or the package may only include a chip. Further details are omitted.

[0081] It should be noted that the numbering of the steps above is not intended to limit the execution order of each step. The execution order of each step can be adjusted if there is no conflict. For the parts not described in detail in the above packaging structure design method, please refer to the relevant description of the above semiconductor device.

[0082] Some embodiments of this disclosure also provide an electronic packaging device comprising any of the semiconductor devices described above. Some embodiments of this disclosure also provide an electronic device comprising the electronic packaging device described above.

[0083] For example, see Figure 11This is a schematic diagram of the structure of an electronic device provided in some embodiments of this disclosure. The electronic device 500 includes a circuit board 400, and the circuit board 400 and the semiconductor device mounted on it constitute an electronic package device 600. The circuit board 400 also includes a power supply circuit 530, an interface circuit 540, and a storage device 550. The power supply circuit 530 supplies power to the semiconductor device, the interface circuit 540 enables signal transmission between the semiconductor device and devices other than the electronic device 500, and the storage device 550 stores data required by the semiconductor device during operation.

[0084] This disclosure does not limit the type of electronic device. According to some embodiments, the electronic device may include a server, a personal computer, a general-purpose computing device (e.g., a laptop computer, or a tablet computer, etc.). According to some embodiments, the electronic device may include an in-vehicle computer or in-vehicle computing platform, a smart home electronic product, a personal AI box, a personal AI terminal / device, etc. According to some embodiments, the electronic device may also include a portable terminal, such as a mobile phone, a personal digital assistant, etc.; or it may include a wearable device, such as a head-mounted device, a device that can be worn on the ear, a device that can be worn on the wrist, etc.

[0085] In the above embodiments, the descriptions of different embodiments have different emphases. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments above can be freely combined as needed. And as technology evolves, the elements described in this disclosure can be replaced by equivalent elements appearing after this disclosure.

Claims

1. A semiconductor device, comprising: A package, the package comprising at least one chip; The circuit board is connected to the package via an array of solder balls. The solder ball array includes multiple regions, including a first region and a second region. At least one warpage compensation characteristic of the first region is different from that of the second region. The warpage compensation characteristic represents the ability of the solder ball array to suppress deformation after the package and the circuit board are connected.

2. The semiconductor device according to claim 1, wherein the warpage compensation characteristic includes: At least one of the following: solder ball density, solder ball spacing, solder ball size, solder ball support height, solder ball material, solder joint structure, and solder joint equivalent stiffness.

3. The semiconductor device according to claim 2, wherein the solder ball density in the first region is different from the solder ball density in the second region.

4. The semiconductor device according to claim 3, wherein the center-to-center distance of the solder balls in the first region is different from that in the second region.

5. The semiconductor device according to claim 3, wherein the solder ball size in the first region is different from the solder ball size in the second region.

6. The semiconductor device according to claim 1, wherein the solder balls in the first region and the solder balls in the second region have different solder joint connection structures.

7. The semiconductor device of claim 1, wherein the first region is located in the central region between the package and the circuit board, and the second region is located in the edge region between the package and the circuit board; The package and the circuit board have the same warping direction in the second region, and the gap between the package and the circuit board in the first region is smaller than the gap between the second regions; The warpage compensation characteristics of the solder ball array in the first region are lower than those of the solder ball array in the second region.

8. The semiconductor device of claim 1, wherein the first region is located in the central region between the package and the circuit board, and the second region is located in the edge region between the package and the circuit board; The package and the circuit board have opposite warping directions in the second region, and the gap between the package and the circuit board in the first region is greater than the gap between the two regions. The warpage compensation characteristics of the solder ball array in the first region are higher than those of the solder ball array in the second region.

9. The semiconductor device of claim 1, wherein the edge region of the connection area between the package and the circuit board includes a first diagonal region and a second diagonal region, the first diagonal region being warped along a first direction and the second diagonal region being warped along a second direction opposite to the first direction; The first region is located in the first diagonal region, and the second region is located in the second diagonal region; The warpage compensation characteristics of the solder ball array in the first region are higher than those of the solder ball array in the second region.

10. The semiconductor device as claimed in claim 1, characterized in that, The package includes a chip and a packaging substrate, the packaging substrate having a first surface and a second surface, the second surface and the first surface being opposite to each other; The solder ball array is disposed between the second surface and the circuit board; The circuit board is connected to the packaging substrate via the solder ball array.

11. The semiconductor device as claimed in claim 1, characterized in that, The package includes a chip having a third surface and a fourth surface, the third surface and the fourth surface being opposite to each other. The solder ball array is disposed between the fourth surface and the circuit board; The circuit board is connected to the chip via the solder ball array.

12. A semiconductor device design method, comprising: Acquire warpage deformation information of the package and circuit board during the soldering process and / or operation process, and determine the degree of warpage mismatch parameters of different regions between the package and the circuit board, wherein the package includes at least one chip; Based on the warpage mismatch parameters of different regions, the area on the package body where the solder ball array is configured is divided into multiple regions, including a first region and a second region. For the plurality of regions, corresponding warp compensation characteristic parameters are determined. The warp compensation characteristic parameters include at least one of solder ball spacing, solder ball density, solder ball size, solder ball support height, solder joint material, solder joint structure, and solder joint equivalent stiffness. At least one warp compensation characteristic of the first region is different from that of the second region. A regionalized solder ball array is formed based on the warp compensation characteristic parameters corresponding to the multiple regions to compensate for the warp mismatch between the package and the circuit board.

13. The semiconductor device design method according to claim 12, wherein determining the corresponding warpage compensation characteristic parameters for the plurality of regions includes: The warpage compensation characteristic parameters are determined based on the degree of local gaps and / or local warpage mismatch in the multiple regions, wherein the solder ball density in regions with larger local gaps is higher than that in regions with smaller local gaps, and the solder ball spacing in regions with strong local constraints is greater than that in regions with weak local constraints.

14. The semiconductor device design method according to claim 12, wherein determining the corresponding warpage compensation characteristic parameters for the plurality of regions includes: Different solder joint structures and / or different solder volumes are determined for the multiple regions, so that the solder ball array forms regionalized warp compensation characteristics.

15. An electronic packaging device comprising the semiconductor device according to any one of claims 1-11.

16. An electronic device comprising the electronic packaging device of claim 15.

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