A chip packaging method

Abstract

This disclosure provides a chip packaging method that simultaneously forms an integrated microchannel on the surface of an intermediate while forming a redistribution layer. The microchannel is integrally fabricated, resulting in a stable structure. When multiple second chips are flip-chip connected to the redistribution layer, the hot spots of the second chips are directly connected to the microchannels, achieving precise liquid cooling of local hot spots on the chip. This significantly shortens the heat dissipation path, making heat dissipation more direct and targeted, improving the chip's heat dissipation level at maximum power peak, and avoiding the inefficient problem of heat needing to pass through the entire chip substrate to dissipate. At the same time, using the intermediate as a channel carrier eliminates the need to occupy additional space on the substrate surface, which is beneficial for the miniaturization of the package. Direct heat dissipation of the chip's hot spots can be achieved using microchannels formed inside the redistribution layer without affecting electrical connections, achieving miniaturized packaging compared to the heat sink structure used in the prior art. The microchannels are integrally fabricated only in the redistribution layer, eliminating the need for complex alignment steps and simplifying the process.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a chip packaging method. Background Technology

[0002] Artificial intelligence requires massive computing power, which in turn consumes a significant amount of energy. The greater the computing power of a single chip, the higher its energy consumption. Current chip power consumption is already in the 2000W range, and it will be even higher in the future. The greater the power consumption, the greater the heat generated, requiring stronger heat dissipation capabilities. To improve heat dissipation performance, the industry has begun using microfluidic liquid cooling technology, which involves creating microchannels on the back of the chip to rapidly remove heat through liquid flow.

[0003] Current microfluidic designs on the back of chips are helpful in improving heat dissipation, but they still have some shortcomings. The main issue is that high-performance chips are packaged using flip-chip technology, with the circuit layer on the front and facing down. Since the heat source is on the circuit layer, the microfluidic channels need to dissipate heat through the chip itself. The chip's thickness affects heat dissipation, especially since the chip doesn't heat up uniformly and has hot spots. Back-side heat dissipation is more like surface-level heat dissipation for these hot spots, lacking specificity. Furthermore, in future 3D stacked packaging, the heat dissipation path between the back microfluidic channels and the front of the chip involves multiple chips and multiple interfaces, making the heat dissipation path even more complex.

[0004] To address the aforementioned issues, it is necessary to propose a chip packaging method that is both rationally designed and effectively solves these problems. Summary of the Invention

[0005] The present disclosure aims to at least solve one of the technical problems existing in the prior art and provide a chip packaging method.

[0006] This disclosure provides a chip packaging method, the packaging method comprising: An intermediary is formed, the intermediary comprising a first molding compound encapsulating a plurality of first chips and a plurality of conductive pillars spaced apart through the thickness of the first molding compound. A redistribution layer is formed on the surface of the intermediary, and microchannels encapsulated within the redistribution layer are integrally formed on the surface of the intermediary. Multiple second chips are flip-chip connected to the redistribution layer, wherein the hot spot area of ​​the second chip is connected to the microchannel; A second molding layer is formed to encapsulate multiple second chips; A first chamber and a second chamber are formed in the second encapsulation layer, wherein the first chamber is connected to the microchannel inlet and the second chamber is connected to the microchannel outlet; An inlet pipe interface and an outlet pipe interface are respectively provided in the first chamber and the second chamber to form a chip package.

[0007] Optionally, a redistribution layer is formed on the surface of the intermediary, and a microchannel structure encapsulated within the redistribution layer is integrally formed on the surface of the intermediary, including: A bottom metal layer is formed by electroplating on the surface of the intermediate, and a microchannel bottom wall is formed by electroplating on the surface of the intermediate. A bottom dielectric layer is formed on the surface of the bottom metal layer; Multiple intermediate metal layers and multiple intermediate dielectric layers are sequentially and spaced apart on the surface of the bottom dielectric layer. At the same time, microchannel sidewalls are gradually grown by electroplating on the bottom wall of the microchannel and microchannel topwalls are formed by electroplating on the microchannel sidewalls. A top dielectric layer is formed on the uppermost intermediate metal layer and the top wall of the microchannel.

[0008] Optionally, during the formation of the microchannel sidewall, a photosensitive material layer is filled into the cavity formed by the microchannel sidewall and the microchannel bottom wall.

[0009] Optionally, a first chamber and a second chamber are formed in the second molding layer, including: The second molding layer is etched at the microchannel inlet and microchannel outlet to form the first chamber and the second chamber respectively, exposing the top wall of the microchannel; Laser is used to remove the top walls of the microchannels at the inlet and outlet to expose the photosensitive material layer.

[0010] Optionally, an inlet pipe interface and an outlet pipe interface are respectively provided in the first chamber and the second chamber, including: The inlet pipe interface and the outlet pipe interface are respectively installed in the first chamber and the second chamber; A sealant layer is filled between the first chamber and the inlet pipe interface, and between the second chamber and the outlet pipe interface.

[0011] Optionally, after providing inlet and outlet pipe interfaces in the first and second chambers respectively, the method further includes: The photosensitive material layer is gradually dissolved by introducing a dissolving solution through the inlet pipe interface.

[0012] Optionally, multiple second chips are flip-chip connected to the redistribution layer, including: Multiple second chips are flip-chip connected to the redistribution layer via thermal bumps, and the hot spots of the second chips are connected to the microchannels via thermal bumps. An underfill layer is formed between the second chip and the redistribution layer to encapsulate the thermal bumps.

[0013] Optionally, the formation of an intermediary includes: Provide temporary carrier board; Multiple first chips are mounted on the temporary carrier board; Multiple conductive pillars are electroplated onto the temporary carrier plate; A first molding compound is formed on the temporary carrier board to encapsulate the plurality of the first chips and the plurality of the conductive pillars; A wiring layer and a plurality of conductive bumps are sequentially formed on the surface of the first molding layer, and the temporary carrier is removed to form the intermediary.

[0014] Optionally, after forming the second molding layer, the method further includes: The components are cut to form multiple independent intermediate packages; Multiple intermediate packages are connected to the substrate via multiple conductive bumps; Multiple solder balls are formed on the side of the substrate opposite to the chip package.

[0015] Optionally, the microchannel is S-shaped with its ends connected, and the cross-section of the microchannel is square.

[0016] The chip packaging method of this disclosure forms an integrated microchannel on the surface of an intermediate while simultaneously forming a redistribution layer. The microchannel is integrally fabricated, resulting in a stable structure. When multiple second chips are flip-chip connected to the redistribution layer, the hot spots of the second chips are directly connected to the microchannels, achieving precise liquid cooling of local hot spots on the chip. This significantly shortens the heat dissipation path, making heat dissipation more direct and targeted, improving the chip's heat dissipation level at maximum power peak, and avoiding the inefficient problem of heat needing to pass through the entire chip substrate to dissipate. Simultaneously, using the intermediate as a channel carrier eliminates the need for additional space on the substrate surface, facilitating miniaturization of the package. Direct heat dissipation of the chip's hot spots can be achieved using microchannels formed within the redistribution layer without affecting electrical connections, achieving miniaturized packaging compared to the heat sink structure used in existing technologies. The microchannels are integrally fabricated only within the redistribution layer, eliminating the need for complex alignment steps and simplifying the process. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a chip packaging method according to one embodiment of the present disclosure; Figures 2 to 21 This is a schematic diagram of the process of a chip packaging method according to another embodiment of this disclosure, wherein, Figures 2 to 14 This is a cross-sectional view along line A-A'. Figure 16 , 18 and Figure 20 This is a cross-sectional view of section B-B'. Figure 22 This is a top view of a microchannel according to another embodiment of this disclosure. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0019] like Figure 1 As shown, this embodiment of the present disclosure provides a chip packaging method S100, which includes: S110. Form an intermediary, the intermediary comprising a first molding compound encapsulating a plurality of first chips and a plurality of conductive pillars spaced apart through the thickness of the first molding compound.

[0020] Specifically, such as Figure 2 As shown, the steps to form the intermediary 100 can be as follows: First, a temporary carrier board is provided, and multiple first chips 111 are mounted on the temporary carrier board. The multiple first chips 111 can be homogeneous chips or heterogeneous chips, which can be selected according to actual needs. Second, multiple conductive pillars 112 are electroplated on the temporary carrier board. In this embodiment, the conductive pillars 112 are copper pillars, meaning copper pillars are electroplated on the temporary carrier board. Third, a first molding compound 113 is formed on the temporary carrier board, encapsulating the multiple first chips 111 and the multiple conductive pillars 112. Finally, a wiring layer 114 is first formed on the surface of the first molding compound 113, and then multiple conductive bumps 115 are formed on the wiring layer 114 to form the intermediary 110. Afterwards, the entire intermediary 110 is mounted and fixed to a temporary glass plate A using a temporary bonding layer. In other words, the intermediary 110 includes a first molding compound 113 encapsulating a plurality of first chips 111, a plurality of conductive pillars 112 spaced apart through the thickness of the first molding compound 113, a wiring layer 114 disposed on the surface of the first molding compound 113, and a plurality of conductive bumps 115 disposed on the wiring layer 114.

[0021] In this step, by encapsulating multiple first chips and conductive pillars together in a first molding layer to form an integrated embedded interposer, high-density, multi-chip embedded interconnects can be achieved at the wafer level. This provides a flat and robust foundation platform for subsequent fabrication of high-precision redistribution layers and microchannels on the surface, while simplifying the manufacturing process of the interposer and reducing the stacking thickness of multilayer substrates.

[0022] For example, such as Figure 21As shown, in another embodiment, the intermediary 110 can be a glass sheet with a plurality of conductive pillars 112. That is, a glass sheet is provided, and then a plurality of conductive pillars 112 penetrating through its thickness are formed on the glass sheet to form the intermediary 110. It should be noted that the material and structural composition of the intermediary 110 are not specifically limited and can be selected according to actual needs.

[0023] S120. A redistribution layer is formed on the surface of the intermediate body, and microchannels encapsulated within the redistribution layer are integrally formed on the surface of the intermediate body.

[0024] Specifically, a redistribution layer 120 is formed on the surface of the intermediary 110, and simultaneously, microchannels 130 encapsulated within the redistribution layer 120 are integrally formed on the surface of the intermediary 110. The specific process of forming step S120 can be as follows: like Figure 3 As shown, a bottom metal layer is electroplated on the surface of the intermediate body 110, and a microchannel bottom wall 131 is electroplated on the surface of the intermediate body 110. The bottom metal layer is a copper layer, and the microchannel bottom wall 131 is a copper wall.

[0025] like Figure 3 As shown, a bottom dielectric layer is formed on the surface of the bottom metal layer; wherein, the bottom dielectric layer forms an opening at the corresponding microchannel bottom wall 131 to expose the microchannel bottom wall 131. The main material of the bottom dielectric layer is polyimide. If the thickness of the microchannel bottom wall 131 formed in a single electroplating is less than 10 μm, multiple dielectric layers can be repeatedly fabricated to achieve a thickness of 10 μm for the microchannel bottom wall 131.

[0026] like Figures 4 to 9 As shown, multiple intermediate metal layers and multiple intermediate dielectric layers are sequentially and spaced apart on the surface of the bottom dielectric layer. Simultaneously, microchannel sidewalls 132 are gradually electroplated and grown on the bottom wall 131 of the microchannel, and a microchannel top wall 133 is electroplated on the sidewalls 132. A top dielectric layer is formed on the uppermost intermediate metal layer and the top wall of the microchannel. During the formation of the microchannel sidewalls 132, a photosensitive material layer 140 is filled within the cavity formed by the sidewalls 132 and the bottom wall 131 of the microchannel.

[0027] Specifically, such as Figure 5 As shown, an intermediate metal layer is formed by electroplating on the bottom dielectric layer, while a microchannel sidewall 132 is grown on the bottom wall 131 of the microchannel. The bottom wall 131 of the microchannel is also made of copper. The microchannel sidewall 132 and the bottom wall 131 of the microchannel form an intermediate chamber.

[0028] like Figure 6As shown, an intermediate dielectric layer is formed on the surface of the intermediate metal layer, and an opening is formed at the corresponding microchannel 130.

[0029] like Figure 7 As shown, a photosensitive polycarbonate material is coated in the middle chamber of the microchannel to form a photosensitive material layer 140. The thermal decomposition temperature of the photosensitive polycarbonate material is above 250℃.

[0030] like Figure 7 and 8 As shown, intermediate dielectric and intermediate metal layers are continuously grown at intervals, while microchannel sidewalls 132 and photosensitive material layers 140 are grown simultaneously, ultimately achieving a photosensitive material layer 140 thickness of over 20 μm. By filling the microchannel cavity with the photosensitive material layer 140, temporary internal support and spacer protection are provided for the subsequent formation of hollow microchannels. The thickness of the photosensitive material layer determines the radial dimension of the microchannel. In the high-temperature, high-stress process environment of multilayer metal layers and copper wall electroplating thickening, this photosensitive material layer can effectively prevent the top wall of the microchannel from collapsing or deforming during electroplating or lamination, ensuring the accuracy of the hollow dimensions inside the microchannel. At the same time, this material has a thermal decomposition temperature above 250°C, which can withstand the high temperatures of subsequent packaging processes without failure.

[0031] like Figure 9 As shown, intermediate dielectric and intermediate metal layers are formed at intervals, and microchannel top walls 133 are formed by electroplating on the microchannel sidewalls 132. At this point, the complete microchannel 130 has been integrally fabricated.

[0032] like Figure 10 As shown, a top metal layer and a top dielectric layer are formed, and finally an opening is made at the top dielectric layer to form a soldering area to form a redistribution layer 120.

[0033] In this step, microchannels are constructed by growing metal layers through electroplating. All metal walls of the microchannels are thickened and formed synchronously with the redistribution layers. The microchannels are integrally electroplated and formed, which significantly improves the structural strength and pressure resistance of the microchannel walls, enabling them to withstand the internal pressure brought by high-speed coolant flow. They are less prone to deformation or leakage, ensuring long-term operational reliability, and without adding additional photolithography or bonding alignment processes.

[0034] S130. A plurality of second chips are flip-chip connected to the redistribution layer, wherein the hot spot area of ​​the second chip is connected to the microchannel.

[0035] like Figure 11 As shown, multiple second chips 150 are flip-chip mounted to the opening of the uppermost dielectric layer via thermal bumps 151, and electrically connected to the uppermost metal layer of the redistribution layer 120. The hot spots of the second chips 150 are connected to the microchannel 130 via thermal bumps 151. Figure 12 As shown, an underfill layer is formed between the second chip 150 and the redistribution layer 120 to enclose the thermal bumps. The underfill layer encloses the thermal bumps, providing physical support and protecting the reliability of the bump connection. The multiple second chips 150 can be homogeneous or heterogeneous chips, which can be selected according to actual needs.

[0036] In this step, the hot spot area of ​​the second chip is directly connected to the microchannel via thermal bumps, creating an ultra-short thermal conduction path from the heat source to the coolant. The thermal bumps themselves are made of a highly thermally conductive metal material, which can rapidly conduct the heat generated in the local hot spot area of ​​the chip to the wall of the microchannel, where it is directly carried away by the flowing coolant. This makes heat dissipation more direct and targeted, improving the chip's heat dissipation level at maximum power peak.

[0037] S140, A second molding compound is formed to encapsulate the plurality of the second chips.

[0038] like Figure 12 As shown, a second molding compound 160 is formed to encapsulate multiple second chips 150, and the second molding compound 160 protects the second chips 150.

[0039] like Figure 13 As shown, the temporary glass substrate A can be removed using a laser debonding method. The completed wafer is then diced to form multiple independent intermediate packages.

[0040] like Figure 14 As shown, multiple intermediate packages are connected to a substrate 170 via multiple conductive bumps 115, and an underfill layer is formed between the conductive bumps 115 and the substrate 170. Multiple solder balls 180 are formed on the side of the substrate 170 opposite to the chip package.

[0041] S150. A first chamber and a second chamber are formed in the second encapsulation layer, wherein the first chamber is connected to the microchannel inlet and the second chamber is connected to the microchannel outlet.

[0042] like Figure 15 and Figure 16 As shown, a first chamber 161 and a second chamber 162 are formed in the second encapsulation layer 160, wherein the first chamber 161 is connected to the microchannel inlet and the second chamber 162 is connected to the microchannel outlet.

[0043] The specific process of step S150 can be as follows: like Figure 16 As shown, the second molding layer 160 is etched at the microchannel inlet and microchannel outlet to form the first chamber 161 and the second chamber 162 respectively, exposing the microchannel top wall 133.

[0044] like Figure 17 and Figure 18 As shown, a laser is used to remove the top wall 133 of the microchannel at the inlet and outlet of the microchannel to expose the photosensitive material layer 140.

[0045] In this step, the first and second chambers are first etched on the second molding layer to expose the top wall of the microchannel. Then, the top wall of the microchannel is removed by laser to expose the internal photosensitive material layer. This allows for precise connection between the microchannel and the external coolant circulation system without damaging the surrounding redistribution and other chip structures. This ensures the accuracy of the connection between the channel system and the external pipeline and the cleanliness of the sealed area.

[0046] S160. An inlet pipe interface and an outlet pipe interface are respectively provided in the first chamber and the second chamber.

[0047] like Figure 19 and Figure 20 As shown, the inlet pipe interface 164 and the outlet pipe interface 165 are respectively installed in the first chamber 161 and the second chamber 162; a sealant layer 163 is filled between the first chamber 161 and the inlet pipe interface 164, and between the second chamber 162 and the outlet pipe interface 165. The inlet pipe interface 164 is connected to the inlet pipe, and the outlet pipe interface 165 is connected to the outlet pipe. Coolant is delivered to the inlet pipe interface 164 through the inlet pipe, enters the microchannel 130 through the microchannel inlet, undergoes heat exchange, enters the outlet pipe interface 165 through the microchannel outlet, and flows out through the outlet pipe, completing the heat exchange process.

[0048] By filling the space between the first chamber and the inlet pipe interface, and between the second chamber and the outlet pipe interface, a reliable sealed connection between the microchannel inlet / outlet and the external liquid cooling circulation system is achieved. The sealant layer completely seals the gaps between the pipe interface and the plastic sealant layer and copper wall, effectively preventing coolant leakage from the interface during high-pressure flow, thus improving the overall fluid sealing safety and long-term stability of the package.

[0049] like Figure 20 As shown, a dissolving solution is introduced through the inlet pipe interface 164 to gradually dissolve the photosensitive material layer 140, achieving a gentle and non-destructive removal of the photosensitive material layer 140. The dissolving solution can be NMP or PGMEA, etc. After the photosensitive polycarbonate photosensitive material layer 140 is completely dissolved, deionized water is introduced for rinsing.

[0050] By employing a chemical dissolution method to dissolve the photosensitive material layer, the filler material layer can be completely dissolved and discharged through the outlet without affecting the properties of the already formed copper metal wall and dielectric layer material, thereby forming a smooth and unobstructed internal cavity flow channel. This ensures that there are no residual debris on the inner wall of the flow channel, effectively reducing the flow resistance of the coolant and improving heat dissipation efficiency.

[0051] For example, such as Figure 22 As shown, the microchannel 130 is S-shaped with its ends connected. Figure 14 As shown, the cross-section of the microchannel 130 is square.

[0052] In this embodiment, by setting the microchannels to an S-shape (serpentine) with connected ends and a square cross-section, the flow path length and heat exchange area of ​​the coolant within the limited package plane area are effectively increased. The S-shaped orientation allows the microchannels to repeatedly pass through multiple areas under the chip, extending the contact time between the coolant and the microchannel walls, thereby removing more heat. At the same time, the square cross-sectional structure is easier to precisely form through photolithography and electroplating in the electroplating process, and the square channel has a uniform stress distribution when subjected to internal fluid pressure, further improving the structural stability and heat dissipation uniformity of the channel.

[0053] The chip packaging method of this disclosure forms an integrated microchannel on the surface of an intermediate while simultaneously forming a redistribution layer. The microchannel is integrally fabricated, resulting in a stable structure. When multiple second chips are flip-chip connected to the redistribution layer, the hot spots of the second chips are directly connected to the microchannels, achieving precise liquid cooling of local hot spots on the chip. This significantly shortens the heat dissipation path, making heat dissipation more direct and targeted, improving the chip's heat dissipation level at maximum power peak, and avoiding the inefficient problem of heat needing to pass through the entire chip substrate to dissipate. Simultaneously, using the intermediate as a channel carrier eliminates the need for additional space on the substrate surface, facilitating miniaturization of the package. Direct heat dissipation of the chip's hot spots can be achieved using microchannels formed within the redistribution layer without affecting electrical connections, achieving miniaturized packaging compared to the heat sink structure used in existing technologies. The microchannels are integrally fabricated only within the redistribution layer, eliminating the need for complex alignment steps and simplifying the process.

[0054] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A chip packaging method, characterized in that, The encapsulation method includes: An intermediary is formed, the intermediary comprising a first molding compound encapsulating a plurality of first chips and a plurality of conductive pillars spaced apart through the thickness of the first molding compound. A redistribution layer is formed on the surface of the intermediary, and microchannels encapsulated within the redistribution layer are integrally formed on the surface of the intermediary. Multiple second chips are flip-chip connected to the redistribution layer, wherein the hot spot area of ​​the second chip is connected to the microchannel; A second molding layer is formed to encapsulate multiple second chips; A first chamber and a second chamber are formed in the second encapsulation layer, wherein the first chamber is connected to the microchannel inlet and the second chamber is connected to the microchannel outlet; An inlet pipe interface and an outlet pipe interface are respectively provided in the first chamber and the second chamber.

2. The method according to claim 1, characterized in that, A redistribution layer is formed on the surface of the intermediary, and a microchannel structure encapsulated within the redistribution layer is integrally formed on the surface of the intermediary, including: A bottom metal layer is formed by electroplating on the surface of the intermediate, and a microchannel bottom wall is formed by electroplating on the surface of the intermediate. A bottom dielectric layer is formed on the surface of the bottom metal layer; Multiple intermediate metal layers and multiple intermediate dielectric layers are sequentially and spaced apart on the surface of the bottom dielectric layer. At the same time, microchannel sidewalls are gradually grown by electroplating on the bottom wall of the microchannel and microchannel topwalls are formed by electroplating on the microchannel sidewalls. A top dielectric layer is formed on the uppermost intermediate metal layer and the top wall of the microchannel.

3. The method according to claim 2, characterized in that, During the formation of the microchannel sidewall, a photosensitive material layer is filled into the cavity formed by the microchannel sidewall and the microchannel bottom wall.

4. The method according to claim 3, characterized in that, A first chamber and a second chamber are formed in the second molding layer, including: The second molding layer is etched at the microchannel inlet and microchannel outlet to form the first chamber and the second chamber respectively, exposing the top wall of the microchannel; Laser is used to remove the top walls of the microchannels at the inlet and outlet to expose the photosensitive material layer.

5. The method according to claim 3, characterized in that, An inlet pipe interface and an outlet pipe interface are respectively provided in the first chamber and the second chamber, including: The inlet pipe interface and the outlet pipe interface are respectively installed in the first chamber and the second chamber; A sealant layer is filled between the first chamber and the inlet pipe interface, and between the second chamber and the outlet pipe interface.

6. The method according to claim 5, characterized in that, After installing inlet pipe interfaces and outlet pipe interfaces in the first chamber and the second chamber respectively, the method further includes: The photosensitive material layer is gradually dissolved by introducing a dissolving solution through the inlet pipe interface.

7. The method according to claim 1, characterized in that, Connecting multiple second chips to the redistribution layer via flip-chip bonding includes: Multiple second chips are flip-chip connected to the redistribution layer via thermal bumps, and the hot spots of the second chips are connected to the microchannels via thermal bumps. An underfill layer is formed between the second chip and the redistribution layer to encapsulate the thermal bumps.

8. The method according to claim 1, characterized in that, The formation of an intermediary includes: Provide temporary carrier board; Multiple first chips are mounted on the temporary carrier board; Multiple conductive pillars are electroplated onto the temporary carrier plate; A first molding compound is formed on the temporary carrier board to encapsulate the plurality of the first chips and the plurality of the conductive pillars; A wiring layer and a plurality of conductive bumps are sequentially formed on the surface of the first molding layer, and the temporary carrier is removed to form the intermediary.

9. The method according to claim 8, characterized in that, After forming the second molding layer, the method further includes: The components are cut to form multiple independent intermediate packages; Multiple intermediate packages are connected to the substrate via multiple conductive bumps; Multiple solder balls are formed on the side of the substrate opposite to the chip package.

10. The method according to claim 1, characterized in that, The microchannels are S-shaped with their ends connected, and the cross-section of the microchannels is square.

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