Semiconductor package

Abstract

This invention discloses a semiconductor package comprising a package substrate, an interposer, at least one first element, and a plurality of second elements. The package substrate includes at least one first embedded interconnect of a first packaging technology. The interposer is mounted on the package substrate and includes at least one second embedded interconnect of a second packaging technology. The at least one first element is mounted on the package substrate and is electrically connected to the interposer via the at least one first embedded interconnect of the package substrate. The plurality of second elements are mounted on the interposer, wherein any two of the plurality of second elements are electrically connected via the at least one second embedded interconnect of the interposer.

Description

Technical Field

[0001] This invention relates to integrated circuit (IC) design, and more particularly to a semiconductor package that utilizes a combination of different packaging technologies to perform die complex expansion. Background Technology

[0002] Advanced packaging refers to a set of semiconductor integration technologies that surpass traditional wire bonding and flip-chip packaging, enabling higher bandwidth, lower power consumption, smaller size, and heterogeneous integration of multiple chips. However, as the size of chip complexes increases, advanced packaging solutions from a single supplier face physical mask limitations and cost constraints. Therefore, there is an urgent need for an innovative semiconductor packaging design that can leverage the advantages of different advanced packaging technologies to scale chip complexes to a scale that traditional semiconductor packaging using a single advanced packaging technology cannot achieve. Summary of the Invention

[0003] One of the objectives of this invention is to provide a semiconductor package that uses a combination of different packaging technologies to achieve chip composite expansion.

[0004] According to one aspect of the present invention, an exemplary semiconductor package is disclosed. The exemplary semiconductor package includes a package substrate, an interposer layer, at least one first element, and a plurality of second elements. The package substrate includes at least one first embedded interconnect of a first packaging technology. The interposer layer is mounted on the package substrate and includes at least one second embedded interconnect of a second packaging technology. The at least one first element is mounted on the package substrate and is electrically connected to the interposer layer via the at least one first embedded interconnect of the package substrate. The plurality of second elements are mounted on the interposer layer, wherein any two second elements are electrically connected via the at least one second embedded interconnect of the interposer layer.

[0005] These and other objectives of the present invention will undoubtedly become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments shown in conjunction with the figures and drawings. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the structure of a semiconductor package according to an embodiment of the present invention.

[0007] Figure 2 This is a top view of a semiconductor package with a maximized computing region according to an embodiment of the present invention.

[0008] Figure 3 for Figure 2 The semiconductor package shown is a cross-sectional view along line A-A'.

[0009] Figure 4 This is a top view of a semiconductor package of an east-west oriented memory stack according to an embodiment of the present invention.

[0010] Figure 5 for Figure 4 The semiconductor package shown is a cross-sectional view along line B-B'.

[0011] The reference numerals in the attached figures are explained as follows: 100: Semiconductor Packaging 102: Packaging substrate 104: Intermediary Layer 106_1, 106_2, 106_N: First element 108_1, 108_2, 108_3, 108_M: Second element 110_1, 110_2, 110_K: First Embedded Interconnect 112_1, 112_2, 112_J: Second embedded interconnect. Detailed Implementation

[0012] Certain terms are used in the following description and claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements with different names but the same function. In the following description and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including but not limited to...". Furthermore, the term "coupled" is intended to indicate an indirect or direct electrical connection. Thus, if one device is coupled to another, the connection can be a direct electrical connection or an indirect electrical connection achieved through other devices and connections.

[0013] Figure 1 This is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention. The semiconductor package 100 includes a packaging substrate (e.g., an organic substrate) 102, an interposer 104, and at least one first element 106_1 to 106_N (…). ), and multiple second elements 108_1~108_M ( The packaging substrate 102 includes at least one first embedded interconnect 110_1 to 110_K of a first packaging technology. Intermediate layer 104 is mounted on package substrate 102 and includes at least one second embedded interconnect 112_J of the second packaging technology. At least one first element 106_1 to 106_N ( ) is mounted on the packaging substrate 102 and connected to at least one first embedded interconnect 110_1 to 110_K of the packaging substrate 102. The second elements 108_1 to 108_M are electrically connected to the intermediate layer 104. ) is installed on the intermediate layer 104, wherein a plurality of second elements 108_1 to 108_M ( Any two second elements in ) are interconnected by at least one second embedded interconnect 112_J in the intermediary layer 104. To achieve electrical connection.

[0014] In some embodiments of the present invention, the first packaging technology may be a Coupled Embedded Multi-die Interconnect Bridge (Co-EMIB), each first embedded interconnect 110_K ( The second packaging technology can be a silicon bridge (i.e., an EMIB bridge) embedded in the packaging substrate 102. In some embodiments of the present invention, the second packaging technology can be a chip-on-wafer-on-substrate with local silicon interconnect (CoWoS-L), where each second embedded interconnect 112_J ( This can be a local silicon interconnect (LSI) embedded in an interposer layer based on a redistribution layer (RDL). For ease of understanding of the technical features of this invention, it is assumed below that the semiconductor package 100 uses a combination of CoWoS-L and Co-EMIB for chip composite expansion. For example, with the aid of Co-EMIB, the first elements 106_1 to 106_N can be placed on the package substrate 102, expanding the chip composite by 8 times.

[0015] The components assembled and packaged in semiconductor package 100 may include chiplets and memory chips. In practical applications, the present invention does not limit the components mounted on the interposer 104 or the components mounted on the package substrate 102. In other words, any semiconductor package that uses different combinations of packaging technologies (e.g., CoWoS-L and Co-EMIB) to extend the chip complex falls within the scope of the present invention.

[0016] High bandwidth memory (HBM) employs a three-dimensional (3D) stacking method, vertically stacking multiple HBM dynamic random access memory (DRAM) chips on a logic chip (also known as the base die), and electrically connecting the HBM DRAM chips to the logic chip using through-silicon vias (TSVs). HBMs can be mounted on either the package substrate 102 or the interposer layer 104, depending on the specific design considerations.

[0017] The compute die can be a graphics processing unit (GPU), a central processing unit (CPU), a system-on-a-chip (SoC), or any data center processor chip. The compute die can be mounted on the packaging substrate 102 or the interposer layer 104, depending on the specific design considerations.

[0018] In some embodiments of the present invention, at least one first element 106_1 to 106_N ( ) is mounted on the packaging substrate 102. ) may include one or more HBMs. In some embodiments of the invention, at least one first element 106_1 to 106_N mounted on the package substrate 102 ( The component may include one or more computing chips. In some embodiments of the invention, at least one first element 106_1 to 106_N mounted on the packaging substrate 102 ( It may include one or more HBMs and one or more computing chips.

[0019] In some embodiments of the present invention, a plurality of second elements 108_1 to 108_M ( ) are mounted on the intermediary layer 104. The invention may include one or more computing chips. In some embodiments of the invention, a plurality of second elements 108_1 to 108_M ( ) mounted on the interposer layer 104 ) may include one or more HBMs. In some embodiments of the invention, a plurality of second elements 108_1 to 108_M mounted on the interposer layer 104 ( It may include one or more computing chips and one or more HBMs.

[0020] In most cases, the interposer 104 is more expensive than the package substrate 102. In some embodiments of the invention, a plurality of second elements 108_1 to 108_M (…) are mounted on the interposer 104. This can include all computing chips assembled and packaged in semiconductor package 100, and HBM is not mounted on interposer 104. This allows interposer 104 to be used entirely for computing, thereby maximizing the compute area. Figure 2 This is a top view of a semiconductor package with a maximized computing area according to an embodiment of the present invention. Figure 3 yes Figure 2 The diagram shows a cross-sectional view of the semiconductor package along line A-A'. In this embodiment, the semiconductor package 100 includes first elements 106_1 and 106_2, which are HBMs, and second elements 108_1 and 108_2, which are computing chips. The second elements (i.e., computing chips) 108_1 and 108_2 are electrically connected via a second embedded interconnect (e.g., a CoWoS-L local silicon interconnect) 112_1. The first element (i.e., HBM) 106_1 is electrically connected to the interposer 104 via a first embedded interconnect (e.g., an EMIB bridge) 110_1. The first element (i.e., HBM) 106_2 is electrically connected to the interposer 104 via another first embedded interconnect (e.g., an EMIB bridge) 110_2. Figure 2 As shown, all HBMs are mounted on the packaging substrate 102. In this way, four compute-intensive computing chips can be mounted on the interposer layer 104.

[0021] In some embodiments of the invention, combinations of different packaging technologies (e.g., CoWoS-L and Co-EMIB) also provide the ability to stack memory chips in the same direction (e.g., east-west (EW) direction). Figure 4 This is a top view of a semiconductor package of an east-west oriented memory stack according to an embodiment of the present invention. Figure 5 yes Figure 4The diagram shows a cross-sectional view of the semiconductor package along line B-B'. In this embodiment, the first elements 106_1 and 106_2 and the second elements 108_1 and 108_3 included in the semiconductor package 100 are HBMs, and the second element 108_2 is a computing chip. The second elements (i.e., the HBM and the computing chip) 108_1 and 108_2 are electrically connected through a second embedded interconnect (e.g., a CoWoS-L local silicon interconnect) 112_1, and the second elements (i.e., the computing chip and the HBM) 108_2 and 108_3 are electrically connected through another second embedded interconnect (e.g., a CoWoS-L local silicon interconnect) 112_2. The first element (i.e., the HBM) 106_1 is electrically connected to the interposer 104 through a first embedded interconnect (e.g., an EMIB bridge) 110_1. The first element (i.e., the HBM) 106_2 is electrically connected to the interposer 104 through another first embedded interconnect (e.g., an EMIB bridge) 110_2.

[0022] like Figure 5 As shown, the first element (i.e., HBM) 106_1 and the second element (i.e., HBM) 108_1 are offset in the vertical direction and arranged side by side in the horizontal direction. The first element (i.e., HBM) 106_2 and the second element (HBM) 108_3 are offset in the vertical direction and arranged side by side in the horizontal direction. Figure 4 As shown, on one side of the second element (computing chip) 108_2, the first element (i.e., HBM) 106_1 and the second element (i.e., HBM) 108_1 are stacked in the east-west direction of the semiconductor package 100 (especially in the east-west direction of the top view of the semiconductor package 100), and arranged in an HBM behind HBM stacking manner without offset in the north-south (NS) direction of the semiconductor package 100 (especially in the north-south direction of the top view of the semiconductor package 100). On the other side of the second element (computing chip) 108_2, the first element (i.e., HBM) 106_2 and the second element (i.e., HBM) 108_3 are stacked in the east-west direction of the semiconductor package 100 (especially in the east-west direction of the top view of the semiconductor package 100), and arranged in an HBM behind HBM stacking manner with offset in the north-south (NS) direction of the semiconductor package 100 (especially in the north-south direction of the top view of the semiconductor package 100). The offset HBM stacking arrangement can reduce the signal routing difficulty in the interposer layer 104. However, this is for illustrative purposes only and is not a limitation of the invention.

[0023] The foregoing has outlined the features of several embodiments, enabling those skilled in the art to fully understand various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A semiconductor package, characterized in that, include: Packaging substrate, including: At least one first embedded interconnect of the first packaging technology; An interposer layer is mounted on the packaging substrate, wherein the interposer layer comprises: At least one second embedded interconnect of the second packaging technology; At least one first element is mounted on the packaging substrate, wherein the at least one first element is electrically connected to the interposer layer via the at least one first embedded interconnect of the packaging substrate; and A plurality of second elements are mounted on the intermediary layer, wherein any two of the plurality of second elements are electrically connected through the at least one second embedded interconnect of the intermediary layer.

2. The semiconductor package as described in claim 1, characterized in that, The first packaging technology is a coupled embedded multi-chip interconnect bridge.

3. The semiconductor package as described in claim 2, characterized in that, The second packaging technology is a stacked packaging of a chip, wafer, and substrate with local silicon interconnects.

4. The semiconductor package as described in claim 1, characterized in that, The second packaging technology is a stacked packaging of a chip, wafer, and substrate with local silicon interconnects.

5. The semiconductor package as described in claim 1, characterized in that, The at least one first element includes at least one high-bandwidth memory.

6. The semiconductor package as described in claim 5, characterized in that, The at least one first element also includes at least one computing chip.

7. The semiconductor package as described in claim 1, characterized in that, The at least one first element includes at least one computing chip.

8. The semiconductor package as described in claim 1, characterized in that, The plurality of second elements includes at least one computing chip.

9. The semiconductor package as described in claim 8, characterized in that, The plurality of second elements also include at least one high-bandwidth memory.

10. The semiconductor package as claimed in claim 1, characterized in that, The plurality of second elements includes at least one high-bandwidth memory.

11. The semiconductor package as claimed in claim 1, characterized in that, The plurality of second elements include a plurality of computing chips, and no high-bandwidth memory is mounted on the intermediary layer.

12. The semiconductor package as claimed in claim 1, characterized in that, The at least one first element includes a first high-bandwidth memory, the plurality of second elements include a second high-bandwidth memory, and the first high-bandwidth memory and the second high-bandwidth memory are stacked in the east-west direction of the semiconductor package and arranged in a high-bandwidth memory stacking manner without offset in the north-south direction of the semiconductor package.

13. The semiconductor package as claimed in claim 1, characterized in that, The at least one first element includes a first high-bandwidth memory, the plurality of second elements include a second high-bandwidth memory, and the first high-bandwidth memory and the second high-bandwidth memory are stacked in the east-west direction of the semiconductor package and arranged in a high-bandwidth memory stacking manner offset in the north-south direction of the semiconductor package.

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