Selective deposition of cobalt and ruthenium and related structures

Abstract

The invention describes a method for selectively depositing a cobalt or ruthenium seed layer onto a semiconductor substrate, a method for forming conductive contacts on the semiconductor substrate, and a semiconductor substrate formed according to the method.

Description

Cross-reference of related applications

[0001] This application claims priority and rights to U.S. Provisional Application No. 63 / 567,608, filed March 20, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0002] The following description relates to methods for selectively depositing cobalt or ruthenium onto a semiconductor substrate, methods for forming bulk metal structures (e.g., conductive contacts) on a semiconductor substrate, and semiconductor substrates formed according to said methods. Background Technology

[0003] For current technology nodes (e.g., N2 nodes and above), the back-side contacts for distribution network (BSPDN) integration are incorporated into direct metal contacts from the back side to the source and drain regions of the GAA (gate-all-around) transistors. The contact vias are small in size and exhibit a high aspect ratio. Low-resistance bulk metal contact structures are required.

[0004] The current method involves first depositing a titanium nitride barrier or "liner" to conformally cover the dielectric sidewalls and the silicide underlayer of the contact holes or "vias" of the dielectric layer, thereby forming source or drain contacts within the contact holes. The vias are then filled conformally (non-selectively) using conventional chemical vapor deposition, such as with tungsten. The titanium nitride liner is undesirable as part of the contact structure because titanium nitride is a high-resistivity metal. Furthermore, conventional chemical vapor deposition for forming bulk tungsten contacts involves conformal deposition, which can create seams or voids within the contacts that increase their resistivity. The presence of the titanium nitride liner on the dielectric sidewalls prevents the selective growth of tungsten from the bottom of the contact hole opening during a bottom-up filling step, which would prevent seam formation. A method that allows for a bottom-up filling step of the conductive contacts is still needed. Summary of the Invention

[0005] For the back-side distribution network in the N2 node, metal contacts (e.g., tungsten or another conductive contact metal) are directly formed onto the source or drain region of the semiconductor layer through vias with a size of tens of nanometers via a bottom-up filling step, without the need for a liner coated on the sidewalls of the dielectric via.

[0006] The bottom-up filling step requires the selective deposition of a conductive "nucleation layer" or "seed layer" on the surface of the doped semiconductor region located at the bottom ("bottom surface") of the contact hole ("opening" or "via"). As described herein, the conductive nucleation layer is deposited with high selectivity on the surface of the doped semiconductor region relative to the surrounding dielectric sidewall surfaces. Low-resistance source or drain contact material ("conductive contacts") can then be selectively deposited using a bottom-up approach to fill the contact hole, creating a liner-free and seamless conductive contact within the via.

[0007] Selective bottom-up via filling requires the selective deposition of a conductive nucleation layer on the bottom surface of the contact via, i.e., without depositing (nucleating) a conductive nucleation layer on the dielectric sidewall surface. The method described involves selectively depositing a thin layer of cobalt or ruthenium as a "seed layer" or "nucleation layer" onto the bottom surface of the via. The cobalt or ruthenium layer will not be deposited on the dielectric sidewalls of the via and will only serve as a nucleation layer on the bottom surface of the via to enable selective, bottom-up deposition of contact metal to fill the via.

[0008] In one aspect, the present invention relates to a method for selectively depositing a conductive seed layer onto a substrate of a microelectronic device. The substrate comprises: a semiconductor layer including a doped semiconductor region having a doped semiconductor region surface comprising a doped semiconductor or a silicide; and a dielectric layer disposed on the semiconductor layer, the dielectric layer including an opening feature above the surface of the doped semiconductor region, the opening feature including a dielectric sidewall surface. The method comprises selectively depositing a conductive seed layer onto the surface of the doped semiconductor region, the conductive seed layer comprising cobalt or ruthenium.

[0009] In another aspect, the present invention relates to a semiconductor substrate comprising: a semiconductor layer including a doped semiconductor region, the doped semiconductor region including a surface of the doped semiconductor region; a dielectric layer disposed on the semiconductor layer, the dielectric layer including a three-dimensional opening feature above the doped semiconductor region, the opening feature including a bottom opening, an upper opening and dielectric sidewalls extending between the bottom opening and the upper opening positioned above the doped semiconductor region; and a conductive seed layer at the surface of the doped semiconductor region, the conductive seed layer comprising cobalt or ruthenium. Attached Figure Description

[0010] To aid in understanding this disclosure, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 This demonstrates a previous method for forming tungsten drain or source contacts through conformal, non-selective deposition of tungsten.

[0012] Figure 2 This demonstrates a method for forming tungsten drain or source contacts using a selective bottom-up filling step.

[0013] Figure 3 This demonstrates a method for forming tungsten drain or source contacts using a selective bottom-up filling step.

[0014] Figure 4 This demonstrates a method for forming drain or source contacts, including cobalt or ruthenium, using a selective bottom-up filling step.

[0015] Figure 5 The invention demonstrates an inventive method for forming drain or source contacts, including cobalt or ruthenium, using a selective bottom-up filling step.

[0016] While various modifications and alternatives are permissible with respect to this disclosure, details thereof have been shown by way of example in the drawings and will be described in detail. However, it should be understood that the invention is not intended to be limited to the described embodiments. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of this disclosure as defined by the appended claims. Detailed Implementation

[0017] Throughout this specification and claims, unless the context clearly indicates otherwise, the following terms shall have the meaning explicitly associated with this document. The phrases “in one embodiment,” “in an embodiment,” and “in some embodiments” as used herein do not necessarily refer to the same embodiment, although they may refer to the same embodiment. Furthermore, the phrases “in another embodiment” and “in some other embodiments” as used herein do not necessarily refer to different embodiments, although they may refer to different embodiments. All embodiments of this disclosure are intended to be combinable without departing from the scope or spirit of this disclosure.

[0018] As used herein, the term "based on" is not exclusive and may be based on additional factors not described, unless the context clearly indicates otherwise. Furthermore, throughout the specification, "a / an" and "the" include plural references. "In" includes both "in" and "on".

[0019] As used herein, the term "between" does not necessarily require immediate proximity to other components. Therefore, in any one or more embodiments disclosed herein, a particular structural component may be positioned between two other structural components in the following ways: directly between both other structural components such that the particular structural component is in direct contact with both other structural components; positioned immediately adjacent to only one of the two other structural components such that the particular structural component is in direct contact with only one of the two other structural components; indirectly positioned near only one of the two other structural components such that the particular structural component is not in direct contact with only one of the two other structural components, and there is another component positioned between the particular structural component and one of the two other structural components; indirectly positioned between both other structural components such that the particular structural component is not in direct contact with both other structural components, and other features may be positioned therebetween; or any combination thereof.

[0020] This invention relates to a semiconductor substrate comprising back-side contacts for power distribution in direct metal contact with source and drain regions, and a method for forming these contacts (“conductive contacts”). According to an example method, a cobalt or ruthenium seed layer is selectively deposited at the bottom of a contact hole onto the surface of a doped semiconductor region, without depositing the seed layer on the dielectric sidewalls; the seed layer deposited on the surface of the doped semiconductor region allows for the formation of conductive contacts within the contact hole using a selective bottom-up filling method to produce low-resistance conductive contacts for back-side contacts in BSPDN integration.

[0021] The source and drain contacts (“conductive contacts”) of a transistor are formed as bulk metal structures within a three-dimensional opening feature (“contact hole” or “via”) of the dielectric layer of a microelectronic device substrate. The substrate comprises a semiconductor layer having doped semiconductor regions and a dielectric layer adjacent to said semiconductor layer. The dielectric layer may be, for example, SiO2, SiN, doped polysilicon, undoped polysilicon, and other resistive silicon-containing material layers. The dielectric layer includes a three-dimensional opening feature (also referred to as a “contact hole” or “via”) positioned above the doped semiconductor regions of the semiconductor layer. Contact metal is deposited onto the substrate to fill the contact hole to form conductive contacts (e.g., source or drain contacts).

[0022] Using a conventional technique known as the "tungsten plugging process," pure tungsten is deposited onto a substrate to fill contact holes and form conductive contacts. Tungsten is frequently used due to the excellent conformability achieved by using tungsten hexafluoride (WF6) as a chemical precursor for chemical vapor deposition. The process requires the use of an adhesive or barrier layer ("liner"), which is first deposited onto the surface of the contact holes to position the tungsten between the dielectric layer and between the tungsten and the semiconductor layer (see [reference]). Figure 1The liner can be made of titanium or titanium nitride (TiN) and is used to protect the dielectric surface from fluorine corrosion and improve the adhesion of tungsten to the dielectric surface.

[0023] Figure 1 An example of this method is shown. The method begins with a semiconductor substrate 100, which includes a semiconductor layer (102), a doped semiconductor region (104) that is part of the semiconductor layer, a dielectric layer (106) (e.g., SiO2) disposed on the semiconductor layer (102), and a three-dimensional opening feature (110) (“contact hole”, “opening”, or “through hole”) formed in the dielectric layer. The three-dimensional opening feature 110 is located above the doped semiconductor region (104) and includes dielectric sidewalls 108.

[0024] Initially, in (i), the contact hole 110 is empty, and the surface of the sidewall 108 is the exposed surface of the dielectric material of the dielectric layer 106. The contact hole 110 can be used to deposit contact metal into the contact hole to form a conductive contact with a bulk deposited contact metal. According to the "silicide formation" step (ii), a silicide layer 120 is formed at the surface of the doped semiconductor region 104, i.e., at the bottom surface of the opening 110. Subsequently, (iii), a conformal deposition liner (e.g., titanium (Ti) and / or titanium nitride (TiN)) 122 is deposited to cover the silicide layer 120 and the dielectric surface of the sidewall 108. The titanium and titanium nitride layers 122 are formed using a conformal, non-selective deposition technique and thus cover both the silicide layer 120 and the dielectric sidewall 108. In some instances, the silicide layer (120) is formed after the deposition liner.

[0025] In step (iv), a tungsten seed layer (124) is conformally deposited over the titanium nitride layer 122. A conductive contact 126 (e.g., bulk tungsten) is formed within the remaining internal space of the contact hole 110 using a subsequent non-selective "filling step" via conformal chemical vapor deposition. As illustrated, because the tungsten contact 126 is formed using conformal (non-selective) deposition, the tungsten contact 126 includes a central gap or "seam" 128, which undesirably reduces the conductivity of the tungsten contact 126. Also undesirable is that the liner (e.g., the titanium nitride layer) 122 has a thickness that consumes space within the contact hole 110, reduces the size of the tungsten contact 126, and further reduces the conductivity of the tungsten contact 126.

[0026] In a subsequent step (not shown), prior to further processing, a layer of material deposited on the upper surface of the dielectric layer 106 and above the contact hole 108, such as the liner material 122 and the tungsten seed layer 124, is removed by a chemical mechanical planarization (also known as chemical mechanical polishing or chemical mechanical polishing) (CMP) step.

[0027] It can perform novel methods as described in this paper to avoid using such Figure 1 The conformal (non-selective) filling step shown here forms an undesirable effect of the aforementioned steps in forming conductive contacts. This method advantageously allows for a "bottom-up" conductive contact filling step by first selectively depositing a "conductive seed layer" as a nucleation layer at the bottom of the opening 110 (e.g., on the surface of the doped semiconductor region 104).

[0028] A conductive seed layer of cobalt or ruthenium can be selectively deposited onto the surface of a doped semiconductor region, such as the surface of the doped semiconductor region or a silicide surface formed on the surface of the doped semiconductor region. The conductive seed layer allows for the selective deposition of contact metal onto the substrate to fill the opening 110 and the formation of conductive contacts through a bottom-up filling step.

[0029] The conductive seed layer is cobalt or ruthenium, which can be selectively deposited onto the surface of the doped semiconductor region. When the conductive seed layer is located at the bottom of the contact hole, subsequent steps can be performed to selectively deposit contact metal only on the conductive seed layer, without depositing contact metal on the dielectric sidewall surfaces; thus, the deposited contact metal accumulates and builds up thickness within the contact hole (filling the contact hole) in a "bottom-up" manner, without accumulating or building up thickness from the side surfaces.

[0030] The semiconductor layer may be a semiconductor material such as silicon, germanium, or silicon-germanium, and has doped regions such as silicon-doped, germanium-doped, or silicon-germanium-doped regions. The doped regions may be "heavily doped," meaning they contain at least 1 x 10⁻⁶ doped regions. 20 at / cm 3 Dopant silicon, germanium, or silicon-germanium.

[0031] The conductive seed layer can be made of cobalt or ruthenium, preferably of high purity.

[0032] A conductive seed layer is selectively deposited onto the surface of a doped semiconductor region of a semiconductor layer. In different versions of the described method, the surface of the doped semiconductor region may be the surface of a doped semiconductor region (e.g., doped silicon, doped germanium, or doped silicon-germanium), or it may be the surface of a silicide layer formed on the doped semiconductor region. According to an example of the former, the conductive seed layer may be selectively deposited directly onto the surface of the doped semiconductor region (e.g., a heavily doped semiconductor region). According to an example of the latter, the surface of the doped semiconductor region may be chemically treated to form a silicide (e.g., WSi2, TaSi2, CrSi2, MoSi2), and the conductive seed layer may be selectively deposited onto the surface of the silicide.

[0033] The contact metal selectively deposited onto the conductive seed layer can be any metal (including alloys) that can be used as a conductive contact and can be selectively deposited as described, such as tungsten, cobalt, ruthenium, copper, rhodium, palladium, nickel, iridium, or combinations thereof.

[0034] According to the example method, a conductive seed layer of ruthenium or cobalt is first selectively deposited onto the surface of a doped semiconductor region, which may be the surface of the doped semiconductor region or the surface of a silicate formed on the doped semiconductor region. After the conductive seed layer is formed, additional contact metal is deposited into the opening, continuously accumulating within the opening in a bottom-up manner without depositing onto the dielectric sidewalls; that is, the bottom-up deposition technique is selective in that it deposits conductive material at the bottom surface of the opening relative to the dielectric sidewalls.

[0035] Advantageously, bottom-up deposition techniques avoid the need for adhesive layers or barriers (“liners”) covering the dielectric sidewall surfaces or the bottom surface of the three-dimensional opening features. The resulting bulk metallic conductive structure (e.g., a conductive contact) deposited into the three-dimensional opening completely fills the opening. Eliminating the need for adhesive or barrier layers and reserving more space for contact metal within the opening advantageously increases the conductivity of the conductive contact. Furthermore, bottom-up deposition techniques do not result in the formation of gaps or “seams” within the conductive contact that would reduce its conductivity.

[0036] While the method does not require and can specifically eliminate the need for a liner, adhesive layer, or barrier layer conformally deposited onto the dielectric sidewalls, the described method allows the dielectric sidewalls to be treated without forming this additive material layer. For example, the dielectric sidewall surface can be modified at the atomic level to enhance the ability to perform the bottom-up filling step of the conductive contacts, i.e., avoiding conformal deposition of the conductive contacts. Modifying the dielectric surface in this way does not add a layer or coating of liner material to the dielectric surface and does not significantly reduce the volume of the contact hole prior to the step of filling the contact hole with the contact metal.

[0037] Figure 2 An example method is illustrated. The method begins with a semiconductor substrate 100, which includes a semiconductor layer (102), a doped semiconductor region (104) that is part of the semiconductor layer, a dielectric layer (106), and a three-dimensional opening feature (110) formed in the dielectric layer. The three-dimensional opening feature 110 is positioned above the doped semiconductor region 104 and includes dielectric sidewalls 108.

[0038] Initially, in (i), the contact hole 110 is empty, and the surface of the sidewall 108 is formed by the exposed dielectric material of the dielectric layer 106. In the "silicide formation" step (ii), a silicide layer 120 is formed at the surface of the doped semiconductor region 104. Subsequently, (iii), a conductive seed layer 130 made of a seed layer metal 130 containing cobalt or ruthenium is selectively deposited onto the surface of the silicide layer, meaning that the seed layer 130 is deposited onto the surface of the silicide 120 and not onto the surface of the sidewall 108.

[0039] In step (iv) (contact metal (e.g., tungsten) filling step), conductive tungsten contacts 132 are formed, for example, by chemical vapor deposition of tungsten. The tungsten contacts 132 are formed by selectively, non-conformal, bottom-up filling of the contact hole 110 with the deposition of a conductive metal (e.g., tungsten), and therefore do not include a central gap or “seam” that would undesirably reduce the conductivity of the tungsten contacts 132. Furthermore, the tungsten contacts 132 advantageously fill the entire space of the contact hole 110 without any adhesive or barrier layer or “liner” included between the sidewall 108 of the dielectric layer 106 and the tungsten contacts 132 that would reduce the size and conductivity of the tungsten contacts 132.

[0040] exist Figure 3 In an alternative example, conductive contact 130 may be deposited directly onto the surface of doped semiconductor region 104 without first forming silicide on the surface of doped semiconductor region 104. As illustrated, in (i), contact hole 110 is initially empty, and the surface of doped semiconductor region 104 is exposed at the bottom of contact hole 110. In step (ii), a conductive seed layer 130 of cobalt or ruthenium is selectively deposited onto the surface of doped semiconductor region 104; this means that seed layer 130 is deposited directly onto the surface of doped semiconductor region 104 and not onto the surface of sidewall 108. In step (iii), conductive contact 132 is formed using a bottom-up deposition technique. Conductive contact 132 formed using a bottom-up technique (e.g., tungsten) does not contain a central gap or "seam" that would undesirably reduce the conductivity of conductive contact 132. The conductive contact 132 fills the entire space of the opening 110, while there is no adhesive or barrier layer or "liner" between the sidewalls 108 of the dielectric layer 106.

[0041] The method described can be used to form conductive contacts from tungsten, such as Figure 2 and 3 This demonstrates that it can also be used to form conductive contacts from another contact metal, such as contact metals comprising ruthenium, cobalt, copper, or similar materials or combinations thereof. An example method is... Figure 4 Place, Figure 4 The display is similar to Figure 2 Steps (i), (ii), and (iii) are described. Figure 2 Step (iv) is different, in Figure 4 In step (iv), the conductive contact 132 is formed, for example, by a bottom-up chemical vapor deposition step, from a contact metal different from tungsten (e.g., cobalt, ruthenium, or a combination thereof).

[0042] Figure 5Another example method is shown in which, in step (ii), a conductive seed layer 130 of cobalt or ruthenium is selectively deposited directly onto the surface of the doped semiconductor region 104. This means that the conductive seed layer 130 is selectively deposited directly onto the surface of the doped semiconductor region 104 and not onto the surface of the sidewall 108. In step (iii), conductive contacts 132 are formed from a contact metal, such as cobalt, ruthenium, or a combination thereof, through a bottom-up deposition step.

[0043] According to an example method using cobalt or ruthenium as a conductive seed layer and subsequently forming conductive contacts from cobalt or ruthenium, the method advantageously allows for the use of the same metal for both the conductive seed layer and the contact metal for forming the conductive contacts. For example, as... Figure 4 and 5 Note that both the conductive seed layer 130 and the conductive contact 132 can be made of cobalt, or both can be made of ruthenium. Using the same metal (cobalt or ruthenium) for both the conductive seed layer and the conductive contact allows both of these structures to be deposited from a single chemical precursor and during a single deposition step.

[0044] An additional advantage of using cobalt or ruthenium instead of tungsten for conductive contacts is that these contact metals eliminate the chemical mechanical planarization (CMP) step required when depositing tungsten as the contact metal to form tungsten contacts. Conventional processes using tungsten deposit tungsten in both the field area and the contact / via area, thus requiring a CMP process.

[0045] The described method involves depositing cobalt or ruthenium as a conductive seed layer onto the surface of a doped semiconductor region, for example, directly onto the surface of the doped semiconductor region or onto a silicide formed on the doped semiconductor region. The method of depositing the conductive seed layer is selective, meaning that the conductive seed layer is deposited onto the bottom surface instead of onto the dielectric sidewall surface of the contact hole.

[0046] The step of selectively depositing ruthenium or cobalt onto the surface of a doped semiconductor region can be performed by any useful deposition technique, such as atomic layer deposition (e.g., PEALD, plasma-enhanced atomic layer deposition), chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition), etc.

[0047] The methods and precursors for selectively depositing ruthenium or cobalt onto a substrate as described in U.S. Patent Publications 2020 / 0157680, 2022 / 0267895, and 2023 / 0245894, the entire contents of which are incorporated herein by reference. Examples of precursors for selectively depositing cobalt or ruthenium include p-cymene-1,3-cyclohexadiene ruthenium (CAS No. 500591-28-6) and bis(N,N'-di-tert-butyl-1,4-diaza-1,3-butadienyl)cobalt (CAS No. 177099-51-3) (C 20 H42 C o N4).

[0048] Those skilled in the art will understand that the scope of this disclosure covers all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments described or illustrated herein. The scope of this disclosure is not limited to the exemplary embodiments described or illustrated herein. Furthermore, those skilled in the art will understand that although this disclosure describes and illustrates the corresponding embodiments herein as including specific components, elements, features, functions, operations, or steps, any of these embodiments may include any combination or substitution of any of the components, elements, features, functions, operations, or steps described or illustrated anywhere herein. Moreover, references in the appended claims to an apparatus or system or a component of an apparatus or system adapted, arranged, capable, configured, enabled, operable, or operated to perform a particular function cover said apparatus, system, or component, whether or not said apparatus, system, component, or the particular function is activated, turned on, or unlocked, provided that said apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operated. Furthermore, although this disclosure describes or illustrates specific embodiments to provide particular advantages, specific embodiments may not provide these advantages, provide some of these advantages, or provide all of them.

Claims

1. A method for selectively depositing a conductive seed layer onto a substrate of a microelectronic device, the substrate comprising: A semiconductor layer comprising a doped semiconductor region having a doped semiconductor region surface comprising a doped semiconductor or a silicide. A dielectric layer disposed on the semiconductor layer, the dielectric layer including an opening feature above the surface of the doped semiconductor region, the opening feature including dielectric sidewall surfaces. The method includes: A conductive seed layer, comprising cobalt or ruthenium, is selectively deposited onto the surface of the doped semiconductor region.

2. The method of claim 1, wherein the conductive seed layer is selectively deposited on the surface of the doped semiconductor region, but not on the surface of the dielectric sidewall.

3. The method according to claim 1, wherein the doped semiconductor region comprises doped silicon, doped germanium, or doped silicon-germanium.

4. The method of claim 1, further comprising selectively depositing contact metal onto the conductive seed layer to form the conductive contact within the opening by bottom-up growth of the conductive contact.

5. The method of claim 1, wherein the surface of the doped semiconductor region comprises heavily doped silicon, heavily doped germanium, or heavily doped silicon-germanium, and the method comprises selectively depositing the conductive seed layer directly onto the doped heavily doped silicon, heavily doped germanium, or heavily doped silicon-germanium.

6. The method of claim 5, wherein the heavily doped silicon, heavily doped germanium, or heavily doped silicon-germanium contains at least 1 x 10⁻⁶ ppm. 20 at / cm 3 Dopant.

7. The method of any claim 1, wherein the surface of the doped semiconductor region comprises a silicide surface formed on the doped semiconductor region, the method comprising: The silicide surface is formed on the doped semiconductor region, and The conductive seed layer is selectively deposited on the silicide surface.

8. The method of claim 1, wherein the dielectric sidewall surface comprises a dielectric silicon material.

9. The method of claim 4, wherein the conductive contact directly contacts the dielectric sidewall surface.

10. The method of claim 4, wherein the conductive contact is tungsten and does not contain a seam formed by conformal deposition of the tungsten.

11. A semiconductor substrate comprising: A semiconductor layer comprising a doped semiconductor region, wherein the doped semiconductor region includes a surface of the doped semiconductor region. A dielectric layer disposed on the semiconductor layer, the dielectric layer including a three-dimensional opening feature above the doped semiconductor region, the opening feature including a bottom opening positioned above the doped semiconductor region, a top opening, and dielectric sidewalls extending between the bottom opening and the top opening, and A conductive seed layer is located on the surface of the doped semiconductor region, and the conductive seed layer comprises cobalt or ruthenium.

12. The semiconductor substrate of claim 11, further comprising conductive contacts that fill the opening feature between the conductive seed layer and the upper opening and contact the dielectric sidewall.

13. The semiconductor substrate of claim 11, wherein the surface of the doped semiconductor region comprises heavily doped silicon, heavily doped germanium, or heavily doped silicon-germanium, and the conductive seed layer contacts the heavily doped silicon, heavily doped germanium, or heavily doped silicon-germanium.

14. The semiconductor substrate of claim 11, wherein the surface of the doped semiconductor region comprises silicide.

15. The semiconductor substrate of claim 11, wherein the conductive contact directly contacts the dielectric sidewall surface.

16. The semiconductor substrate of claim 11, wherein the conductive contact is a source contact or a drain contact.

17. The semiconductor substrate of claim 11, wherein the conductive contact comprises a metal selected from tungsten, cobalt, ruthenium, copper, rhodium, palladium, nickel, and iridium.

18. The semiconductor substrate of claim 11, wherein the conductive contact is tungsten, and the conductive contact does not contain a seam formed by conformal deposition of the tungsten.

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