Display panel and display device

Abstract

A display panel and a display device, the display panel comprising: an array substrate (1) and a counter substrate (2) disposed opposite to each other; a common electrode (22) located on the counter substrate (2); a first adapter structure (Z1) located on a bonding area (BB1); at least one bonding terminal group (D1) located on the bonding area (BB1) of the array substrate (1); at least one first common trace (12) located on the bonding area (BB1) of the array substrate (1), one end of the first common trace (12) being electrically connected to the bonding terminal group (D1), and the other end extending along the extension direction of the bonding area (BB1) and toward a connection area (BB3), and being electrically connected to the common electrode (22) in the bonding area (BB1) via the first adapter structure (Z1).

Description

Display panel and display device Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Vertically aligned (VA) liquid crystal display panels, also known as vertical alignment technology display panels, determine the deflection of liquid crystals within a pixel by the voltage difference between the pixel electrode on the array substrate side and the common electrode on the color filter substrate side. The signal of the common electrode on the color filter substrate side is provided by the driving circuit board, passes through the flexible circuit board to the common trace on the array substrate side, and is then transmitted to the common electrode on the color filter substrate side through the gold balls in the encapsulation. Summary of the Invention

[0003] This disclosure provides a display panel and a display device. The display panel has a display area and a peripheral area surrounding the display area; the peripheral area includes: a bonding area, a bonding opposite area, and a connecting area; the bonding opposite area is disposed opposite to the bonding area, and the connecting area connects the bonding area and the bonding opposite area; wherein, the display panel includes:

[0004] Array substrates and opposing substrates arranged opposite each other;

[0005] The common electrode is located on the opposing substrate;

[0006] A first adapter structure is located in the binding area;

[0007] At least one bonding terminal group is located in the bonding area of ​​the array substrate;

[0008] At least one first common trace is located in the bonding area of ​​the array substrate. One end of the first common trace is electrically connected to the bonding terminal group, and the other end extends along the bonding area and toward the connection area, and is electrically connected to the common electrode in the bonding area through the first adapter structure.

[0009] In one possible implementation, the bonding area includes an end area connected to the connection area, the other end of the first common trace extending to the end area and electrically connected to the common electrode in the end area via the first adapter structure.

[0010] In one possible implementation, the display panel further includes: a sealing adhesive; the sealing adhesive is located between the array substrate and the opposing substrate; the sealing adhesive includes: a conductive portion;

[0011] The array substrate further includes: a substrate, an insulating layer located on the side of the first common trace away from the substrate, and at least one first transition electrode located on the side of the insulating layer away from the first common trace; the insulating layer includes: a plurality of first vias; the first transition electrode is located in the bonding region, and the first transition electrode is electrically connected to the first common trace through the first vias;

[0012] The first adapter structure includes: the conductive part and the first adapter electrode; the first common trace passes through the first adapter electrode and is electrically connected to the common electrode via the conductive part.

[0013] In one possible implementation, the display panel includes: at least one first transition electrode group; the first transition electrode group is located in the end region;

[0014] The first adapter electrode group includes: a plurality of first adapter electrodes arranged along a first direction and spaced apart from each other.

[0015] In one possible implementation, the sealing adhesive has a first outer edge and a second outer edge in the bonding area;

[0016] The orthographic projection of the sealing adhesive onto the substrate covers the orthographic projection of the first adapter electrode onto the substrate, and the minimum distance between the first adapter electrode and the first outer edge is equal to the minimum distance between the first adapter electrode and the second outer edge.

[0017] In one possible implementation, the plurality of first vias includes: a plurality of first sub-via rows; the plurality of first sub-via rows extend along a first direction and are arranged along a second direction;

[0018] The first sub-via row includes: a plurality of first sub-vias arranged along the first direction and spaced apart from each other; the first sub-vias in adjacent first sub-via rows are arranged alternately.

[0019] In one possible implementation, the plurality of first vias includes: a plurality of second sub-via rows; the plurality of second sub-via rows extend along a first direction and are arranged along a second direction;

[0020] The second sub-via row includes: a plurality of second sub-vias arranged along the first direction and spaced apart from each other; the length of the first sub-via in the first direction is greater than the length of the second sub-via in the first direction;

[0021] The first sub-via row and the second sub-via row are arranged alternately along the second direction.

[0022] In one possible implementation, the display panel includes: at least one second common trace and a second adapter structure; one end of the second common trace is connected to a portion of the bonding terminal group, and the other end extends through the bonding area portion, the connection area, the bonding opposite side area, the connection area, to another portion of the bonding area, and is connected to another portion of the bonding terminal group; the second adapter structure is located in the connection area and the bonding opposite side area; the second common trace is electrically connected to the common electrode through the second adapter structure;

[0023] The first common trace is located on the side of the second common trace facing the display area.

[0024] In one possible implementation, the orthographic projection of the first adapter electrode onto the substrate overlaps with the orthographic projection of the first common trace onto the substrate, and also overlaps with the orthographic projection of the second common trace onto the substrate.

[0025] The orthographic projection of the first via on the substrate overlaps only with the orthographic projection of the first common trace on the substrate.

[0026] In one possible implementation, the first common trace and the second common trace are in the same layer and made of the same material;

[0027] The array substrate includes: a plurality of second transition electrodes located on the side of the insulating layer opposite to the second common trace; the insulating layer includes: a plurality of second vias; the second transition electrodes are electrically connected to the second common trace through the second vias;

[0028] The second adapter structure includes: the conductive part and the second adapter electrode.

[0029] In one possible implementation, the plurality of second transition electrodes includes: a second transition electrode group and a third transition electrode group; the third transition electrode group is located on the side of the second transition electrode group facing the display area; both the second transition electrode group and the third transition electrode group include: a plurality of second transition electrodes surrounding the periphery of the display area;

[0030] The second transfer electrode of the third transfer electrode group is located in the gap between two adjacent second transfer electrodes of the second transfer electrode group, and both ends of the second transfer electrode of the third transfer electrode group are respectively electrically connected to the ends of two adjacent second transfer electrodes in the second transfer electrode group.

[0031] In one possible implementation, the array substrate includes: at least one third common trace;

[0032] One end of the third common trace is connected to the bonding terminal group, and the other end passes through part of the bonding area, the connection area, and extends to the bonding opposite side area, where it is electrically connected to the second common trace.

[0033] In one possible implementation, the insulating layer includes: a plurality of third vias;

[0034] The second transfer electrode group includes: a plurality of first sub-transfer electrodes and at least one second sub-transfer electrode; in the direction from the peripheral area to the display area, the width of the second sub-transfer electrode is greater than the width of the first sub-transfer electrode;

[0035] The orthographic projection of the second sub-transfer electrode on the substrate overlaps with the orthographic projection of the portion of the third common trace located in the bonding opposite region on the substrate, and is electrically connected through the third via at the overlapping position.

[0036] In one possible implementation, the array substrate further includes: a connection group; the connection group includes: a plurality of connection portions;

[0037] The connecting part is in the same layer and made of the same material as the second common routing line and the third common routing line; one end of the connecting part is connected to the second common routing line and the other end is connected to the third common routing line.

[0038] In one possible implementation, the orthographic projection of the second sub-transfer electrode onto the substrate covers the orthographic projection of the connection assembly onto the substrate.

[0039] In one possible implementation, the insulating layer further includes: at least one first trench; the first trench is located in the connection region and the bonding opposite region;

[0040] The orthographic projection of the connecting portion onto the substrate overlaps with the portion of the orthographic projection of the first trench onto the substrate.

[0041] In one possible implementation, the array substrate further includes: a fourth common trace group; the fourth common trace group is located on the side of the first common trace facing the display area;

[0042] The fourth common wiring group includes: at least one fourth common wiring; one end of the fourth common wiring is connected to the binding terminal group, and the other end passes through the binding area and extends at least to the connection area.

[0043] In one possible implementation, the other end of the fourth common trace, away from the bonding terminal group, is connected to the second common trace.

[0044] In one possible implementation, the display panel further includes: a fourth adapter structure; the other end of the fourth common trace away from the bonding terminal group is connected to the common electrode via the fourth adapter structure.

[0045] In one possible implementation, the fourth common routing group includes: a first sub-routing; one end of the first sub-routing is connected to the bonding terminal group, and the other end passes through the bonding area and extends to the central area of ​​the connection area in the second direction.

[0046] In one possible implementation, the fourth common routing group includes: a second sub-routing; one end of the second sub-routing is connected to the bonding terminal group, and the other end passes through the bonding area and extends to the end of the connection area near the bonding opposite side area.

[0047] In one possible implementation, the fourth common routing group includes: a third sub-routing; one end of the third sub-routing is connected to the bonding terminal group, and the other end passes through the bonding area, the connection area, and extends to the area of ​​the bonding opposite side area in the first direction from five-sixteenths to seven-sixteenths of the end of the bonding opposite side area.

[0048] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes the display panel as described in embodiments of this disclosure. Attached Figure Description

[0049] Figure 1 is a microscopic image of alternating bright and dark pixels;

[0050] Figure 2A is one of the top views of the display panel provided in the embodiments of this disclosure;

[0051] Figure 2B is a schematic diagram of the binding area, the binding opposite area, and the connection area;

[0052] Figure 3 is one of the cross-sectional schematic diagrams of the display panel provided in the embodiments of this disclosure;

[0053] Figure 4 is an enlarged schematic diagram of Figure 2A at the dashed frame S1;

[0054] Figure 5 is an enlarged schematic diagram of Figure 2A at the dashed frame S2;

[0055] Figure 6A is an enlarged schematic diagram of Figure 4 at point S11 within the dashed line frame;

[0056] Figure 6B is a schematic diagram of the membrane layer where the first common trace in Figure 6A is located;

[0057] Figure 6C is a schematic diagram of the film layer where the first transfer electrode in Figure 6A is located;

[0058] Figure 6D is a schematic diagram of the multiple first vias in Figure 6A;

[0059] Figure 7 is an enlarged view of the dashed frame S3 in Figure 2A;

[0060] Figure 8A is an enlarged view of the dashed frame S4 ​​in Figure 2A;

[0061] Figure 8B is a schematic diagram of the second transfer electrode 131 in Figure 8A;

[0062] Figure 9 is an enlarged view of the dashed frame S5 in Figure 2A;

[0063] Figure 10A is an enlarged schematic diagram of Figure 9 within the dashed box S41;

[0064] Figure 10B is a schematic diagram of the membrane layer where the second common trace 13 in Figure 10A is located;

[0065] Figure 10C is a schematic diagram of the second via in Figure 10A;

[0066] Figure 11A is a second top view of the display panel provided in an embodiment of this disclosure;

[0067] Figure 11B is a third top view of the display panel provided in an embodiment of this disclosure;

[0068] Figure 12A is a top view of the display panel provided in an embodiment of this disclosure;

[0069] Figure 12B is a top view of the fifth embodiment of the display panel provided in this disclosure;

[0070] Figure 13A is a top view of the sixth embodiment of the display panel provided in this disclosure;

[0071] Figure 13B is a top view of the display panel provided in an embodiment of this disclosure. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0073] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0074] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0075] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0076] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0077] The stability of the common signal on the color filter substrate side is crucial for the display of VA LCD panels. Lateral crosstalk (H-Crosstalk) is one of the image quality evaluation standards. In certain scenes, data signals in some areas of a VA LCD panel may couple with the common signal, causing a common offset, as shown in Figure 1. Black represents dark pixels, and R, G, and B colors represent bright pixels. Within the dashed box, the polarity of the sub-pixels alternates between positive and negative. In the bright sub-pixels, the number of positive polarities exceeds the number of negative polarities. The common signal is pulled by the positive polarities more often than the negative polarities, causing a positive offset in the common signal. This results in a voltage difference between the dark pixel voltage and the common voltage, increasing the brightness of the originally dark pixels, thus exhibiting the H-Crosstalk phenomenon. This phenomenon may appear around tables (such as Excel tables) and text, and is particularly severe in large-size and high-refresh-rate products, affecting the user's viewing experience.

[0078] In view of the above, this disclosure provides a display panel, as shown in Figures 2A, 2B, 3, 4, 5, and 6A-6D. Figure 2A is a top view of the display panel provided in this disclosure; Figure 2B is a schematic diagram of the bonding area, the bonding opposite side area, and the connection area; Figure 3 is one of the cross-sectional schematic diagrams of the display panel provided in this disclosure; Figure 4 is an enlarged view of Figure 2A at the dashed frame S1; Figure 5 is an enlarged view of Figure 2A at the dashed frame S2; Figure 6A is an enlarged view of Figure 4 at the dashed frame S11; Figure 6B is a schematic diagram of the film layer of the first common trace in Figure 6A; Figure 6C is a schematic diagram of the film layer of the first transition electrode in Figure 6A; and Figure 6D is a schematic diagram of the plurality of first vias in Figure 6A. The display panel has a display area AA and a peripheral area BB located around the display area AA. The peripheral area BB includes: a binding area BB1, a binding opposite area BB2, and a connecting area BB3. The binding opposite area BB2 is positioned opposite to the binding area BB1, and the connecting area BB3 connects the binding area BB1 and the binding opposite area BB2. For example, as shown in Figures 2A and 2B, the display panel has two connecting areas BB3, one of which (e.g., the left connecting area) connects one end of the binding area BB1 (e.g., the left end) and one end of the binding opposite area BB2 (e.g., the left end), and the other connecting area BB3 (e.g., the right connecting area) connects the other end of the binding area BB2 (e.g., the right end) and the other end of the binding opposite area BB2 (e.g., the right end). The display panel includes:

[0079] Array substrate 1 and opposing substrate 2 are arranged opposite to each other;

[0080] Common electrode 22 is located on the opposing substrate 2;

[0081] The first adapter structure Z1 is located in the binding area BB1;

[0082] At least one bonding terminal group D1 is located in the bonding area BB1 of the array substrate 1; optionally, for example, as shown in FIG2A, the display panel may be provided with two bonding terminal groups D1; ​​each bonding terminal group D1 may include a plurality of bonding terminals arranged sequentially along the first direction X, some bonding terminals may be connected to the corresponding data line, and some bonding terminals may be connected to the common trace.

[0083] At least one first common trace 12 is located in the bonding area BB1 of the array substrate 1. One end of the first common trace 12 is electrically connected to the bonding terminal group D1, and the other end extends along the extension direction of the bonding area BB1 and toward the connection area BB3. It is electrically connected to the common electrode 22 in the bonding area BB1 through the first adapter structure Z1. Optionally, the other end of the first common trace 12 extends to the edge of the bonding area BB1 near the display area AA, and is electrically connected to the common electrode 22 at the edge through the first adapter structure Z1.

[0084] In this embodiment, the array substrate 1 has a first common trace 12 in the bonding area BB1. One end of the first common trace 12 is electrically connected to the bonding terminal group D1, and the other end extends along the extension direction of the bonding area BB1 and toward the connection area BB3. It is electrically connected to the common electrode 22 in the bonding area BB1 through the first adapter structure Z1. This can realize common voltage compensation for the area of ​​the display area AA near the bonding area BB1. Moreover, the first common trace 12 is electrically connected to the common electrode 22 through the first adapter structure Z1, which helps to make the common voltage of each area in the display area AA uniform, thereby improving the lateral crosstalk problem. In addition, the other end of the first common trace 12 extends to the edge of the bonding area BB1 near the display area AA, that is, the other end of the first common trace 12 extends along the extension direction of the bonding area BB1 and toward the connection area BB3, without turning to the position of overlapping with the connection area BB2 (which is usually where the gate driving circuit is located). This not only plays a compensation role, but also does not occupy an additional bezel, which is conducive to the narrow bezel of the display panel.

[0085] In the relevant display panel, the common signal between the array substrate and the opposing substrate is conducted through a conduction point. Conduction points are distributed in the connection area BB3 and the bonding opposite area BB2. The bonding area BB1 only has a conduction point between adjacent bonding terminal groups D1. The bonding area BB1 has no conduction points in its left and right end areas S1. This results in a difference in the common voltage between areas A and C in the display area AA, as shown in Figure 2B, and / or a difference in the common voltage between areas B and D, thus affecting the screen display. In this embodiment, by adding a common voltage conduction point to the bonding area BB1, and... The common voltage sampling point at the corner of the bonded area BB2 is removed and replaced with a common voltage compensation point at the corner of the bonded area BB1. The first common trace 12 is not connected to other common traces on the array substrate (e.g., the second common trace 13), but instead, a first adapter structure Z1 is provided. The common compensation signal is transmitted to the opposing substrate side through the first adapter structure Z1, which can ensure that the common voltage compensation of display area A and area C (and / or, area B and area D) is consistent, as well as the uniformity and stability of the common voltage on the opposing substrate side, thereby improving the H-Crosstalk phenomenon. In addition, the removal of the sampling point reduces the number of traces in the connection area BB3 (where the gate drive circuit can be set), saving space in the connection area BB3 (where the gate drive circuit can be set), which is suitable for narrow bezel products.

[0086] In one possible implementation, referring to Figures 2A, 2B, 3, 4, 5, and 6A-6D, the bonding area BB1 includes an end area S1 (for example, as shown in Figure 2A, the bonding area BB1 may include two end areas S1, namely a first sub-end area S101 and a second sub-end area S102). The end area S1 is connected to the connection area BB3. The other end of the first common trace 12 extends to the end area S1 and is electrically connected to the common electrode 22 in the end area S1 through a first transition structure Z1. In this embodiment, the other end of the first common trace 12 extends to the end area S1 and is electrically connected to the common electrode 22 in the end area S1 through the first transition structure Z1. Since the bonding area BB1 is usually also provided with multiple fan-shaped traces (as shown in Figure 2A, the black fan-shaped area connected to the bonding terminal group D1 can be provided with multiple fan-shaped traces), the first common trace 12 is connected to the common electrode 22 again at the end area S1 of the bonding area BB1, which can avoid the influence on the fan-shaped traces.

[0087] In one possible implementation, referring to Figures 2A, 2B, 3, 4, 5, and 6A-6D, the display panel further includes: a sealing adhesive 3; the sealing adhesive 3 is located between the array substrate 1 and the opposing substrate 2; the sealing adhesive 3 includes: a conductive portion 31; optionally, the sealing adhesive 3 may further include a matrix 30, and the conductive portion 31 may be mixed in the matrix 30; optionally, the conductive portion 31 may be conductive particles, for example, gold spheres;

[0088] The array substrate 1 further includes: a substrate 11, an insulating layer 19 located on the side of the first common trace 12 away from the substrate 11, and at least one first transition electrode 121 located on the side of the insulating layer 19 away from the first common trace 12; the insulating layer 19 includes: a plurality of first vias K1; the first transition electrode 121 is located in the bonding region BB1, and the first transition electrode 121 is electrically connected to the first common trace 12 through the first vias K1;

[0089] The first adapter structure Z1 includes a conductive part 31 and a first adapter electrode 121; the first common trace 12 is electrically connected to the common electrode 22 through the first adapter electrode 121 and the conductive part 31.

[0090] In one possible implementation, referring to Figures 4 and 5, the display panel includes: at least one first transition electrode group 121Z; the first transition electrode group 121Z includes a structure located in the end region S1; for example, the display panel includes two first transition electrode groups 121Z, one of which includes a structure located in one end region S1 (e.g., in the first sub-end region S101), and the other includes a structure located in the other end region S1 (e.g., in the second sub-end region S102); the first transition electrode group 121Z includes: a plurality of first transition electrodes 121 arranged along the first direction X and spaced apart from each other. Optionally, the first transition electrode group 121Z may be located in the end region S1 or at other locations in the bonding region BB1.

[0091] In this embodiment of the present disclosure, the display panel includes at least one first transition electrode group 121Z; the first transition electrode group 121Z includes a plurality of first transition electrodes 121 arranged along the first direction X and spaced apart from each other. Since the adhesion between the first transition electrodes 121 and the sealant 3 is lower than that between the insulating layer 19 and the sealant 3, by arranging the first transition electrodes 121 sequentially along the first direction X and spaced apart, it is possible to avoid large areas of the first transition electrodes 121 contacting the sealant 3, which may lead to a decrease in the sealing performance of the sealant 3 on the display panel.

[0092] In one possible implementation, the first direction X can be parallel to the direction of the pixel row in the display area AA; the second direction Y can be parallel to the direction of the pixel column in the display area AA.

[0093] In one possible implementation, referring to Figures 6A-6D, the sealing adhesive 3 has a first outer edge w1 and a second outer edge w2 in the bonding area BB1; the orthographic projection of the sealing adhesive 3 onto the substrate 11 covers the orthographic projection of the first transfer electrode 121 onto the substrate, and the minimum distance d1 between the first transfer electrode 121 and the first outer edge w1 is equal to the minimum distance d2 between the first transfer electrode 121 and the second outer edge w2 (with an error fluctuation of up to 8%). That is, the orthographic projection of the first adapter electrode 121 onto the substrate 11 is located in the central region of the encapsulating adhesive 3 along the second direction Y on the orthographic projection of the substrate 11. This ensures that even with process errors, the encapsulating adhesive 3 can completely cover the first adapter electrode 121, achieving conduction with the common electrode 22 of the opposing substrate 2. Optionally, as shown in Figures 4 and 6A, the end of the first adapter electrode 121 furthest from the bonding terminal group in the bonding area BB1 (as shown in the leftmost first adapter electrode 121 in Figure 4, or the rightmost first adapter electrode 121 in Figure 5) is located in the bending area of ​​the encapsulating adhesive 3. That is, the end of the first adapter electrode 121 furthest from the bonding terminal group terminates approximately at the point where the encapsulating adhesive 3 begins to bend.

[0094] In one possible implementation, referring to FIG6D, the plurality of first vias K1 include: at least one first sub-via row K110; the at least one first sub-via row K110 extends along a first direction X and is arranged along a second direction Y; the first sub-via row K110 includes: a plurality of first sub-vias K111 arranged along the first direction X and spaced apart from each other; optionally, the first sub-vias K111 can be elongated vias; optionally, the length c1 of the first sub-vias K111 in the first direction X can be one-sixth to one-half of the length of the first adapter electrode 121 in the first direction X; when a plurality of first sub-via rows K110 are provided, the first sub-vias K111 of adjacent first sub-via rows K110 are arranged alternately; that is, a first straight line j1 extending along the second direction Y and passing through the gap between two adjacent first sub-vias K1 in one of the first sub-via rows K110 passes through the central region of the first sub-vias K1 in another adjacent first sub-via row K110. In this embodiment, the first sub-vias K111 of adjacent first sub-via rows K110 are arranged alternately, which can better block the intrusion of external moisture and improve the sealing performance of the display panel.

[0095] In one possible implementation, referring to FIG6D, the plurality of first vias K1 include: at least one second sub-via row K120; the at least one second sub-via row K120 extends along a first direction X and is arranged along a second direction Y; the second sub-via row K120 includes: a plurality of second sub-vias K121 arranged along the first direction X and spaced apart from each other; the length c1 of the first sub-via K111 in the first direction X is greater than the length c2 of the second sub-via K121 in the first direction X, that is, the first sub-via K111 can be an elongated hole; optionally, the second sub-via K121 can be a square hole, a round hole, etc.; optionally, the length c2 of the second sub-via K121 in the first direction X can be less than the distance c3 between two adjacent first sub-vias K111 in the first direction X; the first sub-via row K110 and the second sub-via row K120 are arranged alternately along the second direction Y. Optionally, the first straight line j1 passes through the central region of the second sub-via K121 of the second sub-via row K120. That is, the second sub-via K121 can be located in the region corresponding to the gap between the two first sub-vias K111.

[0096] In one possible implementation, referring to Figures 2A, 7, 8A-8B, 9, and 10A-10C, wherein Figure 7 is an enlarged view of the dashed frame S3 in Figure 2A, Figure 8A is an enlarged view of the dashed frame S4 ​​in Figure 2A, Figure 8B is a schematic diagram of the second transition electrode 131 in Figure 8A, Figure 9 is an enlarged view of the dashed frame S5 in Figure 2A, Figure 10A is an enlarged view of Figure 9 at the dashed frame S41, Figure 10B is a schematic diagram of the film layer where the second common trace 13 in Figure 10A is located, and Figure 10C is a schematic diagram of the second via in Figure 10A; the display panel includes: at least one second common trace 13, and The second adapter structure Q1; one end of the second common trace 13 is partially connected to the bonding terminal group D1, and the other end extends through the bonding area BB1, the connection area BB3, the bonding opposite area BB2, the connection area BB3, to another part of the bonding area BB1, and connects to another part of the bonding terminal group D1; that is, the second common trace 13 forms a semi-closed structure surrounding the display area AA and having an opening in the bonding area BB1; the second adapter structure Q1 is located in the connection area BB3 and the bonding opposite area BB2; the second common trace 13 is electrically connected to the common electrode 22 through the second adapter structure Q1; the first common trace 12 is located on the side of the second common trace 13 facing the display area AA. Optionally, since the first common trace 12 is only located in the bonding area BB1, that is, as shown in FIG2A or FIG6A, the first common trace 12 is located on the side of the second common trace 13 located in the bonding area BB1 facing the display area AA.

[0097] In this embodiment of the present disclosure, the display panel further includes at least one second common trace 13. The second common trace 13 is electrically connected to the common electrode 22 in the connection area BB3 and the bonding opposite area BB2 through the second adapter structure Q1. This enables the common signal of the array substrate 1 to be provided to the common electrode 22 of the opposing substrate 2, and makes the display area AA have a relatively uniform common voltage in each area near the connection area BB3 and the bonding opposite area BB2.

[0098] In one possible implementation, referring to FIG6A, the orthographic projection of the first adapter electrode 121 on the substrate 11 overlaps with the orthographic projection of the first common trace 12 on the substrate 11 and with the orthographic projection of the second common trace 13 on the substrate; the orthographic projection of the first via K1 on the substrate 11 overlaps only with the orthographic projection of the first common trace 12 on the substrate 11. In this embodiment, the orthographic projection of the first adapter electrode 121 on the substrate 11 not only covers part of the first common trace 12 to be connected with the first common trace 12, but also overlaps with the second common trace 13 to increase the area of ​​the first adapter electrode 121, thereby increasing the contact area between the first adapter electrode 121 and the conductive part 31, so that the signal of the first common trace 12 can be connected to the opposing substrate 2. However, the orthographic projection of the first via K1 on the substrate 11 only overlaps with the orthographic projection of the first common trace 12 on the substrate 11. That is, the first via K1 is only connected to the first common trace 12 so that the signal of the first common trace 12 can be directly provided to the common electrode 22 of the opposing substrate 2.

[0099] In one possible implementation, referring to Figures 6A and 6B, the array substrate may include: at least one first signal line 16, at least one second signal line 17, and at least one third signal line 18; wherein, the first signal line 16 may be located on the side of the first common trace 12 facing the display area AA, the second signal line 17 may be located on the side of the first signal line 16 facing the display area AA, and the third signal line 18 may be located on the side of the first common trace 12 away from the display area AA; the first signal line 16 may be a trace providing a common signal to the array substrate side; the second signal line... 17 can be a signal line connected to the gate drive circuit GOA, for example, it can be the frame start signal line 171 (STV) and / or the low level signal line 172 (VGL); the third signal line 18 can be a ground line; as shown in FIG4 and FIG6A, in the bonding area BB1, the end of the first common trace 12 away from the bonding terminal group is located at the bend of the first signal line 16 and / or the second signal line 17, that is, the end of the first common trace 12 away from the bonding terminal group terminates at the beginning of the bend of the first signal line 16 and / or the second signal line 17.

[0100] In one possible implementation, referring to Figures 6A and 6B, the first common trace 12 and the second common trace 13 are on the same layer and made of the same material; referring to Figures 7, 8A-8B, 9, and 10A-10C, the array substrate includes: a plurality of second transition electrodes 131 located on the side of the insulating layer 19 opposite to the second common trace 13; the second transition electrodes 131 may be on the same layer and made of the same material as the first transition electrode 121; the insulating layer 19 includes: a plurality of second vias K2; the second transition electrodes 131 are electrically connected to the second common trace 13 through the second vias K2; the second transition structure Q1 includes: a conductive part 31 and the second transition electrodes 131.

[0101] In one possible implementation, referring to Figures 10A and 10C, the plurality of second vias K2 may include: a third sub-via K21 and a fourth sub-via K22, wherein the length of the third sub-via K21 in the first direction X may be greater than the length of the fourth sub-via K22 in the first direction X; that is, the third sub-via K21 may be an elongated via, and the fourth sub-via K22 may be a square hole, a round hole, etc.; adjacent rows of third sub-vias K21 may also be arranged alternately to better prevent external moisture intrusion.

[0102] In one possible implementation, referring to Figures 7, 8A-8B, 9, and 10A-10C, the plurality of second transfer electrodes 131 include: a second transfer electrode group 131Z1 and a third transfer electrode group 131Z2; the third transfer electrode group 131Z2 is located on the side of the second transfer electrode group 131Z1 facing the display area AA; that is, according to the distance between the plurality of second transfer electrodes 131 and the display area AA, they can be divided into an inner ring of third transfer electrode group 131Z2 that is closer to the display area AA, and an outer ring of first transfer electrode group 131Z1 that is farther away from the display area AA; both the second transfer electrode group 131Z1 and the third transfer electrode group 131Z2 include: a plurality of second transfer electrodes 131 surrounding the periphery of the display area AA.

[0103] The second transfer electrode 131 of the third transfer electrode group 131Z2 is located in the gap between two adjacent second transfer electrodes 131 of the second transfer electrode group 131Z1, and the two ends of the second transfer electrode 131 of the third transfer electrode group 131Z2 are respectively electrically connected to the ends of two adjacent second transfer electrodes 131 in the second transfer electrode group 131Z1. That is, multiple second transfer electrodes 131 are arranged alternately in the direction of distance from the display area AA, surrounding the display area AA. One second transfer electrode 131 is closer to the display area AA, and the next second transfer electrode 131 is farther away from the display area AA. This is to avoid the problem that if the second transfer electrode 131 is arranged as a whole strip around the display area AA, the adhesion between the second transfer electrode 131 and the sealing adhesive 3 is lower than that between the insulating layer 19 and the sealing adhesive 3. By arranging the second transfer electrodes 131 alternately inside and outside, it is possible to avoid a large area of ​​the second transfer electrode 131 coming into contact with the sealing adhesive 3, which may lead to a decrease in the sealing performance of the sealing adhesive 3 on the display panel.

[0104] In one possible implementation, referring to FIG2A, the array substrate includes: at least one third common trace 14; one end of the third common trace 14 is connected to the bonding terminal group D1, and the other end extends through a portion of the bonding area BB1, the connection area BB3, and to the bonding opposite area BB2, where it is electrically connected to the second common trace 13. In this embodiment of the present disclosure, the array substrate further includes the third common trace 14, which can extend from the bonding area BB1 to the bonding opposite area BB2 to achieve better compensation of the common voltage of the opposing substrate 2 at the bonding opposite area BB2. This avoids the problem that when the second common trace 13 compensates for the common voltage at the location of the bonding opposite area BB2 through multiple second transition structures Q1, the signal may have been delayed, resulting in poor compensation effect for the common voltage of the bonding opposite area BB2.

[0105] In one possible implementation, referring to Figures 10A-10C, the insulating layer 19 includes: a plurality of third vias K3; the second transition electrode group 131Z1 includes: a plurality of first sub-transition electrodes 131a, and at least one second sub-transition electrode 131b; in the direction from the peripheral area BB to the display area AA, the width e2 of the second sub-transition electrode 131b is greater than the width e1 of the first sub-transition electrode 131a; the orthographic projection of the second sub-transition electrode 131b on the substrate 11 overlaps with the orthographic projection of the portion of the third common trace 14 located in the bonding opposite side area BB2 on the substrate 11, and is electrically connected at the overlapping position through the third vias K3. That is, the second transfer electrode group 131Z1, which is farther away from the display area AA, may include a wider second sub-transfer electrode 131b and a narrower first sub-transfer electrode 131a. The wider second sub-transfer electrode 131b can be electrically connected to the second common line 13 and also to the end position of the third common line 14, so as to further realize the electrical connection with the common electrode 22 of the opposing substrate 2 through the second transfer structure Q1. Moreover, the third common line 14 realizes the electrical connection with the common electrode 22 of the opposing substrate 2 through the second sub-transfer electrode 131b corresponding to the second common line 13, which can avoid setting up a separate transfer structure, which helps to simplify the manufacturing process of the display panel and reduce the manufacturing cost of the display panel.

[0106] In one possible implementation, referring to FIG10B, the array substrate further includes: a connection group LZ; the connection group LZ includes: a plurality of connection portions L; the connection group LZ is located at the end of the third common trace 14 away from the bonding terminal group D1 and on the side facing the second common trace 13; the connection portion L is in the same layer and material as the second common trace 13 and the third common trace 14; one end of the connection portion L is connected to the second common trace 13, and the other end is connected to the third common trace 14. In this embodiment of the present disclosure, the array substrate further includes: a plurality of connection portions L; the second common trace 13 and the third common trace 14 can be connected through the connection portion L. Since the second common trace 13 is connected to the common electrode 22 of the opposing substrate 2 through the second transition structure Q1, the third common trace 14 can also be made conductive to the common electrode 22 of the opposing substrate 2.

[0107] In one possible implementation, referring to FIG10A, the orthographic projection of the second sub-transfer electrode 131b onto the substrate 11 covers the orthographic projection of the connection group LZ onto the substrate 11. That is, the connection L is only provided at the location of the second sub-transfer electrode 131b. Since the connection group LZ is located between the second common trace 13 and the third common trace 14, and a trench (such as the first trench R1) is usually provided between the second common trace 13 and the third common trace 14 to prevent moisture intrusion, the connection L will be exposed due to the trench of the upper insulating layer 19. By having the second sub-transfer electrode 131b cover the connection L, the connection L can be protected by the second sub-transfer electrode 131b to prevent external moisture corrosion when there is no insulating layer 19 protecting the connection L.

[0108] In one possible implementation, referring to FIG10A, the insulating layer 19 further includes: at least one first trench R1; the first trench R1 is located in the connection area BB3 and the bonding opposite area BB2; the orthographic projection of the connection portion L on the substrate 11 overlaps with the portion of the first trench R1 projected onto the substrate 11. Optionally, the first trench R1 may be located between the second common trace 13 and the third common trace 14; in one possible implementation, referring to FIG9, a portion of the first trench R1 may coincide with the outer edge of the first sub-transfer electrode 131a away from the display area AA, that is, the first trench R1 may be provided along the outer edge of the first sub-transfer electrode 131a. In one possible implementation, the first trench R1 is provided in both the connection area BB3 and the bonding opposite area BB2, that is, forming a semi-closed structure surrounding the display area AA and opening in the bonding area BB1.

[0109] In one possible implementation, referring to FIG8A, the insulating layer 19 further includes: at least one second trench R2; the second trench R2 is located in the bonding opposite region BB2; at least a portion of the second trench R2 projected onto the substrate 11 is located on the side of the sealant 3 facing the display area AA. In one possible implementation, the second trench R2 may be provided only in the bonding opposite region BB2 of the display panel; optionally, the second trench R2 may be a single trench extending along the first direction X, or it may be a combination structure comprising multiple trenches extending along the first direction Y and arranged along the second direction Y.

[0110] In one possible implementation, the display panel may also have one or more grooves on the side of the second transfer electrode 131 of the connection area BB3 facing the display area AA.

[0111] In one possible implementation, the array substrate may further include: a gate line extending along a first direction X, a data line extending along a second direction Y, and a plurality of pixel electrodes; at least one of the first common trace 12, the second common trace 13, and the third common trace 14 may be in the same layer and material as the gate line; at least one of the first transition electrode 121 and the second transition electrode 131 may be in the same layer and material as the pixel electrodes.

[0112] In one possible implementation, as shown in FIG3, the opposing substrate 2 may include: an opposing substrate 21, and a black matrix layer 23 located between the opposing substrate 21 and the common electrode 22.

[0113] In one possible implementation, referring to Figures 11A-11B, 12A-12B, and 13A-13B, the array substrate further includes: a fourth common trace group 15Z; the fourth common trace group 15Z is located on the side of the first common trace 12 facing the display area AA; the fourth common trace group 15Z includes: at least one fourth common trace 15; one end of the fourth common trace 15 is connected to the bonding terminal group D1, and the other end passes through the bonding area BB1 and extends at least to the connection area BB3.

[0114] In one possible implementation, referring to Figures 11A-11B, the fourth common trace group 15Z includes: a first sub-trace 151; one end of the first sub-trace 151 is connected to the bonding terminal group D1, and the other end extends through the bonding area BB1 to the central region of the connection area BB3 in the second direction Y. In this embodiment of the present disclosure, the array substrate further includes the first sub-trace 151, one end of which is connected to the bonding terminal group D1, and the other end extends through the bonding area BB1 to the central region of the connection area BB3 in the second direction Y. This can reduce the common voltage difference between region C and region A (or region E) in the display area AA, and / or reduce the common voltage difference between region D and region B (or region F) in the display area AA, which is beneficial for making the common voltage of the display panel more uniform.

[0115] In one possible implementation, referring to Figures 12A-12B, the fourth common trace group 15Z includes: a second sub-trace 152; one end of the second sub-trace 152 is connected to the bonding terminal group D1, and the other end extends through the bonding area BB1 to the end of the connection area BB3 near the bonding opposite area BB2. In this embodiment, the array substrate further includes the second sub-trace 152; one end of the second sub-trace 152 is connected to the bonding terminal group D1, and the other end extends through the bonding area BB1 to the end of the connection area BB3 near the bonding opposite area BB2, which can achieve a better compensation effect on the common voltage of the far bonding terminal group D1, which is beneficial to make the common voltage of the display panel more uniform.

[0116] In one possible implementation, referring to Figures 13A-13B, the fourth common routing group 15Z includes: a third sub-routing 153; one end of the third sub-routing 153 is connected to the bonding terminal group D1, and the other end passes through the bonding area BB1, the connection area BB3, and extends to the bonding opposite side area BB2 in the first direction X, in a region of five-sixteenths to seven-sixteenths of the distance from the end of the bonding opposite side area BB2. For example, the other end of the third sub-routing 153 may extend to the bonding opposite side area BB2 in the first direction X, in a region of three-eighths of the distance from the end of the bonding opposite side area BB2. In this embodiment of the disclosure, the array substrate further includes a third sub-trace 153; one end of the third sub-trace 153 is connected to the bonding terminal group D1, and the other end passes through the bonding area BB1, the connection area BB3, and extends to the bonding opposite side area BB2 in the first direction X distance from the end of the bonding opposite side area BB2 in a region of five-sixteenths to seven-sixteenths, that is, common voltage compensation is performed in the middle region of the bonding opposite side area BB2, which is more conducive to the uniformity and stability of the common voltage of the display area AA, and can adapt to products with larger size and high refresh rate.

[0117] In one possible implementation, as shown in Figures 11B, 12B, and 13B, the other end of the fourth common trace 15 away from the bonding terminal group D1 is connected to the second common trace 13.

[0118] Optionally, when the other end of the fourth common trace 15 away from the bonding terminal group D1 is connected to the second common trace 13, it can be done in a similar manner to when the third common trace 14 is connected to the second common trace 13. That is, by providing a connecting part between the fourth common trace 15 and the second common trace 13, the fourth common trace 15 and the second common trace 13 are connected through the connecting part; or by widening the second adapter electrode 131 near the display area AA to overlap with the third common trace 15, and electrically connecting it through a via at the overlapping position.

[0119] In one possible implementation, as shown in Figures 11A, 12A, and 13A, the display panel further includes: a fourth adapter structure Z3; the other end of the fourth common trace 15 away from the bonding terminal group D1 is connected to the common electrode 22 via the fourth adapter structure Z3.

[0120] Optionally, when the other end of the fourth common trace 15 away from the bonding terminal group D1 is connected to the common electrode 22 via the fourth adapter structure Z3, it can be similar to the way the first common trace 12 is connected to the common electrode 22. The third adapter structure Z3 may include a conductive part and a third adapter electrode. The third adapter electrode may be in the same layer and material as the first adapter electrode. The third adapter electrode is first electrically connected to the fourth common trace 15 through a via, and then electrically connected to the common electrode of the opposing substrate 2 through the conductive part. In this way, the fourth common trace 15 is connected to the common electrode 22 through the fourth adapter structure Z2.

[0121] In one possible implementation, referring to Figures 6A and 6B, optionally, in the bonding area BB1, the line width d11 of the first common trace 12 can be smaller than the line width d12 of the second common trace 13; optionally, the line width d11 of the first common trace 12 can be equal to the line width d13 of the third common trace 14; optionally, the line width d11 of the first common trace 12 can range from 180μm to 250μm, for example, it can be 180μm, 190μm, 200μm, 210μm, or 220μm. The line width d12 of the second common trace 13 can optionally range from 270μm to 350μm, for example, 270μm, 280μm, 290μm, 300μm, 310μm, 320μm, 330μm, 340μm, or 350μm; the line width d13 of the third common trace 14 can range from 180μm to 250μm, for example, 180μm, 190μm, 200μm, 210μm, or 220μm. The line width d14 of the first signal line 16 can optionally range from 200μm to 280μm, for example, 200μm, 210μm, 220μm, 230μm, 240μm, 250μm, 260μm, or 280μm; the line width d15 of the frame start signal line 171 can optionally range from 100μm to 150μm, for example, 100μm, 110μm, 120μm, or 130μm. 140μm or 150μm; optionally, the line width d16 of the low-level signal line 172 can range from 180μm to 250μm, for example, 180μm, 190μm, 200μm, 210μm, 220μm, 230μm, 240μm, or 250μm; optionally, the line width d17 of the ground line 18 can range from 120μm to 180μm, for example, 120μm, 130μm, 140μm, 150μm, 160μm, or 180μm.

[0122] In one possible implementation, at least one of the first common wiring 12, the second common wiring 13, the third common wiring 14, and the fourth common wiring 15 may be a structure including multiple mesh openings to increase the light transmittance of the first common wiring 12, the second common wiring 13, the third common wiring 14, and the fourth common wiring 15, which is beneficial to improving the curing effect of the sealing adhesive 3 when cured by light.

[0123] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes a display panel as provided in embodiments of this disclosure.

[0124] In some embodiments, the display panel provided in this disclosure may further include a liquid crystal layer between an array substrate and a counter substrate, a first polarizer on the side of the array substrate away from the counter substrate, and a second polarizer on the side of the counter substrate away from the array substrate, wherein the polarization direction of the first polarizer and the polarization direction of the second polarizer are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the scope of this disclosure.

[0125] Based on the same inventive concept, this disclosure also provides a display device, comprising the display panel described above and a backlight module located on the light-incident side of the display panel. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature LEDs (Mini LEDs, Micro LEDs, etc.).

[0126] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0127] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0128] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0129] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A display panel having a display area and a peripheral area located around the periphery of the display area; the peripheral area comprising: Binding area, binding opposite area, and connection area; The binding opposite side area is disposed opposite to the binding area, and the connecting area connects the binding area and the binding opposite side area; wherein, the display panel includes: Array substrates and opposing substrates arranged opposite each other; The common electrode is located on the opposing substrate; A first adapter structure is located in the binding area; At least one bonding terminal group is located in the bonding area of ​​the array substrate; At least one first common trace is located in the bonding area of ​​the array substrate. One end of the first common trace is electrically connected to the bonding terminal group, and the other end extends along the bonding area and toward the connection area, and is electrically connected to the common electrode in the bonding area through the first adapter structure.

2. The display panel as claimed in claim 1, wherein, The bonding area includes an end area, which is connected to the connection area. The other end of the first common trace extends to the end area and is electrically connected to the common electrode in the end area through the first adapter structure.

3. The display panel as described in claim 2, wherein, The display panel further includes: a sealing adhesive; the sealing adhesive is located between the array substrate and the opposing substrate; the sealing adhesive includes: a conductive portion; The array substrate further includes: a substrate, an insulating layer located on the side of the first common trace away from the substrate, and at least one first transition electrode located on the side of the insulating layer away from the first common trace; the insulating layer includes: a plurality of first vias; the first transition electrode is located in the bonding region, and the first transition electrode is electrically connected to the first common trace through the first vias; The first adapter structure includes: the conductive part and the first adapter electrode; the first common trace passes through the first adapter electrode and is electrically connected to the common electrode via the conductive part.

4. The display panel as claimed in claim 3, wherein, The display panel includes: at least one first adapter electrode group; the first adapter electrode group is located in the end region; The first adapter electrode group includes: a plurality of first adapter electrodes arranged along a first direction and spaced apart from each other.

5. The display panel as claimed in claim 4, wherein, The sealing adhesive has a first outer edge and a second outer edge in the bonding area; The orthographic projection of the sealing adhesive onto the substrate covers the orthographic projection of the first adapter electrode onto the substrate, and the minimum distance between the first adapter electrode and the first outer edge is equal to the minimum distance between the first adapter electrode and the second outer edge.

6. The display panel as described in any one of claims 3-5, wherein, The plurality of first vias includes: a plurality of first sub-via rows; the plurality of first sub-via rows extend along a first direction and are arranged along a second direction; The first sub-via row includes: a plurality of first sub-vias arranged along the first direction and spaced apart from each other; the first sub-vias of adjacent first sub-via rows are arranged in an alternating manner.

7. The display panel as claimed in claim 6, wherein, The plurality of first vias includes: a plurality of second sub-via rows; the plurality of second sub-via rows extend along a first direction and are arranged along a second direction; The second sub-via row includes: a plurality of second sub-vias arranged along the first direction and spaced apart from each other; the length of the first sub-via in the first direction is greater than the length of the second sub-via in the first direction; The first sub-via row and the second sub-via row are arranged alternately along the second direction.

8. The display panel as described in any one of claims 3-7, wherein, The display panel includes: at least one second common trace and a second adapter structure; one end of the second common trace is connected to a portion of the bonding terminal group, and the other end extends through the bonding area, the connection area, the bonding opposite side area, the connection area to another portion of the bonding area and is connected to another portion of the bonding terminal group; the second adapter structure is located in the connection area and the bonding opposite side area; the second common trace is electrically connected to the common electrode through the second adapter structure; The first common trace is located on the side of the second common trace facing the display area.

9. The display panel as claimed in claim 8, wherein, The orthographic projection of the first adapter electrode on the substrate overlaps with the orthographic projection of the first common trace on the substrate, and also overlaps with the orthographic projection of the second common trace on the substrate. The orthographic projection of the first via on the substrate overlaps only with the orthographic projection of the first common trace on the substrate.

10. The display panel as claimed in claim 8 or 9, wherein, The first common routing line and the second common routing line are on the same layer and made of the same material; The array substrate includes: a plurality of second transition electrodes located on the side of the insulating layer opposite to the second common trace; the insulating layer includes: a plurality of second vias; the second transition electrodes are electrically connected to the second common trace through the second vias; The second adapter structure includes: the conductive part and the second adapter electrode.

11. The display panel as claimed in claim 10, wherein, The plurality of second transition electrodes include: a second transition electrode group and a third transition electrode group; the third transition electrode group is located on the side of the second transition electrode group facing the display area; both the second transition electrode group and the third transition electrode group include: a plurality of second transition electrodes surrounding the periphery of the display area; The second transfer electrode of the third transfer electrode group is located in the gap between two adjacent second transfer electrodes of the second transfer electrode group, and both ends of the second transfer electrode of the third transfer electrode group are respectively electrically connected to the ends of two adjacent second transfer electrodes in the second transfer electrode group.

12. The display panel as claimed in claim 11, wherein, The array substrate includes: at least one third common trace; One end of the third common trace is connected to the bonding terminal group, and the other end passes through part of the bonding area, the connection area, and extends to the bonding opposite side area, where it is electrically connected to the second common trace.

13. The display panel as claimed in claim 12, wherein, The insulating layer includes: a plurality of third vias; The second transfer electrode group includes: a plurality of first sub-transfer electrodes and at least one second sub-transfer electrode; in the direction from the peripheral area to the display area, the width of the second sub-transfer electrode is greater than the width of the first sub-transfer electrode; The orthographic projection of the second sub-transfer electrode on the substrate overlaps with the orthographic projection of the portion of the third common trace located in the bonding opposite region on the substrate, and is electrically connected through the third via at the overlapping position.

14. The display panel as claimed in claim 13, wherein, The array substrate further includes: a connection group; the connection group includes: a plurality of connection portions; The connecting part is in the same layer and made of the same material as the second common routing line and the third common routing line; one end of the connecting part is connected to the second common routing line and the other end is connected to the third common routing line.

15. The display panel as claimed in claim 14, wherein, The orthographic projection of the second sub-transfer electrode onto the substrate covers the orthographic projection of the connection assembly onto the substrate.

16. The display panel as claimed in any one of claims 14-15, wherein, The insulating layer further includes: at least one first trench; the first trench is located in the connection area and the bonding opposite side area; The orthographic projection of the connecting portion onto the substrate overlaps with the portion of the orthographic projection of the first trench onto the substrate.

17. The display panel according to any one of claims 12-16, wherein, The array substrate further includes: a fourth common trace group; the fourth common trace group is located on the side of the first common trace facing the display area; The fourth common wiring group includes: at least one fourth common wiring; one end of the fourth common wiring is connected to the binding terminal group, and the other end passes through the binding area and extends at least to the connection area.

18. The display panel as claimed in claim 17, wherein, The other end of the fourth common trace, away from the bonding terminal group, is connected to the second common trace.

19. The display panel as claimed in claim 17, wherein, The display panel further includes: a fourth adapter structure; the other end of the fourth common trace away from the bonding terminal group is connected to the common electrode via the fourth adapter structure.

20. The display panel according to any one of claims 17-19, wherein, The fourth common wiring group includes: a first sub-wiring; one end of the first sub-wiring is connected to the bonding terminal group, and the other end passes through the bonding area and extends to the central area of ​​the connection area in the second direction.

21. The display panel according to any one of claims 17-20, wherein, The fourth common routing group includes: a second sub-routing; one end of the second sub-routing is connected to the bonding terminal group, and the other end passes through the bonding area and extends to the end of the connection area near the bonding opposite side area.

22. The display panel according to any one of claims 17-21, wherein, The fourth common routing group includes: a third sub-routing; one end of the third sub-routing is connected to the binding terminal group, and the other end passes through the binding area, the connection area, and extends to the area of ​​the binding opposite side area in the first direction from five-sixteenths to seven-sixteenths of the end of the binding opposite side area.

23. A display device, wherein, Includes the display panel as described in any one of claims 1-22.

Images