Voxel generation techniques

Abstract

Apparatus, systems, and techniques are used to convert point clouds into voxels. In at least one embodiment, the processor converts a point cloud representation of an environment into voxels based at least in part on a data structure that uses point locations to indicate voxels.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for representing point clouds as voxels. At least one embodiment relates to a processor or computing system for generating voxels from a point cloud at least in part based on one or more point locations to indicate voxels in one or more data structures. Background Technology

[0002] Generating voxel representations of objects from point cloud representations requires significant computational resources. The utilization of these resources can be improved. Attached Figure Description

[0003] Figure 1 A block diagram of a system for generating a voxel representation of an environment based on a point cloud representation of the environment, according to at least one embodiment, is shown. Figure 2 A block diagram of a system for generating a hash table for converting point clouds into voxels, according to at least one embodiment, is shown. Figure 3 A block diagram of a system for calculating the mean eigenvalue for each voxel in a voxel grid, based at least in part on a hash table, is shown according to at least one embodiment. Figure 4 The process of using one or more processors to perform voxel representation operations based on a point cloud representation generation environment, according to at least one embodiment, is illustrated. Figure 5 The process is illustrated in at least one embodiment, causing one or more processors to execute application programming interface (API) functions that operate on voxel representations of a point cloud representation generation environment; Figure 6 A block diagram of a driver and / or runtime for causing one or more processors to execute voxel representation API functions based on a point cloud representation generation environment, according to at least one embodiment, is shown. Figure 7A The logic according to at least one embodiment is shown; Figure 7B The logic according to at least one embodiment is shown; Figure 8 The training and deployment of a neural network according to at least one embodiment are illustrated; Figure 9 An example data center system according to at least one embodiment is shown; Figure 10A An example of an autonomous vehicle according to at least one embodiment is shown; Figure 10B The illustration shows an embodiment according to at least one of the embodiments. Figure 10AExamples of camera positions and field of view for autonomous vehicles; Figure 10C This is an illustration based on at least one embodiment. Figure 10A A block diagram of an example system architecture for an autonomous vehicle; Figure 10D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 10A A diagram of a system for communication between autonomous vehicles; Figure 11 This is a block diagram illustrating a computer system according to at least one embodiment; Figure 12 This is a block diagram illustrating a computer system according to at least one embodiment; Figure 13 A computer system according to at least one embodiment is shown; Figure 14 A computer system according to at least one embodiment is shown; Figure 15A A computer system according to at least one embodiment is shown; Figure 15B A computer system according to at least one embodiment is shown; Figure 15C A computer system according to at least one embodiment is shown; Figure 15D A computer system according to at least one embodiment is shown; Figure 15E and Figure 15F A shared programming model according to at least one embodiment is shown; Figure 16 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown; Figures 17A-17B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown; Figures 18A-18B Additional exemplary graphics processor logic according to at least one embodiment is shown; Figure 19 A computer system according to at least one embodiment is shown; Figure 20A A parallel processor according to at least one embodiment is shown; Figure 20B A partitioning unit according to at least one embodiment is shown; Figure 20C A processing cluster according to at least one embodiment is shown; Figure 20D A graphics multiprocessor according to at least one embodiment is shown; Figure 21 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated; Figure 22 A graphics processor according to at least one embodiment is shown; Figure 23 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Figure 24 A deep learning application processor according to at least one embodiment is shown; Figure 25 A block diagram of an example neuromorphic processor is shown according to at least one embodiment; Figure 26 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 27 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 28 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 29 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Figure 30 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment; Figures 31A-31B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0004] Figure 32 A parallel processing unit (“PPU”) according to at least one embodiment is shown. Figure 33 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated. Figure 34 A memory partitioning unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown; Figure 35 A streaming multiprocessor according to at least one embodiment is illustrated; Figure 36 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment; Figure 37 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment; Figure 38 Example illustrations of an advanced computing pipeline for processing imaging data according to at least one embodiment; Figure 39A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment; Figure 39B Includes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment; Figure 40A A data flow diagram of a process for training a machine learning model according to at least one embodiment is shown; Figure 40B This is an example illustration of a client-server architecture for enhancing annotation tools using a pre-trained annotation model, according to at least one embodiment; and Figure 41 Components of a system for accessing a large language model according to at least one embodiment are shown. Detailed Implementation

[0005] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to those skilled in the art that the concepts of the invention can be practiced without one or more of these specific details, and that any two or more aspects of any one or more of the embodiments described herein can be combined.

[0006] In at least one embodiment, one or more processors, including one or more circuits, perform operations to generate one or more voxels using one or more point clouds, at least in part, based on one or more point locations used to indicate one or more voxels in one or more data structures. In at least one embodiment, one or more processors generate voxels by displaying or otherwise activating the voxels on a display device. In at least one embodiment, one or more data structures include one or more hash tables that associate one or more point locations with one or more indications of one or more voxels to be generated, and are at least combined herein with Figure 2The voxelization hash table 208 is further described. In at least one embodiment, a voxel is a unit of representation in three-dimensional (3D) space used in computer graphics and computer vision applications. In at least one embodiment, a voxel is referred to as a 3D pixel. In at least one embodiment, a voxel is visually represented as a cube. In at least one embodiment, voxelization refers to one or more techniques for converting a point cloud representation of an environment and / or object into a voxel representation of that environment and / or object. In at least one embodiment, one or more processors use the hash table described herein to compute a mean feature value of a voxel by indicating voxels that should be generated on a display device without checking feature values ​​in memory locations corresponding to voxels that will not be generated. In at least one embodiment, the feature value is a value used at least in part for generating visual features of the voxel, and is further described herein.

[0007] In at least one embodiment, one or more processors use one or more locations (point locations) of points in a voxel grid stored in one or more hash tables to indicate voxels that should be generated to represent one or more points in a point cloud. In at least one embodiment, the voxel grid is a three-dimensional data structure comprising voxels. In at least one embodiment, one or more processors store each point location in a hash table such that a point location found in the hash table can indicate the corresponding voxel to be generated. In at least one embodiment, one or more processors generate one or more hash tables to allow those one or more processors to efficiently look up one or more indications of one or more voxels to be generated using one or more voxel locations. In at least one embodiment, when the number of voxels in the voxel grid exceeds the number of points in the point cloud, one or more processors generate one or more hash tables to allow those one or more processors to efficiently identify one or more voxels representing one or more points. In at least one embodiment, one or more processors generate one or more hash tables that allow the processors to generate one or more feature values ​​for one or more voxels, at least in part, by iterating on each of the possible voxels in the voxel grid, or by iterating on each of the possible voxels in the voxel grid, in addition to iterating on each of the possible voxels in the voxel grid. In at least one embodiment, one or more processors use hash tables to identify point feature values ​​common to common voxels and allow these processors to compute one or more feature values ​​for voxels, such as sum and mean feature values ​​further described herein. In at least one embodiment, one or more processors voxelize the point cloud using hash tables as part of a process for downsampling the resolution of the point cloud and using the voxel representation of the point cloud as input to a neural network operation such as image classification, image segmentation, autonomous driving, or some combination thereof. In at least one embodiment, voxelizing the point cloud refers to techniques for converting the point cloud into voxels.

[0008] Figure 1 A block diagram of a system 100 including one or more processors is shown. The one or more processors include one or more circuitry for generating one or more voxels using one or more point clouds, at least in part, based on point locations used to indicate one or more voxels within one or more data structures. In at least one embodiment, this is combined with... Figure 1 One or more aspects of the described one or more embodiments are consistent with one or more embodiments described herein (including at least in combination). Figures 2-6The system 100 is composed of one or more aspects described herein. In at least one embodiment, one or more processors perform one or more operations of the system 100. In at least one embodiment, the one or more processors performing one or more operations of the system 100 are any of the processors or combinations of processors described herein, including combinations of... Figure 13 The described CPU 1302, combined with Figure 10C Describing one or more accelerators 1014, combined Figure 17A The graphics processor 1710 described and combined with Figure 32 The parallel processing unit (“PPU”) 3200 is described. In at least one embodiment, one or more processors 102 perform operations used by the system 100, such as loading / storing values ​​output by neural network activation functions in one or more arithmetic logic units (ALUs) (such as one or more ALUs 710 of FIG. 7). In at least one embodiment, one or more processors 102 perform combined... Figure 2 The described one or more operations, such as generating a voxelized hash table 208, are performed. In at least one embodiment, one or more processors 102 perform the combination. Figure 3 The described one or more operations, such as calculating the number of points in a voxel. In at least one embodiment, one or more processors 102 perform the combined... Figure 4 The described one or more operations, such as calculating voxel offsets using operation 402. In at least one embodiment, one or more processors 102 perform the combination Figure 5 The described one or more operations, such as executing a voxelization API function using operation 504. In at least one embodiment, one or more processors 102 perform the combined... Figure 6 Describe one or more operations, such as one or more API 610 operations.

[0009] In at least one embodiment, system 100 is any computing system such as an edge computing system, an accelerated computing system, a high-performance computing system, a data center, a cloud computing system, or some combination thereof. In at least one embodiment, system 100 is used in fields such as healthcare, genomics, engineering, aerospace, urban planning, graphics processing, finance, data storage and management, e-commerce, meteorology, physical modeling, or some combination thereof. In at least one embodiment, system 100 is used to perform artificial intelligence (AI) tasks such as image classification, image segmentation, autonomous driving, manufacturing defect identification, or some combination thereof.

[0010] In at least one embodiment, system 100 includes one or more sensors 101. In at least one embodiment, one or more sensors 101 collect data from the environment, which is used by a processor to generate a point cloud representation of the environment (including objects in the environment). In at least one embodiment, the point cloud representation is a 3D representation of the environment. In at least one embodiment, one or more sensors 101 are 3D scanners, 3D sensors, light detection and ranging (LIDAR or lidar) sensors, or some combination thereof. In at least one embodiment, one or more sensors 101 are used in fields such as autonomous driving, manufacturing defect detection, object recognition, or some combination thereof.

[0011] In at least one embodiment, system 100 includes one or more processors 102. In at least one embodiment, the one or more processors 102 are any of the processors or combinations of processors described herein, including combinations of processors. Figure 13 The described CPU 1302, combined with Figure 10C Describing one or more accelerators 1014, combined Figure 17A The graphics processor 1710 described and combined with Figure 32 The described parallel processing unit (“PPU”) 3200. In at least one embodiment, one or more processors 102 are processors implemented in an edge computing system designed to perform AI tasks such as image classification, autonomous driving, or some combination thereof. In at least one embodiment, one or more processors 102 are AMD® Epyc™ embedded processors and / or NVIDIA® Jetson™ TX2 modules that include multiple types of processors.

[0012] In at least one embodiment, as used in any implementation described herein, unless clearly stated otherwise from the context, terms such as “system,” “device,” “component,” or “module,” as well as nominalized verbs (e.g., compiler and / or other terms), each refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein is referred to as a component. In at least one embodiment, any component described herein is combined with and / or communicatively connected to at least one other component, regardless of how such components are described as being combined and / or communicatively connected in other embodiments. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions. In at least one embodiment, hardware, individually or in any combination, includes hardwired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware storing instructions executed by the programmable circuitry. In at least one embodiment, modules may collectively or separately embody a circuit system forming part of a larger system, such as an integrated circuit (IC), a system-on-a-chip (SoC), etc. In at least one embodiment, any one or more architectures of any circuitry of one or more modules are represented as register-transfer-level (RTL) representations and / or another fabless representation that can be licensed and / or used in tape-out (the final stage of IC design before IC manufacturing).

[0013] In at least one embodiment, one or more processors, including one or more circuits, execute voxelization module 104 to generate one or more voxels using one or more point clouds, at least in part, based on one or more point locations used to indicate one or more voxels in one or more data structures. In at least one embodiment, voxelization module 104 outputs a voxel-based representation of the point cloud data. In at least one embodiment, voxelization module 104 uses at least the methods described herein... Figure 2 The voxelization hash table 208 further describes a type of hash table (i.e., a voxelized hash table) to perform voxelization of the point cloud data 103 (the data of the point cloud). In at least one embodiment, the voxelization module 104 performs operations that downsample the point cloud into a less data-intensive voxel representation. In at least one embodiment, the voxelization module 104 downsamples the point cloud data 103 into voxel data to allow one or more processors 102 to perform AI tasks, such as image classification, with less latency. In at least one embodiment, the voxelization module 104 is capable of performing operations at least in part for using, as described herein, at least in combination with... Figure 2The voxelized hash table 208 further describes exemplary modules for any one or more operations of a point cloud representation of a voxelized environment. In at least one embodiment, a voxel containing one or more points or point locations refers to a voxel that should be generated, displayed, or otherwise activated to represent those one or more points. In at least one embodiment, the points or point locations contained in a voxel are referred to as being assigned to that voxel. In at least one embodiment, a voxel containing one or more points is at least conceptually defined as a voxel encompassing that one or more points, as if the point cloud were positioned to overlap with a voxel mesh. In at least one embodiment, a voxel containing a point is a voxel whose boundary overlaps with that point.

[0014] In at least one embodiment, the voxelization module 104 allocates a amount of memory based on the number of points in the point cloud data 103 to create a voxelized hash table, which is at least combined with... Figure 2 The voxelization hash table 208 further describes the voxelization hash table. In at least one embodiment, a quantity of memory includes multiple memory locations. In at least one embodiment, the voxelization module 104 calculates the position of each point in the point cloud based on the coordinates of each point. In at least one embodiment, the position of a point is referred to as a point position. In at least one embodiment, the point position is referred to as a voxel offset. In at least one embodiment, the voxel offset is one or more values ​​indicating the position of a voxel within a voxel grid. In at least one embodiment, the voxel offset is a set of three coordinates in a 3D coordinate system. In at least one embodiment, the voxel offset is based on a single value of a set of three coordinates. In at least one embodiment, the voxel offset represents the point position by using the distance and direction from a location within the voxel grid (such as the origin (0, 0, 0)). In at least one embodiment, the voxelization module 104 uses the voxel offset to identify a voxel identifier (voxel ID) for the voxel containing this voxel offset. In at least one embodiment, the voxel ID is an identifier (indicator) of a specific voxel within the voxel grid.

[0015] In at least one embodiment, the processor executes the voxelization module 104 to receive and / or otherwise acquire point cloud data 103. In at least one embodiment, the voxel offset and voxel ID of each point in the point cloud data 103 are entered into a hash table for identifying voxels by using each point, as at least in conjunction with this document. Figure 2 Further described. In at least one embodiment, the voxelization module 104 sums all point features in the voxel and outputs this sum, as described herein at least in conjunction with Figure 3 and Figure 4 Further described. In at least one embodiment, the voxelization module 104 calculates the mean feature value for each voxel, as described herein in at least the following combination. Figure 3Further described. In at least one embodiment, the voxelization module 104 outputs the number of points and mean feature values ​​for each voxel for further processing, as described herein in at least the following combination. Figure 3 Further description.

[0016] In at least one embodiment, the neural network (NN) classification module 106 receives and / or otherwise obtains a voxel-based representation of the point cloud data generated by the voxelization module 104. In at least one embodiment, the neural network classification module 106 receives and / or otherwise obtains input data, which includes at least in part this voxel representation based on a data structure indicating the voxels to be generated during the conversion of the point cloud into a voxel representation of the environment, as described herein at least in conjunction with Figures 1-6 In at least one embodiment, the input data is a voxel representation of a 3D medical image. In at least one embodiment, the neural network classification module 106 includes one or more neural networks trained to perform a classification task. In at least one embodiment, one or more processors 102 execute the neural network by performing one or more operations related to the neural network task (such as loading / storing weights) in one or more ALUs (such as one or more ALUs 710 in FIG. 7) during forward or backward propagation. In at least one embodiment, the neural network is referred to as a neural network model, neural model, or model. In at least one embodiment, the neural network includes one or more neural networks. In at least one embodiment, the neural network is a deep learning network or a deep neural network (DNN). In at least one embodiment, the neural network is a recurrent neural network (RNN), a convolutional neural network (CNN), a generative adversarial network (GAN), a transformer, a graph neural network (GNN), or some combination thereof. In at least one embodiment, the training system uses training data to train an untrained neural network to generate a trained neural network that performs inference or prediction at an accuracy level set by a user or application or higher. In at least one embodiment, the neural network classification module 106 is used to identify and label objects in voxel-based data, such as voxel representations of the environment detected by sensors mounted on an autonomous vehicle.

[0017] Figure 2 A block diagram of system 200 is shown, which includes one or more processors, each including one or more circuits for performing one or more operations that, as part of a voxelization process, use information about one or more point clouds and one or more voxel meshes to generate data and store it in a voxelization hash table. In at least one embodiment, this document incorporates... Figure 2 One or more aspects of the described one or more embodiments are consistent with one or more embodiments described herein (including at least in combination). Figure 1 and Figures 3-6 The system 200 combines one or more aspects of the described aspects. In at least one embodiment, the system 200 includes one or more processors for performing one or more operations of the system 200. In at least one embodiment, the one or more processors performing one or more operations of the system 200 are any of the processors or combinations of processors described herein, including combinations of... Figure 13 The described CPU 1302, combined with Figure 10C Describing one or more accelerators 1014, combined Figure 17A The graphics processor 1710 described and combined with Figure 32 The described parallel processing unit (“PPU”) 3200. In at least one embodiment, system 200 includes one or more modules described herein, such as Figure 1 The neural network classification module 106. In at least one embodiment, one or more operations of the system 200 are related to... Figure 3 The system 300 combines one or more operations (such as calculating the number of points per voxel) with the system 200. In at least one embodiment, one or more operations of the system 200 are combined with Figure 4 The process 400 is combined with one or more operations (such as allocating memory locations using operation 401). In at least one embodiment, one or more operations of system 200 are combined with Figure 5 The process 500 combines one or more operations (such as inputting point cloud data into one or more APIs using operation 502). In at least one embodiment, one or more operations of system 200 are one or more operations of one or more APIs 610, such as using voxelization module 304 to calculate the number of points per voxel.

[0018] In at least one embodiment, system 200 includes Figure 1System 200 is one or more components of system 100. In at least one embodiment, system 200 is an edge computing device designed to perform AI tasks such as medical segmentation or autonomous driving. An edge computing system is one or more computing systems whose proximity to other computing systems, such as servers and databases, improves various aspects of computing performance, such as response time and reliability of data transmission. In at least one embodiment, the edge computing system is part of a distributed computing framework in which multiple computing systems are physically separated and connected via a network such as a cloud computing network. In at least one embodiment, the edge computing system is an NVIDIA® Jetson™ computing system or a computing system with an AMD® Epyc™ embedded processor. In at least one embodiment, the edge computing system performing AI-related operations is referred to as an AI hardware platform. In at least one embodiment, system 200 includes Figure 1 The system 200 includes one or more sensors 101, such as camera sensors, radar sensors, lidar sensors, laser sensors, and ultrasonic sensors. In at least one embodiment, the system 200 includes one or more neural network classification modules 106.

[0019] In at least one embodiment, system 200 includes a voxelization module 204. In at least one embodiment, voxelization module 204 includes one or more components of voxelization module 104. In at least one embodiment, voxelization module 204 performs one or more operations of voxelization module 104. In at least one embodiment, voxelization module 204 is at least partially based on one or more sensors (such as...) Figure 1 One or more sensors 101 receive and / or otherwise acquire point cloud data 103. In at least one embodiment, the voxelization module 204 outputs voxel offsets and voxel index values ​​to be loaded / stored in a voxelization hash table, as further described herein.

[0020] In at least one embodiment, system 200 includes one or more point locations, such as voxel offsets 205a-n, where n represents the number of voxel offsets. In at least one embodiment, voxelization module 204 generates and outputs voxel offsets 205a-n. In at least one embodiment, a voxel offset is one or more values ​​representing the position of a point within a corresponding voxel in a voxel grid. In at least one embodiment, a voxel offset is one or more values ​​representing the position of a point in a voxel grid, which are used by a processor to identify the specific voxel in which the point is located. In at least one embodiment, the voxel offset is based at least in part on three coordinate values, such as x, y, and z in a 3D coordinate system. In at least one embodiment, voxel offsets 205a-n are based on the center point of the voxel. In at least one embodiment, the voxel offset value represents the distance from a point in the voxel grid (such as the origin (0, 0, 0)). In at least one embodiment, the voxel offset value alternatively represents the position of a point within the voxel by indicating the distance of the point from a given location (such as the center of the voxel) used to calculate the centroids of two or more points contained within the voxel. In at least one embodiment, the centroids of two or more points contained within the voxel are used to calculate the characteristics of the voxel.

[0021] In at least one embodiment, the voxelization module 204 performs actions that cause application programming interface (API) functions (such as those using...) to... Figure 6 The voxelization hash table 612 contains one or more voxelization functions (one or more functions 612) that associate each point of the point cloud with a voxel in the voxel grid, wherein such functions are identified in pseudocode using names such as map_point_to_voxel(). In at least one embodiment, the voxelization module 204 performs map_point_to_voxel() to compute the position of the voxel based on the overall grid size, the number of voxels, the voxel grid resolution, the dimension of each voxel, or some combination thereof. In at least one embodiment, the voxelization module 204 generates a data structure and indexes each of the one or more point positions in this data structure to one or more voxels also in this data structure, as further described herein. In at least one embodiment, the voxelization module 204 indexes the point positions to voxel IDs using a hash function as further described herein. In at least one embodiment, another method of indexing point positions to voxels loads / stores the point positions in a position in an array and loads / stores the corresponding voxel IDs in a corresponding position in another array.

[0022] In at least one embodiment, the voxelization module 204 assigns a unique voxel ID value to each voxel in the voxel mesh. In at least one embodiment, the voxelization module 204 determines a voxel offset for each point in the point cloud and identifies a specific voxel with a voxel ID by using this voxel offset. In at least one embodiment, the voxelization module 204 outputs a voxel ID 206 an corresponding to a specific voxel containing voxel offsets 205a-n and / or stores it in a data storage location (such as a buffer or cache) indexed by these locations. In at least one embodiment, the index of the data storage location storing the voxel ID is called a voxel index and includes a voxel index value. In at least one embodiment, at least conceptually, the voxelization module 204 identifies a voxel ID for each point in the voxel based on a voxel offset in voxel offsets 205a-n. In at least one embodiment, 3 is any real number in any data format (such as FP16) suitable for uniquely representing each voxel in the voxel mesh.

[0023] In at least one embodiment, the voxelization module 204 outputs voxel offsets 205a-n and voxel index values ​​206a-n (further described herein) to be stored in a voxelized hash table 208. In at least one embodiment, the voxelized hash table 208 is referred to as a hash graph, lookup table, or mapping. In at least one embodiment, the data of the voxelized hash table 208 is loaded / stored in a data storage device (storage device) (also referred to as memory or memory device). In at least one embodiment, the data of the voxelized hash table 208 is loaded / stored in memory, such as cache memory, random access memory (RAM), dynamic random addressable memory (DRAM), static random addressable memory (SRAM), non-volatile memory (e.g., flash memory), other data storage devices, or some combination thereof. In at least one embodiment, the data of the voxelized hash table 208 is loaded / stored in a data storage device, which is any or a combination of data storage devices described herein, including data storage device 701 of FIG. 7.

[0024] In at least one embodiment, the voxelization module 204 generates a data structure including hash tables that store point locations as keys and corresponding voxel indications as values, wherein voxels are generated, displayed, or activated to represent one or more points indicated by those point locations. In at least one embodiment, the voxelization module 204 generates the voxelized hash table by using and / or allocating a amount of memory based on point locations or the number of points. In at least one embodiment, the voxelization module 204 generates the voxelized hash table by allocating a amount of memory in a storage device twice the number of points in the point cloud to store the voxel offset for each point and a corresponding voxel index value identifying the memory location where the stored voxel ID is located. In at least one embodiment, the voxelized hash table stores the corresponding voxel ID, rather than the voxel index value.

[0025] In at least one embodiment, the voxelization hash table 308 stores voxel locations (voxel offsets) as keys and voxel index values ​​or voxel IDs as values ​​corresponding to these keys. In at least one embodiment, as a way of identifying each point, the voxelization module 204 assigns distinct keys (unique values) to each point in the point cloud. In at least one embodiment, the key assigned to each point in the point cloud is a voxel offset in voxel offsets 205a-n. In at least one embodiment, the key is input into a hash function to output a hash value indicating the memory location where the value corresponding to this key is stored, i.e., a unique code for this key. In at least one embodiment, the hash function is any type of function that maps an input value to another value, wherein the output of this function indicates the location of this other value in memory. In at least one embodiment, the hash function uses any type of hashing method, such as division, intermediate square, folding, multiplication, or some combination thereof. In at least one embodiment, one or more indications of one or more point locations are input as keys into the hash function to output one or more indications of one or more voxels, such as voxel index values ​​or voxel IDs. In at least one embodiment, one or more operations that input a key into a hash function to generate an output are indicated by arrows in voxelized hash table 208. In at least one embodiment, one of the voxel offsets 205a-n is a key input into the hash function to output voxel index values ​​210a-n.

[0026] In at least one embodiment, the voxelization module 204 generates a data structure including a hash table based on one or more arrays of one or more point locations and one or more arrays of one or more indices of one or more voxels. In at least one embodiment, the voxelization module 204 loads / stores data as one or more arrays in a voxelization hash table 308. In at least one embodiment, the array storing voxel offsets 205a-n is an array of length equal to the number of points in the point cloud. In at least one embodiment, the array storing voxel index values ​​210a-n is an array of length equal to the number of points in the point cloud.

[0027] In at least one embodiment, the voxelization module 204 identifies valid voxels that are to be generated, displayed, or activated on a display device. In at least one embodiment, a valid voxel is a voxel containing a plurality of points that meet or exceed a threshold number of points. For example, in at least one embodiment, if the threshold number of points is 5, then a valid voxel is a voxel containing 5 or more points. In at least one embodiment, the valid voxel number refers to the voxel ID of the valid voxel.

[0028] In at least one embodiment, each voxel index value in voxel index values ​​210a-n indicates a memory location where voxel IDs in voxel IDs 206a-n corresponding to voxel offsets in voxel offsets 205a-n are stored. In at least one embodiment, the voxel index value indicates a location or index number in an array where a data value is stored, wherein this location is used to access data in the corresponding memory location. In at least one embodiment, each of voxel index values ​​210a-n is a string of numbers and / or letters. In at least one embodiment, each of voxel index values ​​210a-n is not the output of a hash function, but rather a voxel ID identified by voxelization module 204 as associated with a point location, as further described herein. In at least one embodiment, voxelization module 204 receives and / or otherwise obtains data from voxelization hash table 208 for at least partially determining the number of points in each voxel and / or the mean characteristic value of each voxel, which herein is at least combined with Figure 3 Further description.

[0029] Figure 3 A block diagram of a system 300 according to at least one embodiment is shown. The system includes one or more processors, each including one or more circuits for performing one or more operations that cause the calculation of the number of points per voxel and / or the calculation of the mean eigenvalue per voxel using a voxelized hash table. In at least one embodiment, this is combined with... Figure 3One or more aspects of the described one or more embodiments are consistent with one or more embodiments described herein (including at least in combination). Figures 1-2 and Figures 4-6 The system 300 combines one or more aspects of the described aspects. In at least one embodiment, the system 300 includes one or more processors for performing one or more operations of the system 300. In at least one embodiment, the one or more processors performing one or more operations of the system 300 are any of the processors or combinations of processors described herein, including combinations of... Figure 13 The described CPU 1302, combined with Figure 10C Describing one or more accelerators 1014, combined Figure 17A The graphics processor 1710 described and combined with Figure 32 The described parallel processing unit (“PPU”) 3200. In at least one embodiment, system 300 includes one or more modules described herein, such as Figure 1 The neural network classification module 106. In at least one embodiment, one or more operations of the system 300 are related to... Figure 2 The system 200 is combined with one or more operations (such as calculating voxel offsets). In at least one embodiment, one or more operations of the system 300 are combined with Figure 4 The process 400 is combined with one or more operations (such as allocating memory locations using operation 401). In at least one embodiment, one or more operations of system 300 are combined with Figure 5 The process 500 combines one or more operations (such as inputting point cloud data into one or more APIs using operation 502). In at least one embodiment, one or more operations of system 300 are one or more operations of one or more APIs 610, such as using voxelization module 304 to calculate the number of points per voxel.

[0030] In at least one embodiment, voxelized hash table 308 is voxelized hash table 208, which is at least combined herein with Figure 2 To be described in more detail. In at least one embodiment, the voxelized hash table 308 is any data structure that associates points in a point cloud with voxel IDs, such as a linked list, tree graph, multidimensional tensor, or some combination thereof. In at least one embodiment, using the voxelized hash table 308 to associate data values ​​is also referred to as indexing, associating, or linking those data values.

[0031] In at least one embodiment, voxel offset 305a-n is voxel offset 205a-n, which is at least combined herein with Figure 2Further description. In at least one embodiment, the number of voxel offsets 305a-n is equal to the number of points in the point cloud. In at least one embodiment, the amount of memory used to store the data voxel offsets 305a-n of the voxelized hash table 308 is equal to the number of points in the point cloud.

[0032] In at least one embodiment, voxel index 310a-n is voxel index 310a-n, which is at least combined herein with Figure 2 Further description. In at least one embodiment, the number of voxel index values ​​310a-n is equal to the number of points in the point cloud. In at least one embodiment, the amount of memory used to store the data voxel index values ​​310a-n of the voxelized hash table 308 is equal to the number of points in the point cloud.

[0033] In at least one embodiment, voxelization module 304 is voxelization module 204, which is at least combined herein with Figure 2 Further description. In at least one embodiment, the voxelization module 304 generates Figure 2 The voxel offsets 205a-n and voxel IDs 206a-n. In at least one embodiment, for each point in the point cloud, the voxelization module 304 identifies the specific voxel ID of the voxel contained in the point by looking up the corresponding voxel index (hash value or corresponding value) in the voxelization hash table using the voxel offset (key) representing the point.

[0034] In at least one embodiment, the voxelization module 304 calculates the number of points per voxel in the voxel grid. In at least one embodiment, the voxelization module 304 allocates memory locations to load / store the number of points in each voxel, wherein such memory locations are collectively referred to as output space and are represented as output_space in pseudocode. In at least one embodiment, for each point represented by one of voxel offsets 305a-n, the voxelization module 304 identifies the corresponding voxel ID containing this point using voxel index values ​​310a-n. In at least one embodiment, the voxelization module 304 counts the number of points and / or voxel offsets 305a-n for each voxel ID identified in the voxelization hash table 308. In at least one embodiment, by counting the number of points and / or voxel offsets 305a-n associated with each voxel ID, the voxelization module 304 can generate and / or output the number of points for each voxel, such as the number of points per voxel 312a-n. In at least one embodiment, the voxelization module 304 loads / stores the number of points 312a-n per voxel in the output space. In at least one embodiment, the number of points 312a-n per voxel is at least partially used to calculate the mean eigenvalue 314a-n of each voxel.

[0035] In at least one embodiment, the voxelization module 304 identifies data values ​​for performing one or more operations to generate one or more feature values ​​for one or more voxels based on one or more data structures such as a voxelization hash table 308. In at least one embodiment, the feature of a point is any characteristic of the object at that point, represented as a numerical value. In at least one embodiment, point cloud data is augmented, labeled, or encoded with one or more features assigned to each point. In at least one embodiment, the feature of a point includes reflectivity, texture, color, or some combination thereof. In at least one embodiment, the mean feature of a voxel is the average feature value of all points within that voxel. For example, in at least one embodiment, the mean feature value of the intensity of a voxel is the average intensity value of all points in that voxel. In at least one embodiment, the feature of a point is the location (positioning) information of that point within the voxel. For example, in at least one embodiment, the mean feature of the point location of a voxel is the average location of all points within the voxel. In at least one embodiment, the mean feature of the color of a voxel is the average color value of all points in that voxel.

[0036] In at least one embodiment, the eigenvalues ​​of the voxels are mean eigenvalues, also referred to as mean features. In at least one embodiment, the voxelization module 304 calculates one or more mean eigenvalues ​​314a-n per voxel. In at least one embodiment, the voxelization module 304 uses, at least in conjunction with herein, Figure 2 The voxelization hash table is further described to calculate the mean feature value of only those voxels that are valid voxels. In at least one embodiment, the mean feature value per voxel is one or more values ​​indicating the average feature value of each voxel containing points. In at least one embodiment, the feature value is referred to as a feature. In at least one embodiment, the point cloud includes one or more features for each point in the point cloud. In at least one embodiment, the voxelization module 304 calculates the mean feature value 314a-n per voxel using its calculation of the number of points 312a-n per voxel. In at least one embodiment, the voxelization module 304 calculates the mean feature value of the voxel by summing all the values ​​of a type of feature assigned to each point in the voxel and dividing this total by the total number of points in the voxel. In at least one embodiment, other averaging techniques, such as weighted averages, are used. In at least one embodiment, the voxelization module 304 loads / stores each value (mean) of the mean feature value 314a-n per voxel in the output space.

[0037] In at least one embodiment, the values ​​loaded / stored in the output space (such as the number of points per voxel 312a-n and the mean feature value per voxel 314a-n) are further processed to output a voxel representation of the point cloud on a display. For example, in at least one embodiment, the values ​​loaded / stored in the output space are used to display voxels having a certain color, texture, transparency, or some combination thereof.

[0038] Figure 4 A block diagram is shown of a process 400, according to at least one embodiment, for causing a processor to perform one or more operations to generate a voxel representation of a point cloud representation of an environment. In at least one embodiment, this is combined with Figure 4 One or more aspects of the described one or more embodiments are consistent with one or more embodiments described herein (including at least in combination). Figures 1-3 and Figures 5-6 The process 400 is a combination of one or more aspects described herein. In at least one embodiment, one or more processors perform one or more operations of the process 400. In at least one embodiment, the one or more processors performing one or more operations of the process 400 are any of the processors or combinations of processors described herein, including combinations of... Figure 1 Describing one or more processors 102, combined Figure 13 The described CPU 1302, combined with Figure 10C Describing one or more accelerators 1014, combined Figure 17A The graphics processor 1710 described and combined with Figure 32 The described parallel processing unit (“PPU”) 3200. In at least one embodiment, one or more processors 102 execute one or more operations of process 400, such as mapping points to voxels using operation 402. In at least one embodiment, one or more operations of process 400 are Figure 2 One or more operations of system 200, such as the load / store voxel offset of operation 404. In at least one embodiment, one or more operations of process 400 are related to... Figure 3 The system 300 is combined with one or more operations (such as calculating the feature mean using operation 408). In at least one embodiment, one or more operations of process 400 are combined with Figure 5 The process 500 combines one or more operations (such as inputting point cloud data into one or more APIs using operation 502). In at least one embodiment, one or more operations of the process 400 are one or more operations of one or more APIs 610, such as loading / storing voxel offsets of operation 404.

[0039] In at least one embodiment, the processor begins process 400 with operation 401, which involves performing an operation to allocate memory locations for one or more data storage devices. In at least one embodiment, allocating memory locations using process 400 is referred to as initialization. In at least one embodiment, the processor allocates memory locations for one or more data storage devices to store data for one or more arrays, as further described herein. In at least one embodiment, the operation includes allocating memory locations to store an array (or other tensor) of voxel grid resolution information, such as voxel size. In at least one embodiment, the array of voxel grid resolution information includes three-dimensional values, such as the height, width, and depth of the voxel grid. In at least one embodiment, the voxel grid contains all the points of a point cloud. In at least one embodiment, voxel grid resolution refers to the number of voxels suitable for use within a voxel grid in a given dimension (height, width, depth). In at least one embodiment, the array of voxel grid resolution information is identified in pseudocode using a name such as voxel_size.

[0040] In at least one embodiment, operation 401 includes the processor allocating memory locations to store an array (or other tensor) of point cloud data. In at least one embodiment, the point cloud data includes the number of points, the coordinates of each point, features of each point, or some combination thereof. In at least one embodiment, the array of point cloud data is identified in pseudocode using a name such as point_cloud. In at least one embodiment, the processor allocates one or more memory locations (such as buffers) to store aspects of the point cloud data, such as the coordinates of points, features of each point, or some combination thereof.

[0041] In at least one embodiment, operation 401 includes the processor allocating memory locations to store arrays (or other tensors) of voxel IDs and / or mean eigenvalues, which are at least combined herein with Figure 3 Further description. In at least one embodiment, the array of voxel IDs and / or mean feature values ​​is identified in the pseudocode using a name such as output_space.

[0042] In at least one embodiment, operation 401 includes the processor allocating a memory location to store data of the voxelized hash table, which is at least in conjunction with the following herein: Figures 1-3 and Figures 5-6Further description. In at least one embodiment, the amount of memory location allocated for the voxelized hash table is at least twice the number of points in the point cloud. In at least one embodiment, the array used to store the data of the voxelized hash table is identified in pseudocode using a name such as hash_table. In at least one embodiment, the array of voxelized hash tables stores voxel offset values ​​in the array, identified in pseudocode using a name such as voxel_offset.

[0043] In at least one embodiment, once a memory location has been allocated in the data storage device using operation 401, the processor performs operations that cause the processor to calculate one or more voxel offsets (these operations are combined herein at least in the following ways). Figure 2 (Further description) Operation 402 continues process 400. In at least one embodiment, the processor performs operations for mapping each point of the point cloud to a voxel in a voxel mesh, as described herein in at least the following combination. Figure 1 Further description. In at least one embodiment, the function that maps each point of the point cloud to a voxel in the voxel mesh is identified in pseudocode by a name such as map_point_to_voxel(). In at least one embodiment, the processor uses a function such as map_point_to_voxel() to compute the voxel offset for each point based on the 3D coordinates of each point and information about the resolution of the voxel mesh stored in voxel_size. In at least one embodiment, the processor stores the voxel offset values ​​in an array such as voxel_offset. In at least one embodiment, operation 402 includes the processor performing an operation to compute the voxel index value for each voxel offset, which is at least in conjunction with... Figure 2 Further description.

[0044] In at least one embodiment, the processor continues process 400 by performing operation 404, which causes the processor to perform operations that load / store voxel offsets and voxel index values ​​in a voxelized hash table, which is at least in conjunction with the present document. Figure 2 Further description. In at least one embodiment, the processor loads / stores an entry corresponding to each point in the point cloud in a voxelized hash table by pairing keys and values ​​(key, value) using arrays voxel_offset and voxel_idx (voxel_offset, voxel_idx). In at least one embodiment, the processor uses the voxelized hash table to associate a voxel ID with a point in the point cloud using a voxel offset and a voxel index value, the voxel index value being an indication of the memory location where the corresponding voxel ID is stored or to be stored.

[0045] In at least one embodiment, the processor continues process 400 by performing operation 406, which causes the processor to load / store the sum of point feature values ​​for each voxel and the number of points in each voxel into an array such as output_space. In at least one embodiment, the processor iterates over one or more point locations stored in a voxelized hash table to partially generate the sum of feature values ​​in each voxel. In at least one embodiment, the processor iterates over point locations in the voxelized hash table to identify point locations that share a common voxel ID stored in this voxelized hash table, and thus identify points. In at least one embodiment, the processor iterates over point locations in the voxelized hash table to identify data values ​​(such as point feature values ​​of points) corresponding to those point locations, and generates the sum of feature values ​​for each voxel. In at least one embodiment, the processor stores one or more data values ​​indicating features associated with one or more point locations in one or more memory locations (such as buffers) that are to be accessed at least in part based on data stored in one or more data structures such as hash tables. In at least one embodiment, the point feature values ​​identified as being associated with a voxel ID are loaded / stored in an array such as output_space, and then summed by voxel ID and loaded / stored in output_space. In at least one embodiment, different types of feature values ​​are weighted differently before being summed by the processor. In at least one embodiment, the processor calculates the sum of all feature values ​​in each voxel based at least in part on repeatedly computing the voxel offset for each point in the point cloud, so as to store an ordered array or queue of voxel offsets for sequential lookup of the corresponding voxel ID using a voxelized hash table. In at least one embodiment, the processor looks up voxel IDs corresponding to different voxel offsets in parallel. In at least one embodiment, for each voxel ID, the processor identifies the individual points in the point cloud within that voxel ID using the corresponding voxel offset. In at least one embodiment, once the processor has identified the individual points in each voxel ID, the processor can identify the feature values ​​of these individual points by accessing the point cloud data and / or point feature values ​​stored in a buffer, and sum these point feature values ​​and store them in an array such as output_space. In at least one embodiment, also utilizing operation 406, the processor calculates the number of points per voxel ID based on its identification of the individual points mapped to each voxel ID. In at least one embodiment, atomic operations and / or functions (such as those represented in pseudocode as atomicADD, atomicINC, etc.) are used to calculate the number of points mapped to each voxel ID.

[0046] In at least one embodiment, the processor continues process 400 by operation 408, which calculates the mean eigenvalue of each voxel using values ​​loaded / stored in an array such as output_space. In at least one embodiment, the processor calculates the mean eigenvalue of the voxel by summing the eigenvalues ​​of the voxels and dividing the sum by the number of points in that voxel, which will be at least combined herein with Figure 3 Further description. In at least one embodiment, the processor uses the mean feature value to generate, display, or otherwise activate voxels that exhibit the mean feature value on a display device.

[0047] Figure 5 A block diagram is shown of a process 500 for executing an API function using a processor according to at least one embodiment, the API function causing one or more processors to perform a voxelization operation using a voxelized hash table and as otherwise described herein. In at least one embodiment, the voxelization operation is incorporated herein by reference to... Figure 5 One or more aspects of the described one or more embodiments are consistent with one or more embodiments described herein (including at least in combination). Figures 1-4 and Figure 6 The described embodiments are combined with one or more aspects. In at least one embodiment, one or more processors execute one or more operations of process 500. In at least one embodiment, the one or more processors executing one or more operations of process 500 are any of the processors or combinations of processors described herein, including combinations of... Figure 1 Describing one or more processors 102, combined Figure 13 The described CPU 1302, combined with Figure 10C Describing one or more accelerators 1014, combined Figure 17A The graphics processor 1710 described and combined with Figure 32 The described parallel processing unit (“PPU”) 3200. In at least one embodiment, processor 102 executes one or more operations of process 500, such as executing an API voxelization function using a voxelized hash table with operation 504. In at least one embodiment, one or more operations of process 500 are Figure 2 One or more operations of system 200, such as using operation 502 to input point cloud data or its indication into one or more APIs. In at least one embodiment, one or more operations of process 500 are related to... Figure 3The system 300 combines one or more operations (such as those of the voxelization module 304). In at least one embodiment, one or more operations of process 500 are one or more operations of process 400, such as calculating voxel offsets in operation 404. In at least one embodiment, one or more operations of process 500 are one or more operations of API 610, such as executing one or more API voxelization functions in operation 504.

[0048] In at least one embodiment, the user (or application) initiates process 500 by inputting point cloud data or its indication into an API function to perform operation 502. In at least one embodiment, this document at least incorporates Figure 6 Further description of the API function. In at least one embodiment, the API function is part of an API library (such as NVIDIA® CUDA® and AMD® ROCm®) for performing AI operations. In at least one embodiment, the user interface is a mobile application, website, customer portal, AI-assisted conversational user interface, or some combination thereof. In at least one embodiment, the user causes the processor to automatically input point cloud data into the API function, such as based on data installed in an autonomous vehicle (such as in conjunction with...). Figure 10A The autonomous vehicle (1000) described uses sensors to stream point cloud data.

[0049] In at least one embodiment, the processor continues process 500 with operation 504 by causing one or more API voxelization functions to be executed using a voxelized hash table. In at least one embodiment, the API voxelization function is a hash function. In at least one embodiment, the API voxelization function allocates memory locations in one or more data storage locations, as at least in conjunction with the above. Figure 4 Further description. In at least one embodiment, the API voxelization function is map_point_to_voxel(), as described herein in at least one... Figure 4 Further description. In at least one embodiment, the API voxelization function inserts entries into a voxelization hash table, as described herein at least in conjunction with... Figure 4 Further description. In at least one embodiment, the API voxelization function sums all feature points and calculates the total number of points in each voxel, as described herein in at least [the following context is missing]. Figure 4 Further description. In at least one embodiment, the API voxelization function computes the mean feature of each effective voxel, as described herein in at least the following way: Figure 4 Further description.

[0050] In at least one embodiment, the processor continues process 500 via operation 506 using a voxel representation based on the point cloud data output environment. In at least one embodiment, the processor uses the mean feature of each valid voxel and, as additionally as described herein, at least combines... Figure 2 The described operation is used to perform an action that causes one or more valid voxels to be generated, displayed, or activated on a display device.

[0051] Figure 6 A block diagram of a driver and / or runtime according to at least one embodiment is shown, the driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs). In at least one embodiment, any processor or combination of processors executes one or more APIs 610, including Figure 1 One or more processors 102, combined Figure 13 The described CPU 1302, combined with Figure 17A The graphics processor 1710 described, and combined with Figure 32 The parallel processing unit (“PPU”) 3200 is described herein. In at least one embodiment, one or more APIs 610 are further described herein. In at least one embodiment, a call to one or more APIs 610 causes execution Figures 1-3 Any one or more operations of any one or more modules. In at least one embodiment, a call to one or more APIs 610 causes the processor to perform a combination Figures 1-5 Any one or more of the described operations are to be performed. In at least one embodiment, one or more APIs 610 receive point cloud data or its indication as input, and cause... Figure 1 The voxelization module 104 performs operations that partially use a voxelized hash table to voxelize the point cloud representation of the environment. In at least one embodiment, one or more APIs 610 receive point cloud data or their indications and cause the voxelization module 204 to perform one or more operations for loading / storing voxel offsets into the voxelized hash table. In at least one embodiment, invocation of one or more APIs 610 causes the processor to perform one or more operations of the voxelization module 304, such as calculating the feature mean of each voxel in the voxel grid. In at least one embodiment, in Figure 4 Process 400 and Figure 5 The process 500 describes one or more operations that will be performed by the processor when one or more APIs 610 are invoked.

[0052] In at least one embodiment, software program 602 is a software module. In at least one embodiment, software program 602 includes one or more software modules. In at least one embodiment, one or more APIs 610 are software instruction sets that, when executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 610 are distributed or otherwise provided as part of one or more libraries 606, runtimes 604, drivers 604, and / or any other grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 610 perform one or more computational operations in response to a call to software program 602. In at least one embodiment, software program 602 is a collection of software code, commands, instructions, or other text sequences for instructing a computing device to perform one or more computational operations and / or to call one or more other instruction sets (e.g., API 610 or one or more functions 612) to be executed. In at least one embodiment, the functionality provided by one or more APIs 610 includes software functions, such as those that can be used to accelerate one or more portions of software program 602 using one or more parallel processing units (PPUs) (e.g., graphics processing units (GPUs)). In at least one embodiment, the software program is a compiler.

[0053] In at least one embodiment, API 610 is a hardware interface to one or more circuits for performing one or more computational operations. In at least one embodiment, one or more software APIs 610 described herein are implemented as one or more circuits for performing one or more techniques described herein. In at least one embodiment, one or more software programs 602 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform one or more techniques described herein.

[0054] In at least one embodiment, software program 602 (e.g., user-implemented software program) utilizes one or more application programming interfaces (APIs) 610 to perform various computational operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computational operation performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more APIs 610 provide a set of callable functions 612 (referred to herein as APIs, API functions, and / or functions), each performing one or more computational operations, such as computational operations related to parallel computing. For example, in one embodiment, one or more APIs 610 provide one or more functions 612 for causing a scheduler to schedule instructions to be executed by these processors based on the latency of the interconnect coupled to these processors. In at least one embodiment, one or more APIs 610 provide one or more functions 612, which are one or more neural networks, such as those trained to classify objects in an image and... Figure 1 The neural network is implemented on the neural network classification module 106.

[0055] In at least one embodiment, one or more software programs 602 interact with or otherwise communicate with one or more APIs 610 to perform one or more computational operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computational operations using one or more PPUs include at least one or more sets of computational operations that are accelerated at least in part by being performed by said one or more PPUs. In at least one embodiment, one or more software programs 602 interact with one or more APIs 610 to facilitate parallel computation using remote or local interfaces.

[0056] In at least one embodiment, the interface is software instructions that, when executed, provide access to one or more functions 612 provided by one or more APIs 610. In at least one embodiment, when a software developer compiles one or more software programs 602 in conjunction with one or more libraries 606 that include or otherwise provide access to one or more APIs 610, the software program 602 uses the native interface. In at least one embodiment, one or more software programs 602 are statically compiled in conjunction with pre-compiled libraries 606 that include instructions for executing one or more APIs 610 or uncompiled source code. In at least one embodiment, one or more software programs 602 are dynamically compiled, and the one or more software programs are linked to one or more pre-compiled libraries 606 that include one or more APIs 610 using a linker.

[0057] In at least one embodiment, when a software developer executes a software program that utilizes a library 606 including one or more APIs 610 or otherwise communicates with it via a network or other remote communication medium, the software program 602 uses a remote interface. In at least one embodiment, the library 606 including one or more APIs 610 will be executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the library 606 including one or more APIs 610 will be executed by any other computing host that provides the one or more APIs 610 to the software program 602.

[0058] In at least one embodiment, a processor executing or using one or more software programs 602 calls, uses, executes, or otherwise implements one or more APIs 610 to allocate and otherwise manage memory to be used by the software programs 602. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 to allocate and otherwise manage memory to be used by one or more portions of the software programs 602, which are accelerated using one or more PPUs such as GPUs or any other accelerators or processors further described herein. These software programs 602 may be executed by one or more processors at least in part based on latency of the interconnect coupled to one or more processors using one or more functions 612 provided by one or more APIs 610 in the embodiments.

[0059] In at least one embodiment, API 610 is an API for facilitating parallel computing. In at least one embodiment, API 610 is any other API further described herein. In at least one embodiment, API 610 is provided by a driver and / or runtime 604. In at least one embodiment, API 610 is provided by a CUDA user-mode driver. In at least one embodiment, API 610 is provided by a CUDA runtime. In at least one embodiment, driver 604 is a data value and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 612 of API 610 during the loading and execution of one or more portions of software program 602. In at least one embodiment, runtime 604 is a data value and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 612 of API 610 during the execution of software program 602. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 implemented by a driver and / or runtime 604 or otherwise provided to perform combined arithmetic operations by the one or more software programs 602 during execution by one or more PPUs (e.g., GPUs).

[0060] In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by a driver and / or runtime 604 to perform combinatorial arithmetic operations for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more APIs 610 provide combinatorial arithmetic operations via a driver and / or runtime 604, as described above. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by a driver and / or runtime 604 to allocate or otherwise reserve one or more blocks of memory 614 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by a driver and / or runtime 604 to allocate or otherwise reserve blocks of memory. In at least one embodiment, one or more APIs 610 are used to perform combinatorial mathematical functions as described herein.

[0061] In at least one embodiment, to improve the availability of software program 602 and / or optimize one or more portions of said software program 602 that will be accelerated by one or more PPUs such as a GPU, one or more APIs 610 provide one or more API functions 612 to perform a scheduling system that can be used by or by one or more computing devices as described herein. In at least one embodiment, the processor executes one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the processor uses the APIs to cause the scheduler to select a thread selection mechanism and / or otherwise perform the operations described herein. In at least one embodiment, the APIs invoke the scheduler to induce resource allocation. In at least one embodiment, the processor uses exemplary APIs to schedule one or more instructions for execution by one or more processors, at least in part, based on latency coupled to one or more interconnects of one or more processors.

[0062] In at least one embodiment, memory 614 is system memory 1704 of computing system 1700. In at least one embodiment, memory 614 is any form of hardware for storing data and is referred to as a storage device or data storage device. In at least one embodiment, memory 614 stores combined with Figure 4 Data of any one or more arrays described. In at least one embodiment, memory 614 stores data as combined with... Figure 2 Descriptions and data of voxelized hash tables as otherwise described herein. In at least one embodiment, memory 614 stores data used in the various operations described herein, including... Figure 1 The weights of the neural network in the neural network classification module 106 Figure 2 voxel ID 206a-n Figure 3 The mean eigenvalue of each voxel is 314a-n. Figure 4 Operation 404 voxel index value, and using Figure 5 Operation 502 inputs point cloud data into one or more APIs.

[0063] In at least one embodiment, memory 614 is a computer-readable storage medium and / or code stored on said computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, it can be used to perform operations related to... Figure 1At least some of the computer-readable instructions of the described operations are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transient computer-readable medium does not necessarily include a non-transient data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, memory 614 is implemented as a non-transient computer-readable storage medium storing executable instructions that, if executed by one or more processors of a computer system, cause the computer system to infer, as at least in conjunction with this document... Figures 1-6 Further description of the computer system architecture design.

[0064] logic Figure 7A Logic 715 is illustrated. As described elsewhere herein, logic 715 can be used in one or more devices to perform operations such as those discussed herein, according to at least one embodiment. In at least one embodiment, logic 715 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 715 is inference and / or training logic. The following is in conjunction with... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic for providing the functions or operations described herein, wherein the logic may collectively or individually be embodied as part of a circuit forming part of a larger system (e.g., an integrated circuit (IC), a system-on-a-chip (SoC), or one or more processors (e.g., a CPU, a GPU)).

[0065] In at least one embodiment, logic 715 may include, but is not limited to, code and / or data storage 701 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 701 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 701 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters using aspects of one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 701 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0066] In at least one embodiment, any portion of the code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 701 may be a cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 701 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, may depend on the on-chip versus off-chip available storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0067] In at least one embodiment, logic 715 may include, but is not limited to, code and / or data storage 705 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in one or more aspects of the embodiments. In at least one embodiment, during training and / or inference using one or more aspects of the embodiments, code and / or data storage 705 stores weight parameters and / or input / output data for each layer of the neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, an arithmetic logic unit (ALU)). In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 705 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 705 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0068] In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be separate storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be the same storage structure. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 701 and code and / or data storage 705 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0069] In at least one embodiment, logic 715 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 710 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 720, which are functions of input / output and / or weight parameter data stored in code and / or data storage 701 and / or code and / or data storage 705. In at least one embodiment, activations stored in activation storage 720 are generated based on linear algebra and / or matrix-based mathematics performed by ALU 710 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data storage 705 and / or code and / or data storage 701 are used as operands, and other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, may be stored in code and / or data storage 705 or code and / or data storage 701 or other on-chip or off-chip memory.

[0070] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 710, while in another embodiment, one or more ALUs 710 may be external to the processor or other hardware logic device or the circuitry that uses them (e.g., a coprocessor). In at least one embodiment, the ALUs 710 may be included within an execution unit of a processor, or otherwise included in an ALU bank accessible by the execution unit of the processor, which may be within the same processor or distributed among different types of processors (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 701, code and / or data storage 705, and activation storage 720 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 720 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0071] In at least one embodiment, the active memory 720 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 720 may be entirely or partially located within or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 720 is internal to or external to the processor, for example, or including DRAM, SRAM, flash memory, or certain other memory types, may depend on the available on-chip versus off-chip memory, the latency requirements for performing training and / or inference functions, the batch size of the data used in inference and / or training the neural network, or some combination of these factors.

[0072] In at least one embodiment, Figure 7A The logic 715 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor from Intel (e.g., “Lake Crest”). In at least one embodiment, Figure 7A The logic 715 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”).

[0073] Figure 7B A logic 715 according to at least one embodiment is illustrated. In at least one embodiment, the logic 715 is inference and / or training logic. In at least one embodiment, the logic 715 may include, but is not limited to, hardware logic, wherein computational resources, along with weight values ​​or other information corresponding to one or more layers of neurons within a neural network, are used dedicatedly or otherwise exclusively. In at least one embodiment, Figure 7B The logic 715 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor from Intel (e.g., “Lake Crest”). In at least one embodiment, Figure 7B The logic 715 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, logic 715 includes, but is not limited to, code and / or data storage 701 and code and / or data storage 705, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 7B In at least one embodiment shown, each of code and / or data storage 701 and code and / or data storage 705 is associated with dedicated computing resources (e.g., computing hardware 702 and computing hardware 706), respectively. In at least one embodiment, each of computing hardware 702 and computing hardware 706 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) on the information stored in code and / or data storage 701 and code and / or data storage 705, respectively, with the results stored in active storage 720.

[0074] In at least one embodiment, each of the code and / or data storage 701 and 705 and the corresponding computing hardware 702 and 706 corresponds to a different layer of the neural network, such that an activation obtained from one storage / computation pair 701 / 702 of the code and / or data storage 701 and computing hardware 702 is provided as input to the next storage / computation pair 705 / 706 of the code and / or data storage 705 and computing hardware 706, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 701 / 702 and 705 / 706 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) may be included in logic 715 after or in parallel with the storage / computation pairs 701 / 702 and 705 / 706.

[0075] Neural network training and deployment Figure 8 Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 806 is trained using a training dataset 802. In at least one embodiment, the training framework 804 is the PyTorch framework, while in other embodiments, the training framework 804 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 804 trains the untrained neural network 806 and allows it to be trained using the processing resources described herein to generate a trained neural network 808. In at least one embodiment, weights may be selected randomly or pre-trained using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0076] In at least one embodiment, supervised learning is used to train an untrained neural network 806, wherein the training dataset 802 includes inputs paired with desired outputs for input, or wherein the training dataset 802 includes inputs with known outputs and the outputs of the neural network 806 are manually graded. In at least one embodiment, the untrained neural network 806 is trained in a supervised manner and processes inputs from the training dataset 802, comparing the resulting outputs with a set of expected or desired outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 806. In at least one embodiment, a training framework 804 adjusts the weights controlling the untrained neural network 806. In at least one embodiment, the training framework 804 includes tools for monitoring the degree to which the untrained neural network 806 converges to a model (such as a trained neural network 808) suitable for generating correct answers (such as result 814) based on input data (such as a new dataset 812). In at least one embodiment, the training framework 804 repeatedly trains the untrained neural network 806 while adjusting the weights to refine the output of the untrained neural network 806 using a loss function and tuning algorithms such as stochastic gradient descent. In at least one embodiment, the training framework 804 trains the untrained neural network 806 until the untrained neural network 806 reaches the desired accuracy. In at least one embodiment, the trained neural network 808 can then be deployed to implement any number of machine learning operations.

[0077] In at least one embodiment, unsupervised learning is used to train an untrained neural network 806, wherein the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 802 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 806 can learn groupings within the training dataset 802 and can determine how each input relates to the untrained dataset 802. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 808, which is capable of performing operations useful for reducing the dimensionality of a new dataset 812. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 812 that deviate from the normal patterns of the new dataset 812.

[0078] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 802. In at least one embodiment, the training framework 804 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 808 to adapt to a new dataset 812 without forgetting the knowledge injected into the trained neural network 808 during initial training.

[0079] In at least one embodiment, the training framework 804 is a framework that incorporates processing via a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is, for example, a toolkit developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes or uses logic 715 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0080] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations, such as human visual simulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0081] In at least one embodiment, OpenVINO supports neural network models for a variety of tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image inpainting, style transfer, motion recognition, colorization, and / or variations thereof.

[0082] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes the neural network model for execution on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's input (e.g., adjusting the size of the model's input), modifying the size of the model's input (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalizing, standardizing, quantizing (e.g., converting the model's weights from a first representation such as floating-point to a second representation such as integer), and / or variants thereof.

[0083] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to infer input data. In at least one embodiment, the inference engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0084] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computational processes and / or systems utilizing one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or portions of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., executing a first set of layers on a first device (e.g., a GPU) and a second set of layers on a second device (e.g., a CPU).

[0085] In at least one embodiment, OpenVINO includes various functionalities similar to those associated with CUDA programming models, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0086] Data Center Figure 9 An exemplary data center 900 in which at least one embodiment can be used is shown. In at least one embodiment, the data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0087] In at least one embodiment, such as Figure 9As shown, the data center infrastructure layer 910 may include a resource coordinator 912, grouped computing resources 914, and node computing resources (“nodes CR”) 916(1)-916(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 916(1)-916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 918(1)-918(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more of nodes CR 916(1)-916(N) may be servers having one or more of the aforementioned computing resources.

[0088] In at least one embodiment, the grouped computing resources 914 may include individual groups of node CRs housed within one or more racks (not shown), or a plurality of racks housed within data centers (also not shown) in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resources 914 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0089] In at least one embodiment, resource coordinator 912 may be configured or otherwise control one or more nodes CR 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource coordinator 912 may include a Software Design Infrastructure (“SDI”) management entity for data center 900. In at least one embodiment, resource coordinator 912 may include hardware, software, or some combination thereof.

[0090] In at least one embodiment, such as Figure 9As shown, framework layer 920 includes job scheduler 922, configuration manager 924, resource manager 926, and distributed file system 928. In at least one embodiment, framework layer 920 may include a framework of software 932 supporting software layer 930 and / or one or more applications 942 supporting application layer 940. In at least one embodiment, software 932 or application 942 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 920 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark") which can utilize distributed file system 928 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 922 may include Spark drivers for facilitating the scheduling of workloads supported by the various layers of data center 900. In at least one embodiment, configuration manager 924 may be able to configure different layers, such as software layer 930 and framework layer 920 including Spark and distributed file system 928 for supporting large-scale data processing. In at least one embodiment, resource manager 926 may be able to manage clustered or grouped computing resources mapped to or allocated to support distributed file system 928 and job scheduler 922. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 914 at data center infrastructure layer 910. In at least one embodiment, resource manager 926 may coordinate with resource coordinator 912 to manage these mapped or allocated computing resources.

[0091] In at least one embodiment, the software 932 included in the software layer 930 may include software used by at least portions of nodes CR 916(1)-916(N), grouped computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0092] In at least one embodiment, one or more applications 942 included in application layer 940 may include one or more types of applications used by at least portions of nodes CR 916(1)-916(N), grouped computing resources 914, and / or the distributed file system 928 of framework layer 920. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0093] In at least one embodiment, any of the configuration manager 924, resource manager 926, and resource coordinator 912 can implement any amount and type of self-modification movement based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification movement can mitigate potentially poor configuration decisions by data center operators of data center 900 and can avoid underutilization and / or poor performance of the data center.

[0094] In at least one embodiment, data center 900 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 900. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 900 by using weight parameters calculated through one or more training techniques described herein.

[0095] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0096] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7BDetails regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in data center 900 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0097] In at least one embodiment, at least one component shown or described with respect to Figures 7-9 is used to achieve the connection. Figure 1-6 The described techniques and / or functions. In at least one embodiment, logic 715 is used to perform image classification using input data, which includes at least a voxel representation of the environment based on a data structure used to indicate voxels to be generated during the conversion of a point cloud into that voxel representation, such as in combination with... Figure 1 As described herein and elsewhere in this document.

[0098] Autonomous vehicles Figure 10A Examples of autonomous vehicles 1000 according to at least one embodiment are shown. In at least one embodiment, the autonomous vehicle 1000 (which may alternatively be referred to herein as "vehicle 1000") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle accommodating one or more passengers. In at least one embodiment, vehicle 1000 may be a semi-tractor-trailer truck for hauling goods. In at least one embodiment, vehicle 1000 may be an aircraft, robotic vehicle, or other type of vehicle.

[0099] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of that standard). In at least one embodiment, vehicle 1000 may be able to have one or more functions according to levels 1 to 5 of autonomous driving levels. For example, in at least one embodiment, vehicle 1000 may be able to have conditional automation (level 3), high automation (level 4), and / or full automation (level 5), depending on the embodiment.

[0100] In at least one embodiment, vehicle 1000 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1000 may include, but is not limited to, propulsion system 1050, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be connected to the drivetrain of vehicle 1000, which may include, but is not limited to, a transmission, for enabling propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving a signal from throttle / accelerator 1052.

[0101] In at least one embodiment, when the propulsion system 1050 is operating (e.g., when the vehicle 1000 is in motion), the steering system 1054 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1000 (e.g., along a desired path or route). In at least one embodiment, the steering system 1054 may receive signals from the steering actuator 1056. In at least one embodiment, for fully automated (Level 5) functionality, the steering wheel may be optional. In at least one embodiment, the brake sensor system 1046 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1048 and / or brake sensors.

[0102] In at least one embodiment, one or more controllers 1036 may include, but are not limited to, one or more systems-on-a-chip (“SoC”). Figure 10A(not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1000. For example, in at least one embodiment, one or more controllers 1036 may send signals to operate vehicle braking via brake actuator 1048, to operate steering system 1054 via one or more steering actuators 1056, and to operate propulsion system 1050 via one or more throttle / accelerators 1052. In at least one embodiment, one or more controllers 1036 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1000. In at least one embodiment, one or more controllers 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0103] In at least one embodiment, one or more controllers 1036 provide signals for controlling one or more components and / or systems of vehicle 1000 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from, for example, but not limited to, the following sensors: one or more Global Navigation Satellite System (“GNSS”) sensors 1058 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1060, one or more ultrasonic sensors 1062, one or more LIDAR sensors 1064, one or more inertial measurement unit (IMU) sensors 1066 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1096, one or more stereo cameras 1068, one or more wide-angle cameras 1070 (e.g., fisheye cameras), one or more infrared cameras 1072, one or more surround cameras 1074 (e.g., 360-degree cameras), remote cameras ( Figure 10A (not shown in the image), medium-range camera ( Figure 10A(not shown), one or more speed sensors 1044 (e.g., for measuring the speed of vehicle 1000), one or more vibration sensors 1042, one or more steering sensors 1040, one or more brake sensors (e.g., as part of brake sensor system 1046) and / or other sensor types.

[0104] In at least one embodiment, one or more controllers 1036 may receive input (e.g., represented by input data) from the dashboard 1032 of the vehicle 1000 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, a voice signaler, a speaker, and / or via other components of the vehicle 1000. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 10A The data includes (not shown), location data (e.g., the location of vehicle 1000, for example on a map), direction, the location of other vehicles (e.g., occupying a grid), information about objects, and the state of objects perceived by one or more controllers 1036. For example, in at least one embodiment, the HMI display 1034 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers that have been, are being, or will be made (e.g., changing lanes now, reaching exit 34B within two miles, etc.).

[0105] In at least one embodiment, vehicle 1000 further includes a network interface 1024 that can communicate over one or more networks using one or more wireless antennas 1026 and / or one or more modems. For example, in at least one embodiment, network interface 1024 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1026 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (“LPWAN”) (such as LoRaWAN, SigFox, etc. protocols).

[0106] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7BDetails regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in vehicle 1000 for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0107] Figure 10B The illustration shows an embodiment according to at least one of the embodiments. Figure 10A Examples of camera positions and fields of view for an autonomous vehicle 1000. In at least one embodiment, the camera and its respective field of view are exemplary embodiments and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1000.

[0108] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1000. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-to-clear-to-clear (“RCCC”) color filter array, a red-to-clear-to-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera having RCCC, RCCB, and / or RBGC color filter arrays, may be used to improve photosensitivity.

[0109] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0110] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D” printed) assembly, to remove stray light and reflected light from within the vehicle 1000 (e.g., reflected light from the dashboard reflected in the windshield mirror), which may interfere with the camera’s image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated into four pillars at each corner of the cabin.

[0111] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including portions of the environment in front of the vehicle 1000 can be used for surround view to help identify the path and obstacles ahead, and to assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path, with the help of one or more controllers 1036 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions such as traffic sign recognition.

[0112] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor” color imager. In at least one embodiment, a wide-angle camera 1070 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 10B Only one wide-angle camera 1070 is shown, but in other embodiments, the vehicle 1000 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 1098 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1098 can also be used for object detection and classification, as well as basic object tracking.

[0113] In at least one embodiment, any number of stereo cameras 1068 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1068 may include an integrated control unit comprising a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1000, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1068 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1000 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1068 may be used in addition to or instead of those described herein.

[0114] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including portions of the environment on the sides of the vehicle 1000 can be used for surround view, providing information for creating and updating the occupied grid, and generating a side impact collision warning. For example, in at least one embodiment, a surround camera 1074 (e.g., such as...) Figure 10B The four surround cameras shown can be positioned on vehicle 1000. In at least one embodiment, one or more surround cameras 1074 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of vehicle 1000. In at least one embodiment, vehicle 1000 can use three surround cameras 1074 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0115] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including portions of the environment behind the vehicle 1000 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as forward-looking cameras (e.g., long-range camera 1098 and / or mid-range camera 1076, stereo camera 1068, infrared camera 1072, etc.), as described herein.

[0116] Figure 10C This illustrates at least one embodiment. Figure 10AA block diagram of an exemplary system architecture for an autonomous vehicle 1000. In at least one embodiment, Figure 10C Each component, feature, and system of vehicle 1000 is shown as connected via bus 1002. In at least one embodiment, bus 1002 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network within vehicle 1000 used to assist in the control of various features and functions of vehicle 1000, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1002 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1002 can be read to locate steering wheel angle, ground speed, engine rotation speed ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1002 may be an ASIL B compliant CAN bus.

[0117] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, any number of buses forming bus 1002 may be present, including but not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1002 may communicate with any component of vehicle 1000, and two or more buses in bus 1002 may communicate with corresponding components. In at least one embodiment, each of any number of System-on-Chip (“SoC”) 1004 (e.g., SoC 1004(A) and SoC 1004(B)), each of one or more controllers 1036 and / or each computer within the vehicle can access the same input data (e.g., input from sensors of vehicle 1000) and can be connected to a common bus, such as a CAN bus.

[0118] In at least one embodiment, vehicle 1000 may include one or more controllers 1036, such as those described herein. Figure 10AAs described above. In at least one embodiment, controller 1036 can be used for a wide variety of functions. In at least one embodiment, controller 1036 can be coupled to any of various other components and systems of vehicle 1000 and can be used to control vehicle 1000, artificial intelligence of vehicle 1000, infotainment and / or other functions of vehicle 1000.

[0119] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of the SoCs 1004 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1006, a graphics processing unit (“one or more GPUs”) 1008, one or more processors 1010, one or more caches 1012, one or more accelerators 1014, one or more data storage 1016, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1004 may be used to control vehicle 1000 on a wide variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1004 may be combined with a high-definition (“HD”) map 1022 in a system (e.g., the system of vehicle 1000), which may be located from one or more servers via a network interface 1024. Figure 10C (Not shown in the image) Get map refresh and / or update.

[0120] In at least one embodiment, one or more CPUs 1006 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1006 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1006 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1006 may include four dual-core clusters, each with a dedicated L2 cache (e.g., 2 megabytes (MB) L2 cache). In at least one embodiment, one or more CPUs 1006 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, which allows any combination of clusters of one or more CPUs 1006 to be active at any given time.

[0121] In at least one embodiment, one or more CPUs 1006 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware blocks to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; power gating of each core independently; clock gating of each core cluster independently when all cores are clock-gated or power-gated; and / or power gating of each core cluster independently when all cores are power-gated. In at least one embodiment, one or more CPUs 1006 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state to be input for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein work is offloaded to the microcode.

[0122] In at least one embodiment, one or more GPUs 1008 may include an integrated GPU (which may alternatively be referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1008 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1008 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with at least 96 KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512 KB of storage capacity). In at least one embodiment, one or more GPUs 1008 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1008 may use one or more computation application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0123] In at least one embodiment, one or more GPU 1008s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPU 1008s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a scheduler (e.g., a thread bundle scheduler), or a sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, the streaming microprocessor may include separate parallel integer and floating-point data paths for employing a mixture of computation and addressing operations to provide efficient execution of workloads. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0124] In at least one embodiment, one or more GPUs 1008 may include high-bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, used in some examples to provide a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”), such as fifth-generation graphics double data rate type synchronous random access memory (“GDDR5”), may also be used.

[0125] In at least one embodiment, one or more GPUs 1008 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support can be used to allow one or more GPUs 1008 to directly access the page tables of one or more CPUs 1006. In at least one embodiment, when the memory management unit (“MMU”) of one or more GPUs 1008 experiences a miss, an address translation request can be sent to one or more CPUs 1006. In response, in at least one embodiment, two CPUs of one or more CPUs 1006 can look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 1008. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for the memory of both one or more CPUs 1006 and one or more GPUs 1008, thereby simplifying the programming of one or more GPUs 1008 and the porting of applications to one or more GPUs 1008.

[0126] In at least one embodiment, one or more GPUs 1008 may include any number of access counters that can track the frequency with which one or more GPUs 1008 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of sharing memory ranges among processors.

[0127] In at least one embodiment, one or more SoCs 1004 may include any number of caches 1012, including those described herein. For example, in at least one embodiment, one or more caches 1012 may include a Level 3 (“L3”) cache that can be used for both one or more CPUs 1006 and one or more GPUs 1008 (e.g., connected to one or more CPUs 1006 and one or more GPUs 1008). In at least one embodiment, one or more caches 1012 may include a write-back cache that can track the state of each row, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, depending on the embodiment, the L3 cache may include 4 MB of memory or more.

[0128] In at least one embodiment, one or more SoCs 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1008 and offload some tasks from one or more GPUs 1008 (e.g., to free up more cycles of one or more GPUs 1008 to perform other tasks). In at least one embodiment, one or more accelerators 1014 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0129] In at least one embodiment, one or more accelerators 1014 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, rapidly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for protection and / or safety-related events.

[0130] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1008, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1008 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1008 and / or one or more accelerators 1014.

[0131] In at least one embodiment, one or more accelerators 1014 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, a PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1038, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, a PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0132] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, depending on the embodiment, the RISC core may use any of a variety of protocols. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0133] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1006. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0134] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly perform programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0135] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Therefore, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general computer vision algorithms, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or different portions of an image. In at least one embodiment, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory for enhancing overall system security.

[0136] In at least one embodiment, one or more accelerators 1014 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1014. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0137] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0138] In at least one embodiment, one or more SoCs 1004 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to rapidly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0139] In at least one embodiment, one or more accelerators 1014 may have broad applications for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1000, PVA may be designed to run classical computer vision algorithms, as they can be efficient in object detection and integer mathematical operations.

[0140] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure reconstruction from motion, pedestrian recognition, lane detection, etc.) during operation. In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0141] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, for example, the PVA is used to perform time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0142] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks, whose output is a measurement of confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence values. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1066 related to vehicle 1000 orientation, distance, and object 3D position estimates obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1064 or one or more RADAR sensors 1060).

[0143] In at least one embodiment, one or more SoCs 1004 may include one or more data stores 1016 (e.g., memory). In at least one embodiment, one or more data stores 1016 may be on-chip memory of one or more SoCs 1004, which may store neural networks to be executed on one or more GPUs 1008 and / or DLAs. In at least one embodiment, one or more data stores 1016 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data stores 1016 may include one or more L2 or L3 caches.

[0144] In at least one embodiment, one or more SoCs 1004 may include any number of processors 1010 (e.g., embedded processors). In at least one embodiment, one or more processors 1010 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security execution. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1004 and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1004s, and / or power state management of one or more SoCs 1004s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1004s may use the ring oscillator to detect the temperature of one or more CPUs 1006s, one or more GPUs 1008s, and / or one or more accelerators 1014s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1004s into a lower power state and / or place the vehicle 1000 into a driver safe parking mode (e.g., bring the vehicle 1000 to a safe stop).

[0145] In at least one embodiment, one or more processors 1010 may further include a set of embedded processors that can be used as an audio processing engine. The audio processing engine may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0146] In at least one embodiment, one or more processors 1010 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, support for peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0147] In at least one embodiment, one or more processors 1010 may further include a secure cluster engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1010 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1010 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0148] In at least one embodiment, one or more processors 1010 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video playback applications to generate final images for video post-processing functions required by the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1070, one or more surround cameras 1074, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1004, the neural network being configured to recognize in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0149] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion in the video, denoising appropriately weights spatial information to reduce the weight of information provided by adjacent frames. In at least one embodiment, in the case where the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0150] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereoscopic shot frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing, and does not require one or more GPUs 1008 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1008 are powered and active for 3D rendering, the video image compositor can be used to offload one or more GPUs 1008 to improve performance and responsiveness.

[0151] In at least one embodiment, one or more SoCs of SoC 1004 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1004 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0152] In at least one embodiment, one or more SoCs of SoC 1004 may further include extensive peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1004 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1064, one or more RADAR sensors 1060, etc., which may be connected via Ethernet channels), data from bus 1002 (e.g., vehicle 1000 speed, steering wheel position, etc.), data from one or more GNSS sensors 1058 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1004 may further include dedicated high-performance large-scale memory controllers, which may include their own DMA engines and may be used to free one or more CPUs of SoC 1006 from routine data management tasks.

[0153] In at least one embodiment, one or more SoCs 1004 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for a flexible, reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1004 can be faster, more reliable, and even more energy- and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1014, when combined with one or more CPUs 1006, one or more GPUs 1008, and one or more data storage 1016, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0154] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0155] The embodiments described herein allow for the simultaneous and / or sequential execution of multiple neural networks and allow for the combination of results to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPU 1020s) may include text and word recognition, thereby allowing the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing a semantic understanding of the signs, and passing this semantic understanding to a path planning module running on a CPU complex.

[0156] In at least one embodiment, multiple neural networks can run simultaneously for driving levels 3, 4, or 5. For example, in at least one embodiment, a warning sign stating "Caution: flashing lights indicate icy conditions," along with the lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which informs the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1008.

[0157] In at least one embodiment, the CNN for face recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1000. In at least one embodiment, a normally open sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in safe mode, it can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1004 provide protection against theft and / or carjacking.

[0158] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1004 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, such as those identified by one or more GNSS sensors 1058. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1062, to execute emergency vehicle safety routines, such as slowing the vehicle, pulling the vehicle to the side of the road, stopping, and / or idling the vehicle until the emergency vehicle passes.

[0159] In at least one embodiment, vehicle 1000 may include one or more CPUs 1018 (e.g., one or more discrete CPUs or one or more dCPUs) coupled to one or more SoCs 1004 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 1018 may include, for example, x86 processors. One or more CPUs 1018 may be used to perform any of a variety of functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 1004, and / or monitoring the status and health of one or more controllers 1036 and / or the on-chip infotainment system (“infotainment SoC”) 1030. In at least one embodiment, one or more SoCs 1004 include one or more interconnects, and the interconnects may include peripheral component interconnects fast (PCIe).

[0160] In at least one embodiment, vehicle 1000 may include one or more GPUs 1020 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1004 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1020 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on inputs from sensors of vehicle 1000 (e.g., sensor data).

[0161] In at least one embodiment, vehicle 1000 may further include a network interface 1024, which may include, but is not limited to, one or more wireless antennas 1026 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1024 may be used to enable wireless connectivity to Internet cloud services (e.g., with servers and / or other network devices), with other vehicles, and / or with computing devices (e.g., passenger client devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 1000 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1000 with information about vehicles near vehicle 1000 (e.g., vehicles in front, to the side, and / or behind vehicle 1000). In at least one embodiment, the aforementioned functionality may be part of a cooperative adaptive cruise control function of vehicle 1000.

[0162] In at least one embodiment, network interface 1024 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1036 to communicate over a wireless network. In at least one embodiment, network interface 1024 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0163] In at least one embodiment, the vehicle 1000 may further include one or more data storage units 1028, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoC 1004) storage. In at least one embodiment, the one or more data storage units 1028 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0164] In at least one embodiment, the vehicle 1000 may further include one or more GNSS sensors 1058 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including, for example, but not limited to, GPS sensors using a USB connector with an Ethernet-to-serial interface (e.g., RS-232) bridge.

[0165] In at least one embodiment, vehicle 1000 may further include one or more RADAR sensors 1060. In at least one embodiment, one or more RADAR sensors 1060 may be used by vehicle 1000 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1060 may use a CAN bus and / or bus 1002 (e.g., for transmitting data generated by one or more RADAR sensors 1060) to control and access object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more RADAR sensors 1060 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the RADAR sensors 1060 are pulse Doppler RADAR sensors.

[0166] In at least one embodiment, one or more RADAR sensors 1060 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1060 can help distinguish between static and moving objects and can be used by the ADAS system 1038 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1060 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, employing six antennas, the four central antennas can create a focused beammap designed to record the surrounding environment of the vehicle 1000 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling them to quickly detect vehicles entering or leaving the lane of vehicle 1000.

[0167] In at least one embodiment, as an example, a mid-range RADAR system may include a range of up to 160m (front) or 80m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1060 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1038 for blind spot detection and / or lane change assistance.

[0168] In at least one embodiment, the vehicle 1000 may further include one or more ultrasonic sensors 1062. In at least one embodiment, one or more ultrasonic sensors 1062, which may be positioned at the front, rear, and / or sides of the vehicle 1000, may be used for parking assistance and / or creating and updating occupancy grids. In at least one embodiment, a wide variety of ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1062 may operate at the ASIL B functional safety level.

[0169] In at least one embodiment, vehicle 1000 may include one or more LiDAR sensors 1064. In at least one embodiment, one or more LiDAR sensors 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1064 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1000 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1064 that can use Ethernet channels (e.g., to provide data to a Gigabit Ethernet switch).

[0170] In at least one embodiment, one or more LiDAR sensors 1064 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1064 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 1064 may include small devices that can be embedded in the front, rear, side, and / or corner locations of a vehicle 1000. In at least one embodiment, one or more LiDAR sensors 1064, in such an embodiment, may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-mounted LiDAR sensors 1064 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0171] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the area around vehicle 1000 up to approximately 200m. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the propagation time of the laser pulse and the reflected light on each pixel, which in turn corresponds to the range from vehicle 1000 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1000. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0172] In at least one embodiment, the vehicle 1000 may further include one or more IMU sensors 1066. In at least one embodiment, one or more IMU sensors 1066 may be located at the center of the rear axle of the vehicle 1000. In at least one embodiment, one or more IMU sensors 1066 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1066 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1066 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0173] In at least one embodiment, one or more IMU sensors 1066 can be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1066 enable vehicle 1000 to estimate its heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1066, without requiring input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1066 and one or more GNSS sensors 1058 can be combined in a single integrated unit.

[0174] In at least one embodiment, vehicle 1000 may include one or more microphones 1096 placed inside and / or around vehicle 1000. In at least one embodiment, one or more microphones 1096 may be used for emergency vehicle detection and identification.

[0175] In at least one embodiment, vehicle 1000 may further include any number of camera types, including one or more stereo cameras 1068, one or more wide-angle cameras 1070, one or more infrared cameras 1072, one or more surround cameras 1074, one or more long-range cameras 1098, one or more mid-range cameras 1076, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1000. In at least one embodiment, the type of camera used depends on vehicle 1000. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1000. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1000 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may support, by way of example but not limited to, gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, references previously made herein... Figure 10A and Figure 10B Each camera is described in more detail.

[0176] In at least one embodiment, the vehicle 1000 may further include one or more vibration sensors 1042. In at least one embodiment, the one or more vibration sensors 1042 may measure vibrations of components of the vehicle 1000 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1042 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0177] In at least one embodiment, vehicle 1000 may include ADAS system 1038. In at least one embodiment, ADAS system 1038 may include, but is not limited to, SoC in some examples. In at least one embodiment, ADAS system 1038 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) system, cooperative adaptive cruise control (“CACC”) system, forward collision warning (“FCW”) system, automatic emergency braking (“AEB”) system, lane departure warning (“LDW”) system, lane keeping assist (“LKA”) system, blind spot warning (“BSW”) system, rear cross traffic warning (“RCTW”) system, collision warning (“CW”) system, lane centering (“LC”) system and / or other systems, features and / or functions.

[0178] In at least one embodiment, the ACC system may use one or more RADAR sensors 1060, one or more LIDAR sensors 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of vehicle 1000 and automatically adjusts the speed of vehicle 1000 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1000 change lanes if necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0179] In at least one embodiment, the CACC system uses information from other vehicles, which may be received indirectly from other vehicles via a wireless link or through a network connection (e.g., via the Internet) via network interface 1024 and / or one or more wireless antennas 1026. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately ahead (e.g., a vehicle immediately in front of vehicle 1000 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicles in front of vehicle 1000, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0180] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual, haptic, and / or rapid braking pulses.

[0181] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply braking if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system can automatically apply braking to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or collision proximity braking.

[0182] In at least one embodiment, when vehicle 1000 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is not activated when the driver indicates intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1000 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 1000.

[0183] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of the car. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses turn signals. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback such as a display, speaker, and / or vibration components.

[0184] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when the vehicle 1000 detects an object outside the range of the rear camera while reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0185] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, vehicle 1000 decides for itself whether to follow the result of the main computer or auxiliary computer (e.g., the first or second controller in controller 1036). For example, in at least one embodiment, ADAS system 1038 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, output from ADAS system 1038 may be provided to a supervisory MCU. In at least one embodiment, if output from the main computer and output from the auxiliary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0186] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU, indicating the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0187] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU may learn when the FCW system is recognizing a metallic object that is not actually dangerous, such as a drain grat or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1004s.

[0188] In at least one embodiment, the ADAS system 1038 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and the not-quite-same software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can have greater confidence that the overall results are correct, and the vulnerability in the software or hardware on the host computer will not lead to a major error.

[0189] In at least one embodiment, the output of the ADAS system 1038 may be fed into the perception block and / or the dynamic driving task block of the main computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a forward collision warning due to an object directly ahead, the perception block may use the information when the object is identified. In at least one embodiment, as described herein, the assistance computer may have its own neural network, which is trained to reduce the risk of false alarms.

[0190] In at least one embodiment, vehicle 1000 may further include an infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1030 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1030 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1000. For example, the infotainment SoC 1030 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1034, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1030 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1000, such as information from ADAS system 1038, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0191] In at least one embodiment, the infotainment SoC 1030 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1030 may communicate with other devices, systems, and / or components of the vehicle 1000 via bus 1002. In at least one embodiment, the infotainment SoC 1030 may be coupled to a supervisory MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of one or more main controllers 1036 (e.g., the main computer and / or backup computer of the vehicle 1000). In at least one embodiment, the infotainment SoC 1030 may place the vehicle 1000 into a driver-to-safe parking mode, as described herein.

[0192] In at least one embodiment, vehicle 1000 may further include instrument panel 1032 (e.g., digital instrument panel, electronic instrument panel, digital instrument cluster, etc.). In at least one embodiment, instrument panel 1032 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1032 may include, but is not limited to, any number and combination of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1030 and instrument panel 1032. In at least one embodiment, instrument panel 1032 may be included as part of infotainment SoC 1030, or vice versa.

[0193] Figure 10D It is based on at least one embodiment in one or more cloud-based servers and Figure 10AA diagram of a system for communication between autonomous vehicles 1000. In at least one embodiment, the system may include, but is not limited to, one or more servers 1078, one or more networks 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, one or more servers 1078 may include, but is not limited to, multiple GPUs 1084(A)-1084(H) (collectively referred to herein as GPU 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switch 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPU 1080). In at least one embodiment, GPU 1084, CPU 1080, and PCIe switch 1082 may be interconnected with high-speed interconnects, such as, for example, but not limited to, NVLink interface 1088 and / or PCIe connection 1086 developed by NVIDIA. In at least one embodiment, the GPU 1084 is connected via NVLink and / or NVSwitch SoC, and the GPU 1084 and PCIe switch 1082 are connected via PCIe interconnect. Although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1078 may include, but is not limited to, any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination. For example, in at least one embodiment, one or more servers 1078 may each include eight, sixteen, thirty-two, and / or more GPUs 1084.

[0194] In at least one embodiment, one or more servers 1078 may receive image data representing images from vehicles via one or more networks 1090, the images showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 1078 may send updated neural network 1092 and / or map information 1094 to vehicles via one or more networks 1090, including but not limited to information about traffic and road conditions. In at least one embodiment, updates to map information 1094 may include, but are not limited to, updates to HD map 1022, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 1092 and / or map information 1094 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed at a data center (e.g., using one or more servers 1078 and / or other servers).

[0195] In at least one embodiment, one or more servers 1078 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 1090, and / or the machine learning model may be used by one or more servers 1078 to remotely monitor the vehicle).

[0196] In at least one embodiment, one or more servers 1078 may receive data from the vehicle and apply the data to a state-of-the-art real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1078 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1084, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1078 may include a deep learning infrastructure in a data center using CPU power.

[0197] In at least one embodiment, the deep learning infrastructure of one or more servers 1078 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as image sequences and / or objects located by vehicle 1000 in the image sequences (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1000, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1000 is malfunctioning, one or more servers 1078 may signal to vehicle 1000, instructing vehicle 1000's fail-safe computer to take control, notify passengers, and complete a safe stopping operation.

[0198] In at least one embodiment, one or more servers 1078 may include one or more GPUs 1084 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, servers driven by CPUs, FPGAs, and other processors may be used for inference, such as in situations where performance is less critical. In at least one embodiment, one or more hardware structures 715 are used to execute one or more embodiments. This document incorporates... Figure 7A and / or Figure 7B Provide details about the 715 hardware architecture.

[0199] In at least one embodiment, regarding Figure 10A-10D At least one component shown or described is used to achieve the combination Figure 1-6 The described techniques and / or functions. In at least one embodiment, the accelerator 1014 is a hardware resource used to perform image classification using input data, which includes at least a voxel representation of the environment based on a data structure used to indicate voxels to be generated during the conversion of a point cloud into that voxel representation, such as in combination with... Figure 1 As described herein and elsewhere in this document.

[0200] Computer System Figure 11This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system with interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include execution units for executing instructions. In at least one embodiment, according to this disclosure, such as in the embodiments described herein, computer system 1100 may include, but is not limited to, components such as processor 1102 for employing execution units (including logic) to execute algorithms for process data. In at least one embodiment, computer system 1100 may include a processor, such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, the computer system 1100 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0201] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0202] In at least one embodiment, the computer system 1100 may include, but is not limited to, a processor 1102, which may include, but is not limited to, one or more execution units 1108 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1100 is a single-processor desktop or server system, but in another embodiment, the computer system 1100 may be a multiprocessor system. In at least one embodiment, the processor 1102 may include, but is not limited to, for example, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1102 may be coupled to a processor bus 1110, which can transmit data signals between the processor 1102 and other components in the computer system 1100.

[0203] In at least one embodiment, processor 1102 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to processor 1102. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1106 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0204] In at least one embodiment, an execution unit 1108, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1102. In at least one embodiment, the processor 1102 may also include a microcode (“ucode”) read-only memory (“ROM”) storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1108 may include logic for processing a packaged instruction set 1109. In at least one embodiment, by including the packaged instruction set 1109 in the instruction set of the general-purpose processor and the associated circuitry to be executed, operations used by numerous multimedia applications can be performed using packaged data in the processor 1102. In at least one embodiment, numerous multimedia applications can be accelerated and executed more efficiently by performing operations on packaged data using the full width of the processor's data bus, eliminating the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0205] In at least one embodiment, execution unit 1108 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1100 may include, but is not limited to, memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1120 may store one or more instructions 1119 and / or data 1121 represented by data signals executable by processor 1102.

[0206] In at least one embodiment, the system logic chip may be coupled to processor bus 1110 and memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1116 may direct data signals between processor 1102, memory 1120, and other components in computer system 1100, and bridge data signals between processor bus 1110, memory 1120, and system I / O interface 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1116 can be coupled to memory 1120 via high-bandwidth memory path 1118, and graphics / video card 1112 can be coupled to MCH 1116 via Accelerated Graphics Port (“AGP”) interconnect 1114.

[0207] In at least one embodiment, the computer system 1100 may use the system I / O interface 1122 as a proprietary hub interface bus to couple the MCH 1116 to the I / O controller hub (“ICH”) 1130. In at least one embodiment, the ICH 1130 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1120, chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub (“Flash BIOS”) 1128, a wireless transceiver 1126, a data storage 1124, a conventional I / O controller 1123 including a user input and keyboard interface 1125, a serial expansion port 1127 (such as a Universal Serial Bus (“USB”) port), and a network controller 1134. In at least one embodiment, the data storage 1124 may include a hard disk driver, a floppy disk driver, a CD-ROM device, a flash memory device, or other mass storage device.

[0208] In at least one embodiment, Figure 11 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 11 An exemplary SoC can be shown. In at least one embodiment, Figure 11 The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1100 are interconnected using a Compute Fast Link (CXL) interconnect.

[0209] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in computer system 1100 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0210] In at least one embodiment, regarding Figure 11 At least one component shown or described is used to achieve the combination Figure 1-6 The described techniques and / or functions. In at least one embodiment, processor 1102 performs image classification using input data, which includes at least a voxel representation of the environment based on a data structure used to indicate voxels to be generated during the conversion of a point cloud into the voxel representation, such as in combination with... Figure 1 As described herein and elsewhere in this document.

[0211] Figure 12 This is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210 according to at least one embodiment. In at least one embodiment, the electronic device 1200 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0212] In at least one embodiment, the electronic device 1200 may, but is not limited to, a processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1210 uses a bus or interface coupling, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advanced Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 12 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 12 An exemplary SoC can be shown. In at least one embodiment, Figure 12 The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0213] In at least one embodiment, Figure 12This may include a display 1224, a touchscreen 1225, a touchpad 1230, a near-field communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, a fast chipset (“EC”) 1235, a trusted platform module (“TPM”) 1238, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1222, a DSP 1260, a driver 1220 (such as a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1250, a Bluetooth unit 1252, a wireless wide area network unit (“WWAN”) 1256, a global positioning system (GPS) unit 1255, a camera (“USB 3.0 camera”) 1254 (such as a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0214] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the components described herein. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1236, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, earphone 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1262, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250, Bluetooth unit 1252, and WWAN unit 1256 may be implemented as next-generation form factors (“NGFF”).

[0215] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in electronic device 1200 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0216] In at least one embodiment, regarding Figure 12 At least one component shown or described is used to achieve the combination Figure 1-6 The described techniques and / or functions. In at least one embodiment, processor 1210 performs image classification using input data, which includes at least a voxel representation of the environment based on a data structure used to indicate voxels to be generated during the conversion of a point cloud into the voxel representation, such as in combination with... Figure 1 As described herein and elsewhere in this document.

[0217] Figure 13 A computer system 1300 according to at least one embodiment is shown. In at least one embodiment, the computer system 1300 is configured to implement various processes and methods described throughout this disclosure.

[0218] In at least one embodiment, the computer system 1300 includes, but is not limited to, at least one central processing unit (“CPU”) 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Fast (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1300 includes, but is not limited to, main memory 1304 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in the main memory 1304, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1322 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using the computer system 1300.

[0219] In at least one embodiment, the computer system 1300 includes, but is not limited to, an input device 1308, a parallel processing system 1312, and a display device 1306, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1308 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein may reside on a single semiconductor platform to form the processing system.

[0220] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7BDetails are provided regarding inference and / or training logic 715. In at least one embodiment, logic 715 may be used in computer system 1300 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0221] In at least one embodiment, regarding Figure 13 At least one component shown or described is used to achieve the combination Figure 1-6 The described techniques and / or functions. In at least one embodiment, the computer system 1300 performs one or more operations of image classification using input data, which includes at least a voxel representation of the environment based on a data structure used to indicate voxels to be generated during the conversion of a point cloud into the voxel representation, such as in combination with... Figure 1 As described herein and elsewhere in this document.

[0222] Figure 14 A computer system 1400 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1400 includes, but is not limited to, a computer 1410 and a USB flash drive 1420. In at least one embodiment, the computer 1410 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1410 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0223] In at least one embodiment, the USB flash drive 1420 includes, but is not limited to, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, the processing unit 1430 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1430 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1430 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1430 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1430 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0224] In at least one embodiment, the USB interface 1440 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1440 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1450 may include any amount and type of logic enabling the processing unit 1430 to interface with a device (e.g., computer 1410) via the USB connector 1440.

[0225] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in computer system 1400 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0226] In at least one embodiment, regarding Figure 14 At least one component shown or described is used to achieve the combination Figure 1-6 The described techniques and / or functions. In at least one embodiment, the computer system 1400 performs one or more operations of image classification using input data, which includes at least a voxel representation of the environment based on a data structure used to indicate voxels to be generated during the conversion of a point cloud into the voxel representation, such as in combination with... Figure 1 As described herein and elsewhere in this document.

[0227] Figure 15A An exemplary architecture is shown in which multiple GPUs 1510(1)-1510(N) are communicatively coupled to multiple multi-core processors 1505(1)-1505(M) via high-speed links 1540(1)-1540(N) (e.g., bus, point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1540(1)-1540(N) support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more of the multiple GPUs 1510(1)-1510(N) include, Figure 18A and Figure 18BThe disclosed one or more graphics cores (also simply referred to as "cores") 1800. In at least one embodiment, one or more graphics cores 1800 may be referred to as streaming multiprocessors ("SM"), streaming processors ("SP"), streaming processing units ("SPU"), compute units ("CU"), execution units ("EU"), and / or slices, wherein a slice in this context may refer to a portion of the processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread bootstrap, or a scheduler).

[0228] Furthermore, in at least one embodiment, two or more GPUs 1510 are interconnected via high-speed links 1529(1)-1529(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 1540(1)-1540(N). Similarly, two or more multi-core processors 1505 can be connected via high-speed link 1528, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 15A This shows all communication between the various system components.

[0229] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to processor memory 1501(1)-1501(M) via memory interconnects 1526(1)-1526(M), and each GPU 1510(1)-1510(N) is communicatively coupled to GPU memory 1520(1)-1520(N) via GPU memory interconnects 1550(1)-1550(N). In at least one embodiment, memory interconnects 1526 and 1550 may utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1501(1)-1501(M) and GPU memory 1520 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-RAM. In at least one embodiment, some portions of the processor memory 1501 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0230] As described herein, although the individual multi-core processors 1505 and GPUs 1510 can be physically coupled to specific memories 1501 and 1520 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the individual physical memories. For example, processor memories 1501(1)–1501(M) can each include 64 GB of system memory address space, and GPU memories 1520(1)–1520(N) can each include 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M = 2 and N = 4. Other values ​​for N and M are possible.

[0231] Figure 15B Additional details are shown regarding the interconnection between a multi-core processor 1507 and a graphics acceleration module 1546 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1546 may include one or more GPU chips integrated on a line card coupled to the processor 1507 via a high-speed link 1540 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1546 may alternatively be integrated on a package or chip having the processor 1507.

[0232] In at least one embodiment, the processor 1507 includes a plurality of cores 1560A-1560D (which may be referred to as “execution units”), each core having a translation back cover buffer (“TLB”) 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, the cores 1560A-1560D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1562A-1562D may include Level 1 (L1) and Level 2 (L2) caches. Furthermore, one or more shared caches 1556 may be included in the caches 1562A-1562D and shared by the respective groups of cores 1560A-1560D. For example, one embodiment of the processor 1507 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1507 and the graphics acceleration module 1546 are connected to the system memory 1514, which may include... Figure 15A The processor memory 1501(1)-1501(M) in the memory.

[0233] In at least one embodiment, consistency of data and instructions stored in the various caches 1562A-1562D, 1556 and system memory 1514 is maintained via inter-core communication through the consistency bus 1564. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1564 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1564 to snoop on cache accesses.

[0234] In at least one embodiment, proxy circuitry 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564, thereby allowing graphics acceleration module 1546 to participate in cache coherence protocols as a peer of cores 1560A-1560D. Specifically, in at least one embodiment, interface 1535 provides connectivity to proxy circuitry 1525 via high-speed link 1540, and interface 1537 connects graphics acceleration module 1546 to high-speed link 1540.

[0235] In at least one embodiment, the accelerator integrated circuit 1536 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546. In at least one embodiment, each of the graphics processing engines 1531(1)-1531(N) may include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546 includes one or more graphics cores 1800, such as in combination Figure 18A and Figure 18B The discussion continues. In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may alternatively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit (block transport) engines. In at least one embodiment, the graphics acceleration module 1546 may be a GPU having multiple graphics processing engines 1531(1)-1531(N), or the graphics processing engines 1531(1)-1531(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0236] In at least one embodiment, the accelerator integrated circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1514. In at least one embodiment, the MMU 1539 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1538 may store commands and data for efficient access by graphics processing engines 1531(1)-1531(N). In at least one embodiment, a fetch unit 1544 may be used to keep data stored in cache 1538 and graphics memory 1533(1)-1533(M) consistent with core caches 1562A-1562D, 1556 and system memory 1514. As previously stated, this can represent cache 1538 and memory 1533(1)-1533(M) being implemented via proxy circuit 1525 (e.g., sending updates related to the modification / access of cache lines on processor caches 1562A-1562D, 1556 to cache 1538 and receiving updates from cache 1538).

[0237] In at least one embodiment, a set of registers 1545 stores context data of threads executed by graphics processing engines 1531(1)-1531(N), and context management circuitry 1548 manages the thread context. For example, context management circuitry 1548 may perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1548 may store the current register value in a designated area of ​​memory (e.g., identified by a context pointer). The register value can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1547 receives and processes interrupts received from system devices.

[0238] In at least one embodiment, MMU 1539 translates virtual / effective addresses from graphics processing engine 1531 into real / physical addresses in system memory 1514. In at least one embodiment, accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1546 may be dedicated to a single application executing on processor 1507, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 1531(1)-1531(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0239] In at least one embodiment, the accelerator integrated circuit 1536 acts as a bridge to the system of the graphics acceleration module 1546 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1536 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1531(1)-1531(N).

[0240] In at least one embodiment, since the hardware resources of the graphics processing engines 1531(1)-1531(N) are explicitly mapped to the real address space seen by the host processor 1507, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1536 is the physical separation of the graphics processing engines 1531(1)-1531(N), making them appear as independent units to the system.

[0241] In at least one embodiment, one or more graphics memories 1533(1)-1533(M) are coupled to each graphics processing engine 1531(1)-1531(N), where N = M. In at least one embodiment, graphics memories 1533(1)-1533(M) store instructions and data being processed by each graphics processing engine 1531(1)-1531(N). In at least one embodiment, graphics memories 1533(1)-1533(M) may be volatile memories, such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0242] In at least one embodiment, to reduce data traffic on the high-speed link 1540, a biasing technique can be used to ensure that the data stored in the graphics memory 1533(1)-1533(M) is the data most frequently used by the graphics processing engine 1531(1)-1531(N), and preferably the data that the cores 1560A-1560D do not use (or at least do not use frequently). Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not needed by the graphics processing engine 1531(1)-1531(N)) in the caches 1562A-1562D, 1556 and system memory 1514.

[0243] Figure 15C Another exemplary embodiment is shown, wherein the accelerator integrated circuit 1536 is integrated within the processor 1507. In this embodiment, the graphics processing engines 1531(1)-1531(N) communicate directly with the accelerator integrated circuit 1536 via a high-speed link 1540 through interfaces 1537 and 1535 (again, which can be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1536 can perform operations related to... Figure 15B The described operation is similar, but due to its close proximity to the coherence bus 1564 and caches 1562A-1562D, 1556, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The programming models may include a programming model controlled by the accelerator integrated circuit 1536 and a programming model controlled by the graphics acceleration module 1546.

[0244] In at least one embodiment, graphics processing engines 1531(1)-1531(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1531(1)-1531(N), thereby providing virtualization within a VM / partition.

[0245] In at least one embodiment, graphics processing engines 1531(1)-1531(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1531(1)-1531(N) to allow access by each operating system. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1531(1)-1531(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1531(1)-1531(N) to provide access to each process or application.

[0246] In at least one embodiment, the graphics acceleration module 1546 or the individual graphics processing engine 1531(1)-1531(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1514 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1531(1)-1531(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0247] Figure 15D An exemplary accelerator integration slice 1590 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 1536. In at least one embodiment, the application is an effective address space 1582 in system memory 1514, which stores process element 1583. In at least one embodiment, process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on processor 1507. In at least one embodiment, process element 1583 contains the process state of the corresponding application 1580. In at least one embodiment, a job descriptor (WD) 1584 contained in process element 1583 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1584 is a pointer to a job request queue in the effective address space 1582 of the application.

[0248] In at least one embodiment, the graphics acceleration module 1546 and / or the various graphics processing engines 1531(1)-1531(N) may be shared by all processes or subsets of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1584 to the graphics acceleration module 1546 to begin operations in a virtualized environment.

[0249] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1536 for the owned partition; when the graphics acceleration module 1546 is assigned, the operating system initializes the accelerator integrated circuit 1536 for the owned process.

[0250] In at least one embodiment, during operation, the WD acquisition unit 1591 in the accelerator integration slice 1590 acquires the next WD 1584, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. In at least one embodiment, data from the WD 1584 may be stored in register 1545 and used by MMU 1539, interrupt management circuitry 1547, and / or context management circuitry 1548, as shown. For example, one embodiment of MMU 1539 includes segment / page walk circuitry for accessing segment / page tables 1586 within the OS virtual address space 1585. In at least one embodiment, interrupt management circuitry 1547 may process interrupt events 1592 received from the graphics acceleration module 1546. In at least one embodiment, when performing graphics operations, a valid address 1593 generated by graphics processing engines 1531(1)-1531(N) is translated into a real address by MMU 1539.

[0251] In at least one embodiment, register 1545 is copied for each graphics processing engine 1531(1)-1531(N) and / or graphics acceleration module 1546, and register 1545 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 1590. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. Table 2 shows exemplary registers that can be initialized by the operating system. In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531(1)-1531(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1531(1)-1531(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0252] Figure 15E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1598, in which a list of process elements 1599 is stored. In at least one embodiment, the hypervisor real address space 1598 can be accessed via a hypervisor 1596, which virtualizes the graphics acceleration module engine for an operating system 1595.

[0253] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models in which the graphics acceleration module 1546 is shared by multiple processes and partitions, namely time-slice sharing and graphics-oriented sharing.

[0254] In at least one embodiment, in this model, the hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, for the graphics acceleration module 1546 to support virtualization through the hypervisor 1596, the graphics acceleration module 1546 may comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1546 must provide a context saving and restoring mechanism, (2) the graphics acceleration module 1546 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1546 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, the fairness of the graphics acceleration module 1546 among processes must be ensured.

[0255] In at least one embodiment, application 1580 needs to make system calls to operating system 1595 using the graphics acceleration module type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1546 and can take the form of graphics acceleration module 1546 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1546.

[0256] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1536 (not shown) and the graphics acceleration module 1546 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1596 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 1583. In at least one embodiment, CSRP is one of the registers 1545 that contains the effective address of a region in the effective address space 1582 of the application for the graphics acceleration module 1546 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0257] Upon receiving a system call, the operating system 1595 can verify that the application 1580 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the operating system 1595 uses the information shown in Table 3 to invoke the hypervisor 1596. In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1596 verifies that the operating system 1595 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the hypervisor 1596 adds the process element 1583 to a linked list of process elements of the corresponding graphics acceleration module 1546 type. In at least one embodiment, the process element may include the information shown in Table 4. In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1590 registers 1545.

[0258] like Figure 15F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1501(1)-1501(N) and GPU memories 1520(1)-1520(N). In this implementation, operations performed on GPUs 1510(1)-1510(N) utilize the same virtual / effective memory address space to access processor memories 1501(1)-1501(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501(1), a second portion to second processor memory 1501(N), a third portion to GPU memory 1520(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1501 and GPU memories 1520, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0259] In at least one embodiment, the bias / coherence management circuitry 1594A-1594E within one or more MMUs 1539A-1539E ensures cache coherence between one or more host processors (e.g., 1505) and the cache of the GPU 1510, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 15F Several instances of bias / coherence management circuitry 1594A-1594E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 1505 and / or within the accelerator integrated circuit 1536.

[0260] One embodiment allows GPU memory 1520 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability of GPU memory 1520 to be accessed as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 1505 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1520 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1510. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0261] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising 1 or 2 bits of memory pages attached per GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPU 1510, the bias table can be implemented over one or more stolen memory ranges of GPU memory 1520. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0262] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1520 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 1510 to find its page in the GPU bias is directly forwarded to the corresponding GPU memory 1520. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to processor 1505 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 1505 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request to a GPU bias page can be forwarded to GPU 1510. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed by a software-based mechanism, a hardware-assisted software mechanism, or, in a limited set of cases, by a purely hardware-based mechanism.

[0263] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn invokes the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrating from the host processor 1505 bias to the GPU bias, but not for the reverse migration.

[0264] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1505 cannot cache. In at least one embodiment, to access these pages, the processor 1505 may request access from the GPU 1510, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1505 and the GPU 1510, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU, not those needed by the host processor 1505, and vice versa.

[0265] One or more hardware structures 715 are used to execute one or more embodiments. This document may combine... Figure 7A and / or Figure 7B Provide details about one or more hardware structures 715.

[0266] Figure 16Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which can be manufactured using one or more IP cores. In addition to those illustrated, at least one embodiment may also include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0267] Figure 16 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1600 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic including a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I2S / I2C controller 1640. In at least one embodiment, the integrated circuit 1600 may include a display device 1645 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1650 and a Mobile Industrial Processor Interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits also include an embedded security engine 1670.

[0268] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in integrated circuit 1600 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0269] In at least one embodiment, regarding Figure 15A-16 At least one component shown or described is used to achieve the combination Figure 1-6 The described techniques and / or functions. In at least one embodiment, the SOC integrated circuit 1600 performs one or more operations of image classification using input data, which includes at least a voxel representation of the environment based on a data structure used to indicate voxels to be generated during the conversion of a point cloud into the voxel representation, such as in combination with... Figure 1 As described herein and elsewhere in this document.

[0270] Figures 17A-17B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be fabricated using one or more IP cores. In addition to those illustrated, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0271] Figures 17A-17B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 17A An exemplary graphics processor 1710 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 17B An additional exemplary graphics processor 1740 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 17A The graphics processor 1710 is a low-power graphics processor core. In at least one embodiment, Figure 17B The graphics processor 1740 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1710, 1740 may be... Figure 16 A variant of the 1610 graphics processor.

[0272] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D to 1715N-1 and 1715N). In at least one embodiment, the graphics processor 1710 may execute different shader programs via separate logic, such that the vertex processor 1705 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1705 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1715A-1715N use the primitive and vertex data generated by the vertex processor 1705 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1715A-1715N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0273] In at least one embodiment, the graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, one or more caches 1725A-1725B, and one or more circuit interconnects 1730A-1730B. In at least one embodiment, the one or more MMUs 1720A-1720B provide virtual-to-physical address mapping for the graphics processor 1710 (including for the vertex processor 1705 and / or fragment processors 1715A-1715N), and may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1725A-1725B. In at least one embodiment, the one or more MMUs 1720A-1720B may be synchronized with other MMUs within the system, including with... Figure 16 One or more application processors 1605, graphics processors 1615, and / or video processors 1620 are associated with one or more MMUs, enabling each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable the graphics processor 1710 to interface with other IP cores within the SoC via the SoC's internal bus or via direct connection.

[0274] In at least one embodiment, the graphics processor 1740 includes, as shown below: Figure 17B The one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F to 1755N-1 and 1755N) shown provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1755A-1755N and a tile unit 1758 to accelerate tile-based rendering operations, where scene rendering operations are subdivided in image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0275] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in graphics processors 1710 and / or 1740 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0276] In at least one embodiment, regarding Figures 17A-17B At least one component shown or described is used to achieve the combination Figure 1-6 The described techniques and / or functions. In at least one embodiment, the graphics processor 1700 performs one or more operations of image classification using input data, which includes at least a voxel representation of the environment based on a data structure used to indicate voxels to be generated during the conversion of a point cloud into the voxel representation, such as in combination with... Figure 1 As described herein and elsewhere in this document.

[0277] Figures 18A-18B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, in... Figures 18A-18B The image shown and the combination Figures 18A-18B The described components are integrated into a single system, such as a graphics processing unit (GPU), a SoC, or another type of processor. In at least one embodiment, Figure 18A The example shown in at least one embodiment may include [the following]. Figure 16The graphics core 1800 is located within the graphics processor 1610, and in at least one embodiment, the graphics core 1800 may be as follows: Figure 17B The unified shader cores shown are 1755A-1755N. Figure 18B A highly parallel general-purpose graphics processing unit (“GPGPU”, which may also be referred to as a “graphics processing unit”) 1830 suitable for deployment on a multi-chip module is illustrated in at least one embodiment. In at least one embodiment, the graphics processing unit 1830 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1600 includes a graphics core 1800, for example, for forming an integrated circuit and / or a SoC, wherein such integrated circuit and / or such SoC performs the operations described herein.

[0278] In at least one embodiment, the graphics core 1800 includes a shared instruction cache 1802, texture units 1818, and cache / shared memory 1820 (e.g., including L1, L2, L3, last-level cache, or other caches), which are shared for execution resources within the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1800. In at least one embodiment, each slice 1801A-1801N refers to the graphics core 1800. In at least one embodiment, slices 1801A-1801N have sub-slices that are part of slices 1801A-1801N. In at least one embodiment, slices 1801A-1801N are independent of other slices or dependent on other slices. In at least one embodiment, slices 1801A-1801N may include supporting logic including local instruction caches 1804A-1804N, thread schedulers (orderers) 1806A-1806N, thread dispatchers 1807A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional functional units (AFU 1812A-1812N), floating-point units (FPU 1814A-1814N), integer arithmetic logic units (ALU 1816A-1816N), address calculation units (ACU 1813A-1813N), double-precision floating-point units (DPFPU 1815A-1815N), and matrix processing units (MPU 1817A-1817N). In at least one embodiment, MPU 1817A-1817N is referred to as a matrix engine.

[0279] In at least one embodiment, each slice 1801A-1801N includes one or more engines for floating-point and integer vector operations, and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating-point (also known as "FP16"), 32-bit floating-point (also known as "FP32"), or 64-bit floating-point (also known as "FP64"). In at least one embodiment, one or more slices 1801A-1801N include 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, wherein the vector engines and math units are exposed via matrix expansion. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, such as 16 cores and ray tracing units or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, the graphics core 1800 includes one or more matrix engines for performing matrix operations, such as when performing tensor operations.

[0280] In at least one embodiment, one or more slices 1801A-1801N include one or more ray tracing units for calculating ray tracing operations (e.g., 16 ray tracing units per slice 1801A-1801N). In at least one embodiment, the ray tracing units calculate ray traversal, triangle intersection, bounding box intersection, or other ray tracing operations.

[0281] In at least one embodiment, one or more slices 1801A-1801N include media slices that encode, decode, and / or transcode data; scale and / or format convert data; and / or perform video quality operations on video data.

[0282] In at least one embodiment, one or more slices 1801A-1801N are linked to an L2 cache and memory architecture, link connectors, a high-bandwidth memory (HBM) stack (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 1801A-1801N include multiple cores (e.g., 16 cores) paired with each core and multiple ray tracing units (e.g., 16). In at least one embodiment, one or more slices 1801A-1801N have one or more L1 caches. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) (e.g., corresponding to instructions) for storing data; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., shapes) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by shapes); one or more hierarchical depth buffers (Hiz) for caching data; and / or one or more pixel back-ends. In at least one embodiment, slices 1801A-1801N include memory structures, such as L2 caches.

[0283] In at least one embodiment, the FPU 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1815A-1815N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1817A-1817N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1812A-1812N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric function operations (e.g., sine, cosine, etc.).

[0284] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in graphics core 1800 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0285] In at least one embodiment, the graphics core 1800 includes an interconnect and link structure sublayer attached to a switch and a GPU-GPU bridge that enables multiple graphics processors 1800 (e.g., eight) to be interconnected without glue using load / memory units (LSUs), data transfer units, and synchronization semantics across the multiple graphics processors 1800. In at least one embodiment, the interconnect includes standardized interconnects (e.g., PCIe) or some combination thereof.

[0286] In at least one embodiment, the graphics core 1800 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, wherein the individual dies may be interconnected (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 1800 includes compute tiles, storage tiles (e.g., where storage tiles may be exclusively accessed by different tiles or different chipsets, such as Rambo tiles), base tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, wherein all tiles are packaged together in the graphics core 1800 as part of the GPU. In at least one embodiment, the graphics core 1800 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile may have eight graphics cores 1800, an L1 cache; and a base tile may have a host interface employing PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight links, and eight ports with an embedded switch. In at least one embodiment, the blocks are connected to face-to-face (F2F) chip bonding via fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 1800 includes a memory structure comprising memory and being a block accessible to the multiple blocks. In at least one embodiment, the graphics core 1800 stores, accesses, or loads its own hardware context in memory, wherein the hardware context is a set of data loaded from registers prior to process resumption, and wherein the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0287] In at least one embodiment, the graphics core 1800 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream, or a parallel data stream into a serial data stream.

[0288] In at least one embodiment, the graphics core 1800 includes a high-speed, consistent unified architecture (GPU-to-GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected via an embedded switch, wherein the GPU-to-GPU bridge is controlled by a controller.

[0289] In at least one embodiment, the graphics core 1800 executes an API, wherein the API abstracts the hardware of the graphics core 1800 and utilizes an instruction access library to perform mathematical operations (e.g., a mathematical kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communication, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0290] Figure 18B A GPGPU 1830 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1830 can be directly linked to other instances of the GPGPU 1830 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 for establishing a connection to a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and uses a global scheduler 1834 (which may be referred to as a thread sequencer and / or asynchronous computing engine) to allocate the execution threads associated with those commands to a set of computing clusters 1836A-1836H. In at least one embodiment, the computing clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, cache memory 1838 may be used as a higher-level cache than cache memory within compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H include slices, or referred to as "slices". In at least one embodiment, GPGPU 1830 is part of a SoC, such as integrated circuit 1600 (… Figure 16 Part of ).

[0291] In at least one embodiment, the GPGPU 1830 includes memories 1844A-1844B coupled to the compute cluster 1836A-1836H via a set of memory controllers 1842A-1842B (e.g., one or more controllers of HBM2e). In at least one embodiment, memories 1844A-1844B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0292] In at least one embodiment, each of the computing clusters 1836A-1836H includes a set of graphics cores, such as Figure 18A The graphics core 1800 may include various types of integer and floating-point logic units that can perform computational operations over a range of precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0293] In at least one embodiment, multiple instances of the GPGPU 1830 can be configured to operate as a compute cluster. In at least one embodiment, the communication used for synchronization and data exchange by the compute clusters 1836A-1836H varies between embodiments. In at least one embodiment, the multiple instances of the GPGPU 1830 communicate via a host interface 1832. In at least one embodiment, the GPGPU 1830 includes an I / O hub 1839 that couples the GPGPU 1830 to a GPU link 1840, which provides direct connectivity to other instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between the multiple instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of the GPGPU 1830 reside in a separate data processing system and communicate via a network device accessible via the host interface 1832. In at least one embodiment, in addition to or as an alternative to host interface 1832, GPU link 1840 may also be configured to implement a connection to the host processor.

[0294] In at least one embodiment, the GPGPU 1830 can be configured to train a neural network. In at least one embodiment, the GPGPU 1830 can be used within an inference platform. In at least one embodiment, when using the GPGPU 1830 for inference, the GPGPU 1830 may include fewer compute clusters 1836A-1836H compared to when using the GPGPU 1830 to train a neural network. In at least one embodiment, the memory technology associated with the memories 1844A-1844B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1830 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0295] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in the GPGPU 1830 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0296] In at least one embodiment, regarding Figures 18A-18B At least one component shown or described is used to achieve the combination Figure 1-6 The described techniques and / or functions. In at least one embodiment, the GPGPU 1830 performs one or more image classification operations using input data, which includes at least a voxel representation of the environment based on a data structure used to indicate voxels to be generated during the conversion of a point cloud into that voxel representation, such as in combination with... Figure 1 As described herein and elsewhere in this document.

[0297] Figure 19This is a block diagram illustrating a computing system 1900 according to at least one embodiment. In at least one embodiment, the computing system 1900 includes a processing subsystem 1901 having one or more processors 1902 and system memory 1904 communicating via interconnect paths that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset assembly or may be integrated within one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In at least one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that enables the computing system 1900 to receive input from one or more input devices 1908. In at least one embodiment, the I / O hub 1907 enables a display controller to provide output to one or more display devices 1910A, the display controller being included in one or more processors 1902. In at least one embodiment, one or more display devices 1910A coupled to the I / O hub 1907 may include local, internal, or embedded display devices.

[0298] In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 coupled to a memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 may use one of any number of standards based on a communication link technology or protocol (such as, but not limited to, PCI Express), or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, one or more parallel processors 1912 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as integrated many-core (MIC) processors. In at least one embodiment, some or all of the parallel processors 1912 form a graphics processing subsystem that can output pixels to one or more display devices 1910A coupled via an I / O hub 1907. In at least one embodiment, one or more parallel processors 1912 may also include a display controller and a display interface (not shown) for implementing direct connection to one or more display devices 1910B. In at least one embodiment, the parallel processor 1912 includes one or more cores, such as the graphics core 1800 discussed herein.

[0299] In at least one embodiment, system storage unit 1914 may be connected to I / O hub 1907 to provide a storage mechanism for computing system 1900. In at least one embodiment, I / O switch 1916 may be used to provide an interface mechanism for enabling connectivity between I / O hub 1907 and other components, such as network adapter 1918 and / or wireless network adapter 1919 integrated into the platform, and various other devices that can be added via one or more additional devices 1920. In at least one embodiment, network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1919 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless devices.

[0300] In at least one embodiment, the computing system 1900 may include other components, not explicitly shown, that may also be connected to the I / O hub 1907, including USB or other port connections, optical storage drivers, video capture devices, etc. In at least one embodiment, the interconnect can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect or interconnect protocols). Figure 19 The communication paths of each component.

[0301] In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU), such as a graphics core 1800. In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1912, a memory hub 1905, one or more processors 1902, and an I / O hub 1907 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1900 may be integrated into a multi-chip module (MCM), which may interconnect with other MCMs to a modular computing system.

[0302] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in computing system 1900 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0303] In at least one embodiment, regarding Figure 19 At least one component shown or described is used to achieve the combination Figure 1-6 The described techniques and / or functions. In at least one embodiment, the parallel processor 1912 performs one or more operations of image classification using input data, which includes at least a voxel representation of the environment based on a data structure used to indicate voxels to be generated during the conversion of a point cloud into that voxel representation, such as in combination with... Figure 1 As described herein and elsewhere in this document.

[0304] processor Figure 20A A parallel processor 2000 according to at least one embodiment is illustrated. In at least one embodiment, the various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2000 is according to an exemplary embodiment. Figure 19 Variations of the one or more parallel processors 1912 shown. In at least one embodiment, the parallel processor 2000 includes one or more graphics cores 1800.

[0305] In at least one embodiment, the parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, the parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of the parallel processing unit 2002. In at least one embodiment, the I / O unit 2004 can be directly connected to other devices. In at least one embodiment, the I / O unit 2004 is connected to other devices via a hub or switch interface (e.g., a memory hub 2005). In at least one embodiment, the connection between the memory hub 2005 and the I / O unit 2004 forms a communication link 2013. In at least one embodiment, the I / O unit 2004 is connected to a host interface 2006 and a memory crossbar switch 2016, wherein the host interface 2006 receives commands for performing processing operations, and the memory crossbar switch 2016 receives commands for performing memory operations.

[0306] In at least one embodiment, when host interface 2006 receives a command buffer via I / O unit 2004, host interface 2006 can route work operations for executing those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010 (which may be referred to as sequencer), which is configured to assign commands or other work items to processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is correctly configured and in an active state before assigning tasks to clusters in processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing cluster array 2012. In at least one embodiment, host software can demonstrate workloads for scheduling on processing cluster array 2012 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing cluster array 2012 by the scheduler 2010 logic within the microcontroller, which includes the scheduler 2010.

[0307] In at least one embodiment, the processing cluster array 2012 may include up to "N" processing clusters (e.g., clusters 2014A, 2014B to 2014N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other diagrams). In at least one embodiment, each cluster 2014A-2014N of the processing cluster array 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may use various scheduling and / or work allocation algorithms to allocate work to clusters 2014A-2014N in the processing cluster array 2012, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2010, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N in the processing cluster array 2012 may be assigned to process different types of programs or to perform different types of computations.

[0308] In at least one embodiment, the processing cluster array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0309] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via I / O unit 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) and then written back to system memory.

[0310] In at least one embodiment, when the parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among multiple clusters 2014A-2014N in the processing cluster array 2012. In at least one embodiment, portions of the processing cluster array 2012 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2014A-2014N can be stored in a buffer to allow intermediate data to be transferred between the clusters 2014A-2014N for further processing.

[0311] In at least one embodiment, the processing cluster array 2012 may receive processing tasks to be executed via a scheduler 2010, which receives commands defining the processing tasks from a front end 2008. In at least one embodiment, the processing task may include index values ​​of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2010 may be configured to acquire index values ​​corresponding to the task, or may receive index values ​​from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing cluster array 2012 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0312] In at least one embodiment, each of one or more instances of the parallel processing unit 2002 may be coupled to the parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 may be accessed via a memory crossbar switch 2016, which may receive memory requests from the processing cluster array 2012 and the I / O unit 2004. In at least one embodiment, the memory crossbar switch 2016 may access the parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, the memory interface 2018 may include a plurality of partition units (e.g., partition units 2020A, 2020B to 2020N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2022. In at least one embodiment, the number of partition units 2020A-2020N is configured to be equal to the number of memory units, such that the first partition unit 2020A has a corresponding first memory unit 2024A, the second partition unit 2020B has a corresponding second memory unit 2024B, and the Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory units.

[0313] In at least one embodiment, memory cells 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2024A-2024N may also include 3D stacked memory, including but not limited to high-bandwidth memory (HBM), HBM2e, and HDM3. In at least one embodiment, rendering targets such as framebuffers or texture maps can be stored across memory cells 2024A-2024N, allowing partitioning cells 2020A-2020N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2022. In at least one embodiment, local instances of the parallel processor memory 2022 may be excluded to facilitate a unified memory design that utilizes system memory and local cache memory.

[0314] In at least one embodiment, any of clusters 2014A-2014N in the processing cluster array 2012 can process data to be written to any memory cell 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar switch 2016 can be configured to transfer the output of each cluster 2014A-2014N to any partition cell 2020A-2020N or another cluster 2014A-2014N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with the memory interface 2018 via the memory crossbar switch 2016 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar switch 2016 has a connection to a memory interface 2018 for communicating with I / O unit 2004, and a connection to a local instance of parallel processor memory 2022, enabling processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory not local to parallel processing unit 2002. In at least one embodiment, the memory crossbar switch 2016 may use virtual channels to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0315] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system including one or more instances of the parallel processing unit 2002 or the parallel processor 2000 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0316] Figure 20B This is a block diagram of a partitioning unit 2020 according to at least one embodiment. In at least one embodiment, the partitioning unit 2020 is... Figure 20AThis is an example of one of the partitioning units 2020A-2020N. In at least one embodiment, the partitioning unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster operation unit). In at least one embodiment, the L2 cache 2021 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 2016 and the ROP 2026. In at least one embodiment, the L2 cache 2021 outputs read misses and urgent write-back requests to the frame buffer interface 2025 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 2025. In at least one embodiment, the frame buffer interface 2025 communicates with memory cells in the parallel processor memory (such as...). Figure 20A It is coupled to one of the memory cells 2024A-2024N (e.g., within the parallel processor memory 2022).

[0317] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2026 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2026 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data per tile.

[0318] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., Figure 20A Clusters 2014A-2014N are used instead of partition units 2020. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted via a memory crossbar switch 2016. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 19 Displayed on one or more display devices 1910, routed by processor 1902 for further processing, or by... Figure 20A One of the processing entities within the parallel processor 2000 is routed for further processing.

[0319] Figure 20C This is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 20AAn instance of one of the processing clusters 2014A-2014N. In at least one embodiment, the processing cluster 2014 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issuing technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, Single Instruction Multiple Threading (SIMT) technology is used to support the parallel execution of a large number of typically synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0320] In at least one embodiment, the operation of the processing cluster 2014 can be controlled via a pipeline manager 2032 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032... Figure 20A The scheduler 2010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2034 and / or texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2014 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2014 may include one or more instances of the graphics multiprocessor 2034. In at least one embodiment, the graphics multiprocessor 2034 can process data, and the data crossover switch 2040 can be used to allocate the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2032 can facilitate the allocation of processed data by specifying the destination of the processed data to be allocated via the data crossover switch 2040.

[0321] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0322] In at least one embodiment, instructions sent to the processing cluster 2014 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group can be assigned to a different processing engine within the graphics multiprocessor 2034. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2034, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on the graphics multiprocessor 2034.

[0323] In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 may forgo the internal cache and use a cache memory within the processing cluster 2014 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 may also access partition units (e.g., Figure 20A The L2 cache is located within partition units 2020A-2020N, ​​which are shared among all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2002 can be used as global memory. In at least one embodiment, the processing cluster 2014 includes multiple instances of the graphics multiprocessor 2034, which can share common instructions and data that can be stored in the L1 cache 2048.

[0324] In at least one embodiment, each processing cluster 2014 may include a memory management unit (“MMU”) 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside in Figure 20AThe memory interface 2018 is located within the MMU 2045. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2045 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2034, the L1 cache 2048, or the processing cluster 2014. In at least one embodiment, physical addresses are processed to allocate surface d...

Claims

1. A processor, comprising: One or more circuits, the one or more circuits being used to generate the one or more voxels using one or more point clouds, at least in part based on the point locations of one or more voxels used to indicate one or more voxels in one or more data structures.

2. The processor of claim 1, wherein the one or more circuits are configured to generate the one or more data structures, the one or more data structures comprising one or more hash tables, the one or more hash tables storing the one or more point locations as keys and storing one or more indications of the one or more voxels as one or more corresponding values.

3. The processor of claim 1, wherein the one or more circuits are configured to generate the one or more data structures using a amount of memory at least partially based on the number of point locations in the one or more point clouds.

4. The processor of claim 1, wherein the one or more circuits are configured to access one or more data values ​​using the one or more data structures, and to generate one or more feature values ​​of the one or more voxels based at least in part on the one or more data values.

5. The processor of claim 1, wherein the one or more circuits are configured to store one or more data values, the one or more data values ​​indicating features associated with one or more point locations within one or more memory locations to be accessed at least in part based on data stored in the one or more data structures.

6. The processor of claim 1, wherein the one or more circuits are configured to iterate at the one or more point locations to generate one or more feature values ​​of the one or more voxels using the one or more data structures.

7. The processor of claim 1, wherein the one or more circuits are configured to input one or more indications of the one or more point locations into a hash function to output one or more indications of the one or more voxels.

8. A system comprising: One or more processors, the one or more processors being used to generate the one or more voxels using one or more point clouds, at least in part based on the point locations of one or more voxels used to indicate one or more voxels in one or more data structures.

9. The system of claim 8, wherein the one or more processors are configured to generate the one or more data structures, the one or more data structures comprising, at least in part, one or more arrays of ... arrays of one or more arrays of arrays of one or more arrays of arrays of one or more arrays of arrays of one or 10. The system of claim 8, wherein the one or more processors are configured to generate the one or more data structures using a memory amount at least twice the number of the one or more point locations.

11. The system of claim 8, wherein the one or more processors are configured to generate the one or more data structures, the one or more data structures comprising one or more tables for indexing the one or more voxels as functions of the one or more point locations.

12. The system of claim 8, wherein the one or more processors are configured to indicate the one or more voxels at least in part based on one or more indications of memory locations used to store the one or more indications of the one or more voxels.

13. The system of claim 8, wherein the one or more processors are configured to iterate at the one or more point locations to generate one or more mean feature values ​​of the one or more voxels using the one or more data structures.

14. The system of claim 8, wherein the one or more processors are configured to input one or more indications of the one or more point locations into a hash function to output one or more indications of one or more memory locations used to store the one or more indications of the one or more voxels.

15. A method comprising: The one or more voxels are generated using one or more point clouds, at least in part based on the location of one or more points used to indicate one or more voxels in one or more data structures.

16. The method of claim 15, further comprising: Generate one or more data structures, the one or more data structures comprising one or more hash tables that use the one or more point locations as keys to indicate the one or more voxels to be generated.

17. The method of claim 15, further comprising: The one or more data structures are generated using a amount of memory that is at least partially based on the number of points in the one or more point clouds.

18. The method of claim 15, further comprising: Access one or more indications of a memory location used to store one or more indications of the one or more individual elements.

19. The method of claim 15, further comprising: Iterate at one or more point locations to generate one or more summation feature values ​​for one or more voxels using one or more data structures.

20. The method of claim 15, further comprising: Use the one or more data structures to access one or more data values, and generate the one or more voxels based at least in part on the one or more data values.

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