Boot capacitor refresh control apparatus and method

Abstract

An apparatus includes: a bootstrap capacitor refresh pulse generation circuit configured to generate a refresh pulse to turn on the low-side switch once the off-time of the low-side switch of a power converter exceeds a predetermined threshold; and a logic gate configured to receive the refresh pulse and a low-side pulse width modulation (PWM) signal, and generate a drive signal applied to the gate of the low-side switch of the power converter.

Description

[0001] Cross-reference of related applications

[0002] This patent application claims priority to U.S. Patent Application No. 18 / 958,586, filed November 25, 2024, entitled “Bootstrap Capacitor Refresh Control Apparatus and Method,” and is, in particular, a continuation-in-the-file of that U.S. patent application, which is hereby incorporated herein by reference as if reproduced in its entirety. Technical Field

[0003] This disclosure generally relates to the field of power converters, and in certain embodiments, to techniques and mechanisms for maintaining the voltage of a bootstrap capacitor in a buck power converter. Background Technology

[0004] In power conversion systems, bootstrap capacitors are typically used to establish a floating voltage higher than the input voltage. This technique is particularly useful in circuits that require a higher voltage to drive the high-side switches. For example, a driver integrated circuit (IC) is configured to drive a power converter that includes two power switches connected in series between the input voltage bus and ground, and an inductor connected between the common node of the two power switches and the output voltage bus. The driver IC receives its operating voltage from a bias voltage source. In a typical system configuration, the driver IC includes a high-side driver and a low-side driver responsible for driving the high-side and low-side switches, respectively. The bootstrap capacitor is placed between the bias voltage node and the common node of the high-side and low-side switches. This arrangement provides the required floating voltage for the high-side driver. During operation, when the low-side power switch is turned on, the bias voltage charges the bootstrap capacitor, thus supplementing the floating voltage required for operation.

[0005] However, a significant problem arises when long-term shutdown of the low-side switch is involved. Some control methods adjust the switching frequency or temporarily and completely halt the switching. In such scenarios, the controller reduces or stops the low-side switch from being on, effectively shutting off the refresh path required to recharge the bootstrap capacitor. When this refresh path remains inactive for an extended period, the bootstrap capacitor cannot draw sufficient charge from the bias voltage, leading to depletion of the floating voltage supply required by the high-side driver. This results in an insufficient power supply from the bootstrap capacitor, potentially causing the high-side switch to lose the necessary gate drive voltage, which can lead to circuit instability, reduced efficiency, or high-side driver malfunction. It would be desirable to have a simple bootstrap capacitor refresh control device through which the bootstrap capacitor can be fully charged, thereby providing a consistent high-side drive power supply. This disclosure addresses that need. Summary of the Invention

[0006] Technical advantages are typically achieved through embodiments of the bootstrap capacitor refresh control device described in this disclosure.

[0007] According to an embodiment, an apparatus includes: a bootstrap capacitor refresh pulse generation circuit configured to generate a refresh pulse to turn on the low-side switch once the off-time of the low-side switch of a power converter exceeds a predetermined threshold; and a logic gate configured to receive the refresh pulse and a low-side pulse width modulation (PWM) signal, and generate a drive signal applied to the gate of the low-side switch of the power converter.

[0008] Optionally, in the foregoing aspects, the power converter is a buck converter comprising: a high-side switch and the low-side switch connected in series between the input voltage bus and ground; an inductor connected in series between the common node of the high-side switch and the low-side switch and the output voltage bus; and an output capacitor connected between the output voltage bus and ground.

[0009] Optionally, in any of the foregoing aspects, the logic gate is an OR gate, and the bootstrap capacitor refresh pulse generation circuit is a timer configured to measure the duration after the low-side switch is turned off, and to generate the refresh pulse once the off time of the low-side switch exceeds the predetermined threshold, wherein the low-side gate drive signal is fed into the first input of the OR gate, the output of the timer is fed into the second input of the OR gate, and the output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

[0010] Optionally, in any of the foregoing aspects, the logic gate is an OR gate, and the bootstrap capacitor refresh pulse generation circuit is a counter configured to count the number of clock cycles after the low-side switch is turned off, and to generate the refresh pulse once the off time of the low-side switch exceeds the predetermined threshold, wherein the low-side gate drive signal is fed into the first input of the OR gate, the output of the counter is fed into the second input of the OR gate, and the output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

[0011] Optionally, in any of the foregoing aspects, the predetermined threshold is dynamically adjustable, and wherein the predetermined threshold is negatively correlated with the current flowing through the power converter.

[0012] Optionally, in any of the foregoing aspects, the width of the refresh pulse is dynamically adjustable, and the width of the refresh pulse is negatively correlated with the slope of the current flowing through the power converter.

[0013] Optionally, in any of the foregoing aspects, the width of the refresh pulse is dynamically adjustable, and the width of the refresh pulse is proportional to the difference between the output voltage of the power converter and the setting value of the power converter.

[0014] Optionally, in any of the foregoing aspects, the width of the refresh pulse is dynamically adjustable, and the width of the refresh pulse is negatively correlated with the compensation voltage of the power converter.

[0015] According to another embodiment, a method includes: configuring a power conversion system to operate in a discontinuous conduction mode, wherein the power conversion system includes a power converter connected between an input voltage bus and an output voltage bus and a controller electrically coupled to the power converter; configuring a bootstrap capacitor refresh control device to measure the off-time of a low-side switch of the power converter; and configuring the bootstrap capacitor refresh control device to generate a refresh pulse to turn on the low-side switch of the power converter once the off-time of the low-side switch exceeds a predetermined threshold.

[0016] Optionally, in the foregoing aspects, the method further includes: configuring a timer in the bootstrap capacitor refresh control device to measure the duration after the low-side switch is turned off; configuring the bootstrap capacitor refresh control device to generate the refresh pulse once the off time of the low-side switch exceeds the predetermined threshold; and resetting the timer once the low-side switch is turned on.

[0017] Optionally, in any of the foregoing aspects, the bootstrap capacitor refresh control device includes an OR gate and the timer, wherein a low-side PWM signal is fed into a first input of the OR gate, the output of the timer is fed into a second input of the OR gate, and the output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

[0018] Optionally, in any of the foregoing aspects, the method further includes: configuring a counter in the bootstrap capacitor refresh control device to count the number of clock cycles after the low-side switch is turned off; configuring the bootstrap capacitor refresh control device to generate the refresh pulse once the off time of the low-side switch exceeds the predetermined threshold; and resetting the counter once the low-side switch is turned on.

[0019] Optionally, in any of the foregoing aspects, the bootstrap capacitor refresh control device includes an OR gate and the counter, wherein a low-side PWM signal is fed into a first input of the OR gate, the output of the counter is fed into a second input of the OR gate, and the output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

[0020] Optionally, in any of the foregoing aspects, the method further includes dynamically adjusting the predetermined threshold based on the current flowing through the power converter.

[0021] Optionally, in any of the foregoing aspects, the method further includes dynamically adjusting the width of the refresh pulse based on the slope of the current flowing through the power converter.

[0022] Optionally, in any of the foregoing aspects, the method further includes dynamically adjusting the width of the refresh pulse based on the compensation signal of the power converter.

[0023] Optionally, in any of the foregoing aspects, the method further includes: determining a first width of the refresh pulse based on the slope of the current flowing through the power converter; and determining a second width of the refresh pulse based on a compensation signal of the power converter, wherein the width of the refresh pulse is alternately set using the first width and the second width.

[0024] According to another embodiment, a system includes: a power converter connected between an input voltage bus and an output voltage bus; and a controller electrically coupled to the power converter, wherein the controller includes a bootstrap capacitor refresh control device, and wherein the bootstrap capacitor refresh control device is configured to measure the off-time of a low-side switch of the power converter, and the bootstrap capacitor refresh control device is configured to generate a refresh pulse to turn on the low-side switch of the power converter once the off-time of the low-side switch exceeds a predetermined threshold.

[0025] Optionally, in the foregoing aspects, the power converter includes: a high-side switch and the low-side switch connected in series between the input voltage bus and ground; an inductor connected in series between the common node of the high-side switch and the low-side switch and the output voltage bus; and an output capacitor connected between the output voltage bus and ground.

[0026] Optionally, in any of the foregoing aspects, the bootstrap capacitor refresh control device includes an OR gate and a timer, wherein a low-side PWM signal is fed into a first input of the OR gate, the output of the timer is fed into a second input of the OR gate, and the output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

[0027] The features described in the background of one embodiment can be used in conjunction with other embodiments. For example, each of the optional features described above in the background of the device can be used in conjunction with the system. Each of the optional features described above in the background of the method can be used in conjunction with the system. Each of the optional features described above in the background of the device can be used in conjunction with the method.

[0028] The features and technical advantages of this disclosure have been broadly outlined above to better understand the detailed description thereof below. Additional features and advantages of this disclosure, which form the subject matter of the claims, will be described below. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be readily used as the basis for modifying or designing other structures or processes for carrying out the same purpose as this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure as set forth in the appended claims. Attached Figure Description

[0029] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0030] Figure 1 Illustrate block diagrams of power conversion systems according to various embodiments of the present disclosure;

[0031] Figure 2 Description of various embodiments according to this disclosure Figure 1 A schematic diagram of the power converter shown in the image;

[0032] Figure 3 Description of various embodiments according to this disclosure Figure 2 A schematic diagram of the first embodiment of the bootstrap capacitor refresh control device shown in the figure;

[0033] Figure 4 Description of various embodiments according to this disclosure Figure 3 The various signals associated with the bootstrap capacitor refresh control device are shown in the figure;

[0034] Figure 5 Description of various embodiments according to this disclosure Figure 2 A schematic diagram of the second embodiment of the bootstrap capacitor refresh control device shown in the figure;

[0035] Figure 6 Description of various embodiments according to this disclosure Figure 5 The various signals associated with the bootstrap capacitor refresh control device are shown in the figure;

[0036] Figure 7 Description of various embodiments according to this disclosure Figure 2 The diagrams shown in the figure illustrate the third and fourth implementation schemes of the bootstrap capacitor refresh control device.

[0037] Figure 8 Description of various embodiments according to this disclosure Figure 2 A schematic diagram of the fifth embodiment of the bootstrap capacitor refresh control device shown in the figure;

[0038] Figure 9 Description of various embodiments according to this disclosure Figure 2 A schematic diagram of the sixth embodiment of the bootstrap capacitor refresh control device shown in the figure;

[0039] Figure 10 Description of various embodiments according to this disclosure Figure 2 A schematic diagram of the seventh embodiment of the bootstrap capacitor refresh control device shown in the diagram; and

[0040] Figure 11 Description of various embodiments of the present disclosure for control Figure 1 The flowchart of the power conversion system method shown in the figure.

[0041] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding components. The figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale. Detailed Implementation

[0042] The following describes in detail the making and use of embodiments of this disclosure. However, it should be understood that the concepts disclosed herein can be embodied in a wide variety of specific contexts, and the specific embodiments discussed herein are merely illustrative and not intended to limit the scope of the claims. Furthermore, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0043] Furthermore, features from one or more of the embodiments described below may be combined to create alternative embodiments not explicitly described, and features suitable for such combinations should be understood to be within the scope of this disclosure. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

[0044] This disclosure describes embodiments in a specific context (i.e., a bootstrap capacitor refresh control device for maintaining the bootstrap capacitor voltage in a buck converter). However, this disclosure can also be applied to various power converters. Various embodiments will be explained in detail below with reference to the accompanying drawings.

[0045] Figure 1 This illustration shows block diagrams of power conversion systems according to various embodiments of the present disclosure. The power conversion system includes a power converter 100 and a controller 200. (As...) Figure 1 As shown, the power converter 100 is connected between the input voltage bus VIN and the output voltage bus Vo. A load (not shown) is coupled to the output voltage bus Vo. In some embodiments, the load may be a processor (e.g., a central processing unit).

[0046] In some embodiments, the power converter 100 is implemented as a buck power converter. The buck power converter comprises two power switches and an output filter. The two power switches include a high-side power switch and a low-side power switch connected in series between the input voltage bus VIN and ground. The high-side and low-side power switches are controlled to regulate the output voltage of the buck power converter. The power converter 100 also includes a gate driver circuitry system for controlling the high-side and low-side power switches, thereby optimizing the speed and efficiency of switching operation. The power converter 100 may further include other critical components, such as current sensing, temperature sensing, and the like. The following will discuss... Figure 2 Describe the detailed structure of the power converter 100.

[0047] In alternative embodiments, the power converter 100 may be implemented as any suitable power conversion topology, such as an inductor-inductor-capacitor (LLC) converter, a switched capacitor converter, a hybrid switched capacitor converter, a full-bridge power converter, a half-bridge power converter, a boost converter, a buck-boost converter, any combination thereof, and the like.

[0048] like Figure 1 As shown, controller 200 is electrically coupled to power converter 100. Specifically, controller 200 is configured to generate PWM signals QHP and QLP to control power converter 100. In operation, controller 200 generates PWM signals QHP and QLP to regulate the output voltage Vo based on the output voltage Vo.

[0049] In some embodiments, controller 200 may be a system controller or a system control device. Controller 200 may be implemented as a microprocessor, digital signal processor, or the like.

[0050] In some embodiments, the controller 200 includes a bootstrap capacitor refresh control device. In some embodiments, the bootstrap capacitor refresh control device includes a bootstrap capacitor refresh pulse generation circuit and logic gates. In some embodiments, the bootstrap capacitor refresh pulse generation circuit is implemented as a timer. The logic gates are implemented as OR gates. In an alternative embodiment, the bootstrap capacitor refresh pulse generation circuit is implemented as a counter.

[0051] It should be noted that Figure 1 The block diagrams shown are merely examples and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, depending on different design requirements, power switches, drivers, and controllers may be integrated into a single semiconductor package.

[0052] In operation, in order to maintain the voltage across the bootstrap capacitor, the bootstrap capacitor refresh control device is configured to generate a low-side turn-on pulse once the low-side switch turn-off time exceeds a predetermined threshold.

[0053] At least seven control methods can be used to maintain the voltage across the bootstrap capacitor. The following will discuss... Figures 3 to 10 These seven control methods are described in detail.

[0054] In a first embodiment of the control method, the bootstrap capacitor refresh pulse generation circuit includes a timer. The timer is configured to measure the off-time of the low-side switch. Once the off-time of the low-side switch exceeds a predetermined threshold, the bootstrap capacitor refresh pulse generation circuit is configured to generate a bootstrap capacitor refresh pulse to turn on the low-side switch. Turning on the low-side switch results in a bias voltage charging the bootstrap capacitor, thus replenishing it. The following will discuss... Figures 3 to 4 The detailed operating principle of the first implementation scheme is described.

[0055] In a second embodiment of the control method, the bootstrap capacitor refresh pulse generation circuit includes a counter. The counter is configured to count clock cycles in which the low-side switch remains off. Once the number of clock cycles exceeds a predetermined threshold, the bootstrap capacitor refresh pulse generation circuit is configured to generate a bootstrap capacitor refresh pulse to turn on the low-side switch. Turning on the low-side switch results in a bias voltage charging the bootstrap capacitor, thus replenishing it. The following will discuss... Figures 5 to 6 The detailed operating principle of the second implementation scheme is described.

[0056] In a third embodiment of the control method, the bootstrap capacitor refresh pulse generating circuit includes a timer or counter. Once the off-time of the low-side switch exceeds a predetermined threshold, the bootstrap capacitor refresh pulse generating circuit is configured to generate a bootstrap capacitor refresh pulse to turn on the low-side switch. In operation, the predetermined threshold is dynamically adjustable. More specifically, the predetermined threshold is adjusted based on the current flowing through the power converter 100. The following will discuss... Figure 7 The detailed operating principles of the third implementation scheme are described.

[0057] In a fourth embodiment of the control method, the bootstrap capacitor refresh pulse generation circuit includes a timer or counter. Once the off-time of the low-side switch exceeds a predetermined threshold, the bootstrap capacitor refresh pulse generation circuit is configured to generate a bootstrap capacitor refresh pulse to turn on the low-side switch. In operation, the width of the bootstrap capacitor refresh pulse is dynamically adjustable. More specifically, the width of the bootstrap capacitor refresh pulse is adjusted based on the slope of the current flowing through the power converter 100. The following will discuss... Figure 7 The detailed operating principles of the fourth implementation scheme are described.

[0058] In a fifth embodiment of the control method, the bootstrap capacitor refresh pulse generating circuit includes a timer or counter. Once the off-time of the low-side switch exceeds a predetermined threshold, the bootstrap capacitor refresh pulse generating circuit is configured to generate a bootstrap capacitor refresh pulse to turn on the low-side switch. In operation, the width of the bootstrap capacitor refresh pulse is dynamically adjustable. More specifically, the width of the bootstrap capacitor refresh pulse is adjusted based on the output voltage of the power converter 100. The following will discuss... Figure 8 The detailed operating principles of the fifth implementation scheme are described.

[0059] In a sixth embodiment of the control method, the bootstrap capacitor refresh pulse generation circuit includes a timer or counter. Once the off-time of the low-side switch exceeds a predetermined threshold, the bootstrap capacitor refresh pulse generation circuit is configured to generate a bootstrap capacitor refresh pulse to turn on the low-side switch. In operation, the width of the bootstrap capacitor refresh pulse is dynamically adjustable. More specifically, the width of the bootstrap capacitor refresh pulse is adjusted based on the compensation (comp) signal of the power converter 100. The following will discuss... Figure 9 The detailed operating principles of the sixth implementation scheme are described.

[0060] In a seventh embodiment of the control method, the bootstrap capacitor refresh pulse generating circuit includes a timer or counter. Once the off-time of the low-side switch exceeds a predetermined threshold, the bootstrap capacitor refresh pulse generating circuit is configured to generate a bootstrap capacitor refresh pulse to turn on the low-side switch. In operation, the width of the bootstrap capacitor refresh pulse is dynamically adjustable. More specifically, the width of the bootstrap capacitor refresh pulse is adjusted based on a combination of the fourth, fifth, and sixth embodiments. The following will discuss... Figure 10 The detailed operating principle of the seventh implementation scheme is described.

[0061] Figure 2 Description of various embodiments according to this disclosure Figure 1 The diagram shows a schematic of a power converter. Power converter 100 is a buck converter. A buck converter includes a high-side switch QH, a low-side switch QL, an output inductor L1, and an output capacitor Co. (As shown...) Figure 2 As shown, the high-side switch QH and the low-side switch QL are connected in series between the input voltage bus VIN and ground. The output inductor L1 is connected between the common node (SW) of the high-side switch QH and the low-side switch QL and the output voltage bus Vo. The output capacitor Co is connected between the output voltage bus Vo and ground.

[0062] The power converter 100 further includes a high-side driver 201, a low-side driver 202, and a bootstrap capacitor C. BS And diode D1. Diode D1 and bootstrap capacitor C BS It is connected in series between the bias voltage Vb and the common node of QH and QL. The positive supply terminal of the high-side driver 201 is connected to diode D1 and bootstrap capacitor C. BS The common node of QH and QL. The negative supply terminal of the high-side driver 201 is connected to the common node of QH and QL. The positive supply terminal of the low-side driver 202 is connected to the bias voltage Vb. The negative supply terminal of the low-side driver 202 is connected to ground.

[0063] The high-side driver 201 is configured to receive a high-side PWM signal QHP from the controller 200. Based on the received signal, the high-side driver 201 generates a high-side gate drive signal QH_G that is applied to the gate of the high-side switch QH through the high-side driver 201.

[0064] The bootstrap capacitor refresh control device 203 is configured to receive a low-side PWM signal QLP1 from the controller 200. Based on the low-side PWM signal QLP1, the bootstrap capacitor refresh control device 203 is configured to generate a modified low-side PWM signal QLP fed into the low-side driver 202. Based on the received signal, the low-side driver 202 generates a low-side gate drive signal QL_G for the low-side switch QL.

[0065] In operation, when the high-side switch QH is turned on and the low-side switch QL is turned off, current flows from the input voltage VIN through the output inductor L1 to the load. The output inductor L1 resists sudden changes in current by storing energy in its magnetic field. The output capacitor Co supplies current to the load, thus smoothing the output voltage Vo. When the high-side switch QH is turned off and the low-side switch QL is turned on, the output inductor L1 releases its stored energy to maintain current flow to the load. The output capacitor Co continues to smooth the output voltage. In operation, the duty cycle (the ratio of the on-time of the high-side switch QH to the total switching period) is used to control the output voltage Vo. By adjusting the duty cycle, the output voltage Vo can be regulated to a predetermined level.

[0066] According to an embodiment, the switches (e.g., switches QH and QL) may be metal-oxide-semiconductor field-effect transistor (MOSFET) devices. Alternatively, the switches may be any controllable switches, such as insulated-gate bipolar transistor (IGBT) devices, integrated gate commutated thyristor (IGCT) devices, gate turn-off thyristor (GTO) devices, silicon controlled rectifier (SCR) devices, junction gate field-effect transistor (JFET) devices, MOS controlled thyristor (MCT) devices, gallium nitride (GaN)-based power devices, silicon carbide (SiC)-based power devices, and the like.

[0067] It should be noted that, although Figure 2 The switches QH and QL are shown as a single n-type transistor, but those skilled in the art will recognize that many variations, modifications, and alternatives are possible. For example, depending on the application and design requirements, switches QH and QL may be implemented as p-type transistors. Furthermore, Figure 2 Each switch shown can be implemented as multiple switches connected in parallel. Furthermore, a capacitor can be connected in parallel with one switch to achieve zero-voltage switching (ZVS) / zero-current switching (ZCS).

[0068] Figure 3 Description of various embodiments according to this disclosure Figure 2 The diagram illustrates a first embodiment of the bootstrap capacitor refresh control device. The bootstrap capacitor refresh control device 203 includes a logic gate 304 and a timer 302. In some embodiments, the logic gate 304 is an OR gate. The timer 302 is implemented as any suitable timer. The timer 302 serves as a bootstrap capacitor refresh pulse generation circuit. Figure 3 As shown, the low-side PWM signal QLP1 generated by the controller is fed into the first input of OR gate 304 and the input of timer 302. The output of timer 302 is fed into the second input of OR gate 304. The output of OR gate 304 is applied to the gate of low-side switch QL through low-side driver 202.

[0069] During operation, as both QH and QL switch in each cycle, the voltage across the bootstrap capacitor is maintained at a sufficient level. The low-side PWM signal QLP1 is routed through OR gate 304 and delivered to the gate of QL via low-side driver 202. Timer 302 is triggered by the falling edge of the low-side PWM signal QLP1. Because the low-side switch QL turns on before reaching a predetermined threshold, timer 302 is reset at the end of each PWM cycle, thereby preventing it from generating a refresh pulse.

[0070] Under light load conditions (e.g., during discontinuous mode operation), timer 302 generates a refresh pulse to turn on the low-side switch QL when the off-time of QL exceeds a predetermined threshold. More specifically, timer 302 is triggered by the falling edge of the low-side PWM signal QLP1 when the low-side switch QL is off. If the low-side switch QL remains off for a sufficient time to exceed the predetermined threshold, the output of timer 302 generates a refresh pulse to turn on the low-side switch QL via OR gate 304 and low-side driver 202. This process enables bootstrap capacitor refresh control device 203 to measure the duration since the low-side switch was off, and thus generate a refresh pulse once this off-time of the low-side switch QL exceeds the predetermined threshold.

[0071] Figure 4 Description of various embodiments according to this disclosure Figure 3 The image shows various signals associated with the bootstrap capacitor refresh control device. The horizontal axis represents the time interval. There are three rows. The first row represents the gate drive signal (QH_G) of the high-side switch QH. The second row represents the gate drive signal (QL_G) of the low-side switch QL. The third row represents the timer output signal.

[0072] At time t1, the gate drive signal QH_G of the high-side switch changes from a logic low state to a logic high state. In response to this change, the high-side switch QH is turned on. From t1 to t2, the current flowing through inductor L1 increases linearly.

[0073] At time t2, the high-side switch QH is turned off, and the low-side switch QL is turned on. From t2 to t3, the current flowing through inductor L1 decreases linearly. Figure 3 As shown, at t3, the low-side switch QL is turned off. From t3 onwards, the power conversion system operates in discontinuous conduction mode. From t3 to t4, both the high-side switch QH and the low-side switch QL are turned off. At t3, a timer measures the turn-off time of the low-side switch QL, starting from the falling edge of the low-side gate drive signal QL_G.

[0074] At t4, the turn-off time of the low-side switch QL reaches the predetermined threshold T. OFFTHThe output of timer 302 generates a refresh pulse T. RF Return to reference. Figure 3 Refresh pulse T RF A bias voltage Vb is applied to the gate of the low-side switch QL via OR gate 304 and low-side driver 202. Therefore, from t4 to t5, the low-side gate drive signal QL_G is in a logic high state. From t4 to t5, the low-side switch QL is turned on. Once the low-side switch QL is turned on, the bias voltage Vb is applied to the bootstrap capacitor C. BS Perform a supplement and reset the timer. After t5, repeat the process described above.

[0075] Figure 5 Description of various embodiments according to this disclosure Figure 2 The diagram shows a second embodiment of the bootstrap capacitor refresh control device. The second embodiment is related to... Figure 3 The first embodiment shown is similar, except that the timer is replaced by a counter. Figure 5 As shown, the low-side PWM signal QLP1 generated by the controller is fed into the first input of OR gate 504 and the input of counter 502. The output of counter 502 is fed into the second input of OR gate 504. The output of OR gate 504 is applied to the gate of low-side switch QL through low-side driver 202.

[0076] Under light load conditions (e.g., during discontinuous mode operation), if the off-time of the low-side switch QL exceeds a predetermined threshold, counter 502 can generate a refresh pulse to turn QL on. More specifically, when the low-side switch QL is off, counter 502 begins counting clock cycles. Once the number of clock cycles reaches a predetermined value, the output of counter 502 generates a refresh pulse T. RF The low-side switch QL is turned on via OR gate 304 and low-side driver 202.

[0077] In some embodiments, counter 502 operates using a clock. A predetermined number is determined by dividing a predetermined threshold by the time period of the clock.

[0078] Figure 6 Description of various embodiments according to this disclosure Figure 5 The diagram shows the various signals associated with the bootstrap capacitor refresh control device. The horizontal axis represents the time interval. There are three rows. The first row represents the gate drive signal (QH_G) of the high-side switch QH. The second row represents the gate drive signal (QL_G) of the low-side switch QL. The third row represents the counter output signal.

[0079] At time t1, the gate drive signal QH_G of the high-side switch changes from a logic low state to a logic high state. In response to this change, the high-side switch QH is turned on. From t1 to t2, the current flowing through inductor L1 increases linearly.

[0080] At time t2, the high-side switch QH is turned off, and the low-side switch QL is turned on. From t2 to t3, the current flowing through inductor L1 decreases linearly. Figure 5 As shown, at t3, the low-side switch QL is turned off. Starting at t3, the power conversion system operates in discontinuous conduction mode. From t3 to t4, both the high-side switch QH and the low-side switch QL are turned off. At t3, the counter begins counting clock cycles starting from the falling edge of the low-side gate drive signal QL_G.

[0081] At t4, the number of clock cycles reaches the predetermined number N. OFFTH The counter's output generates a refresh pulse T. RF Return to reference. Figure 5 Refresh pulse T RF A bias voltage Vb is applied to the gate of the low-side switch QL via OR gate 504 and low-side driver 202. Therefore, from t4 to t5, the low-side gate drive signal QL_G is in a logic high state. From t4 to t5, the low-side switch QL is turned on. Once the low-side switch QL is turned on, the bias voltage Vb is applied to the bootstrap capacitor C. BS Perform a supplement and reset the counter. After t5, repeat the process described above.

[0082] Figure 7 Description of various embodiments according to this disclosure Figure 2 The diagrams shown illustrate the third and fourth embodiments of the bootstrap capacitor refresh control device. Figure 7 As shown, the bootstrap capacitor refresh control device 203 is configured to receive a current IL flowing through the power converter 100. In a third embodiment, the current is used to dynamically adjust a predetermined threshold. Additionally, in a fourth embodiment, the slope of the current is used to dynamically adjust the width of the refresh pulse.

[0083] In a third embodiment, the predetermined threshold (e.g., a time threshold for a timer) is dynamically adjustable. In some embodiments, the predetermined threshold is inversely proportional to the current flowing through the power converter 100. For example, under light load conditions, the current flowing through the power converter 100 is in the range of 1 mA to 100 mA. The predetermined threshold at 1 mA is approximately 100 times larger than the predetermined threshold at 100 mA. In an alternative embodiment, the predetermined threshold is negatively correlated with the current flowing through the power converter 100. For example, as the current flowing through the power converter 100 increases, the refresh pulse width decreases, and as the current flowing through the power converter 100 decreases, the refresh pulse width increases.

[0084] In the fourth embodiment, the refresh pulse width is dynamically adjustable. In some embodiments, this pulse width is negatively correlated with the slope of the current flowing through the power converter 100. In other words, as the current slope increases, the refresh pulse width decreases, and as the current slope decreases, the refresh pulse width increases.

[0085] The advantage of dynamically adjusting the refresh pulse width is that decreasing the pulse width as the current slope increases helps minimize the impact of turning on the low-side switch on the output voltage. Conversely, increasing the pulse width at higher slopes enables the bootstrap capacitor C... BS Complete recharging.

[0086] Figure 8 Description of various embodiments according to this disclosure Figure 2 The diagram shows a fifth embodiment of the bootstrap capacitor refresh control device. Figure 8 As shown, the bootstrap capacitor refresh control device 203 is configured to receive the output voltage Vo of the power converter 100. The output voltage Vo is used to dynamically adjust the width of the refresh pulse.

[0087] In some embodiments, the pulse width is proportional to the difference between the output voltage of the power converter 100 and a set value. Under light load conditions, the output voltage may exceed this set value. Upon detecting an increased output voltage, the pulse width is increased to ensure full recharging of the bootstrap capacitor.

[0088] Figure 9 Description of various embodiments according to this disclosure Figure 2 A schematic diagram of the sixth embodiment of the bootstrap capacitor refresh control device shown in the figure. Figure 9 As shown, the bootstrap capacitor refresh control device 203 is configured to receive the compensation signal COMP from the power converter 100. The compensation signal is used to dynamically adjust the width of the refresh pulse.

[0089] In some embodiments, a compensation signal is tapped at the output of the error amplifier. The inverting input of the error amplifier is connected to the output of the power converter 100 via a resistor divider. The non-inverting input of the error amplifier is configured to receive a predetermined reference. A compensation network is coupled between the output of the error amplifier and ground.

[0090] The width of the refresh pulse is dynamically adjustable. In some embodiments, the width of the refresh pulse is negatively correlated with the voltage of the compensation signal. In other words, as the voltage of the compensation signal increases, the refresh pulse width decreases, and as the voltage of the compensation signal decreases, the refresh pulse width increases.

[0091] Figure 10Description of various embodiments according to this disclosure Figure 2 The diagram shows a seventh embodiment of the bootstrap capacitor refresh control device. (See figure.) Figure 10 As shown, the bootstrap capacitor refresh control device 203 is configured to receive the current IL flowing through the power converter 100, the output voltage Vo, and the compensation signal COMP. In some embodiments, a first width of the refresh pulse is determined based on the slope of the current flowing through the power converter 100. A second width of the refresh pulse is determined based on the compensation signal of the power converter 100. To further improve the performance of the bootstrap capacitor refresh control device 203, the width of the refresh pulse is set alternately using the first width and the second width.

[0092] Figure 11 Description of various embodiments of the present disclosure for control Figure 1 The flowchart of the power conversion system method shown in the figure. Figure 11 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 11 The steps shown in the document.

[0093] At step 1102, the power conversion system is configured to operate in a discontinuous conduction mode, wherein the power conversion system includes a power converter connected between the input voltage bus and the output voltage bus and a controller electrically coupled to the power converter.

[0094] At step 1104, the bootstrap capacitor refresh control device is configured to measure the turn-off time of the low-side switch of the power converter.

[0095] At step 1106, the bootstrap capacitor refresh control device is configured to generate a refresh pulse to turn on the low-side switch of the power converter once the off time of the low-side switch exceeds a predetermined threshold.

[0096] The method further includes: configuring a timer in the bootstrap capacitor refresh control device to measure the duration after the low-side switch is turned off; configuring the bootstrap capacitor refresh control device to generate a refresh pulse once the low-side switch is turned off for more than a predetermined threshold; and resetting the timer once the low-side switch is turned on.

[0097] In some embodiments, the bootstrap capacitor refresh control device includes an OR gate and a timer, wherein a low-side PWM signal is fed into a first input of the OR gate, the output of the timer is fed into a second input of the OR gate, and the output of the OR gate is applied to the gate of a low-side switch via a low-side driver.

[0098] The method further includes: configuring a counter in the bootstrap capacitor refresh control device to count the number of clock cycles after the low-side switch is turned off; configuring the bootstrap capacitor refresh control device to generate a refresh pulse once the off time of the low-side switch exceeds a predetermined threshold; and resetting the counter once the low-side switch is turned on.

[0099] In some embodiments, the bootstrap capacitor refresh control device includes an OR gate and a counter, wherein a low-side PWM signal is fed into a first input of the OR gate, the output of the counter is fed into a second input of the OR gate, and the output of the OR gate is applied to the gate of a low-side switch via a low-side driver.

[0100] The method further includes dynamically adjusting a predetermined threshold based on the current flowing through the power converter.

[0101] The method further includes dynamically adjusting the width of the refresh pulse based on the slope of the current flowing through the power converter.

[0102] The method further includes dynamically adjusting the width of the refresh pulse based on the compensation signal of the power converter.

[0103] The method further includes: determining a first width of the refresh pulse based on the slope of the current flowing through the power converter; and determining a second width of the refresh pulse based on a compensation signal of the power converter, wherein the width of the refresh pulse is set alternately using the first width and the second width.

[0104] Although this description has been described in detail, it should be understood that various changes, alternatives, and modifications may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, as it will be readily apparent from this disclosure to those skilled in the art that processes, machines, manufactures, material compositions, components, methods, or steps (currently existing or to be developed) that can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein can be utilized according to this disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods, or steps within their scope.

Claims

1. An apparatus comprising: A bootstrap capacitor refresh pulse generation circuit is configured to generate a refresh pulse to turn on the low-side switch once the off-time of the low-side switch of the power converter exceeds a predetermined threshold. and A logic gate configured to receive the refresh pulse and the low-side pulse width modulation (PWM) signal, and to generate a drive signal applied to the gate of the low-side switch of the power converter.

2. The device according to claim 1, wherein the power converter is a buck converter, comprising: The high-side switch and the low-side switch are connected in series between the input voltage bus and ground; An inductor is connected in series between the common node of the high-side switch and the low-side switch and the output voltage bus; and An output capacitor is connected between the output voltage bus and ground.

3. The device according to claim 1 or 2, wherein: The logic gate is an OR gate; and The bootstrap capacitor refresh pulse generation circuit is a timer configured to measure the duration after the low-side switch is turned off, and generates the refresh pulse once the off-time of the low-side switch exceeds the predetermined threshold, wherein: The low-side gate drive signal is fed into the first input of the OR gate; The output of the timer is fed into the second input of the OR gate; and The output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

4. The device according to claim 1 or 2, wherein: The logic gate is an OR gate; and The bootstrap capacitor refresh pulse generation circuit is a counter configured to count the number of clock cycles after the low-side switch is turned off, and to generate the refresh pulse once the off-time of the low-side switch exceeds the predetermined threshold, wherein: The low-side gate drive signal is fed into the first input of the OR gate; The output of the counter is fed into the second input of the OR gate; and The output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

5. The device according to any one of claims 1 to 4, wherein: The predetermined threshold is dynamically adjustable, and the predetermined threshold is negatively correlated with the current flowing through the power converter.

6. The device according to any one of claims 1 to 5, wherein: The width of the refresh pulse is dynamically adjustable, and the width of the refresh pulse is negatively correlated with the slope of the current flowing through the power converter.

7. The device according to any one of claims 1 to 5, wherein: The width of the refresh pulse is dynamically adjustable, and the width of the refresh pulse is proportional to the difference between the output voltage of the power converter and the setting value of the power converter.

8. The device according to any one of claims 1 to 5, wherein: The width of the refresh pulse is dynamically adjustable, and the width of the refresh pulse is negatively correlated with the compensation voltage of the power converter.

9. The device according to any one of claims 1 to 5, wherein: The first width of the refresh pulse is determined based on the slope of the current flowing through the power converter; and The second width of the refresh pulse is determined based on the compensation signal of the power converter, wherein the width of the refresh pulse is alternately set using the first width and the second width.

10. A method comprising: Configure a power conversion system to operate in a discontinuous conduction mode, wherein the power conversion system includes a power converter connected between an input voltage bus and an output voltage bus and a controller electrically coupled to the power converter; Configure a bootstrap capacitor refresh control device to measure the turn-off time of the low-side switch of the power converter; and The bootstrap capacitor refresh control device is configured to generate a refresh pulse to turn on the low-side switch of the power converter once the off-time of the low-side switch exceeds a predetermined threshold.

11. The method of claim 10, further comprising: Configure a timer in the bootstrap capacitor refresh control device to measure the duration after the low-side switch is turned off; The bootstrap capacitor refresh control device is configured to generate the refresh pulse once the off-time of the low-side switch exceeds the predetermined threshold. and Once the low-side switch is turned on, the timer is reset.

12. The method of claim 11, wherein the bootstrap capacitor refresh control device comprises an "OR" gate and the timer, and wherein: The low-side PWM signal is fed into the first input of the OR gate; The output of the timer is fed into the second input of the OR gate; and The output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

13. The method of claim 10, further comprising: Configure the counter in the bootstrap capacitor refresh control device to count the number of clock cycles after the low-side switch is turned off. The bootstrap capacitor refresh control device is configured to generate the refresh pulse once the off-time of the low-side switch exceeds the predetermined threshold. and Once the low-side switch is turned on, the counter is reset.

14. The method of claim 13, wherein the bootstrap capacitor refresh control device comprises an OR gate and the counter, and wherein: The low-side PWM signal is fed into the first input of the OR gate; The output of the counter is fed into the second input of the OR gate; and The output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

15. The method according to any one of claims 10 to 14, further comprising: The predetermined threshold is dynamically adjusted based on the current flowing through the power converter.

16. The method according to any one of claims 10 to 15, further comprising: The width of the refresh pulse is dynamically adjusted based on the slope of the current flowing through the power converter.

17. The method according to any one of claims 10 to 15, further comprising: The width of the refresh pulse is dynamically adjusted based on the difference between the output voltage of the power converter and the set value of the power converter.

18. The method according to any one of claims 10 to 15, further comprising: The width of the refresh pulse is dynamically adjusted based on the compensation signal of the power converter.

19. The method according to any one of claims 10 to 15, further comprising: The first width of the refresh pulse is determined based on the slope of the current flowing through the power converter; and The second width of the refresh pulse is determined based on the compensation signal of the power converter, wherein the width of the refresh pulse is alternately set using the first width and the second width.

20. A system comprising: A power converter that connects between the input voltage bus and the output voltage bus; and A controller electrically coupled to the power converter, wherein the controller includes a bootstrap capacitor refresh control device, and wherein: The bootstrap capacitor refresh control device is configured to measure the turn-off time of the low-side switch of the power converter; and The bootstrap capacitor refresh control device is configured to generate a refresh pulse to turn on the low-side switch of the power converter once the off-time of the low-side switch exceeds a predetermined threshold.

21. The system of claim 20, wherein the power converter comprises: The high-side switch and the low-side switch are connected in series between the input voltage bus and ground; An inductor is connected in series between the common node of the high-side switch and the low-side switch and the output voltage bus; and An output capacitor is connected between the output voltage bus and ground.

22. The system of claim 20 or 21, wherein the bootstrap capacitor refresh control device comprises an OR gate and a timer, and wherein: The low-side PWM signal is fed into the first input of the OR gate; The output of the timer is fed into the second input of the OR gate; and The output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

23. The system of claim 20 or 21, wherein the bootstrap capacitor refresh control device comprises an OR gate and a counter, and wherein: The low-side PWM signal is fed into the first input of the OR gate; The output of the counter is fed into the second input of the OR gate; and The output of the OR gate is applied to the gate of the low-side switch via a low-side driver.

24. The system according to any one of claims 20 to 23, wherein: The predetermined threshold is dynamically adjustable, and the predetermined threshold is negatively correlated with the current flowing through the power converter.

25. The system according to any one of claims 20 to 24, wherein: The width of the refresh pulse is dynamically adjustable, and the width of the refresh pulse is negatively correlated with the slope of the current flowing through the power converter.

26. The system according to any one of claims 20 to 24, wherein: The width of the refresh pulse is dynamically adjustable, and the width of the refresh pulse is proportional to the difference between the output voltage of the power converter and the setting value of the power converter.

27. The system according to any one of claims 20 to 24, wherein: The width of the refresh pulse is dynamically adjustable, and the width of the refresh pulse is negatively correlated with the compensation voltage of the power converter.

28. The system according to any one of claims 20 to 24, wherein: The first width of the refresh pulse is negatively correlated with the slope of the current flowing through the power converter; and The second width of the refresh pulse is negatively correlated with the compensation signal of the power converter, wherein the width of the refresh pulse is alternately set using the first width and the second width.

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