Switching driver

Abstract

This application relates to methods and apparatus for switch-mode drivers. A BTL driver has a switch network operable in different switch states, wherein, in each switch state, each of a first and a second output node is connected to a corresponding one of a first switch voltage, a second switch voltage, or an intermediate switch voltage provided by a driver capacitor between the first and second switch voltages. A controller is configured to control the switch network to operate in a sequence of switch states to generate a differential drive signal based on an input signal. The controller is configured to provide voltage regulation to the intermediate voltage provided by the driver capacitor when the driver switch network operates in the sequence of switch states to generate the differential drive signal.

Description

[0001] Representative embodiments of this disclosure relate to methods, apparatuses, and / or implementations related to switch driver circuits, and more particularly to switch driver or amplifier circuits that can be used to drive transducers (e.g., audio transducers).

[0002] Many electronic devices include transducer driver circuitry systems for driving transducers with drive signals, such as driving the audio output transducer of a device or its connected accessories with audio drive signals.

[0003] In some applications, the transducer drive circuitry may include a switch driver, such as a Class D amplifier or similar device, to generate the drive signal. Switch drivers, sometimes called switch-mode drivers or switch-mode amplifiers, can have relatively high power efficiency and are therefore advantageous in certain applications. Switch drivers typically operate to switch the output node between different switching voltages, with their duty cycle providing the desired drive signal voltage on average over one or more switching cycles.

[0004] Multilevel switching drivers (also known as multilevel converters) have been proposed that modulate the output node of the switching driver between selected voltages from a set of at least three different switching voltages. For example, instead of modulating the output node only between high and low switching voltages (e.g., VDD and ground), the relevant output node can be modulated between an intermediate voltage (e.g., VDD / 2) and a selected one of the high and low switching voltages with a controlled duty cycle, depending on the desired output voltage. Switching between VDD and VDD / 2, or between VDD / 2 and ground, reduces the amplitude of voltage modulation at the output node, offering the advantage of reduced ripple current and EMI emissions. In some cases, capacitors can be used as part of the switching driver, for example as flying capacitors, to provide at least one of the stated switching voltages. One example is a multilevel switching driver arrangement based on a known flying capacitor multilevel inverter topology.

[0005] Known multilevel flying capacitor switch drivers typically require relatively complex control arrangements to monitor the voltage of the flying capacitor and adjust the switching sequence accordingly to maintain charge balance, thereby keeping the correct voltage on the flying capacitor.

[0006] Embodiments of this disclosure relate to methods and apparatus for mitigating at least some of the aforementioned problems in a switch driver.

[0007] According to one aspect of this disclosure, a switch driver circuit for driving a load is provided, comprising: first and second output nodes for outputting a differential drive signal for driving the load; a driver switch network capable of operating in a variety of different switching states, wherein, in each switching state, each of the first and second output nodes is connected to a corresponding one of at least a first switching voltage, a second switching voltage, and an intermediate switching voltage, wherein the intermediate switching voltage is a voltage between the first and second switching voltages and is provided by a driver capacitor selectively connected to each of the first and second output nodes; and a controller configured to control the driver switch network to operate in a sequence of the switching states to generate the differential drive signal based on an input signal; wherein the controller is configured to provide voltage regulation of the intermediate voltage provided by the driver capacitor when the driver switch network operates in the sequence of the switching states to generate the differential drive signal.

[0008] In some implementations, operation in the switching state can cause load current to flow to the load, and wherein the controller can be configured such that, for at least some values ​​of the differential drive signal, the switching state sequence includes at least one instance of a switching state in which the driver capacitor is charged by the load current and at least one instance of a switching state in which the driver capacitor is discharged by the load current. The differential output voltage between the first output node and the second output node can be the same in the switching state in which the driver capacitor is charged by the load current and in the switching state in which the driver capacitor is discharged by the load current. The controller can be configured such that the load current flowing during at least one instance of the switching state in which the driver capacitor is charged by the load current substantially matches the load current flowing during at least one instance of the switching state in which the driver capacitor is discharged by the load current. The controller can be configured such that the total duration of the at least one instance of the switching state in which the driver capacitor is charged by the load current in the switching cycle is the same as the total duration of the at least one instance of the switching state in which the driver capacitor is discharged by the load current in the switching cycle.

[0009] The first voltage can be a first power supply voltage, and the second voltage can be a second power supply voltage. The value of the first power supply voltage can be V, the second power supply voltage can be ground, and the value of the intermediate voltage can be equal to V / 2. In this case, the switching state in which the driver capacitor is charged by the load current can include a switching state in which one of the first and second output nodes is connected to the first power supply voltage V, and the other of the first and second output nodes is connected to the driver capacitor at the intermediate voltage V / 2; and the switching state in which the driver capacitor is discharged by the load current can include a switching state in which one of the first and second output nodes is connected to the driver capacitor at the intermediate voltage V / 2, and the other of the first and second output nodes is connected to the second voltage which is ground.

[0010] In some implementations, the driver capacitor may include a driver capacitor connected in use between first and second capacitor nodes, wherein the first capacitor node is selectively connected to each of the first and second output nodes, and the second capacitor node is connected to a defined reference voltage. The defined reference voltage may be one of a first or second voltage. The defined reference voltage may be ground. In some implementations, the driver capacitor may be the only capacitor that the first and second output nodes can be connected to.

[0011] In some implementations, the driver switch network may include, for each of the first and second output nodes: a first set of three switches for selectively connecting a first common node to the first switch voltage, the intermediate switch voltage, and the associated output node, respectively; and a second set of three switches for selectively connecting a second common node to the second switch voltage, the intermediate switch voltage, and the associated output node, respectively; wherein the controller is configured such that, in a switching state where the output node is connected to the intermediate switch voltage, the associated switches in the first and second sets of three switches are controlled to be turned on.

[0012] In some implementations, the switch driver circuit may further include a bias switch network configured to selectively connect nodes of the driver switch network to the intermediate voltage to bias the nodes of the driver switch network to the intermediate voltage, thereby managing voltage stress across the driver switch network when the switches are in the off state, wherein the controller is configured to control the bias switch network based on the switching state of the driver switch network. The bias switch network may be configured such that substantially no current flows through the bias switch network in any of the switching states.

[0013] In another aspect, a multi-channel amplifier system is provided, comprising a plurality of switch driver circuits according to any embodiment described herein, wherein a common capacitor connected to a common capacitor node is configured as a driver capacitor for each switch driver circuit. The multi-channel amplifier system may be configured such that a first switch driver circuit of the plurality of switch driver circuits is configured to operate in a switching state in which load current in the first switch driver circuit is supplied to the common capacitor node, while a second switch driver circuit of the plurality of switch driver circuits is configured to operate in a switching state in which load current in the second switch driver circuit is supplied to the common capacitor node.

[0014] On the other hand, a multilevel switch driver circuit is provided for driving a load connected between first and second output nodes with a differential drive signal. The multilevel switch driver circuit includes: first and second power supply nodes for receiving first and second power supply voltages; first and second capacitor nodes for connection to a driver capacitor in use; a switch network configured to selectively connect each of the first and second output nodes to a corresponding one of the first power supply node, the second power supply node, or the first capacitor node; and a controller for controlling the switch network according to a switch state sequence to generate the differential drive signal, wherein the driver switch network provides charge balance to the driver capacitor when operating according to the switch state sequence to generate the differential drive signal.

[0015] In some implementations, the second capacitor node may be connected to a defined reference voltage.

[0016] On the other hand, a multilevel switch driver circuit is provided for driving a load in a bridged load configuration, the multilevel switch driver circuit comprising: first and second output nodes for connection to the load in use; first and second capacitor nodes for connection to a driver capacitor in use, wherein the first capacitor node is selectively connectable to each of the first and second output nodes via a switch network, and the second capacitor node is connected to a defined reference voltage; and a controller configured to control the multilevel switch driver circuit to generate differential drive signals across the load based on an input signal, wherein the controller is configured to operate in a switching cycle including the following states for at least some differential drive signal values: a first state in which the first capacitor node is connected to one of the first and second output nodes and charged by a current flowing through the first and second output nodes; and a second state in which the first capacitor node is connected to the other of the first and second output nodes and discharged by a current flowing through the other of the first and second output nodes.

[0017] On the other hand, a multi-channel amplifier system is provided, comprising: a plurality of switch drivers, each of the switch drivers being configured to selectively modulate a voltage at at least one output node of the switch driver between selected switching voltages to drive a corresponding load; wherein one of the switching voltages is a capacitor voltage provided in use by a common driver capacitor shared by the plurality of switch drivers and connected to a common capacitor node; and a controller for controlling the operation of the plurality of switch drivers in a switching cycle such that a load current flowing between each of the plurality of switch drivers and the common capacitor node provides voltage regulation of the capacitor voltage.

[0018] In another aspect, a switch driver circuit for driving a load is provided, comprising: first and second output nodes for outputting a differential drive signal via a filter including a series inductor to drive the load. The switch driver circuit includes: first and second power supply nodes configured to receive first and second power supply voltages, respectively; and an intermediate voltage node configured to receive an intermediate voltage provided by a driver capacitor, the intermediate voltage being a voltage level between the first and second power supply voltages. A driver switch network is configured such that each of the first and second output nodes can be selectively connected to a correspondingly selected one of the first power supply node, the second power supply node, and the intermediate voltage node. A controller is configured to control the driver switch network to operate in a sequence of switching states to generate the differential drive signal based on an input signal. The controller is configured to adjust the intermediate voltage provided by the driver capacitor when the driver switch network operates in the sequence of switching states to generate the differential drive signal.

[0019] In some implementations, the intermediate voltage provided by the driver capacitor may be equal to half of the input voltage defined by the first and second power supply voltages. In some implementations, the intermediate voltage provided by the driver capacitor may be equal to a first proportion of the input voltage defined by the first and second power supply voltages, wherein the first proportion is not equal to half.

[0020] The controller can be configured to adjust the intermediate voltage of the driver capacitor to dynamically change the value of the intermediate voltage based on at least one operating parameter of the switch driver circuit. The operating parameter may include at least one of the following: the level of the input signal; the generated output voltage; the load current; the output power level; and the operating mode of the switch driver circuit.

[0021] In some implementations, the filter arrangement may also include parallel capacitors.

[0022] In some implementations, for input signal levels below a first threshold, the controller may be configured to operate in an operating mode in which the driver switching network is configured to transfer energy from at least one of the first and second power supply voltages to the driver capacitor via inductors arranged in the filter, according to the switching state sequence.

[0023] In some implementations, the driver switch network may include, for each of the first and second output nodes: a first set of switches for selectively connecting one of the first or second output nodes to the first power node or the intermediate voltage node, and a second set of switches for selectively connecting one of the first or second output nodes to the second power node. Each of the first set of switches may include a first switch coupled between the corresponding one of the first or second output nodes and a corresponding first common node, a second switch coupled between the corresponding first common node and the first power voltage node, and a third switch coupled between the corresponding first common node and the intermediate voltage node. Each second set of switches may include one or more switches connected in series between the corresponding one of the first or second output nodes and the second power node. Each second set of switches may also be configured to selectively connect one of the first or second output nodes to the intermediate voltage node, and each second set of switches may include a fourth switch coupled between the corresponding one of the first or second output nodes and a corresponding second common node, a fifth switch coupled between the corresponding second common node and the second power voltage node, and a third switch coupled between the corresponding second common node and the intermediate voltage node. In some implementations, in at least one operating mode, the controller may be configured to turn on each of the first, second, fourth, and fifth switches in the first and second sets of switches for one of the first or second output nodes, so as to connect the one of the first or second output nodes to the intermediate voltage node.

[0024] In some implementations, the driver switch network may be implemented by MOSFET switches with unidirectional current blocking capability.

[0025] In some implementations, the input signal can be an audio signal. The load can be an audio output transducer.

[0026] A driver device may include such a switch driver circuit, as well as the filter arrangement and the load.

[0027] In another aspect, a switch driver circuit for driving a load is provided, comprising: a first output node for outputting an output signal to a filter arrangement including a series inductor; first and second power supply nodes configured to receive first and second power supply voltages, respectively; and an intermediate voltage node configured to receive an intermediate voltage provided by a driver capacitor, the intermediate voltage being at a voltage level between the first and second power supply voltages. A driver switch network is configured such that the first output node can be selectively connected to a selected one of the first power supply node, the second power supply node, and the intermediate voltage node. A controller is configured to control the driver switch network to operate according to a sequence of switching states based on an input signal, such that the output signal filtered by the filter arrangement corresponds to the input signal. The controller is configured to adjust the intermediate voltage provided by the driver capacitor when the driver switch network operates according to the sequence of switching states to generate the differential drive signal.

[0028] In some implementations, the filter arrangement may further include parallel capacitors. In some implementations, for input signal levels below a first threshold, the controller may be configured to operate in an operating mode in which the driver switching network is configured to transfer energy from at least one of the first and second power supply voltages to the driver capacitor via the inductors of the filter arrangement, according to the switching state sequence.

[0029] In another aspect, a switch driver circuit for driving a load is provided, comprising: first and second output nodes for outputting a differential drive signal for driving the load; first and second power supply nodes configured to receive first and second power supply voltages, respectively; and an intermediate voltage node configured to receive an intermediate voltage provided by a driver capacitor, the intermediate voltage being a voltage level between the first and second power supply voltages. A driver switch network is configured such that each of the first and second output nodes can be selectively connected to a correspondingly selected one of the first power supply node, the second power supply node, and the intermediate voltage node. A controller is configured to control the driver switch network to operate in a sequence of switching states to generate the differential drive signal based on an input signal. The driver switch network includes, for each of the first and second output nodes: a first set of switches for selectively connecting an associated one of the first or second output nodes to the first power supply node or the intermediate voltage node; and a second set of switches for selectively connecting an associated one of the first or second output nodes to the second power supply node. Each of the first set of switches includes a first switch coupled between the relevant one of the first or second output nodes and a corresponding first common node, a second switch coupled between the corresponding first common node and the first power supply voltage node, and a third switch coupled between the corresponding first common node and the intermediate voltage node.

[0030] It should be noted that, unless otherwise expressly indicated or clearly incompatible herein, any feature described herein may be implemented in combination with any other one or more of the described features.

[0031] To better understand the examples of this disclosure and to more clearly illustrate how these examples are implemented, reference will now be made to the following figures only by way of example, wherein: Figure 1 An example of a known multilevel flying capacitor switch driver is shown; Figure 2 An example of a multilevel switch driver according to an embodiment is shown; Figure 3 It shows the use of Figure 2 An example of a modulation control scheme for a switch driver; Figure 4 shows various waveforms of the switch driver under different operating states; Figure 5 An example of a multilevel switch driver according to an embodiment is shown; Figure 6a and Figure 6b Another example of a multilevel switch driver according to an embodiment is shown; Figure 7 A multi-channel system with a common driver capacitor is shown; and Figure 8 An example of a single-ended multilevel switch driver is shown.

[0032] The following description illustrates exemplary embodiments according to this disclosure. Further exemplary embodiments and implementations will be apparent to those skilled in the art. Furthermore, those skilled in the art will recognize that various equivalent techniques can be employed in place of or in combination with the embodiments discussed below, and all such equivalents should be considered to be included within the scope of this disclosure.

[0033] Multilevel switch drivers or switch-mode amplifiers for driving transducers have been previously proposed. Figure 1 An example of a multilevel switch driver 100 with a flying capacitor is shown for driving a load 101 based on a known flying capacitor multilevel inverter topology. The switch driver 100 is configured to drive the load 101 in a bridged load (BTL) configuration; in this example, the load is an audio transducer. Therefore, in use, the load 101 is connected between a first output node 102L and a second output node 102R. Each output node is modulated with a controlled duty cycle between selected switching voltages in use, thereby averaging the desired drive signal voltage across the load over one or more switching cycles.

[0034] Switches S1L and S2L are connected in series between the first power supply voltage (VDD in this example) and output node 102L, with node N1L between the switches. Switches S3L and S4L are connected in series between output node 102L and the second power supply voltage (ground in this example), with node N2L between the switches. The first and second power supply voltages define the input voltage of the switch driver, which in this example is equal to VDD. Capacitor CFL is coupled as a first flying capacitor between nodes N1L and N2. The other side of the load has an equivalent set of switches S1R to S4R, the output node is connected between switches S2R and S3R, and a second flying capacitor CFR is connected between nodes N1R and N2R. In use, the first and second flying capacitors CFL and CFR are each charged to an intermediate voltage between the first and second power supply voltages, which in this example is equal to VDD / 2.

[0035] Two sets of switches S1L to S4L and S1R to S4R are operable such that any differential voltage of +VDD, +VDD / 2, zero, -VDD / 2, or -VDD can be applied across the load in different switching states. Controller 103 is configured to generate a switching control signal Scon based on the input signal Sin for controlling switches S1L to S4L and S1R to S4R, thereby switching between selected states with a controlled duty cycle to generate a desired drive voltage across the load, wherein the drive voltage is the average voltage over one or more switching cycles.

[0036] Despite such as Figure 1 The switch driver shown can be used effectively in a variety of applications, but a complex issue lies in balancing the charge on the flying capacitors CFL and CFR to maintain the correct voltage on each driver capacitor. A standard switching sequence of the switch driver 100 typically alternates between charging one of the flying capacitors while delivering voltage to the load, and then discharging that flying capacitor using a switching configuration. To maintain the correct charge balance, and thus the voltage on the flying capacitors, it is usually necessary to measure the voltage of each flying capacitor and modify the switching sequence as needed, which may require relatively complex monitoring and control functions.

[0037] It has also been proposed that the intermediate voltage can be generated and regulated using a specific power supply. For example, US 10,985,717 describes a multilevel Class D amplifier in which a multilevel power supply is used to provide separate voltage levels, such as VDD and VDD / 2. This avoids the problems associated with using flying capacitors to generate the intermediate voltage, but requires a power supply to generate and regulate the intermediate voltage.

[0038] At least some embodiments of this disclosure relate to switch drivers that at least alleviate some of the problems.

[0039] Figure 2 An example of a switch driver 200 (or amplifier) ​​according to an embodiment of the present disclosure is shown, wherein, with reference to... Figure 1 The similar parts discussed are identified using the same reference numerals.

[0040] Figure 2 A load 101 (which may be a transducer load such as an audio output transducer) is shown connected in a BTL configuration between a first output node 102L and a second output node 102R. (Refer to reference...) Figure 1In a similar arrangement of the switch driver discussed, switches S1L and S2L are connected in series between the first power supply voltage (VDD in this example) and output node 102L, with a midpoint node N1L between these switches. Similarly, switches S1R and S2R are connected in series between the first power supply voltage and output node 102R, with a midpoint node N1R. However, in Figure 2 In the example, there is a single switch S34L connected between the output node 102L and the second power supply voltage (ground in this example), and similarly, there is a single switch S34L connected between the output node 102LR and the second power supply voltage.

[0041] Figure 2 The example has a driver capacitor C1 connected in series between a first capacitor node NC1 and a second capacitor node NC2. The first capacitor node NC1 (connected to the first electrode of the driver capacitor C1) can be selectively and independently connected to (or disconnected from) each of nodes N1L and N1R via switches S5L and S5R, respectively. The second capacitor node NC2 (connected to the second electrode of the driver capacitor C1) is coupled to a defined voltage, which in this case is a second supply voltage, i.e., ground in this example. This defined voltage remains substantially unchanged during use, i.e., it is maintained at a nominal constant value; therefore, the second electrode of the driver capacitor C1 is effectively connected to this defined voltage during use, for example, ground.

[0042] In use, the driver capacitor C1 is charged to a desired voltage, which can be a proportion (such as half) of the input voltage defined by the first and second power supply voltages. For example, in the illustrated example, the driver capacitor is charged to a voltage equal to +VDD / 2 in use. However, it should be noted that the voltage of the driver capacitor C1 can be set to some other proportion of the input voltage defined by the first and second power supply voltages.

[0043] In some implementations, the initial charge on the driver capacitor C1 can be established when the switch driver 200 starts up by arranging the driver capacitor C1 as part of a capacitive voltage divider. For example, an additional capacitor ( Figure 2(Not shown in the diagram) It can be connected between the power supply voltage VDD and node NC1, so that during startup, the driver capacitor C1 and the additional capacitor are connected in series between VDD and ground, and node NC1 is unloaded, for example, switches S5L and S5R are open. In this way, the voltage VDD will be divided between the additional capacitor and the driver capacitor C1 according to their respective capacitance values. For example, if the additional capacitor and the driver capacitor C1 have the same capacitance value, the voltage will be divided equally, and the driver capacitor C1 will be charged to VDD / 2. It should be noted that this capacitor divider arrangement can provide an initial charge to the driver capacitor C1 during startup, but as described below, the voltage of the driver capacitor C1 will subsequently be regulated during use. Those skilled in the art will also understand that in other embodiments, other methods can be implemented to initially charge the driver capacitor C1 to the desired voltage during startup.

[0044] Switches S1L to S5L and S1R to S5R constitute the switching network of the switch driver. This switching network is operable such that, in use, each of the output nodes 102L and 102R can be selectively and independently connected to a first power supply voltage (i.e., VDD), the voltage of the driver capacitor C1 (i.e., VDD / 2), or a second power supply voltage (i.e., ground). In use, the controller 203 can control the switching network of the switch driver 200 to operate in a sequence of different states, thereby generating the desired drive signal for the load 101.

[0045] In at least some implementations, an output filter arrangement 201 may be present for applying filtering in the output path to the load. Those skilled in the art will understand that some filtering in the output path may be important for certain applications, such as for relatively high-power applications (e.g., driving 10 mW or more of output power), and / or when the output path between the output node of the switching driver and the load 101 may be relatively long (e.g., on the order of tens of centimeters or longer). For example, audio systems in automotive applications and home theaters often require relatively high output power, and the output path between the switching driver and the driven speaker may be on the order of tens of centimeters to several meters; in such applications, EMI may be a particular concern. Therefore, filtering of the output path may be important. Typically, the output filter may comprise an LC (inductor-capacitor) filter arrangement separate from the load 101. Figure 2An example of a basic filter arrangement is shown, which has a series inductor Lfil in the output path and a capacitance Cfil between the output path on each side of the load and a defined reference voltage (such as ground). However, as those skilled in the art will understand, other LC filter arrangements may be implemented, but typically there may be some significant inductance in the output path. Additionally, there may be some capacitance across the load 101. The filter arrangement 201 will typically be configured to provide the desired filtering characteristics for the relevant application; for example, for audio applications, the filter arrangement 201 may be implemented to provide a cutoff frequency higher than about 20 kHz. Therefore, embodiments of this disclosure can be configured to drive a load via an LC filter arrangement having at least one inductor in the output path. In the case of a full-bridge (BTL) configuration, the filter arrangement will typically be symmetrical.

[0046] Figure 2 The switch driver 200 and the reference Figure 1 The discussed switching driver has various advantages compared to other switching drivers. The switching driver 200 can be implemented using only a single driver capacitor C1 to provide an intermediate voltage (i.e., VDD / 2) to either the output terminal 102L or 102R, without requiring a separate capacitor like the one described above. Figure 1 Unlike switching drivers, which require two flying capacitors, this can be beneficial in terms of smaller circuit area and / or reduced cost.

[0047] Furthermore, as mentioned above, the second electrode of the driver capacitor C1 is connected to a reference voltage, such as ground, via the second capacitor node NC2. This can improve the efficiency of the switch driver 200. Additionally, this means that the capacitor voltage of the driver capacitor C1 can be monitored in a relatively direct manner if needed. Figure 1 In the example, for each flying capacitor CFL and CFR, the voltage at the first electrode of the flying capacitor depends not only on the voltage of the flying capacitor itself, but also on the voltage at the second electrode. The voltage at the second electrode may change during use as the flying capacitor switches between different switching states, which complicates the monitoring of the capacitor voltage. For Figure 2 The driver capacitor C1 has its second electrode connected to ground (or other defined fixed voltage) via the second capacitor node NC2. Therefore, if necessary, the voltage of the driver capacitor C1 can be monitored by monitoring the voltage at the first capacitor node NC1.

[0048] also, Figure 2The switching driver 200 can be controlled such that the operation of the switching driver 200 to generate the desired load drive signal also substantially balances the charge on the driver capacitor C1. That is, the switching of the switching driver 200 between selected switching states (in order to modulate the output voltage across the load and provide the desired drive signal) also provides regulation of the voltage on the driver capacitor C1. As will be described in more detail below, for at least some output voltages, the switching driver 200 can selectively operate in two different states, both resulting in the same differential voltage across the load, one state involving charging the driver capacitor C1 by the current in the output load 101, and the other state involving discharging the driver capacitor C1 to provide the load current. By appropriately using examples of these two states in the switching cycle, the charge on the driver capacitor C1 can be substantially balanced while operating the switching driver 200 to generate the desired output voltage based on the input signal. Therefore, the voltage on the driver capacitor is regulated by the operation of the driver itself, rather than by the operation of a separate power supply. Therefore, the driver device 200 does not require any separate circuitry to separately supply charge to the driver capacitor C1 during normal operation.

[0049] For the purposes of this disclosure, different operating states of the switch driver 200 will be identified and marked using two-letter codes, where the first letter indicates the voltage at output node 102L, the second letter indicates the voltage at output node 102R, and where “V” indicates that the relevant output node is connected to the first power supply voltage, i.e., VDD, “C” indicates that the relevant output node is connected to the first capacitor node NC1, and therefore connected to the driver capacitor voltage, i.e., VDD / 2, and “G” indicates that the relevant output node is connected to the second power supply voltage, i.e., ground. For the purposes of this disclosure, references to a positive voltage or a positive differential output voltage across the load should be understood as meaning that the voltage at output node 102L is more positive than the voltage at output node 102R, and references to a negative output voltage should be understood as having the opposite meaning. Therefore, state VG is the state where output node 102L is connected to VDD and output node 102R is connected to ground, and the voltage across load 101 is equal to +VDD; state CG is the state where output node 102L is connected to the capacitor voltage of VDD / 2 and output node 102R is connected to ground, and the voltage across load 101 is equal to +VDD / 2. Positive load current should also be understood as the load current flowing from output node 102L to output node 102R, and negative current should be understood as the current in the opposite direction.

[0050] The switching driver 200 can operate in state VG to generate a positive differential voltage of +VDD across the load, or in the opposite state GV to generate -VDD. In both states, the driver capacitor C1 is disconnected from the output terminals 102L and 102R, and therefore disconnected from the load 101, so it is neither charged nor discharged by any load current.

[0051] To generate a zero-differential voltage across the load, the two output nodes 102L and 102R can be connected to the same voltage. The zero-differential voltage can be generated in any of the states VV, CC, or GG; however, in some implementations, using state CC as the zero-differential voltage state may be advantageous to avoid any discontinuities in the common-mode voltage between different operating states. In state CC, the first electrode of the driver capacitor C1 is connected to both sides of the load 101, so the driver capacitor C1 does not undergo significant charging or discharging.

[0052] To generate a voltage of magnitude VDD / 2 with a given polarity across the load, two different states can be used. For example, +VDD / 2 can be output across the load in state CG or state VC. In state CG, output node 102L is connected to the first electrode of driver capacitor C1, and output node 102R is connected to ground. For ease of explanation, it is assumed that the load current and voltage are in phase, i.e., a positive voltage across the load results in a positive load current, and vice versa. Therefore, the positive load current will be provided by driver capacitor C1, and in this state CG, driver capacitor C1 will be discharged by the load current. Conversely, in state VC, output node 102L is connected to the supply voltage VDD, and output node 102R is connected to the first electrode of driver capacitor C1. As mentioned above, the second electrode of driver capacitor C1 is connected to ground. Therefore, in this state VC, the positive load current comes from the VDD supply, and this load current will charge driver capacitor C1. Similarly, the two opposite states for generating -VDD / 2, namely states CV and GC, involve the charging and discharging of driver capacitor C1 by negative load current, respectively.

[0053] These two different states, used to generate the same differential output voltage, involve charging or discharging the driver capacitor, respectively. They can be used as part of the modulation scheme of the switching driver device 200 to provide charge balance for the driver capacitor C1, i.e., as part of the normal operation of the switching driver device 200 to generate the desired output voltage based on the input signal Sin. Since the two related states generate the same differential voltage across the load, these states can be used in a way that produces a substantially matched load current in each case, i.e., the same average current. This means that charge balance can be achieved simply by ensuring that the durations of the charging and discharging states are equal.

[0054] For example, to generate a drive signal voltage in the range of +VDD / 2 and +VDD, the switch driver 200 can modulate the output voltage of +VDD across the load for a portion of the switching cycle and modulate the output voltage of +VDD / 2 for the remainder of the switching cycle. The voltage +VDD can be generated by operating in state VG. In embodiments of this disclosure, the switch driver operation can be divided into equal time periods spent in state VC and state CG, with the switching cycle ratio of the output voltage +VDD / 2, so that the driver capacitor is charged and discharged by equal amounts during the switching cycle. In this way, the charge balance on the driver capacitor C1 can be maintained. The controller 203 can therefore be configured to control the switch driver 200 to operate in a state sequence such that any instance of operation in state VC is matched by an instance of operation in state CG, the time spent in state VC is matched by the time spent in state CG, and similarly, any instance of state CV is matched by an instance of state GC of equal total duration.

[0055] Therefore, to generate a positive drive voltage, the switch driver 200 can cyclically operate in a state sequence that includes at least one instance of each of states VC and CG, wherein the amount of time spent in state VC during the sequence is equal to the amount of time spent in state CG. For a positive drive voltage with an amplitude of up to 0.5VDD, the sequence may also include at least one instance of state CC, i.e., the sequence includes an instance of each of states VC, CG, and CC. For voltages between +0.5VDD and +VDD, the sequence may include at least one instance of state VG, i.e., the sequence includes an instance of each of states VC, CG, and CC.

[0056] For a negative drive voltage that may result in a negative load current, the opposite state may be used, i.e., the state sequence may include at least one instance of each of states CV and GC, wherein the time spent in state CV is equal to the time spent in state GC, and for drive voltages with an amplitude of up to VDD / 2, at least one instance of state CC may exist, while for drive voltages between -0.5VDD and -VDD, the sequence may include at least one instance of state GV.

[0057] There are several ways to implement such modulation schemes. In one example, a dual-slope control mechanism can be implemented. For instance, four triangular slope waveforms can be used as different carrier waveforms, wherein the slope waveforms have the same slew rate and offset range, but the carrier waveforms have a 90° phase difference from each other, such as... Figure 3 As shown. Figure 3The first, second, third, and fourth ramp waveforms 301, 302, 303, and 304 are shown. These waveforms rise and fall within the operating range, which is shown as a normalized range of -1 to +1 for ease of discussion.

[0058] In use, controller 302 compares the signal Sd (which is based on the input signal and indicates the desired drive voltage within a normalized range, where +1 corresponds to the drive voltage of +VDD and -1 corresponds to the drive voltage of -VDD) with each of the carrier waveforms 301-304, and controls the relevant operating state of the switch driver device 200 based on this comparison. In an open-loop control scheme, where the output drive signal is generated based on the input signal Sin without any feedback control, signal Sd can simply be the input signal Sin, possibly with some gain control applied. However, in a closed-loop implementation, signal Sd can be obtained by processing the input signal Sin together with some feedback signal, as those skilled in the art will understand.

[0059] Figure 3 The different operating states of the switch driver 200 are illustrated, which can be mapped to operating regions based on the relative values ​​of carrier waveforms. For example, state VG can be used when the signal Sd is greater than all four carrier waveforms 301 to 304; similarly, the opposite state GV can be used when the signal Sd is less than all four carrier waveforms. Conversely, if the signal Sd is less than only one carrier waveform (and therefore greater than the other three), then the state can be VC when the carrier waveform greater than Sd is one of 301 or 303 (i.e., one of two carriers with a 180° phase difference from each other), and CG when the carrier waveform greater than Sd is one of the other carrier waveforms (i.e., 302 or 304). If the value of the signal Sd is exactly less than two carrier waveforms (whichever two they are), then the relevant state can be CC. If the value of signal Sd is only higher than one carrier waveform (and therefore lower than the other three), then the state can be CV when the carrier waveform lower than Sd is one of 301 or 303 (i.e., one of two carriers with a 180° phase difference from each other), and the state can be GC when the carrier waveform lower than Sd is one of the other carrier waveforms (i.e., 302 or 304).

[0060] As an example of how to control the switch sequence. Figure 3 The line indicating an Sd value of +0.75 is shown, corresponding to a drive signal voltage of +0.75VDD. Each carrier waveform 301-304 slopes up and down at a carrier frequency significantly higher than the highest frequency component of the desired drive signal, for example, significantly higher than the maximum audio frequency component of the audio drive signal. Therefore, the value of signal Sd does not change significantly over the periodic timescale of the carrier waveform.

[0061] Starting at time t1, the value of Sd is greater than all carrier waveforms, and the switch driver 200 is operating in state VG. At time t2, carrier waveform 301 slopes above Sd, and controller 203 switches the switch driver 200 to state VC and holds it until carrier waveform 301 subsequently drops back below Sd at time t3, at which point the switch driver 200 switches back to state VG. At time t4, carrier waveform 302 slopes above Sd, and switch driver 200 switches to state CG and holds it until time t5 when carrier waveform 302 drops below Sd, at which point the switch driver 200 switches back to state VG. Since carrier waveforms 301 and 302 have the same slew rate and offset range, the time period between t2 and t3 (corresponding to the operating period of state VC) is equal to the time period between t4 and t5 (corresponding to the operating period of state CG). Similarly, the time period between t1 and t2 is the same as the time period between t3 and t4, and these time periods correspond to operation in state VG. This ensures that the load current at the start of state VC is substantially the same as the load current at the start of state CG, and that the load current during the duration of state VC is substantially matched with the load current during the duration of state CG, resulting in the driver capacitor C1 charging and discharging in substantially the same amount in both states.

[0062] This cycle of states VG, VC, VG, CG then repeats between time intervals t5, t6, t7, t8, and t9, due to the sloping of carrier waveforms 303 and 304 to values ​​above and below Sd, respectively, causing the same operation as carriers 301 and 304. It should be understood that while the operation has been described with reference to four carrier waveforms sloping from -1 to +1 with a 90° phase difference between them and back, this can be equivalently viewed as two positive carriers sloping between 0 and +1 (at twice the frequency), with a 180° phase difference between them, defining when operation occurs in state VC and when in state CG, respectively. Similarly, two equivalent load waveforms sloping between 0 and -1 are used to determine when operation occurs in states CV and GC. Therefore, for the drive signal voltage of +0.75VDD, the controller 203 can control the switch driver 200 in a switching cycle having a state sequence VG, VC, VG, CG, wherein the time spent in state VC during the sequence is equal to the time spent in state CG, thereby achieving charge balance of the driver capacitor C1.

[0063] It should be understood that Figure 3 This is merely an example of a suitable control scheme that controller 203 can implement to control the operation of switch driver 200; other modulation schemes may be implemented in other examples.

[0064] Figures 4a to 4dThe diagram illustrates switching waveforms for various voltages and currents of the switch driver 200 for different drive voltages, assuming an inductance in the load path. This inductance can be the inductance of the load itself and / or a series inductor component located between the output node 102L or 102R and the load. For example, as mentioned above, some applications may use inductive filtering in the load path, where the inductance can be at least partially attributed to the inductor Lfil of the filter arrangement 201. Each of these figures shows the voltage V at the output nodes 102L and 102R within one switching cycle. 102L and V 102R The obtained differential voltage V DIFF and the driving voltage V of the obtained driving signal DRV These graphs also show the load current I. LOAD This indicates the voltage V of the driver capacitor C1. CAP How it changes, and the current I from the VDD power supply. SUPP It should be noted that these waveforms are idealized for illustrating the operating principle, and the scales of each graph may differ from one another; for example, the capacitor voltage V... CAP The scale of the graphs is much larger than that of other voltage graphs in order to show the voltage ripple on the driver capacitor. These waveforms also assume that the voltage and current are in phase.

[0065] Figure 4a The driving signal voltage V is shown. DIFF The switching waveform is +0.75VDD. As mentioned above, this drive voltage can be generated by operating in the state sequence VG, VC, VG, CC.

[0066] During state VG, output node 102L is driven to voltage VDD (via closed switches S1L and S2L), and output node 102R is driven to ground via closed switch S34R, which results in voltage V across the load. DIFF It is +VDD. In this state, the load current I... LOAD The voltage increases, but the driver capacitor C1 neither charges nor discharges, therefore the driver capacitor voltage V... CAP There is no significant change. The load current is supplied by the input power source, therefore there is an increased supply current I. SUPP .

[0067] In state VC, output node 102L is reconnected to voltage VDD, but output node 102R is switched to be connected to driver capacitor C1 (e.g., by opening switch S34R and closing switches S2 and S5R), which results in a voltage V across the load. DIFF It is +VDD / 2. Because this voltage is lower than the drive voltage V... DRV Load current I LOADIt will begin to slope downwards, but in the example shown, it remains positive. The load current I... LOAD It comes from the VDD power supply, therefore there is a power supply current I. SUPP This causes the driver capacitor C1 to charge, thereby increasing the capacitor voltage V. CAP .

[0068] The switch driver 200 then switches back to state VG, which in this example again results in a positive load current I. LOAD and power supply current I SUPP The slope changes, but the capacitor voltage V CAP No change. The duration of state VG causes the load current I to... LOAD Before switching to state CG, the voltage rises back to its previous peak. State CG involves connecting output node 102L to driver capacitor C1 (e.g., by opening switch S1 and closing switch S5L while switch S2 remains closed), while output node 102R remains connected to ground (via switch S34R). This results in a differential voltage V across the load. DIFF It is +VDD / 2. Similarly, since this voltage is lower than the drive voltage V... DRV Load current I LOAD The slope drops (but remains positive), but in this state, the positive load current comes from the driver capacitor C1, which discharges the driver capacitor C1, thereby reducing V. CAP And there is no significant power supply current I. SUPP In state CG, the current from the driver capacitor C1 is equal to the current supplied to the driver capacitor C1 in state VC, therefore the capacitor voltage V CAP Return to essentially the same voltage as at the start of the switching sequence.

[0069] Figure 4b The driving signal voltage V is shown. DIFF Greater than +0.75VDD and close to the maximum positive drive signal voltage V DRV The switching waveform at (i.e., +VDD). In this case, the switch driver 200 again operates in state cycles VG, VC, CG, VG, but the proportion of switching cycles spent in state VG is greater. In this case, the positive load current I... LOAD It does indeed rise in state VG and fall in both states VC and GC, but the higher V... DRV This value implies that the current ramp-up rate decreases in state VG, while the ramp-down rate increases in states VC and CG. Similarly, the current supplied to the driver capacitor C1 in state VC is approximately equal to the current drawn from the driver capacitor C1 in state CG, therefore the voltage V across the driver capacitor C1 is... CAP It is maintained within the switching cycle.

[0070] Figure 4c The driving signal voltage V is shown. DRV The switching waveform is below +0.75VDD and only slightly above +0.5VDD. The switch driver 200 operates again in state cycles VG, VC, CG, VG, but the proportion of switching cycles spent in state VG is less than... Figure 4a The proportions in the example.

[0071] It will be noted that, for Figures 4a to 4c For each example, the voltage V at node 102L is output. 102L It is at VDD for most of the switching cycle and modulated to VDD / 2 during the duration of state CG, while the voltage V at output node 102R is... 102R The voltage is grounded for most of the switching cycles and modulated to VDD / 2 for the duration of state VC, which is the same as the duration of state VC. Therefore, it can be seen that the common-mode component of the voltage at these output nodes is equal to VDD / 2.

[0072] Figure 4d The driving signal voltage V is shown. DRV The switching waveform shows that the drive signal voltage is essentially equal to +0.25VDD. In this case, as... Figure 3 As shown, the switch driver 200 can operate in the state sequence CC, VC, CC, CG.

[0073] In state CC, output nodes 102L and 102R are both connected to driver capacitor C1 (switches S2L, S5L, S2R, and S5R are closed), therefore both output nodes are driven to VDD / 2, resulting in a differential voltage V across the load. DIFF It is zero. Load current I LOAD (In this example, the positive load current) may still flow due to the inductance of the load path, but this load current will gradually decrease and be effectively recirculated, thus the capacitor voltage V CAP No significant changes will occur.

[0074] The switch driver 200 then switches to state VC, connecting output node 102L to the power supply voltage VDD (by opening switch S5L and closing switch S1L, while S2L remains closed). In this state, the voltage at output node 102L rises to VDD, and the differential output voltage V... DIFF Increase to +VDD / 2, which is greater than the drive voltage V. DRV This leads to a load current I LOAD The current rises from the VDD power supply, thus generating the power supply current I. SUPP This causes the driver capacitor C1 to charge and the capacitor voltage V to increase. CAPThe voltage increases. Then, switch driver 200 switches back to state CC, and then to state CG, where output node 102R is grounded (by opening switches S2R and S5R and closing switch S34R). This generates a differential voltage VDD / 2 across the load. DIFF This value is greater than the driving voltage V. DRV This leads to a load current I LOAD The load current rises, but it comes from the driver capacitor C1, causing the driver capacitor C1 to discharge, and the capacitor voltage V... CAP The corresponding reduction.

[0075] It should be pointed out that, in Figure 4d In the example, the voltage V at output node 102L is... 102L The voltage is VDD / 2 for most of the switching cycle and is modulated to VDD during state VC, while the voltage V at output node 102R is... 102R The common-mode voltage is also VDD / 2 for most of the switching cycles and is modulated to ground during state CG, which lasts for the same duration as state VC. Therefore, it can be seen that the common-mode component of the voltage at these output nodes is again equal to VDD / 2.

[0076] negative drive voltage V DRV This will be generated by using an appropriate reverse state, for example, for a negative drive voltage V with a maximum amplitude of 0.5VDD. DRV The operating states are CC, CV, CC, and GC; for negative drive voltages V with amplitudes in the range of 0.5VDD to VDD. DRV The states used are GV, CV, GV, and GC. In this case, the capacitor voltage V CAP and power supply current I SUPP The waveform will be the same as the associated opposite state; for example, state CV will result in a supply current I drawn from the VDD power supply. SUPP The ramp-up and charging of the driver capacitor C1 cause the capacitor voltage V to rise. CAP Increase, but load current I LOAD It will flow in the opposite direction, thus becoming a negative load current with a steeper amplitude.

[0077] As mentioned above, Figures 4a to 4dThe examples assume no phase difference between voltage and current, and also show an example where the current direction does not change during the selected switching state sequence. However, it should be understood that the same regulation mechanism described above still applies even if there is a phase difference between the load voltage and load current applied across the load, for example, if the load exhibits some resonant characteristic, and / or if the load current changes direction during the switching state sequence. Operating according to the state sequence will result in the driver capacitor being charged by a positive load current / discharged by a negative load current for at least one period, and this period matches the period during which at least one driver capacitor is discharged by a positive load current / charged by a negative load current, and the positive / negative currents are, on average, the same during said period, so that the amount of charge charged and discharged by the driver capacitor is the same.

[0078] From the above discussion, it is clear that by simply using the aforementioned state sequence and following the timing defined by the control scheme, the charge balance of the driver capacitor C1 and the resulting regulation of its voltage can be essentially achieved. There is no need to monitor the actual voltage or the driver capacitor voltage, nor is it necessary to monitor the actual load current I. LOAD This allows for the aforementioned adjustment—although in some implementations, the capacitor voltage V CAP and / or load current I LOAD It may still be monitored for certain additional functional purposes. The control of the switch driver 200 ensures that if the driver capacitor is used in a state that causes the driver capacitor C1 to charge, there is at least one state that causes the driver capacitor C1 to discharge, and the timing of the relevant states provides a substantially desired charge balance.

[0079] However, if, for any reason, equal durations of operation in the charging and discharging states (e.g., states VC and CG) fail to result in proper charge balance of the driver capacitor—for example, due to unequal load currents or leakage in these states—the problem can be addressed by altering the relative durations of these states. For instance, if it is determined that more charge is supplied to the driver capacitor in state VC than is drawn from the capacitor in state CG, or more generally, if the capacitor voltage V is determined... CAP If the value is higher than the desired value, the duration of state VC within the switching cycle can be shortened, while the duration of state CG can be extended accordingly. The total proportion spent on states VC and CG during the switching cycle remains unchanged, thus driving the voltage V. DRV The charge supplied to the driver capacitor C1 will decrease during state VC, while the charge drawn from the driver capacitor C1 will increase during state CG. For example, this change can be achieved by the controller by effectively altering the phase of carriers 302 and 304 relative to carriers 301 and 303.

[0080] One potential problem during use is adjusting the charge on the driver capacitor when there is no load current or the load current level is low, for example, to compensate for leakage in the driver capacitor. Consider, for instance, a scenario where the differential drive signal is expected to be at or near zero and there is no significant load current. Figure 3 It can be seen that if signal Sd is at or near zero for a prolonged period, the switch driver 200 may be in state CC for all or most of the time, with states VC and CG only appearing briefly. During such periods, if leakage occurs in the driver capacitor C1, the voltage of the driver capacitor may not be maintained at the correct desired level, for example, it may not be maintained at VDD / 2. Therefore, it may be necessary to transfer charge to the driver capacitor to maintain the correct voltage level, but this can be challenging when the load current within the switching cycle is at or near zero due to the direction of current flowing into and out of the nodes. In embodiments of this disclosure, when a significant inductance (e.g., a filter inductor Lfil) is present in the output path, energy can be transferred from a voltage source (e.g., VDD) to a driver capacitor C1 via the inductor without any significant load current. Therefore, a switching sequence may involve transferring energy from a voltage source (e.g., VDD) to a filter inductor, and then transferring energy from the filter inductor to the driver capacitor C1. By appropriately selecting the switching states and timing, the average inductor current within the switching cycle can be zero, resulting in zero total load current, but with the net effect of drawing charge from the corresponding power supply and supplying charge to the driver capacitor. Such operations may involve modifications... Figure 3 The switching sequence shown may involve, for example, a brief entry state VG to inject charge from the power supply into the switch driver, which is then transferred to the driver capacitor C1 via the filter inductor Lfil. Those skilled in the art will understand that various switching sequences exist that can be used to provide the desired average driver voltage and current within a switching cycle while transferring charge to the driver capacitor C1. Therefore, in at least some embodiments, the controller 203 may be configured to operate in an operating mode that transfers energy to the driver capacitor C1 via the inductor Lfil of the filter arrangement 104 for signal levels below a first threshold (corresponding to no substantial load current or only low load current).

[0081] The above discussion focuses on balancing the charge on the driver capacitor C1, considering leakage or other losses, to maintain the voltage of the driver capacitor C1 at a desired voltage level, such as VDD / 2 in the example above. It should be understood that the voltage on the driver capacitor C1 can be adjusted to any desired intermediate voltage between the first and second supply voltages. Furthermore, it should be understood that the ability to operate in a state sequence to provide a desired drive voltage, but to change the net charge or discharge of the driver capacitor C1 on that state sequence by altering the relative duration of the relevant states, can, in some implementations, be used to controllably change the voltage of the driver capacitor C1 during use. Therefore, the voltage to which the driver capacitor C1 is regulated can vary dynamically during use.

[0082] However, in certain use cases, it may be advantageous to dynamically change the nominal value of the driver capacitor C1 voltage during operation. For example, in some cases, power efficiency and / or other performance aspects can be improved by dynamically changing the intermediate voltage value of the driver capacitor C1 (e.g., based on a certain operating parameter). In some cases, it may be beneficial to change the intermediate voltage value of the driver capacitor C1 based on the level of the input / output signal, for example, by changing it based on the signal amplitude in a manner somewhat similar to envelope tracking in other amplifier topologies. Thus, for example, in some use cases, the driver capacitor voltage may be set to VDD, but in other use cases, the driver capacitor voltage may be set to a different value, for example, reduced to VDD / 4. In some implementations, the intermediate voltage value of the driver capacitor C1 may be dynamically controlled based on at least one of the following: the received input signal; the generated output voltage; the load current or output power level provided at the output node. The driver capacitor voltage may additionally or alternatively be controlled based on the efficiency metric of the switching driver and / or the switching frequency of the switching state of the switching network. In some cases, the driver capacitor voltage may depend on the system configuration; for example, a switching driver may be configured to operate in a relatively low-power, low-performance mode or in a relatively high-power, high-performance mode.

[0083] Return to reference Figure 2 Each of the switches S1L to S4L and S1R to S4R can be implemented by any suitable switching device, and in at least some implementations, it can be implemented by a suitable MOSFET switch.

[0084] exist Figure 2In the example, each of switches S34L and S34R is rated to withstand a voltage stress equal to VDD because each of output nodes 102L and 102R can be driven to a voltage equal to VDD when the corresponding switch S34L or S34R is turned off. However, for switches S1L, S2L, and S5L, and equivalently switches S1R, S2R, and S5R, the voltage ratings of these switches do not need to be so high because the maximum voltage stress across these switches during normal operation can be VDD / 2. For example, when output node 102L is connected to the power supply voltage VDD, switches S1L and S2L are turned on, while switch S5L, in the off state, is located between node N1L at VDD and the first capacitor electrode NC1 at VDD / 2; therefore, the voltage stress across switch S5L is equal to VDD / 2. When output node 102L is reconnected to the first capacitor node NC1, switches S2L and S5L are turned on, and the voltage at node N1L is VDD / 2. Therefore, the voltage difference across switch S1L is VDD / 2. When output node 102L is grounded, switches S1L and S2L are both turned off. These switches are connected in series between the power supply voltage VDD and the grounded output node 102L, thus sharing the voltage across them. Switch S5L can be closed to regulate node N2L to the capacitor voltage VDD / 2, thereby ensuring that each of switches S1L and S2L only withstands a voltage of VDD / 2. Therefore, switches S1, S2, and S5, and equivalent switches S1R, S2R, and S5R, are rated to withstand voltage stresses of at least VDD / 2 but possibly less than VDD.

[0085] It should be noted that capacitor node NC1 is not directly connected to output nodes 102L and 102R via switches S5L and S5R respectively. Instead, switches S5L and S5R connect capacitor node NC1 to nodes N1L and N1R respectively. This arrangement allows switches S5L and S5R to be implemented using a single conventional MOSFET device. As those skilled in the art will understand, most conventional MOSFETs have a body diode that conducts when forward biased. Therefore, a conventional MOSFET can be considered a unidirectional device in terms of blocking current flow in the off state. If switch S5L connects capacitor node NC1 to output node 102L (which can be driven to voltage VDD in VG or VC state, or to ground in GC or GV state), the voltage across switch S5L in the off state may be +VDD / 2 or -VDD / 2. Therefore, the switch S5L cannot be implemented with a single conventional MOSFET that has unidirectional current blocking capability. Instead, it requires two back-to-back MOSFET devices, which increases size and resistance loss, or a MOSFET with bidirectional current blocking capability, which is often more complex and more expensive than a conventional MOSFET.

[0086] In some applications, it may be advantageous to use switches with a rated voltage lower than VDD for all switches in a switch driver, or at least for all switches in a switch driver that may carry load current during use. In some cases, switches with lower rated voltages may provide improved performance compared to switches with higher rated voltages. For example, it has recently been proposed in automotive applications to use 48V power distribution in the electrical systems of vehicles, instead of the conventional 12V power distribution previously used. For switch drivers used in automotive applications, the first and second supply voltages can be 48V and ground, i.e., VDD can be 48V. Transistors rated at 48V can be used to implement switches S34L and S34R of switch driver 200, but transistors rated at 24V may have certain performance advantages. In such examples, it may therefore be desirable to use transistors rated at 24V instead of transistors rated at 48V to implement the switch driver.

[0087] Figure 5 An example of a switch driver 500 (or amplifier) ​​according to one embodiment is shown, which can be implemented using a switch that is only required to withstand a voltage stress of VDD / 2. The switch driver 500 includes a reference... Figure 2 The switch driver 500 discusses switches S1L, S2L, S5L, S1R, S2R, and S5R, but each of the individual switches S34L and S34R is replaced by two switches connected in series. That is, the switch driver 500 includes switches S3L and S4L located between the output node 102L and the second power supply voltage (i.e., ground), and switches S3R and S4R located between the output node 102L and the second power supply voltage, in the manner described in the reference. Figure 1 The methods discussed are similar.

[0088] When output node 102L is driven to VDD, voltage VDD is thus applied across the series connection of switches S3L and S4L, and each of these switches should only bear a portion of this voltage in terms of voltage stress across the switches. While ideally the voltage stress should be evenly distributed between the two switches such that the midpoint node N2L between these switches equals VDD / 2, in practice it may be advantageous to actively bias this node to the desired voltage VDD / 2, so that neither switch bears a voltage stress greater than VDD / 2.

[0089] The switch driver 500 therefore includes a bias network 501 for biasing the nodes of the switch driver 500 to maintain the maximum voltage stress across each switch at VDD / 2.

[0090] As described above, switches S5L and S5R can be closed in any state where the relevant output node 102L or 102R is driven to ground, to bias the voltages at nodes N1L and N1R to the capacitor voltage VDD / 2, respectively. This ensures that each of switches S1L and S2L or S1R and S2R experiences a maximum transverse stress of VDD / 2 in the open or closed state. The biasing network 501 is also arranged to bias the voltages at nodes N2L and N2R to VDD / 2 in any state where the voltage at the relevant output node 102L or 102R is VDD, thereby ensuring that each of switches S3L and S4L or S3R and S4R experiences a maximum transverse stress of VDD / 2 in the open or closed state. Therefore, when operating in VC or VG states, the bias network can be operated to bias node N2L to voltage VDD / 2, and similarly, when operating in CV or GV states, the bias network can be operated to bias node N2R to voltage VDD / 2.

[0091] exist Figure 5 In the example, bias network 501 includes four switches: switches SB1L and SB1R that connect bias node NB to nodes N1L and N1R, respectively, and switches SB2L and SB2R that connect bias node NB to nodes N2L and N2R, respectively. In VC and VG states, switch S5R can be turned on to drive the voltage at node N1R to VDD / 2. This is either part of driving output node 102R to that voltage in VC state, or for managing voltage stress across switches S1R and S2R in VG state. In this case, switches S2L and S1R of bias network 501 can be closed or turned on, causing bias nodes NB and N2L to be biased to voltage VDD / 2. This ensures that the maximum voltage stress across either switch S3L or S4L is limited to VDD / 2.

[0092] These switches SB2L and SB1R can also be turned on in the CG state because switches S3L and S4L will be turned off, and node N1R will be biased to VDD / 2 by switch S5R to manage the voltage stress across switches S1R and S2R in the CG state. Therefore, switches SB2L and SB1R of the bias network can be closed or turned on in the VG, VC, and CG states, which can be used only when generating a positive drive voltage.

[0093] For the opposite states used to generate the negative drive voltage, namely GV, CV, and GC, switches S2L and S1R of bias network 501 can be open, while switches S1L and S1B can be closed. In a similar manner to that discussed above, switch S5L can be closed in all these states to drive the voltage at node N1L to VDD / 2, either as part of driving output node 102L to VDD / 2, or to manage the voltage stress across switches S1L and S2L when output node 102L is grounded. Therefore, bias network 501 can connect node N1L to node N2R, thereby biasing node N1L to VDD / 2 to manage the voltage stress across switches S3R and S4R.

[0094] In state CC, switches SB1L to SB2R of the bias network can each be open or closed as needed, because in this state, output nodes 102L and 102R are both driven to VDD / 2, and the voltage stress across switches S1L to S4L and S1R to S4R will be less than VDD / 2. However, in at least some implementations, all switches of the bias network 501 can be closed in state CC, as this may be advantageous for the way the bias network switches between positive and negative drive voltages. For a positive drive voltage, switches SB2L and SB1R are closed, while switches SB1L and SR2R are open, for at least a portion of the switching sequence; while for a negative drive voltage, switches SB1L and SB2R are closed, while switches SB2L and SR1R are open, for at least a portion of the switching sequence. Any transition between the positive drive voltage and the negative drive voltage will involve an instance of state CC, so the bias network 501 can transition from a state in which only switches SB2L and SB1R are on to a state in which all switches are on, and then into a state instance in which switches SB2L and SB1R are off while SB1L and SB2R remain on.

[0095] Table 1 below shows an example of different operating states of the switch driver, whether each switch is closed or on, open or off, and the resulting voltage at each node.

[0096] Table 1 It should be understood that this is merely an example of individual switch controls used to provide switch states, and for at least some states, the control method of one or more switches (i.e., whether the relevant switch is on or off) can be changed without affecting the voltage at the output node or any voltage stress across the off switch. For example, in the VC state, switch S3R can be controlled to turn on to eliminate the floating voltage FLOAT at node N2R, and in the CV state, switch S3L can be controlled to turn on to eliminate the floating voltage at node N2L.

[0097] Therefore, the switch driver 500 with bias network 501 can be implemented using switches that only need to withstand a voltage stress rating of VDD / 2 in the off state. The switches of bias network 501 itself (i.e., switches SB1L to SB2R) can also have similar voltage ratings because the bias node NB is biased to VDD / 2 in all states, so the maximum stress that any switch in bias network 501 withstands in the off state is equal to VDD / 2.

[0098] It should be noted that the bias network is used to provide bias for each node of the switch driver 500 in order to manage the voltage stress across certain switches of the switch driver. However, in use, no substantial load current flows through the bias network 501, therefore the load current is not transmitted through the bias network 501. Figure 5 In the example bias network 501, the bias network 501 is used to connect the portions of the switch driver associated with opposite sides of the load 101, that is, the portions located on opposite sides of the bridge circuit of the switch driver 500. However, this is done to bias the switch driver itself, for example, to manage voltage stress across the switch or other components of the switch driver, rather than to drive the load. It should be understood, of course, Figure 5 The bias network 501 shown is only an example; other bias network arrangements can also be implemented.

[0099] A novel aspect of this disclosure is a switch driver with a bias network for biasing nodes of the switch driver, particularly for connecting portions of a BTL switch driver on opposite sides of a load to provide voltage bias for the switch driver. Thus, one aspect is a switch driver configured to drive a load connected between first and second output nodes in a bridged load configuration, comprising: a first switch branch and a second switch branch respectively connected to the first and second output nodes, the first and second switch branches being configured to operate in different switching states to provide different voltages to the respective output nodes; and a bias network connected between the first and second switch branches, the bias network being configured to selectively connect nodes of the first and second switch branches to a controlled voltage to control voltage stress across the switches of the switch branches in the off state.

[0100] It should be pointed out that, in Figure 5In the example, switch S5L selectively connects the first capacitor node NC1 to the midpoint node N1L between switches S1L and S2L, located between the output node 102L and the supply voltage VDD, i.e., the high-side midpoint node, while switch S5R provides a similar connection to the high-side midpoint node N1R on the other side of the load. However, it should be understood that switches S5L and S5R can alternatively connect the first capacitor node NC1 to the corresponding low-side midpoint nodes N2L and N2R. In this case, in CV, CG, or CC states, switch S5L can be closed together with switch S3L to provide the capacitor voltage to the output node 102L via the low-side midpoint node N2L; while in VG or VC states, switch S5L can be closed with switches S3L and S3R open to regulate the voltage at the low-side midpoint node N2L—while simultaneously operating the bias network 501 to utilize the voltage at node N2L to also regulate the voltage at the high-side node N1R on the other side of the load in these states. Switch S5R will provide a similar operation for the other side of the load.

[0101] In some implementations, it may be advantageous to selectively connect the first capacitor node NC1 to the midpoint connection between the high and low sides of each side of the load, such as... Figure 6a As shown. Figure 6a The figure illustrates a switch driver or amplifier, which is related to a reference. Figure 5 Similar to the discussion, switches S5L and S5R selectively connect the first capacitor node NC1 to the high-side midpoint nodes N1L and N1R, respectively, in the same manner as referenced. Figure 5 The same applies, but in addition, switches S6L and S6R selectively connect the first capacitor node NC1 to the low-side midpoint nodes N2L and N2R, respectively. This arrangement avoids the reference... Figure 5 The required bias network 501 discussed.

[0102] To provide capacitor voltage to output node 102L in CV, CG, or CC states, switch S5L can be closed along with switch S2L, or switch S6L can be closed along with switch S3L. However, it is advantageous to close switches S5L and S6L together with switches S2L and S3L to reduce the total resistance of current flow between the first capacitor node NC1 and output node 102L. When switches S5L and S2L are closed together with switches S6L and S3L, these two switch paths are connected in parallel, thus reducing the resistance compared to using only one of the switch paths (assuming similar switch on-resistance). In states VG or VC, switch S6L can be closed (while switches S3L and S4L are open) to regulate the voltage at the low-side midpoint node N2L; in states GC or GV, switch S5L can be closed (while switches S1L and S2L are open) to regulate the voltage at the high-side midpoint node N1L. Switches S5R and S6R on the other side of the load can operate in a similar manner. Therefore, this arrangement has the advantage of reducing resistance in certain switching states and avoids the need for a separate bias network.

[0103] It should be understood that, in some embodiments, the direct switching connection between the first capacitor node and the corresponding output nodes 102L and 102R may be implemented additionally or alternatively, wherein at least some of the switches are rated at the full supply voltage VDD, or different bias network arrangements may be used to manage the voltage stress across the switches.

[0104] As mentioned above, for Figure 2 , Figure 5 and Figure 6a In each example, each switch can be implemented by a suitable semiconductor switching device, such as a MOSFET with unidirectional current blocking capability. Figure 6b It shows Figure 6aThe example switch driver can be implemented using conventional MOSFET devices for each switch. Switch S1L is implemented by a MOSFET, and its body diode is configured to be reverse biased by voltage VDD when the switch is off and the voltage at node N1L is driven to VDD / 2. The body diode of switch S2L is configured to be reverse biased when the switch is off and the voltage at node N1L is driven to VDD / 2 and the voltage at node 102L is driven to ground. Similarly, switches S3L and S4L have body diodes that are reverse biased when the switch is off and the voltage at node N2L is driven to VDD / 2 and the voltage at node 102L is driven to VDD. The body diode of switch S5L is reverse biased when the switch is off and node N1L is driven to VDD (through switch S1L conducting). The body diode of switch S6L is reverse biased when the switch is off and node N2L is driven to ground (through switch S4L conducting). Switches S1R to S6R are arranged in a similar manner. This arrangement allows the switch driver to be implemented using conventional FET devices with unidirectional current blocking capability.

[0105] Figure 6a and Figure 6b An example is also shown in which the second driver capacitor C2 is connected between the first power supply voltage VDD and the first capacitor node NC1. This arrangement means that driver capacitors C1 and C2 are effectively connected in series between the first power supply voltage VDD and ground, and together maintain the capacitor voltage at the first capacitor node NC1. As previously stated, this may be advantageous in terms of establishing an initial charge on each driver capacitor C1 and C2 during startup, wherein the capacitor voltage at the first capacitor node NC1 is regulated during use by the operation of the switch driver 600; however, it should be understood that the embodiment may be implemented using only one of the driver capacitors C1 or C2.

[0106] It should be understood that embodiments of the switching driver can be implemented with one or more driver capacitors, and references to the driver capacitor in this disclosure refer to a capacitor used to store a voltage used to provide one of the switching voltages, which may in particular be an intermediate voltage between a first supply voltage and a second supply voltage. Allowing the use of only one driver capacitor, which can be used to provide a switching voltage to either side of the load in a BTL configuration, is an advantageous aspect of this disclosure. However, in some applications, it may be desirable to use more than one driver capacitor. For example, in some cases, it may be desirable to have a driver capacitor formed by a combination of two or more discrete capacitors, for example, a driver capacitor equivalent to a single driver capacitor C1 can be effectively formed by two or more smaller parallel capacitors, and / or the driver capacitors can be connected in series as shown in FIG. 6. Generally, the switching driver can be implemented with a driver capacitor that can be used to provide a switching voltage to either side of the load, and the switching driver can be controlled to regulate the voltage on the driver capacitor to cause the switching driver to generate the desired load drive voltage.

[0107] In some examples, driver capacitor C1 (and, if present, driver capacitor C2) can be shared among multiple switching drivers, i.e., among multiple amplifiers, such as among multiple audio amplifiers in a multi-channel audio system. As mentioned above, the operation of a single driver or amplifier can be controlled to regulate the voltage on driver capacitor C1, thereby maintaining it at the correct voltage. Therefore, this driver capacitor voltage can also be used as the switching voltage for one or more other switching drivers; that is, a common capacitor connected to a common capacitor node can exist, which serves as the driver capacitor for each of the multiple switching drivers.

[0108] Figure 7 An example of an amplifier system 700 including multiple switch drivers with a shared driver capacitor C1 is shown. Figure 7 In the example, there are two switch drivers, 701a and 701b, but it should be understood that more may be present in some applications. Figure 7 In the examples, each switch driver 701a and 701b has the structure discussed with reference to FIG. 6, but it should be understood that any embodiment discussed herein can be used as switch drivers 701a and 702a. It should be noted that... Figure 7 The filter arrangement in the output path for load 101 is not shown, but it is understood that filters can be implemented at least in some applications, such as references. Figure 2 The LC filter under discussion.

[0109] Each switch driver 701a and 701b is therefore connected to the first capacitor node NC1 and can operate in a state sequence as described above, these states being controlled such that during the state sequence, the total current drawn by the switch driver from the first capacitor node NC1 is equal to the total current supplied to the first capacitor node, thereby providing charge balance for the driver capacitor C1. Each switch driver 701a and 701b can therefore operate independently and effectively based on the relevant input signal to drive its corresponding transducer.

[0110] In some implementations, different switch drivers can be configured to attempt to minimize the charge change of the driver capacitor C1. If two switch drivers 701a and 701b are simultaneously operated in a state that causes the corresponding load current to be drawn from the driver capacitor C1, the charge of the driver capacitor C1 may experience a relatively significant decrease, accompanied by a corresponding drop in the capacitor voltage. Similarly, if two switch drivers 701a and 701b simultaneously supply current to the driver capacitor C1, the charge of the driver capacitor C1 may experience a relatively significant increase. However, if one switch driver 701a and 701b is operated in a state that supplies load current to the first capacitor node NC1, while another switch driver simultaneously draws load current from the first capacitor node NC1, the charge change of the driver capacitor C1 will be a result of the current difference, thereby reducing the charge change of the driver capacitor C1 and the resulting voltage ripple, which may also allow for the use of a smaller driver capacitor.

[0111] Therefore, at least in some applications, the operation of switch drivers 701a and 701b can be arranged such that a state instance causing switch driver 701a to draw load current from the first capacitor node NC1 may occur simultaneously with a state instance causing switch driver 701b to supply load current to the first capacitor node NC1. For example, if the respective input signals SinA and SinB of switch drivers 701a and 701b are the same, then an instance of each state VC or CV of switch driver 701a may coincide with an instance of state CG or GC of switch driver 701a, and vice versa. In cases where operation in a state sequence is controlled by comparing different carrier waveforms, for example, referring to... Figure 3 The discussion suggests that the same carrier can be used for each switch driver, but the mapping of states can be appropriately changed, or in fact, a 180° phase shift can be applied to the carriers of different switch drivers.

[0112] In some applications, controller 702 can control the operation of all switch drivers 701a and 701b sharing the driver capacitor so as to control the switch drivers to drive their respective transducers based on the corresponding input signals (e.g., SinA or SinB) and collectively operate the switch drivers in a selected state sequence to provide charge balance for the driver capacitor C1.

[0113] refer to Figure 2 , Figure 5 , Figure 6a and Figure 6b The discussed embodiments illustrate a BTL configuration, i.e., a switching driver, for driving a load, wherein the output nodes 102L and 102R on both sides of the load can be selectively driven to any one of a first supply voltage (i.e., VDD), an intermediate capacitor voltage, or a second supply voltage (i.e., ground), thereby generating a differential output voltage across the load in the range of +VDD to -VDD. The BTL embodiment is advantageous in allowing adjustment of the capacitor voltage within a given amplifier's switching cycle.

[0114] Various aspects of this disclosure also relate to single-ended drivers.

[0115] Figure 8 An example of a single-ended switch driver 800 according to one embodiment is shown, wherein similar components previously described are identified by the same reference numerals. Figure 8 In the example, output node 102L is connected to VDD via a series connection of switches S1L and S2L, and grounded via a series connection of switches S3L and S4L. The high-side and low-side midpoint nodes N1L and N2L between these switches are connected to the first capacitor node NC1 via corresponding switches S5L and S6L, in a manner similar to that discussed with reference to Figure 6. Therefore, output node 102L can be selectively connected to VDD, ground, or the capacitor voltage of driver capacitor C1. However, in Figure 8 In the example, the output node 102R is connected to the first capacitor node NC1, so the intermediate capacitor voltage at the first capacitor terminal NC1 remains essentially constant during use.

[0116] In use, the single-ended switch driver 800 can therefore operate in any of the three states VC, CC or GC to generate a voltage in the range of +VDD / 2 to -VDD / 2 across the load.

[0117] For the switch driver 800, in state VC, the driver capacitor C1 will be charged by any positive load current flowing from output node 102L to 102R, but discharged by any negative load current. In state CG, the driver capacitor C1 will be discharged by any negative load current, but charged by any positive load current. In this case, the charge on the driver capacitor C1 may not be balanced within a single switching cycle, as described above, but can be adjusted based on the signal itself, for example, within one cycle of the signal. In some cases, this may involve modifying the switching cycle, i.e., modifying the signal, to attempt to ensure that the average current is zero over a specific time period. Therefore, the driver capacitor C1 can be appropriately sized to provide the expected amount of charge over the relevant time range without excessive voltage drops.

[0118] Additional or alternative ground, two or more single-ended amplifiers (e.g. Figure 8 (As shown) can have a common driver capacitor, as in the reference. Figure 7 The discussion focuses on controlling the operation of two or more single-ended drivers to provide voltage regulation of the driver capacitors. Specifically, two amplifiers can be arranged such that the driver capacitors are connected such that a positive voltage and positive load current from one amplifier causes driver capacitor C1 to charge, while a positive voltage and positive load current from the other amplifier causes driver capacitor C1 to discharge. In this way, a common drive signal from both amplifiers will cause the charging and discharging of driver capacitor C1, which facilitates voltage regulation of the driver capacitor.

[0119] The above examples have been described in the context of a switch drive receiving first and second voltages as positive supply voltages and ground; however, it will be understood that embodiments can be implemented with split-rail power supplies, such as using positive and negative supply voltages. The supply voltage used herein refers to the voltage source provided to the switch driver circuitry. In some cases, there may be upstream circuitry systems that process the received voltage, such as battery voltage or similar voltage, to provide the supply voltage VDD to the switch driver, for example, by applying some form of regulation and / or level shifting.

[0120] The examples above are primarily discussed in the context of driving audio transducers (such as speakers), and the embodiments can be implemented as audio switch drivers, i.e., audio amplifiers. However, the embodiments can be used to drive other types of transducers and are suitable for driving any load based on an input signal to drive a driving signal.

[0121] The embodiments can be implemented as integrated circuits. The embodiments can be implemented in a host device, which can be a portable and / or battery-powered host device, such as a mobile computing device, like a laptop computer, notebook computer, or tablet computer, or a mobile communication device, such as a mobile phone, like a smartphone. The device can be a wearable device such as a smartwatch. The host device can be a game console, remote control device, home automation controller or home appliance, toy, machine such as a robot, audio player, or video player. It should be understood that the embodiments can be implemented as part of a system installed in a home appliance or vehicle. A host device incorporating the above embodiments is also provided.

[0122] Those skilled in the art will recognize that certain aspects of the above-described apparatus and methods, such as the processing of various signals, can be implemented as processor control code, for example on non-volatile media such as disks, CD-ROMs, or DVD-ROMs, on programmable memory such as read-only memory (firmware), or on data carriers such as optical or electrical signal carriers. For some applications, embodiments can be implemented on DSPs (Digital Signal Processors), ASICs (Application-Specific Integrated Circuits), or FPGAs (Field-Programmable Gate Arrays). Therefore, the code can include conventional program code or microcode, or, for example, code for setting up or controlling an ASIC or FPGA. The code can also include code for dynamically configuring reconfigurable devices, such as reprogrammable logic gate arrays. Similarly, the code can include code for hardware description languages, such as Verilog™ or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language). As those skilled in the art will understand, the code can be distributed among multiple coupled components that communicate with each other. Where appropriate, embodiments can also be implemented using code running on field-programmable analog arrays or similar devices to configure analog hardware.

[0123] It should be noted that the above embodiments are illustrative and not restrictive, and those skilled in the art will be able to devise many alternative embodiments without exceeding the scope of the appended claims. The word "comprising" does not exclude the presence of other elements or steps besides those listed in the claims, "an" or "a" does not exclude a plurality, and a single feature or other unit may perform the function of multiple units recited in the claims. Any reference numerals or markings in the claims should not be construed as limiting their scope.

Claims

1. A switch driver circuit for driving a load, comprising: The first and second output nodes are used to output differential drive signals for driving the load; A driver switching network capable of operating in multiple different switching states, wherein in each switching state, each of the first and second output nodes is connected to a corresponding one of a first switching voltage, a second switching voltage, and an intermediate switching voltage, wherein the intermediate switching voltage is a voltage between the first and second switching voltages and is provided by a driver capacitor selectively connected to each of the first and second output nodes. A controller configured to control the driver switching network to operate in sequence according to the switching states to generate the differential drive signal based on the input signal; The controller is configured to provide voltage regulation to the intermediate voltage provided by the driver capacitor when the driver switching network operates in the switching state sequence to generate the differential drive signal.

2. The switch driver circuit according to claim 1, wherein, Operating in the switching state causes load current to flow to the load, and wherein the controller is configured such that, for at least some values ​​of the differential drive signal, the switching state sequence includes at least one instance of a switching state in which the driver capacitor is charged by the load current and at least one instance of a switching state in which the driver capacitor is discharged by the load current.

3. The switch driver circuit according to claim 2, wherein, In the switching state where the driver capacitor is charged by the load current and in the switching state where the driver capacitor is discharged by the load current, the differential output voltage between the first output node and the second output node is the same.

4. The switch driver circuit according to claim 2 or 3, wherein the controller is configured such that the load current flowing through the switch state during which the driver capacitor is charged by the load current substantially matches the load current flowing through the switch state during which the driver capacitor is discharged by the load current.

5. The switch driver circuit according to any one of claims 2 to 4, wherein, The controller is configured such that the total duration of at least one instance of the switching state in which the driver capacitor is charged by the load current in the switching cycle is the same as the total duration of at least one instance of the switching state in which the driver capacitor is discharged by the load current in the switching cycle.

6. The switch driver circuit according to any one of claims 2 to 5, wherein, The first voltage is a first power supply voltage, and the second voltage is a second power supply voltage.

7. The switch driver circuit according to claim 6, wherein, The first power supply voltage is V, the second power supply voltage is ground, and the intermediate voltage is equal to V / 2.

8. The switch driver circuit according to claim 7, wherein: The switching state in which the driver capacitor is charged by the load current includes a switching state in which one of the first and second output nodes is connected to the first power supply voltage V, and the other of the first and second output nodes is connected to the driver capacitor at the intermediate voltage V / 2; and The switching state in which the driver capacitor is discharged by the load current includes a switching state in which one of the first and second output nodes is connected to the driver capacitor at the intermediate voltage V / 2, and the other of the first and second output nodes is connected to the second voltage which is ground.

9. The switch driver circuit according to any one of claims 1 to 8, wherein, The driver capacitor includes a driver capacitor connected in use between a first and a second capacitor node, wherein the first capacitor node is selectively connected to each of the first and second output nodes, and the second capacitor node is connected to a defined reference voltage.

10. The switch driver circuit according to claim 9, wherein, The defined reference voltage is one of the first and second voltages.

11. The switch driver circuit according to claim 9 or 10, wherein, The defined reference voltage is ground.

12. The switch driver circuit according to any one of claims 9 to 11, wherein, The driver capacitor is the only capacitor that can be connected to the first and second output nodes.

13. The switch driver circuit according to any one of claims 1 to 12, wherein, The driver switching network includes, for each of the first and second output nodes: The first group of three switches is used to selectively connect the first common node to the first switch voltage, the intermediate switch voltage, and the relevant output node, respectively; and The second group of three switches is used to selectively connect the second common node to the second switch voltage, the intermediate switch voltage, and the relevant output node, respectively. The controller is configured such that, in the switching state where the output node is connected to the intermediate switch voltage, the relevant switches in the first group and the second group of three switches are all controlled to be turned on.

14. The switch driver circuit according to any one of claims 1 to 13, further comprising: A biasing switch network is configured to selectively connect nodes of the driver switch network to the intermediate voltage to bias the nodes of the driver switch network to the intermediate voltage, thereby managing the voltage stress across the driver switch network when the switches are in the off state. The controller is configured to control the bias switch network based on the switching state of the driver switch network.

15. The switch driver circuit according to claim 14, wherein, The bias switch network is configured such that substantially no current flows through the bias switch network in any of the said switching states.

16. A multi-channel amplifier system comprising a plurality of switch driver circuits according to any one of claims 1 to 15, wherein, The common capacitor connected to the common capacitor node is configured as the driver capacitor for each switch driver circuit.

17. The multichannel amplifier system of claim 16, configured such that a first switch driver circuit of the plurality of switch driver circuits is configured to operate in a switching state in which load current in the first switch driver circuit is supplied to the common capacitor node, while a second switch driver circuit of the plurality of switch driver circuits is configured to operate in a switching state in which load current in the second switch driver circuit is supplied to the common capacitor node.

18. A multilevel switch driver circuit for driving a load connected between first and second output nodes with differential drive signals, the multilevel switch driver circuit comprising: First and second power supply nodes are used to receive first and second power supply voltages; First and second capacitor nodes are used to connect to the driver capacitor during use; A switching network configured to selectively connect each of the first and second output nodes to a corresponding one of the first power node, the second power node, or the first capacitor node; as well as A controller is configured to control the switching network according to a sequence of switching states to generate the differential drive signal. When the driver switch network operates according to the switch state sequence to generate the differential drive signal, it provides charge balance for the driver capacitor.

19. The multilevel switch driver circuit according to claim 17, wherein, The second capacitor node is connected to a defined reference voltage.

20. A multilevel switch driver circuit for driving a load in a bridged load configuration, the multilevel switch driver circuit comprising: First and second output nodes are used to connect to the load during use; First and second capacitor nodes for connection to a driver capacitor in use, wherein the first capacitor node is selectively connectable to each of the first and second output nodes via a switching network, and the second capacitor node is connected to a defined reference voltage; and A controller is configured to control the multilevel switch driver circuit to generate differential drive signals across the load based on an input signal, wherein the controller is configured to operate in a switching cycle including the following states for at least some differential drive signal values: In a first state, wherein the first capacitor node is connected to one of the first and second output nodes and is charged by a current flowing through one of the first and second output nodes; and In the second state, the first capacitor node is connected to the other of the first and second output nodes and is discharged by the current flowing through the other of the first and second output nodes.

21. A multi-channel amplifier system, comprising: Multiple switch drivers, each of the switch drivers being configured to selectively modulate the voltage at at least one output node of the switch driver between selected switching voltages to drive a corresponding load; Wherein, one of the switching voltages is a capacitor voltage, provided in use by a common driver capacitor, which is shared by the plurality of switching drivers and connected to a common capacitor node; and A controller for controlling the operation of the plurality of switch drivers in a switching cycle, such that the load current flowing between each of the plurality of switch drivers and the common capacitor node provides voltage regulation of the capacitor voltage.

22. A switch driver circuit for driving a load, comprising: The first and second output nodes are configured to output differential drive signals through filters including series inductors to drive the load; The first and second power nodes are configured to receive the first and second power supply voltages, respectively. An intermediate voltage node is configured to receive an intermediate voltage provided by a driver capacitor, the intermediate voltage being a voltage level between the first and second power supply voltages; A driver switching network configured such that each of the first and second output nodes can be selectively connected to a correspondingly selected one of the first power node, the second power node, and the intermediate voltage node; A controller configured to control the driver switching network to operate in sequence according to the switching states to generate the differential drive signal based on the input signal; The controller is configured to adjust the intermediate voltage provided by the driver capacitor when the driver switching network operates in the switching state sequence to generate the differential drive signal.

23. The switch driver circuit according to claim 22, wherein, The controller is configured to adjust the intermediate voltage of the driver capacitor to dynamically change the value of the intermediate voltage based on at least one operating parameter of the switch driver circuit.

24. The switch driver circuit according to claim 22 or 23, wherein, For input signal levels below a first threshold, the controller is configured to operate in an operating mode in which the driver switching network is configured to transfer energy from at least one of the first and second power supply voltages to the driver capacitor via inductors arranged in the filter, according to the switching state sequence.

25. The switch driver circuit according to any one of claims 22 to 24, wherein, The driver switching network includes, for each of the first and second output nodes: A first set of switches is used to selectively connect one of the first or second output nodes to the first power node or the intermediate voltage node, and The second set of switches is used to selectively connect one of the first or second output nodes to the second power supply node; wherein, Each of the first set of switches includes a first switch coupled between the relevant one of the first or second output nodes and a corresponding first common node, a second switch coupled between the corresponding first common node and the first power supply voltage node, and a third switch coupled between the corresponding first common node and the intermediate voltage node.

26. The switch driver circuit according to claim 25, wherein, Each second set of switches is also used to selectively connect one of the first or second output nodes to the intermediate voltage node, and wherein each second set of switches includes a fourth switch coupled between the one of the first or second output nodes and a corresponding second common node, a fifth switch coupled between the corresponding second common node and the second power supply voltage node, and a third switch coupled between the corresponding second common node and the intermediate voltage node.

27. The switch driver circuit according to claim 26, wherein, In at least one operating mode, the controller is configured to turn on each of the first, second, fourth, and fifth switches in the first and second sets of switches for one of the first or second output nodes, so as to connect the one of the first or second output nodes to the intermediate voltage node.

28. A switch driver circuit for driving a load, comprising: The first output node is used to arrange the output signal to a filter including a series inductor; The first and second power nodes are configured to receive the first and second power supply voltages, respectively. An intermediate voltage node is configured to receive an intermediate voltage provided by a driver capacitor, the intermediate voltage being at a voltage level between the first and second power supply voltages; A driver switching network configured such that the first output node can be selectively connected to a selected one of the first power node, the second power node, and the intermediate voltage node; A controller is configured to control the driver switching network to operate in sequence of the switching states based on an input signal, such that the output signal after being filtered by the filter arrangement corresponds to the input signal; The controller is configured to adjust the intermediate voltage provided by the driver capacitor when the driver switching network operates in the switching state sequence to generate the differential drive signal.

29. A switch driver circuit for driving a load, comprising: The first and second output nodes are used to output differential drive signals for driving the load; The first and second power nodes are configured to receive the first and second power supply voltages, respectively. An intermediate voltage node is configured to receive an intermediate voltage provided by a driver capacitor, the intermediate voltage being a voltage level between the first and second power supply voltages; A driver switching network configured such that each of the first and second output nodes can be selectively connected to a correspondingly selected one of the first power node, the second power node, and the intermediate voltage node; A controller configured to control the driver switching network to operate in sequence according to the switching states to generate the differential drive signal based on the input signal; The driver switching network includes, for each of the first and second output nodes: A first set of switches is used to selectively connect one of the first or second output nodes to the first power node or the intermediate voltage node, and The second set of switches is used to selectively connect one of the first or second output nodes to the second power supply node; wherein, Each of the first set of switches includes a first switch coupled between the relevant one of the first or second output nodes and a corresponding first common node, a second switch coupled between the corresponding first common node and the first power supply voltage node, and a third switch coupled between the corresponding first common node and the intermediate voltage node.

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