Drive circuit and method for temporarily storing gate charge in a capacitor

Abstract

A driving circuit (TR) has a driving output stage (TE) with a gate potential (GP). The driving circuit (TR) has a switchable capacitor (SK), via which the gate potential (GP) is connected to a reference potential (M) of the driving circuit (TR). Furthermore, a corresponding method for temporarily storing gate charge is described.

Description

Background Technology

[0001] Electric vehicles have an inverter or converter and a motor operated by the inverter. It is known to use pulse-width modulation (PWM) control signals to control the motor, thereby turning the inverter switches on and off. The desired current acting on the motor is generated by the duty cycle of the control signal (PWM signal). It is known to use switches (semiconductor switches) in the inverter that are either fully closed or fully open. These switches are typically not driven in linear operation because this would result in a voltage drop across the switches while current flows, leading to high power loss. In other words, for efficiency reasons and due to undesirable heat generation, it is known to avoid having the electronic switches driving the inverter remain in linear operation for longer than necessary, during which a voltage drop occurs across the switches and current flows. Therefore, it is desirable to have the largest possible edge steepness within achievable limits.

[0002] For example, silicon-based IGBTs can be used to implement such inverters, while SiC-based or GaN-based FETs can achieve higher edge steepness. However, using these transistors also generates (albeit lower) power losses. These transistors are so-called wide-bandgap semiconductors, which enable high edge steepness (due to increased electron mobility). Meanwhile, semiconductors used for fast switching require minimum control voltage or gate voltage to efficiently (rapidly) execute the switching process, and therefore frequent switching also leads to associated losses due to the variable control voltage on the FET's gate. Current drive circuits thus generate undesirable power losses when driving the gate; therefore, the object of this invention is to reduce the power losses generated by switching in the drive circuit in a simple and reliable manner. Summary of the Invention

[0003] This task is addressed by the subject matter of the independent claims. Further nature, features, embodiments, and advantages are given in the dependent claims, the description, and the drawings.

[0004] The proposed approach is to preferably connect the capacitor to the gate of the power semiconductor for a defined time during each switching process (on and off, triggered by a PWM signal). This connection is performed after a defined duration following the switching process. In particular, the capacitor is connected only for a predefined duration.

[0005] The connection procedure performed for switching on involves connecting a capacitor to the gate shortly after switching on. At switch-on, the gate voltage is (still) lower than the capacitor voltage, thus transferring charge from the capacitor to the gate. This applies a portion of the charge stored in the capacitor directly to the gate. This charge no longer needs to be removed from the supply or operating voltage source. During this process, the capacitor discharges to a specific value (voltage value). At switch-off, the capacitor is again connected to the gate at a defined time point. Specifically, after the switch-off process, the capacitor is connected to the gate for a specific duration.

[0006] Before connection, the gate (still) has a voltage higher than that of the capacitor (which has been partially discharged during the previous turn-on process). Accordingly, it is also possible to reduce the charge supplied by the power supply voltage source or operating voltage source that must flow between the drive signal source and the gate to perform the switching process. Therefore, a portion of the gate charge can be stored on the capacitor (when the gate is turned off) or removed from the capacitor (when the gate is turned on) to support the switching process. The duration of the capacitor's connection to the gate during turn-on can be the same as the duration of its connection during turn-off. In a further embodiment, different durations can be set for turn-on and turn-off. The process is repeated; after turn-off, there is a next turn-on command, and the described cycle restarts. Thus, a portion of the gate charge can be recovered without being removed from the operating voltage or corresponding power supply.

[0007] The method described herein can be implemented using a drive circuit. The drive circuit has a drive output stage with a gate potential. This gate potential can be applied to the power transistor. For this purpose, the drive output stage can also have a reference potential that can be directed to the power transistor. Thus, the voltage between the gate potential and the reference potential can be applied to the power transistor as a control voltage for driving. The reference potential is preferably the source potential or ground potential, thereby applying the control voltage to the power transistor as a gate-source voltage. The reference potential can also differ from the source potential or ground potential by a potential difference, wherein this potential difference is constant or its magnitude is adjustable, but preferably it does not have a different polarity itself or with respect to the switchable capacitor.

[0008] The drive circuit also includes a switchable capacitor. The gate potential is connected to the reference potential of the drive circuit via the switchable capacitor. Therefore, the switchable capacitor has one end that is fixedly connected to the reference potential of the drive circuit, just as the source potential is also fixedly connected to the reference potential. In particular, the switchable capacitor has one end that is fixedly connected to the reference potential of the drive circuit, just as the source potential is also fixedly connected to the reference potential. Therefore, the desired effect can be achieved by driving only one switchable element of the capacitor.

[0009] The reference potential is directly connected to the gate potential (i.e., without a resistive element) via a switchable capacitor (as a series circuit element). This enables high current flow. The switchable capacitor consists of a switch and a capacitor connected in series. The switch can be connected to the reference potential via the capacitor. The switch can also be connected to the gate potential via the capacitor. Preferably, the switch is directly connected to the reference potential, while the capacitor connects the switch (or via the switch's reference potential) to the gate potential. Thus, the switching signal of the switch can be directly related to the reference potential. The switch of the switchable capacitor is preferably a semiconductor switch, especially a transistor, such as a MOSFET.

[0010] Furthermore, the switchable capacitor can be connected to the gate potential via a resistor. The switchable capacitor can also be directly connected to the gate potential and connected to the reference potential via a resistor. The switchable capacitor can also have its own current-limiting resistor, which is connected in series within the switchable capacitor. The switchable capacitor can have its own current-limiting resistor, or its connection to a potential (with the reference potential or the gate potential) can have a current-limiting resistor. The current-limiting resistor is connected in series (with the mentioned components). This results in a current-limited current. The series connection of the switchable capacitor and the resistor (for current limiting) can connect the reference potential to the gate potential.

[0011] The reference potential to which the switchable capacitor is connected (directly or fixedly) can be ground, the source potential, or the potential of a (constant) voltage source through which the switchable capacitor is connected to ground or the source potential. In particular, the gate potential can be connected via the switchable capacitor to the negative potential of a negative voltage source or to the positive potential of a positive voltage source, which can be part of a drive output stage of a drive circuit. The reference potential can be connected to the gate potential via the switchable capacitor and via a voltage source (in this order or vice versa). For example, if the reference potential is ground, the gate potential can be connected via the switchable capacitor and via a voltage source (in this order or vice versa).

[0012] The switchable capacitor is connected to the reference potential, particularly directly, with potential offset (i.e., via a voltage source), and / or via passive circuitry (e.g., a resistor or a circuit with a resistor and / or a capacitor, e.g., in series). The switchable capacitor in the drive circuit is connected to the reference potential with its polarity maintained; that is, one end of the switchable capacitor facing the reference potential when on also faces the reference potential when off. In other words, the connection between the switchable capacitor and the reference potential cannot reverse the polarity of the switchable capacitor relative to the gate potential.

[0013] The drive circuit may have a control unit (control device). This control unit is connected to or via the switching drive of the switchable capacitor. The control unit is configured to delay the switchable capacitor's entry into an active state relative to the switching edge of the drive circuit. The delay in putting the switchable capacitor into the active (conducting) state may correspond to a predetermined duration, for example, between 0, 1, and 1 ns or less than 2 ns. Other embodiments specify that this duration is no greater than 5 ns, 20 ns, 100 ns, or no greater than 1 µs, 5 µs, or 20 µs. This delay is preferably no longer than the PWM cycle, on-cycle, or off-cycle starting at the switching edge.

[0014] The delay is preferably constant, for example, fixedly implemented in the drive circuit. The delay can be predetermined. The control unit can be implemented as a control device, such as a control circuit or logic circuit, a microprocessor running software code (which at least partially implements the described manner), or a combination thereof.

[0015] The control unit is preferably configured to terminate the active state of the switchable capacitor after a predetermined on-duration. In this way, the amount of charge transferred between the gate and the capacitor is also controlled or limited. Specifically, the voltage swing of the capacitor is limited during the connection of the capacitor or during the on-duration. The control unit can be configured such that the duration of the capacitor charging the gate and the duration of the gate charging the capacitor (corresponding to the on-duration or the active state) are no greater than 2%, 1%, or 0.7% of the duration of one PWM cycle of the pulse-mode signal. Here, the pulse-mode signal is the drive signal of the power transistor.

[0016] A power circuit can be configured having a power transistor and a drive circuit as described herein. The power transistor has a gate (with a gate potential). The power transistor also has a source; a gate-source voltage exists between the gate and source of the power transistor. The power circuit also includes the drive circuit described herein, wherein its gate potential is connected to the gate of the power transistor. A reference potential of the drive circuit is connected to the source of the power transistor. The power transistor is preferably a power MOSFET or a power IGBT. The power transistor is particularly designed for voltages > 60 V, particularly at least 400 V or at least 800 V, and where appropriate for a turn-off voltage of at least 1200 V. The power transistor is preferably designed for a rated current of at least 10 A, at least 50 A, or at least 100 A.

[0017] The method described herein can also be implemented by a procedure. The circuit described herein is preferably configured to perform this procedure. A method for temporarily storing the charge on the gate of a power transistor is described. After the on-edge of the power transistor, a capacitor charges the gate. This is achieved by configuring the capacitor as a switchable capacitor (as described herein) and activating it, for example, through the on-state of the capacitor's switch. After the off-edge of the power transistor, the gate charges the capacitor, i.e., the gate discharges toward the capacitor. This step is also preferably performed by activating the switchable capacitor. The charging process causes a desired change in the gate potential, particularly increasing the switching speed, i.e., increasing the edge steepness when the power transistor is turned on and off. This is achieved by configuring the capacitor as a switchable capacitor (as described herein) and activating it, for example, through the on-state of the capacitor's switch.

[0018] Specifically, within the scope of this method, it is specified that the duration of the capacitor charging the gate and the duration of the gate charging the capacitor (i.e., the duration of the active state of the capacitor switching) constitute only a small fraction of one PWM cycle of the pulse-mode signal driving the power transistor. In particular, the duration of the capacitor charging the gate and the duration of the gate charging the capacitor do not exceed 2%, 1%, or 0.7% of the duration of one PWM cycle of the pulse-mode signal driving the power transistor.

[0019] Furthermore, preferably, the voltage swing across the capacitor element of the switchable capacitor is only a portion of the voltage swing at the transistor's gate (the swing between the gate's on and off levels). Therefore, the capacitor stores only a portion of the charge applied to and removed from the gate. The magnitude of the voltage swing resulting from charging at the capacitor is particularly no greater than 40%, 30%, or 25% of the voltage swing between the gate's on and off levels.

[0020] The charging (of the gate) or the start of charging after the turn-on edge is delayed for a predetermined duration relative to the turn-on edge. The charging (of the capacitor) after the turn-off edge is delayed for a predetermined duration relative to the turn-off edge. This delay is designed so that the gate level remains at least 80%, at least 90%, or at least 95% of the level present on the gate immediately preceding that edge. The gate level relates to a reference potential and can therefore be considered as a voltage relative to that reference potential. The duration of the delay between the charging (or its start) and the respective preceding edge is in particular no greater than 4%, 2%, 1%, or 0.7% of the duration of one PWM cycle of the pulse-mode signal driving the power transistor. Attached Figure Description

[0021] Figure 1 Exemplary implementations of the drive circuit are used to illustrate this.

[0022] Figure 2 This is used to illustrate the operation of the exemplary drive circuit and to illustrate exemplary implementations of the methods described herein. Detailed Implementation

[0023] Figure 1 A drive circuit TR is shown, having a bipolar voltage supply comprising a first voltage source V1 and a second voltage source V2. The voltage of voltage source V2 is adapted to the desired turn-off level of the gate G of the power transistor T, for example, -3 to -5 volts (e.g., 4 volts) relative to ground M. The voltage of voltage source V1 is adapted to the desired turn-on level of the gate G of the power transistor T, for example, 10 to 15 volts (e.g., 12 volts) relative to ground M. The voltages of the voltage sources can also be numerically greater than the desired gate voltage to support the switching process.

[0024] The connection point formed by the series connection of two voltage sources V1 and V2 is connected to the reference potential M (ground). Voltage sources V1 and V2 are part of the drive output stage TE. The drive output stage TE also has two switches S1 and S2, where switch S1 is connected to the first positive voltage source V1, and switch S2 is connected to the second negative voltage source V2. Therefore, the voltage output of voltage sources V1 and V2 is switchable. Switches S1 and S2 are connected to the gate potential GP via their respective resistors R1 and R2. The gate potential GP is part of the output of the drive circuit TR or the drive output stage TE. If switch S1 is closed (and S2 is open), the gate potential GP receives the positive potential of voltage source V1. If switch S2 is closed (and S1 is open), the gate potential GP receives the negative potential of voltage source V2.

[0025] A power transistor T is connected in the drive circuit TR, and especially after the drive output stage TE or output A. Its gate terminal G is connected to the gate potential GP of the drive circuit TR. The drain D and source S of the power transistor T are connected to the positive potential H- and negative potential H+, but not directly; instead, they are connected via a load (not shown), which can be switched by the switching state of the power transistor T. The gate G, or its potential, determines the switching state of the power transistor T. Therefore, the magnitude of the gate potential GP of the drive circuit TR (relative to the reference potential M, which is also part of the output A) is decisive for the switching state of the power transistor. The control signal for the power transistor is given by the voltage between potentials GP and M, where GP changes as shown during drive.

[0026] To support the switching process and to avoid power loss in the drive output stage TE, a switchable capacitor SK is provided. As shown, the switchable capacitor SK consists of a capacitor C and a switching element S3 connected in series. The switching element S3, also referred to as switch S3, is assigned to or connected in series with the switchable capacitor SK. The switching element S3 is, in particular, a MOSFET or another transistor. The reference potential is connected to the capacitor C via switch S3. The end of the capacitor C opposite to switch S3 is connected to the drive output stage TE or its gate potential GP. Therefore, the switchable capacitor SK is connected to the drive circuit TR or the output A of the drive output stage. When switch S3 is closed, the capacitor C of the switchable capacitor SK is connected in parallel to the reference potential and the gate potential GP. Therefore, there is a gate potential or a reference potential (ground) at both ends of the capacitor C. The voltage between these potentials is then applied to the capacitor. The voltage across the capacitor is then applied to these potentials GP and M. The voltage between the reference potential M and the gate potential GP is then applied to the capacitor C. The parasitic series and parallel resistances of capacitor C are not shown; these resistances are preferably considered when precisely examining the charging process shown below (especially the parasitic series resistance that restricts the flow of current to / from the capacitor). Figure 1 The diagram shows a switchable capacitor SK connected to both the gate potential GP and the reference potential M. However, the switchable capacitor can also be connected between the gate potential GP and a potential that is offset relative to the reference potential M, such as a negative potential connected to voltage source V2 or a positive potential connected to voltage source V1. Due to the presence of the voltage source, these two potentials are offset relative to the reference potential M (ground). However, it is generally specified that the switchable capacitor SK connects the gate potential GP to a potential that is fixed relative to the gate potential or a potential referenced by its voltage (directly or indirectly). Only the connection between the switchable capacitor SK and the reference potential M is shown; other possible connections are not shown for better clarity. In principle, the switchable capacitor SK is connected between the gate potential GP and a potential connected to its current (with or without a potential offset caused by a voltage source).

[0027] Furthermore, a signal source exists for a pulse-mode or pulse-width modulation signal (see reference PWM), which controls switches S1 and S2. As symbolically shown, control unit ST is driven by switches S1, S2, and S3. Control unit ST constitutes a signal source for the pulse-width modulation signal (“PWM signal”), which drives switches S1 and S2, or generates a gate control voltage at output A according to the PWM signal. Control unit ST can be considered as… Figure 2 The signal source of the pulse mode PWM (pulse width modulation control signal) is shown in the figure.

[0028] The control unit ST is configured to alternately drive switches S1 and S2 (or both of them to be in the off state). Thus, when switch S1 is closed, a voltage with a first level (on level, positive level) is generated at the gate potential GP relative to the reference potential M, corresponding to the positive voltage of voltage source V1. When switch S2 is closed, a second level (off level, negative level) is generated, where the resulting second level corresponds to the negative potential of the second voltage source.

[0029] As described, the speed of the switching process is crucial to the power loss at transistor T, where switching losses also occur in the drive circuit TR due to the alternating voltage at gate potential GP or gate G. During switching between these two levels, gate G is charged or discharged depending on the direction of the switching edge, requiring a high-speed removal of charge from or application of charge to the gate each time. To support this and thereby reduce the current that voltage sources V1 and V2 must provide for the charge commutation process, a switchable capacitor SK is provided. It provides charge to gate G via gate potential GP or via output A, thus charging the gate in addition to voltage source V1. When switch S2 is closed and therefore voltage source V2 is active, the gate is discharged. In this case, capacitor C supports the discharge process by absorbing charge. A supporting current flow is generated between the switchable capacitor SK and gate potential GP, which supports the level change caused by driving output stage TE.

[0030] The current flowing from the switchable capacitor SK to the gate potential GP of output A has the same current flow direction as the current simultaneously flowing from the first voltage source V1 to output A or its gate potential GP. The same is true for voltage source V2, which takes charge from gate G (when S2 is closed), where the switchable side SK supports this by generating additional current flows in the same direction (from gate G or away from the output, respectively).

[0031] The control unit ST also controls switch S3, particularly with a delayed control relative to switches S1 and S2. The control unit ST controls switch S3 using a capacitor control signal KS, or generally controls the controllable capacitor SK. The control unit ST connects switch S3 when switch S1 is closed, but only for a short period during the on-state of switch S1. The same applies to switch S2, where switch S3 is connected when switch S2 is controlled, but for a shorter duration than the on-state of switch S2.

[0032] Figure 2 This provides a more detailed explanation of the timing sequence of the control process implemented by the control unit ST (as a device). The timing diagram above shows the pulse-wave modulation signal PWM, which switches according to the signal. Figure 1Switches S1 and S2 are used. When the pulse width modulation signal PWM is low (Low-Pegel – the off level of transistor T), switch S2 is closed and switch S1 is open. When the pulse width modulation signal PWM is high (High-Pegel – the on level of transistor T), switch S1 is closed and switch S2 is open. A conduction edge PF1 is generated when switch S1 is turned on. A switching edge PF2 is generated when switching to the closed switch S2.

[0033] The time graphs below show the change of the capacitor switching signal KS relative to the pulse width modulation signal PWM (PWM signal for short). Both time graphs involve a time progression t extending to the right. It can be seen that there is a switching edge F1 (on-edge) of the capacitor switching signal KS, which occurs after the on-edge PF1 of the PWM signal. The on-edge F1 of signal KS is set to be delayed for a duration tD after the on-edge PF1. Furthermore, it can be seen that the off-edge F2 of the capacitor switching signal KS is clearly preceding the off-edge PF2 of the PWM signal. The on-duration of the capacitor switching signal KS is shown as tON, and is significantly shorter than the positive level duration between the edges PF1 and PF2 of the PWM signal. During the delay tD, the gate is not fully charged. More precisely, there is a conduction phase where the gate has only a fraction of the voltage present at the end of the conduction phase (shortly before edge PF2). If capacitor C is now connected during the duration tON between the edges F1 (on edge) and F2 (the subsequent off edge) of the capacitor switching signal JS, the higher voltage of capacitor SK relative to the gate can help charge the gate. This provides the desired support for the gate pass-through process. Capacitor K has a voltage due to the previous process during the duration tON, which is greater than the voltage set for the gate G at this point, and up to this point, this voltage is only a portion of the final voltage (at the end of the PWM signal's on-phase). Therefore, a supporting current flow is generated from capacitor C to the gate G.

[0034] Figure 2It is also shown that the same process is repeated after the turn-off edge PF2. When the PWM signal has a turn-off edge PF2, the capacitor is connected during the duration tON' between the turn-on edge F1' and the turn-off edge F2' of the capacitor switching signal KS, shortly after this switching edge PF2. Since the turn-on duration tON' is at the beginning of the relevant period of the signal PWM, the gate G is only partially discharged shortly after the turn-off edge PF2 of the PWM signal. The capacitor C or SK is then connected for support, where, in this case, the capacitor C or SK absorbs charge. Since the capacitor is only connected for a relatively short time, it neither reaches the high level nor its low level of the PWM signal. More precisely, the voltage swing of the capacitor (between F1, F2 and subsequent levels or between F1', F2' and subsequent levels) is only a portion of the voltage swing of the gate voltage as shown in the PWM signal above. Figure 2 It can be seen that the temporary connection of the switchable capacitor ZK is performed either directly or shortly after the switching edge of the PWM signal, or for all switching edges; however, it can also be performed only for a subset of switching edges. There may be operating ranges within which it is advantageous to keep the capacitor continuously off.

[0035] Figure 1 The control unit ST shown is equipped to perform the methods described herein, and its switching process is... Figure 2 The example is illustrated below. The control unit ST is, in particular, a control circuit, such as logic circuitry, or at least partially implemented as software code running on a processor. This software code is configured to execute the methods described herein when running on the processor. For this purpose, the processor may have a virtual or physical output interface for outputting the signal and, where appropriate, the signal PWM. The control unit may be configured to generate only the signal KS, while another driving device generates the PWM signal. The control unit can receive the PWM signal from the driving device to generate the KS signal (with a time delay and a shorter on-time duration) according to the switching edge of the PWM signal. The delay tD is optional. Preferably, tON is less than 10%, 5%, or 1% of the on-time duration of the PWM signal. This depends on the size of the capacitor C and the gate capacitance acting on the gate G.

Claims

1. A driving circuit (TR) having a driving output stage (TE) with a gate potential (GP), wherein, The drive circuit (TR) also includes a switchable capacitor (SK), through which the gate potential (GP) is connected to the reference potential (M) of the drive circuit (TR).

2. The driving circuit (TR) according to claim 1, wherein, The switchable capacitor (SK) connects the reference potential (M) directly to the gate potential (GP), or the reference potential (M) is connected to the gate potential (GP) via the switchable capacitor (SK) and via a voltage source (V2), or the series circuit of the switchable capacitor (SK) and a resistor connects the reference potential (M) to the gate potential (GP).

3. The drive circuit (TR) according to claim 1 or 2, wherein, The switchable capacitor (SK) is composed of a switch (S3) and a capacitor (C) connected in series.

4. The drive circuit (TR) according to claim 1, 2 or 3 further includes a control unit (ST) operatively connected to the switchable capacitor (SK) and configured to cause the switchable capacitor (SK) to enter an active state (F1) with a delay (tD) relative to the switching edge (PF1, PF2) of the drive circuit (TR).

5. The drive circuit (TR) according to claim 4, wherein, The delay (tD) that causes the switchable capacitor (SK) to enter the active state corresponds to a predetermined duration, or the delay (tD) ends when a predetermined size of the gate potential (GP) is reached.

6. The drive circuit (TR) according to claim 4 or 5, wherein, The control unit (ST) is configured to terminate (F2) the active state of the switchable capacitor (SK) after a predetermined on-time (tON) period.

7. A power circuit comprising a power transistor (T) having a gate (G), wherein, The power circuit includes a drive circuit (TR) according to any one of the preceding claims, the gate potential (GP) of which is connected to the gate (G) of the power transistor (T).

8. A method for temporarily storing the gate charge of the gate (G) of a power transistor (T), wherein, After the on edge (PF1) of the power transistor (T), the capacitor (C) is connected (F1) and the gate (G) is charged, and wherein, after the off edge (PF2) of the power transistor (T), the capacitor (C) is further connected (F2), whereby the gate (G) charges the capacitor (C).

9. The method according to claim 8, wherein, The duration (tON) of the capacitor (C) charging the gate (G) and the duration (tON′) of the gate (G) charging the capacitor (C) are not greater than 2%, 1% or 0.7% of the duration of the PWM period of the pulse-mode signal used to drive the power transistor.

10. The method according to claim 8 or 9, wherein, The magnitude of the voltage swing caused by recharging at the capacitor is no greater than 40%, 30%, or 25% of the voltage swing between the on and off levels of the gate (G).

11. The method according to any one of claims 8, 9 or 10, wherein, The recharging after the on edge (PF1) of the power transistor is delayed by a predetermined time duration (tD) relative to the on edge (PF1), and the recharging after the off edge (PF2) is delayed by a predetermined time duration (tD′) relative to the off edge (PF2).

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