Circuit board and semiconductor package comprising the same

Abstract

An embodiment of the present invention discloses a circuit board, comprising: a glass core layer; a core electrode unit disposed in the glass core layer; a multilayer insulating unit disposed on the glass core layer; and a multilayer wire unit disposed in the multilayer insulating unit, wherein the outermost surface of the glass core layer is inclined relative to the outermost surface of the multilayer insulating unit.

Description

Technical Field

[0001] The present invention relates to circuit boards and semiconductor packages. Background Technology

[0002] With advancements in the performance of electrical / electronic products, techniques for attaching a large number of packages to substrates of finite size have been proposed and researched. However, since typical packaging is based on mounting a single semiconductor chip within it, there are limitations in achieving the desired performance.

[0003] A typical circuit board or packaging substrate has a processor package in which a processor chip is disposed and a memory package with a memory chip attached thereto, which are connected to form a single unit. The advantage of this type of packaging substrate is that by manufacturing the processor chip and memory chip as a single integrated package, the chip mounting area can be reduced, and high-speed signal transmission can be achieved through a shortened path. Due to these advantages, the aforementioned packaging substrate is widely used in mobile devices and the like.

[0004] Meanwhile, in recent years, as the specifications of electronic devices such as mobile devices have become increasingly sophisticated and high-bandwidth memory (HBM) has been adopted, package sizes have been continuously increasing. Furthermore, as the required functions of application processors have increased, it is necessary to form a separate processor chip for each function and provide a circuit board on which to mount the processor chip. In this situation, even when the application processor is divided into two processor chips for each function, the number of input / output terminals provided in each processor chip is also increasing.

[0005] Furthermore, due to advancements in 5G, the Internet of Things (IoT), improved image quality, and faster communication speeds, the number of power and signal lines has increased, leading to a trend towards more terminals on processor chips. Consequently, the area and thickness of circuit boards, as well as the density of circuit patterns, are also increasing. Increased circuit board area and thickness can cause problems such as difficulties in miniaturization, reliability issues related to board warpage, and increased product costs. Therefore, increasing circuit pattern density rather than increasing circuit board area and thickness is more advantageous in terms of product cost, warpage-related reliability, and miniaturization. This necessitates finer circuit patterns and through-electrodes.

[0006] In particular, as circuit boards become thinner, deformations such as warping and twisting that occur during circuit board manufacturing increase. To prevent this, a glass-core structure has been proposed, in which a glass plate is formed in the core of the circuit board.

[0007] However, when the core is formed from a glass plate, there may be issues with adhesion between the glass plate and other electrode components, as well as reduced reliability.

[0008] In particular, the glass itself may have poor reliability, and there is a problem that the reliability of the circuit boards is further weakened by breakage that occurs in the glass during the manufacturing of individual circuit boards from the panel into units. In addition, difficulties may be encountered when producing glass boards as individual units, such as additional damage to components caused by beveling and separation between the insulation layer and the glass. Summary of the Invention

[0009] Technical issues

[0010] Embodiments of the present invention provide a circuit board and a semiconductor package including the circuit board, wherein the strength of the glass core layer is improved by a tilted structure between the glass core layer and the build-up insulating portion, and reliability is improved by suppressing separation between the build-up insulating portion and the glass core layer and damage thereto.

[0011] Furthermore, embodiments can realize a circuit board and a semiconductor package including the circuit board, wherein the tilt angles of the respective outer surfaces of the glass core layer and the multilayer insulating portion are set to be different from each other, thereby suppressing damage caused by chamfering, reducing residual stress, and preventing breakage.

[0012] Furthermore, embodiments can realize a circuit board and a semiconductor package including the circuit board, wherein chipped portions are removed by chamfering, torsion is suppressed by structural symmetry, and mechanical strength is prevented from being reduced.

[0013] Furthermore, embodiments can realize a circuit board and a semiconductor package including the circuit board, wherein mechanical reliability is improved by allowing the multilayer insulating portion and the glass core layer to have coplanar surfaces formed by the same process, so that stress is uniformly distributed therebetween.

[0014] The objectives to be addressed by the embodiments are not limited to those described above, and will include those that can be identified and their effectiveness can be determined by the solutions and embodiments for those objectives described below.

[0015] Technical solution

[0016] The circuit board according to an embodiment of the present invention includes a glass core layer, a core electrode portion disposed in the glass core layer, a laminated insulation portion disposed on the glass core layer, and a laminated line portion disposed in the laminated insulation portion, wherein the inclination of the outermost surface of the glass core layer is different from the inclination of the outermost surface of the laminated insulation portion.

[0017] The first tilt angle of the outermost surface of the laminated insulation portion relative to the upper surface of the glass core layer may be different from the second tilt angle of the outermost surface of the glass core layer relative to the upper surface of the glass core layer.

[0018] The first tilt angle can be smaller than the second tilt angle.

[0019] The outer surface of the glass core may include a first surface as the outermost surface and a second surface that is in contact with the first surface and is inclined relative to the first surface.

[0020] The second surface can contact the upper or lower surface of the glass core layer.

[0021] The length of the first surface in the vertical direction can be greater than the length of the second surface in the vertical direction.

[0022] The second surface can be located between the upper and lower surfaces of the glass core layer.

[0023] The second surface can contact the outermost surface of the laminated insulating portion and be positioned parallel to the outermost surface.

[0024] The third tilt angle of the second surface relative to the upper surface of the glass core layer can be equal to the first tilt angle of the outermost surface of the laminated insulation relative to the upper surface of the glass core layer.

[0025] The third tilt angle of the second surface relative to the upper surface of the glass core layer may be different from the second tilt angle of the outermost surface of the glass core layer relative to the upper surface of the glass core layer of the laminated insulating portion.

[0026] The outermost surface of the glass core layer can be spaced apart from the outermost surface of the laminated insulation portion by a predetermined distance.

[0027] The upper or lower surface of the glass core may include an exposed surface, that is, it may be partially exposed.

[0028] The circuit board may also include a cover layer disposed on the outer surface of the glass core layer and the outer surface of the laminated insulation portion.

[0029] The cover layer can be formed to extend inward beyond the outermost surface of the laminated insulation portion.

[0030] The circuit board may also include a protective film spaced apart from the outermost surface of the glass core layer and disposed on the outer surface of the laminated insulating portion.

[0031] Beneficial effects

[0032] Embodiments of the present invention provide a circuit board and a semiconductor package including the circuit board, wherein the strength of the glass core layer can be improved by a tilted structure between the glass core layer and the multilayer insulating portion, and reliability can be improved by suppressing the separation between the multilayer insulating portion and the glass core layer and the damage caused therefrom.

[0033] Furthermore, embodiments may provide a circuit board and a semiconductor package including the circuit board, wherein the tilt angles of the outer surfaces of the glass core layer and the multilayer insulating portion can be set to be different from each other, thereby suppressing damage caused by chamfering, reducing residual stress, and preventing breakage.

[0034] Furthermore, embodiments may provide a circuit board and a semiconductor package including the circuit board, wherein chipping can be removed by chamfering, torsion can be suppressed by structural symmetry, and reduction in mechanical strength can be prevented.

[0035] Furthermore, embodiments may provide a circuit board and a semiconductor package including the circuit board, wherein mechanical reliability can be improved by allowing the multilayer insulating portion and the glass core layer to have coplanar surfaces formed by the same process, so that stress is uniformly distributed therebetween.

[0036] The various advantages and effects of the present invention are not limited to those described above, and can be more easily understood through the description of specific embodiments of the present invention. Attached Figure Description

[0037] Figure 1 This is a plan view of a circuit board according to a first embodiment of the present invention.

[0038] Figure 2 It is along Figure 1 The view intercepted by line A-A'.

[0039] Figure 3 yes Figure 2 An enlarged view of part K1 in the image.

[0040] Figure 4 It shows Figure 3 Another example.

[0041] Figure 5 It shows Figure 3 Another example.

[0042] Figure 6 It shows Figure 3 Another example.

[0043] Figure 7 It shows Figure 3 Another example.

[0044] Figures 8 to 15This is a view used to describe a method of manufacturing a circuit board according to an embodiment.

[0045] Figure 16 This is a cross-sectional view of the circuit board according to the second embodiment.

[0046] Figure 17 yes Figure 16 An enlarged view of part K2.

[0047] Figure 18 This is a cross-sectional view of the circuit board according to the third embodiment.

[0048] Figure 19 yes Figure 18 An enlarged view of part K3.

[0049] Figure 20 It shows Figure 19 Another example.

[0050] Figure 21 This is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0051] Figure 22 This is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0052] Figure 23 This is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0053] Figure 24 This is a cross-sectional view showing a semiconductor package according to the fourth embodiment. Detailed Implementation

[0054] While the invention is open to various modifications and alternatives, specific embodiments thereof are illustrated by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the invention is not intended to be limited to the specific forms disclosed; rather, the invention encompasses all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

[0055] In the following, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0056] However, the spirit of the invention is not limited to the embodiments described, and can be implemented in various forms, and one or more elements in the embodiments can be selectively combined and replaced for use within the scope of the spirit of the invention.

[0057] Furthermore, unless specifically defined and described, the terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having the meaning commonly understood by those skilled in the art, and commonly used terms, such as those defined in dictionaries, may be understood taking into account their contextual meaning in the relevant field.

[0058] Furthermore, the terminology used in the embodiments of the present invention is for describing embodiments of the invention only and is not for limiting purposes. In this specification, unless the context clearly indicates otherwise, the singular form includes its plural form, and in the case of describing “at least one (or one or more) of A, B, and C,” this may include at least one of all combinations that can be made of A, B, and C.

[0059] It should be understood that although the terms "second," "first," etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of the invention, a first component may be referred to as a second component, and a second component may similarly be referred to as a first component. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. These terms are used only to distinguish a component from other components, and the nature, order, sequence, etc., of the components are not limited by these terms.

[0060] Furthermore, when a component is described as “connected,” “coupled,” or “linked” to another component, the component may include not only cases where it is directly connected, coupled, or linked to another component, but also cases where it is connected, coupled, or linked to another component through another component between the component and other components.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, singular forms are intended to include plural forms as well, unless the context clearly indicates otherwise. It should also be understood in this application that, when used in this specification, the terms “comprising,” “including,” “containing,” and / or “comprising” designate the presence of said features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0062] Furthermore, when a component is described as being formed "above" or "below" another component, the terms "above" or "below" include cases where the two components are in direct contact with each other, or cases where one or more components are (indirectly) disposed between the two components. Additionally, when an element is described as being disposed "above or below" another element, such a description can include cases where the element is disposed on the upper or lower side relative to the other element.

[0063] Furthermore, the statement “part A is positioned between part B and part C” should be understood to encompass a configuration in which part A is configured to at least partially overlap with part B and part C in the horizontal and / or vertical directions.

[0064] The description of directions may include horizontal and vertical directions, and the horizontal direction may include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. According to the Cartesian coordinate system, these directions may be referred to as the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis). The expression "overlapping in the horizontal direction" should be understood to encompass overlap in the first horizontal direction and / or overlap in the second horizontal direction.

[0065] Furthermore, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, rather than that component A is exposed from the entire product. That is, when component A is described as being exposed from component B, at least a portion of component A can be understood as being covered by component C.

[0066] Furthermore, when component A is described as "in contact" with component B, this contact can include not only the case where component A and component B are in direct contact, but also the case where component A contacts component B through another component located between component A and component B. Therefore, component A is described as "in direct contact" with component B when it is intended to be understood as only being in direct contact with component B.

[0067] Furthermore, when component A is described as being "covered" by component B, it should be understood that component A is covered by component B to the extent necessary to achieve its intended function and purpose. Unless there are special circumstances, this statement is not necessarily to be interpreted as meaning that component A is entirely covered by component B.

[0068] Unless otherwise defined, all terms used herein, including technical or scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art. It should also be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0069] Before describing the embodiments, the electronic device with a circuit board and semiconductor package of the application embodiments will be briefly described. The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor devices, and the semiconductor devices may be mounted on the circuit board.

[0070] Semiconductor devices can include active and / or passive devices. Active devices can be semiconductor chips in the form of integrated circuits (ICs), where hundreds to millions or more devices are integrated into a single chip. Semiconductor chips can be logic chips, memory chips, etc. Logic chips can be non-memory chips, such as central processing units (CPUs), pattern processing units (GPUs), or field-programmable gate arrays (FPGAs). For example, a logic chip can be an application processor (AP) chip that includes at least one of a CPU, GPU, digital signal processor, cryptographic processor, microprocessor, and microcontroller. Alternatively, a logic chip can be an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc., or a chipset that includes a specific combination of those listed so far.

[0071] Memory chips can be stacked memories such as high-bandwidth memory (HBM). Furthermore, memory chips can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0072] Meanwhile, the semiconductor packaging product group in the application embodiment can be any one of chip-scale package (CSP), flip chip-scale package (FC-CSP), flip chip ball grid array (FC-BGA), package on package (POP), and system in package (SIP), but the present invention is not limited thereto.

[0073] In addition, electronic devices can be smartphones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smartwatches, and automobiles.

[0074] Figure 1 This is a plan view of a circuit board according to a first embodiment of the present invention. Figure 2 It is along Figure 1 The view intercepted by line A-A' Figure 3 yes Figure 2 An enlarged view of part K1. Figure 4 Show Figure 3 Another example, Figure 5 Show Figure 3 Another example, Figure 6 Show Figure 3 Another example, and Figure 7 Show Figure 3 Another example.

[0075] refer to Figure 1 and Figure 2 The circuit board 100 according to the first embodiment may include an insulating portion 110 and an electrode portion 120. In an embodiment, the insulating portion 110 may have a structure with multiple stacked insulating layers. The electrode portion 120 may be configured to be embedded in each insulating layer of the plurality of insulating portions 110 and may be used to transmit signals and / or power from a main circuit board (not shown) to a semiconductor device.

[0076] Furthermore, the circuit board 100 may include a protective layer SR and a multilayer structure. The multilayer structure may include multilayer insulating portions and multilayer line portions. Additionally, the multilayer structure may include a core portion comprising a glass core layer 111 and a core electrode portion 121. Furthermore, the multilayer insulating portions may include multiple stacked layers. For example, when the circuit board includes a core layer, multilayer insulating portions 112 and 113 may include an upper multilayer insulating portion 112 and a lower multilayer insulating portion 113, as in this embodiment. Specifically, in this embodiment, the circuit board may include an upper multilayer insulating portion 112 disposed on the upper surface of the core layer and a lower multilayer insulating portion 113 disposed on the lower surface of the core layer. Specifically, as shown, the circuit board 100 may include a glass core layer 111, multilayer insulating portions 112 and 113, a core electrode portion 121, and multilayer line portions 122 and 123. Furthermore, the circuit board 100 may also include a protective layer SR disposed on the upper surface of the upper multilayer insulating portion and / or the lower surface of the lower multilayer insulating portion. Furthermore, in the embodiments of the invention described below, the upper stacked insulating portion 112 and / or the lower stacked insulating portion 113 may include a plurality of insulating layers stacked in a vertical direction (Y-axis direction). In this embodiment, the horizontal direction may be a first direction or the X-axis direction, while the vertical direction (or stacking direction) may be a second direction or the Y-axis direction. The horizontal and vertical directions may be perpendicular to each other. Stacked line portions 122 and 123 may be configured to be embedded in each layer (e.g., insulating layer) of the stacked insulating portions 112 and 113 and may be used to transmit signals and / or power from a main circuit board (not shown) to a semiconductor device. Stacked line portions 122 and 123 may include circuit layers and via electrodes. Circuit layers may be disposed on one surface of each of the plurality of insulating layers included in the upper and / or lower stacked insulating portions and may be used to transmit signals and / or power. Via electrodes may pass through at least a portion of each of the plurality of insulating layers and may be used to electrically connect the circuit layers to each other. In addition, the circuit layer may include a bonding portion (not shown) disposed on the multilayer insulating portion and configured to electrically connect semiconductor devices and / or electronic devices to the circuit board.

[0077] The insulating portion 110 of the circuit board, or each insulating layer included in the insulating portion 110, may comprise chemically strengthened / chemically semi-strengthened glass, such as soda lime glass or aluminosilicate glass. For example, the insulating portion 110 of the circuit board may comprise rigid or flexible plastics, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating portion 110 of the circuit board may comprise sapphire. For example, the insulating portion 110 of the circuit board may comprise an optically isotropic film. For example, the insulating portion 110 of the circuit board may comprise a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating portion 110 of the circuit board may be formed of a material comprising fillers and insulating resins. For example, the insulating portion 110 of the circuit board may have a structure in which silica or alumina filler is disposed in a thermosetting or thermoplastic resin. The insulating portion 110 may have a structure in which multiple different insulating materials are stacked. Exemplary arrangement structures will be described in more detail below.

[0078] In one embodiment, the insulating portion 110 may include a glass core layer 111, which includes a reinforcing member.

[0079] The glass core layer 111 can be formed of a glass material. For example, the glass core layer 111 may include pure silica (approximately 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc. The glass core layer 111 is not limited to silica-based glass compositions; alternative glass materials such as fluoride glass, phosphate glass, and chalcogenide glass may also be used. Furthermore, the glass core layer 111 may include additional additives to form a glass with specific physical properties. Such additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda ash), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and may include carbonates and / or oxides of these elements and other elements. Additionally, the glass core layer 111 may include an insulating material.

[0080] The glass core layer 111 can suppress warpage that may occur when the circuit board becomes thinner. In other words, warpage can be reduced by arranging a glass layer (or glass core) with high stiffness and a low coefficient of thermal expansion (CTE) at the center or core of the circuit board. For example, the glass core layer 111 can have higher stiffness and a lower coefficient of thermal expansion than other insulating or protective layers.

[0081] Furthermore, the upper laminated insulating portion 112 or the lower laminated insulating portion 113 can be formed of any insulating resin, such as thermosetting resins and / or photocurable resins. As a thermosetting resin, ABF (Ajinomoto Build-up Film), a product issued by Ajinomoto Corporation, can be used, and prepreg (PPG) including glass fibers can also be used. As a photocurable resin, insulating resins such as photoimageable dielectric (PID) resins can be used. The aforementioned insulating resins can be, for example, epoxy resins, bismaleimide triazine (BT) resins, phenolic resins, etc., and include inorganic fillers such as silica. When the insulating resin is used as a core, the insulating resin can include reinforcing materials or reinforcing components, such as glass fibers or aramid fibers. For example, when manufacturing the insulating portion 110, ABF, a product issued by Ajinomoto Corporation, can be used, and insulating resins such as FR-4, BT (Bismaleimide Triazine), and PID resins can also be used. The aforementioned insulating resin can be, for example, epoxy resin, bismaleimide triazine (BT) resin, phenolic resin, BT, etc. For example, when the circuit board 100 is without a core, the insulating portion 110 can have a structure in which ABF is stacked in the absence of a core layer.

[0082] Furthermore, the line or electrode portion 120 according to the embodiment can be configured to provide an electrical connection between a chip (or semiconductor device or die) and a motherboard, etc. The electrode portion 120 may include line portions (e.g., circuit patterns, circuit pattern layers, pads or pattern portions) and via portions (or via electrodes).

[0083] For example, the line portion of electrode portion 120 may include patterns and pads disposed on the upper surface of the insulating layer. Hereinafter, the term "line portion" may be used interchangeably with the terms "circuit pattern" and "pattern portion". Furthermore, electrode portion 120 may also include via portions or via electrodes passing through the insulating layer. Therefore, in embodiments, electrode portion 120 will be described as including line portions (circuit patterns) and via electrodes in each insulating layer. Furthermore, the line portion of electrode portion 120 may be designed in various forms to transmit signals and / or power to and from semiconductor devices, and may be disposed in each insulating layer of the stacked multilayer insulating portions 112 and 113.

[0084] In electrode portion 120, via electrodes (or via portions) can be configured to pass through at least a portion of each insulating layer of stacked insulating portions 112 and 113 to vertically connect circuit patterns disposed in the insulating layers. Via electrodes can electrically connect multiple circuit patterns (line portions) to each other. Multiple via electrodes can be provided, as in the case of line portions. That is, the insulating layer may include vias for arranging the via electrodes. Furthermore, via electrodes can have a wider width than the circuit patterns used for impedance optimization or heat dissipation, but are not limited to this and can be freely designed.

[0085] In electrode portion 120, line portions (circuit patterns) can be provided in each insulating layer. Furthermore, the circuit patterns can be electrically connected to each other. Additionally, the line portions (or circuit patterns) can be connected to via electrodes. Furthermore, the circuit patterns provided on the upper and lower surfaces of the insulating layers in the laminated insulating portions 112 and 113 can be electrically connected to semiconductor devices and / or motherboards, substrates, etc. For example, electrode portion 120 can be located in each layer (insulating layer) of glass core layer 111, upper laminated insulating portion 112, and lower laminated insulating portion 113.

[0086] Specifically, in this embodiment, electrode portion 120 may include core electrode portion 121 and stacked wire portions 122 and 123. Stacked wire portions 122 and 123 may include upper electrode portion 122 and lower electrode portion 123. Upper electrode portion 122 and lower electrode portion 123 may be stacked wire portions. Furthermore, upper electrode portion 122 may be disposed in each insulating layer of upper stacked insulating portion 112 and may be referred to as "upper stacked wire portion". Similarly, lower electrode portion 123 may be disposed in each insulating layer of lower stacked insulating portion 113 and may be referred to as "lower stacked wire portion". Alternatively, electrode portions may include stacked wire portions and stacked via electrodes (via portions).

[0087] The core electrode portion 121 may include a core wire portion 121a disposed on the upper and lower surfaces of the glass core layer 111 and a core through-hole electrode 121b passing through the glass core layer 111.

[0088] The upper electrode portion 122 may include an upper wire portion 122a and an upper through-hole electrode 122b. The upper wire portion 122a is a wire portion disposed on the upper and lower surfaces of each insulating layer of the upper stacked insulating portion 112. The upper through-hole electrode 122b is a through-hole electrode. The upper through-hole electrode 122b may pass through each insulating layer of the upper stacked insulating portion 112.

[0089] Furthermore, the lower electrode portion 123 may include a lower wire portion 123a and a lower through-hole electrode 123b. The lower wire portion 123a is a wire portion disposed on the upper and lower surfaces of the lower multilayer insulating portion 113, and the lower through-hole electrode 123b is a through-hole electrode. Additionally, the lower through-hole electrode 123b may pass through each insulating layer of the lower multilayer insulating portion 113.

[0090] Furthermore, in the embodiments, the line portions of the upper electrode portion (and / or the lower electrode portion) may include line portions with fine pitch (second line portions) and line portions with a larger pitch than the second line portions (first line portions).

[0091] A protective layer SR can be used to protect solder pads from external moisture or contaminants. To prevent short circuits during bonding between the circuit board and semiconductor devices and / or the motherboard, the protective layer SR can be formed of, for example, a solder resist. Specifically, the semiconductor devices and / or the motherboard can have multiple terminals for connection to the circuit board. Furthermore, the multiple terminals can be arranged in a high density. Solder can be used as an example when the multiple terminals are bonded to the solder pads of the circuit board. When using solder, solder short circuits can occur between the high-density terminals, and to address this short circuit problem, a solder resist with poor solder wetting properties can be provided. Furthermore, the protective layer SR can be formed of a material with insulating properties relative to the electrical connection. The protective layer SR can include resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acrylic monomers, etc. Additionally, the protective layer SR can include any of a photoresist layer, a cover-lay, and a polymer material. The protective layer SR can have at least one opening for connection between the terminals of the semiconductor device and the solder pads of the circuit board. For example, in an embodiment, the protective layer SR can be formed of a resin and a filler used as a reinforcing member.

[0092] A protective layer SR can be disposed on the laminated insulating portions 112 and 113. Furthermore, the protective layer SR can include various fillers. Specifically, the protective layer SR can include a first protective layer SR1 disposed on the upper laminated insulating portion 112 and a second protective layer SR2 disposed below the lower laminated insulating portion 113. Considering the warpage of the circuit board, the first protective layer SR1 and the second protective layer SR2 can be spaced apart from each other in the stacking direction and can have different thicknesses. In the following description, the protective layer will be based on the first protective layer SR1.

[0093] In addition, the circuit board 100 may also include components located on its outer surface.

[0094] As shown in the figure, the cover layer CV can be located on the outermost side of the circuit board 100. Furthermore, the cover layer CV can cover the outer surface of the glass core layer 111 and the outer surfaces of the multilayer insulating portions 112 and 113. Additionally, the cover layer CV can also cover the outer surface of the protective layer SR. With this configuration, the strength of the glass core layer can be improved after the glass core layer 111 is chamfered, and the outer surface of the glass core layer can be easily protected. Furthermore, the coating layer can suppress separation between the multilayer insulating portions and the glass core layer, pattern lifting, damage, etc. Therefore, the reliability of the circuit board can be improved.

[0095] A joining portion (not shown) may be provided on the protective layer SR. For example, the joining portion (not shown) may be provided on the upper surface of the protective layer SR. The joining portion (not shown) may be located outside the laminated line portions 122 and 123. For example, the joining portion (not shown) may be located above the laminated line portions 122 and 123 relative to the upper laminated insulation portion 112. Furthermore, the joining portion (not shown) may include a protrusion provided on the upper surface of the protective layer SR and a through-hole region passing through the protective layer SR. In embodiments, each of the through-hole region and the protrusion may include a plurality of protrusions or raised portions projecting toward the adjacent protective layer SR. For example, on the first protective layer SR1, the through-hole region and the protrusion may include a plurality of protrusions (or raised portions) projecting toward the first protective layer SR1.

[0096] Furthermore, the joint (not shown) may include multiple metal layers, or additional metal layers may be disposed on the joint. This can further improve the durability and reliability of the joint (not shown). For example, the joint or metal layer may include at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or combinations thereof. Therefore, the bonding strength between the metal layer and the joint (not shown) can be improved, the corrosion resistance and durability of the joint (not shown) can be enhanced, and the loss of electrical signals can be minimized. The metal layer can be formed on the joint (not shown) using deposition, electroplating, or other methods with various metals.

[0097] Furthermore, semiconductor devices can be disposed above the upper laminated insulating portion 112. The semiconductor devices can be electrically connected to the second line portion, which is a finely patterned portion, etc. The circuit board can be configured to have a high line density for signal connections to the semiconductor devices. Furthermore, the second line portion, as a finely patterned portion, can provide signal paths for signal connections between semiconductor devices, or can provide signal connections (e.g., to the lower substrate) for each semiconductor device. Therefore, unnecessary increases in the size of the semiconductor devices can be prevented, thereby increasing the yield of the semiconductor devices.

[0098] Furthermore, circuit boards can be classified as packaging substrates or interposers based on their function. Packaging substrates are used to mount semiconductor devices and / or interposers. Due to increasing data volume, circuit board yield can significantly decrease due to increases in circuit board area or the number of stacked insulating layers. Therefore, by separating the circuit board into interposers and packaging substrates, the yield of circuit boards with a large number of stacked layers can be improved. Additionally, as the density of semiconductor device terminals increases, it may be difficult to implement pads on the packaging substrate with areas corresponding to the semiconductor device terminals. Therefore, the interposer can act as a buffer between the pad size of the packaging substrate and the fine pattern size of the semiconductor device terminals.

[0099] As described above, depending on the configuration of the insulating layer, the packaging substrate and the interposer can each be classified as a core substrate or a coreless substrate. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may be a layer including reinforcing members in the stacked insulating layers. The reinforcing members may be glass fiber. The core layer may be set to be thicker than other insulating layers to prevent warping of the circuit board during processing. However, the core layer may cause problems such as voltage drop and signal loss, or may make it difficult to achieve thinning. Therefore, depending on the application, a coreless substrate in which the insulating layer of the circuit board does not include a core layer can be used.

[0100] Further reference Figure 3In the circuit board 100 according to the embodiment, the outermost surface IS1 of the glass core layer 111 may be positioned obliquely relative to the outermost surface IS2 of the multilayer insulating portion. As described above, the upper multilayer insulating portion 112 may be located on the upper surface US of the glass core layer 111, and the lower multilayer insulating portion 113 may be located on the lower surface BS of the glass core layer 111. Hereinafter, the multilayer insulating portions will be described based on the upper multilayer insulating portion.

[0101] Furthermore, in this embodiment, the tilt angle of the outermost surface IS1 of the glass core layer 111 may be different from the tilt angle of the outermost surface IS2 of the laminated insulating portion 112. That is, the first tilt angle θ1 may be different from the second tilt angle θ2. The first tilt angle θ1 may be the tilt angle of the outermost surface IS2 of the laminated insulating portion 112 relative to the upper surface US of the glass core layer 111. Furthermore, the second tilt angle θ2 may be the tilt angle of the outermost surface IS1 of the glass core layer 111 relative to the upper surface US1 of the glass core layer 111. The second tilt angle θ2 may be the tilt angle formed between a portion of the outermost surface IS1 of the glass core layer 111 and the upper surface US of the glass core layer 111. For example, the second tilt angle θ2 may be the tilt angle formed in the stacking direction (Y-axis direction) between the outermost surface IS1 and the upper surface US of the glass core layer 111 at the central portion of the outermost surface IS1 of the glass core layer 111. In the figures, the tilt angles are illustrated using virtual surfaces VUS1 and VUS2 parallel to the upper surface US of the glass core layer 111. Furthermore, the tilt angle can be measured based on the inside of the circuit board rather than its outside.

[0102] Furthermore, due to the chamfering of the glass core layer 111, the tilt angles (e.g., a first tilt angle θ1 and a second tilt angle θ2) of the outermost surface IS1 of the glass core layer 111 and the outermost surface IS2 of the laminated insulation portion 112 can be different from each other. Therefore, chipping of the glass core layer 111 (chipped portions) can be easily removed, thereby further improving the strength of the glass core layer 111. Residual stress can be reduced, thereby preventing glass core layer fracture. Furthermore, damage to the upper laminated insulation portion 112 caused by the chamfering can be further suppressed. Therefore, the reliability of the circuit board can be further improved.

[0103] Furthermore, in this embodiment, the first tilt angle θ1 can be smaller than the second tilt angle θ2. With this configuration, during chamfering, the laminated insulating portion 112 that contacts the upper surface US of the glass core layer 111 can be located further away from the chamfering equipment or machine. Therefore, damage to the laminated insulating portion 112 can be further prevented. Additionally, the area of ​​the glass core layer 111 from which chipped portions are removed by chamfering can be increased, and the glass core layer 111 can maintain structural symmetry even after chamfering. In other words, by suppressing the formation of shapes such as grooves in the outermost surface IS1 of the glass core layer 111, the degradation of mechanical strength can be reduced, torsional deformation can be suppressed, and thermal imbalance problems can also be resolved.

[0104] Furthermore, the outer surface IS1 of the glass core layer 111 may include a first surface IS1a and a second surface IS1b. The first surface IS1a may be the outermost surface of the outer surface IS1 of the glass core layer. Furthermore, the second surface IS1b may be the outer surface located between the first surface IS1a and the upper surface US (or the lower surface BS). Therefore, the second surface IS1b may be in contact with the upper surface US or the lower surface BS of the glass core layer 111. For example, the second surface IS1b may be parallel to and coplanar with the upper surface US or the lower surface BS of the glass core layer 111.

[0105] Furthermore, the first surface IS1a may contact the second surface IS1b. The first surface IS1a may deviate from the second surface IS1b in the horizontal direction (X-axis direction). That is, the first surface IS1a and the second surface IS1b may not overlap in the horizontal direction (X-axis direction).

[0106] Furthermore, the first surface IS1a and the second surface IS1b may be components of the outer surface IS1 of the glass core layer 111, and may be located between the upper surface US and the lower surface BS of the glass core layer 111.

[0107] In this embodiment, the first surface IS1a may not be parallel to the second surface IS1b. That is, the first surface IS1a may not be coplanar with the second surface IS1b, and may be inclined at a predetermined angle relative to the second surface IS1b.

[0108] In other words, the angle formed between the first surface IS1a and the virtual surface VUS2 can correspond to the second tilt angle θ2. The angle formed between the second surface IS1b and the virtual surface VUS1 can be different from the second tilt angle θ2. Furthermore, the angle formed between the second surface IS1b and the virtual surface VUS1 can be a third tilt angle θ3. In other words, the third tilt angle θ3 can be the tilt angle of the second surface IS1b relative to the upper surface US of the glass core layer 111.

[0109] Furthermore, the third tilt angle θ3 according to the embodiment can be equal to the first tilt angle θ1. In other words, in the circuit board according to the embodiment, at least a portion of the outer surface IS of the glass core layer 111 (e.g., the second surface IS1b) can be coplanar with the outer surface IS2 of the multilayer insulating portion 112. Furthermore, the second surface IS1b can contact and be positioned parallel to the outer surface IS2 of the multilayer insulating portion 112.

[0110] This configuration allows for the simultaneous application of the same cutting or chamfering process to both the multilayer insulating portion 112 and the glass core layer 111. Consequently, stress can be uniformly distributed at the interface between the multilayer insulating portion 112 and the glass core layer 111, or separation between them can be suppressed. This further improves the reliability of the circuit board.

[0111] Furthermore, the third tilt angle θ3 according to the embodiment may be different from the second tilt angle θ2. In other words, in the circuit board according to the embodiment, one region and another region of the outer surface IS of the glass core layer 111 may not form surfaces parallel to each other.

[0112] With this configuration, although the laminated insulation portion 112 is located on the upper surface US or the lower surface BS of the glass core layer 111, the laminated insulation portion 112 can be spaced as far as possible from the first surface IS1a of the glass core layer 111 in the horizontal direction (X-axis direction).

[0113] Furthermore, at least a portion of the outer surface of the laminated insulation portion 112 may be spaced apart from the second surface IS1b in the horizontal direction (X-axis direction).

[0114] This configuration further suppresses damage to the upper laminated insulation caused by chamfering. Therefore, the reliability of the circuit board can be further improved.

[0115] Furthermore, the thickness T1 of the first surface IS1a can be different from or equal to the thickness T2 of the second surface IS1b. The thickness T1 of the first surface IS1a can be the length of the first surface IS1a in the vertical direction (Y-axis direction). Similarly, the thickness T2 of the second surface IS1b can be the length of the second surface IS1b in the vertical direction (Y-axis direction). In this embodiment, the thickness T1 of the first surface IS1a can be different from the thickness T2 of the second surface IS1b. Furthermore, the thickness T1 of the first surface IS1a can be greater than the thickness T2 of the second surface IS1b.

[0116] This configuration allows for a relative increase in the area (or volume) of the central portion of the glass core layer. Therefore, the mechanical strength of the circuit board can be easily maintained. Furthermore, stress concentration at the central portion of the glass core layer can be reduced.

[0117] Furthermore, the cover layer CV can be disposed on the outer side of the outer surface IS1 of the glass core layer 111. Additionally, the cover layer CV can also be disposed on the outer surface IS2 of the multilayer insulating portion. Therefore, the outer surface of the circuit board can be easily protected. In particular, it can prevent the formation of cracks or the like on the outer surface of the glass core layer 111 located inside the circuit board, thereby improving the reliability of the circuit board.

[0118] Furthermore, the cover layer CV may extend inward beyond the outer surface IS1 of the laminated insulation portion 112. For example, the cover layer CV may be located on the exposed upper (or lower) surface of the laminated insulation portion.

[0119] In addition, the capping layer CV can also be located on the outer surface of the protective layer SR. The capping layer CV can be located on the exposed upper (or lower) surface of the protective layer.

[0120] Furthermore, as described above, the upper laminated insulating portion 112 may include multiple layers. For example, the upper laminated insulating portion 112 may include a first upper laminated insulating portion 112a and a second upper laminated insulating portion 112b. The first upper laminated insulating portion 112a and the second upper laminated insulating portion 112b may be stacked sequentially in the stacking direction. Furthermore, the first-1 tilt angle θ1a of the outermost surface of the first upper laminated insulating portion 112a and the first-2 tilt angle θ1b of the second upper laminated insulating portion 112b may be equal to or different from each other. For example, as shown, the first-1 tilt angle θ1a of the outermost surface of the first upper laminated insulating portion 112a may be different from the first-2 tilt angle θ1b of the second upper laminated insulating portion 112b. Furthermore, the first-1 tilt angle θ1a of the outermost surface of the first upper laminated insulating portion 112a may be greater than the first-2 tilt angle θ1b of the second upper laminated insulating portion 112b. Furthermore, the first-1 tilt angle θ1a of the outermost surface of the first upper laminated insulation portion 112a can be smaller than the first-2 tilt angle θ1b of the second upper laminated insulation portion 112b.

[0121] Furthermore, in the modified example, the tilt angle of the outer surface of at least some layers of the upper laminated insulation portion 112 may correspond to the second tilt angle.

[0122] Further reference Figure 4The first tilt angle θ1 can be the tilt angle of the outer surface IS2 of the laminated insulating portion relative to the upper surface US2 of the glass core layer 111. Furthermore, the second tilt angle θ2 can be the tilt angle of the outermost surface IS1 of the glass core layer 111 relative to the upper surface US of the glass core layer 111. Additionally, the third tilt angle θ3 can be the angle formed between the second surface IS1b and the virtual surface, or the tilt angle of the second surface IS1b relative to the upper surface US of the glass core layer 111.

[0123] In another example, the third tilt angle θ3 may differ from the first tilt angle θ1. In other words, in the circuit board according to the embodiment, the outer surface IS of the glass core layer 111 that contacts the multilayer insulating portion may not have a surface parallel to the outer surface IS2 of the multilayer insulating portion 112. That is, the outer surface IS of the glass core layer 111 may be coplanar with the outer surface IS2 of the multilayer insulating portion 112. For example, the third tilt angle θ3 may be greater than the first tilt angle θ1. With this configuration, the maximum possible separation distance can be ensured between the outermost surface of the glass core layer 111 and the multilayer insulating portion. Therefore, damage caused by chamfering can be further suppressed, while the strength of the glass core layer is improved by chamfering. Therefore, the reliability of the circuit board can be further improved.

[0124] Further reference Figure 5 In the glass core layer 111, the thickness can vary depending on the region. For example, the thickness T1 of the first surface IS1a can be different from the thickness T2 of the second surface IS1b. In another example, the thickness T1 of the first surface IS1a can be greater than the thickness T2 of the second surface IS1b.

[0125] Furthermore, the thickness of the second surface IS1b can vary depending on the position of the second surface. For example, in the glass core layer 111, the thickness T2a of the second surface in contact with the upper surface US can be different from the thickness T2b of the second surface in contact with the lower surface BS. The thickness T2a of the second surface in contact with the upper surface US of the glass core layer 111 can be less than or greater than the thickness T2b of the second surface in contact with the lower surface BS.

[0126] With this configuration, the area (or volume) of the central portion of the glass core layer can be relatively increased. For example, the thickness of each region of the second surface can be adjusted according to the circuit pattern provided above or below the glass core layer 111, the thickness of the laminated insulating portion, etc. Therefore, stress concentration can be reduced, thermal expansion can be easily controlled, the mechanical strength of the circuit board can be easily maintained, and thus the reliability of the substrate can be improved.

[0127] Furthermore, corresponding to this thickness difference, the second surface can have different tilt angles depending on its location. Further reference Figure 6 According to another example, the tilt angle in each region of the outer surface IS1 of the glass core layer 111 can be different. In the circuit board, one region and another region of the outer surface IS1 of the glass core layer 111 may not form surfaces parallel to each other. Therefore, the third tilt angle θ3 can be different from the second tilt angle θ2.

[0128] Furthermore, the third tilt angle θ3 in the second surface contacting the upper surface US and the third tilt angle θ3' in the second surface contacting the lower surface BS can also be different from each other. For example, the third tilt angle θ3 in the second surface contacting the upper surface US can be less than or equal to the third tilt angle θ3' in the second surface contacting the lower surface BS.

[0129] Furthermore, the first tilt angle θ1 can be equal to the third tilt angle θ3. However, the first tilt angle θ1 of the outer surface of the upper laminated insulation portion 112 can be different from the first tilt angle θ1′ of the outer surface of the lower laminated insulation portion 113.

[0130] Furthermore, the second tilt angles θ2 and θ2′ on the outermost surfaces IS2 and IS2′ of the laminated insulating portion 112 that contact the upper surface US and the lower surface BS can be different from each other.

[0131] The fourth tilt angle θ4 of the outer surface of the first protective layer SR1 can be equal to the first tilt angle θ1. Furthermore, the tilt angle can vary depending on the location of the protective layer.

[0132] For example, the fourth tilt angle θ4 of the outer surface of the first protective layer SR1 may be different from the fourth tilt angle θ4' of the outer surface of the second protective layer SR2.

[0133] With this configuration, the separation distance between the upper laminated insulation portion and the outermost surface of the glass core layer 111 can differ from the separation distance between the lower laminated insulation portion and the outermost surface of the glass core layer. This can also be applied to protective layers disposed on the laminated insulation portions. Furthermore, the angle of each region of the second surface can be adjusted according to the circuit pattern in the upper or lower laminated insulation portion, the thickness of the laminated insulation portion, etc. Therefore, stress and thermal expansion can be easily controlled, thereby improving the reliability of the circuit board.

[0134] Further reference Figure 7The thickness T1 of the first surface IS1a can be different from the thickness T2 of the second surface IS1b. In this embodiment, the thickness T1 of the first surface IS1a can be less than the thickness T2 of the second surface IS1b. Corresponding to the thickness of the second surface IS1b, the separation distance between the laminated insulating portion and the first surface IS1a, which is the outermost surface of the glass core layer 111, can be increased. Therefore, the separation distance between the chamfering device or chamfering machine and the laminated insulating portion can be easily ensured during chamfering. Therefore, damage to the laminated insulating portion can be further prevented.

[0135] Figures 8 to 15 This is a view illustrating a method of manufacturing a circuit board according to an embodiment.

[0136] The same reference numerals refer to the same elements described above, and repeated descriptions of the same elements will be omitted; only the differences will be described.

[0137] Furthermore, the circuit board according to the embodiment can correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board can include multiple unit circuit boards. The mother circuit board can be divided into multiple unit circuit boards along a sawing line. To form the mother circuit board, a glass layer can be first formed. The glass layer (or glass core layer) can be manufactured by various methods. Furthermore, the following description will be based on the manufacturing of the unit circuit boards.

[0138] A method for manufacturing a circuit board according to an embodiment may include: preparing a glass core layer; forming a first through-hole in the glass core layer; forming a core electrode portion on the upper and lower surfaces of the glass core layer and on the inner surface of the first through-hole; forming an upper laminated insulation portion and a lower laminated insulation portion; forming a laminated line portion; forming a protective layer, etc.; performing cutting; chamfering the outer surface of the cut circuit board; and forming a protective film or cover layer.

[0139] Reference Figure 8 In the method for manufacturing a glass core layer (or core substrate) in a circuit board according to the embodiment, a glass core layer 111 made of glass may be provided first. The glass core layer 111 may correspond to the glass core layer or core layer described above.

[0140] Reference Figure 9 Then, a first through-hole 111h can be formed in the glass core layer 111. The first through-hole 111h can correspond to the aforementioned through hole. The first through-hole 111h can be formed by etching both surfaces of the glass core layer 111. For example, a through-hole electrode can be formed in a via hole or through hole in the glass layer. For example, the first through-hole 111h can be formed by various etching methods, such as photolithography using a photomask or laser processing.

[0141] refer to Figure 10 The seed layer 121′ of the core electrode portion can be formed on one surface (upper or lower surface) of the glass core layer 111. For example, the seed layer 121′ of the core electrode portion can be formed on the upper and lower surfaces of the glass core layer 111 and on the inner wall of the first through hole 111h. For example, the seed layer 121′ of the core electrode portion can be formed using dry processes (such as sputtering) or wet processes. In particular, spin coating, diffusion coating, spray coating, dip coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., can be used.

[0142] refer to Figure 11 The deposition can be performed on the seed layer 121' of the core electrode portion. Various methods can be used to perform the deposition on the seed layer 121' of the core electrode portion. Therefore, the core electrode portion 121 can be formed.

[0143] For example, seed layers and coating layers can be formed by sputtering. This sputtering can be a technique in which an inert element, such as argon, collides with a target (metal plate), causing metal molecules to be ejected and then a film deposited on the surface. When a direct current is applied to the target while an inert gas is supplied as the sputtering gas to a chamber in which a vacuum is maintained, plasma can be generated between the substrate to be deposited and the target. Furthermore, in the plasma, the inert gas can be ionized into positive ions by a high-output direct current source. In this case, the positive ions of the inert gas can be accelerated towards the cathode by the direct current source and can collide with the surface of the target. The target material colliding in this way can exchange momentum due to perfectly elastic atomic collisions and can be ejected outward from the surface. When ions collide with kinetic energy greater than the interatomic bonding energy of the material, atoms in the material lattice can be displaced to another position through ion collisions, and surface escape of atoms can occur at this time. This phenomenon is called sputtering. Besides sputtering, various coating methods described above can be used. Therefore, core electrode portions can be formed.

[0144] Furthermore, as described above, the core electrode portion can be formed from a first layer and a second layer. The core electrode portion can be recrystallized by heat treatment methods or the like that satisfying conditions 2 and 3 as described above. Therefore, the core electrode portion can have the density of crystal orientation planes and the average grain size as described above.

[0145] Reference Figure 12After forming the core electrode portion 121 on the glass core layer 111, an upper stacked insulating portion 112, a lower stacked insulating portion 113, and so on can also be formed. Similarly, through-holes can be formed in each insulating layer, and stacked line portions can be formed in each insulating layer. The stacked line portions can be formed by printed circuit board manufacturing processes, such as additive processes, subtractive processes, modified semi-additive processes (MSAP), or semi-additive processes (SAP).

[0146] Furthermore, a protective layer may be formed on the laminated insulating portions 112 and 113. For example, the protective layer may be formed above the upper laminated insulating portion 112 and / or below the lower laminated insulating portion 113. Additionally, an opening region for a conductive member may be formed in the protective layer.

[0147] Furthermore, in some areas of the glass core layer 111, the laminated insulating portions 112 and 113 and the protective layer may not be formed. Additionally, dicing may be performed on the exposed glass core layer 111.

[0148] First, the circuit board can be manufactured into individual units by cutting a large panel. Before cutting, defects in the panel (e.g., scratches, open circuits, etc.) can be inspected.

[0149] In addition, cutting can be performed to manufacture individual circuit board units. In this case, cutting can be performed using various methods. For example, cutting can be performed using various cutting methods such as mechanical dicing, laser dicing, and etching dicing.

[0150] As shown, cutting can be performed at various angles. For example, cutting can be performed in a direction perpendicular to or not perpendicular to the upper surface of the glass core layer. Therefore, the outer surface of each circuit board separated into individual units by cutting can have a shape that combines the outer surface described according to various embodiments of the circuit board.

[0151] refer to Figure 13Chamfering can be performed after cutting. Chamfering can be performed on the outer surface of the circuit board. Chamfering can include mechanical chamfering, chemical chamfering, thermal chamfering, waterjet chamfering, ultrasonic chamfering, etc. However, chamfering can also be referred to as "edge treatment," etc.

[0152] In this example, a chamfering apparatus HE can be used to perform hot chamfering, allowing chamfering to be performed quickly on the outer surface of the glass core layer 111 without causing mechanical cracks. Furthermore, through precision machining, cracks such as microcracks formed on the outer surface of the glass core layer 111 can be easily removed.

[0153] Reference Figure 14 and 15 A protective film can be formed on the outer surface of the laminated insulating portion (protective layer) (see...). Figure 19 (etc.). The protective film may be spaced apart from the outermost surface of the glass core layer 111 in the horizontal direction.

[0154] In addition, a capping layer CV can be formed. The capping layer CV can be disposed on the outer surface of the glass core layer 111 and the laminated insulating portions 112 and 113.

[0155] After that, chips and other components can be mounted on the circuit board, and additional processes such as molding can be performed.

[0156] Furthermore, the structures according to the various embodiments and modified examples described above can also be equivalently applied to the circuit board according to this embodiment.

[0157] Figure 16 This is a cross-sectional view of the circuit board according to the second embodiment, and Figure 17 yes Figure 16 An enlarged view of part K2.

[0158] refer to Figure 16 and 17 According to the second embodiment, the circuit board 100A may include an insulating portion 110 and an electrode portion 120. In this embodiment, the insulating portion 110 may have a structure with multiple stacked insulating layers. The electrode portion 120 may be configured to be embedded in each insulating layer of the multiple insulating portions 110 and may be used to transmit signals and / or power from a main circuit board (not shown) to a semiconductor device. Furthermore, the circuit board 100 may also include a protective layer, a bonding layer, a cover layer, etc., disposed on the electrode portion 120.

[0159] Furthermore, in addition to the content described below, the configurations described in the various embodiments of the present invention can be applied equivalently. Furthermore, in addition to the content described below, the structures based on the various modified examples described above can also be applied equivalently to this embodiment.

[0160] In this embodiment, the outermost surface IS1 of the glass core layer 111 can be spaced apart from the outermost surface IS2 of the laminated insulating portion 112 by a predetermined distance gap1 or gap2.

[0161] Therefore, at least a portion of the upper surface US and the lower surface BS of the glass core layer 111 can be exposed. That is, the upper surface US of the glass core layer 111 may include an exposed surface OA1. Similarly, the lower surface BS of the glass core layer 111 may include an exposed surface OA2. Furthermore, at least a portion of the upper surface US and the lower surface BS of the glass core layer 111 may not contact the laminated insulating portions 112 and 113. In other words, at least a portion of the upper surface US and the lower surface BS of the glass core layer 111 may not overlap with the laminated insulating portions 112 and 113 in the vertical direction (Y-axis direction).

[0162] This can also be applied to the protective layer. Furthermore, due to the chamfer, the outermost surface IS1 of the glass core layer 111 can have a circular or curved structure. Additionally, the second tilt angle θ2 of the outermost surface IS1 of the glass core layer 111 can differ from the first tilt angle θ1 of the outer surfaces IS2 of the laminated insulating portions 112 and 113.

[0163] Furthermore, the first separation distance gap1 between the upper laminated insulating portion 112 and the outermost surface IS1 of the glass core layer 111 may be equal to or different from the second separation distance gap2 between the lower laminated insulating portion 113 and the outermost surface IS1 of the glass core layer 111.

[0164] For example, the first separation distance gap1 between the upper laminated insulation portion 112 and the outermost surface IS1 of the glass core layer 111 may be different from the second separation distance gap2 between the lower laminated insulation portion 113 and the outermost surface IS1 of the glass core layer 111.

[0165] The position and area of ​​the upper laminated insulating portion 112 and the lower laminated insulating portion 113 can be controlled relative to the glass core layer 111. Therefore, stress and thermal expansion can be easily controlled, thereby improving the reliability of the circuit board.

[0166] Figure 18 This is a cross-sectional view of the circuit board according to the third embodiment. Figure 19 yes Figure 18 An enlarged view of part K3, and Figure 20It shows Figure 19 Another example.

[0167] refer to Figures 18 to 20 According to the third embodiment, the circuit board 100B may include an insulating portion 110 and an electrode portion 120. In this embodiment, the insulating portion 110 may have a structure with multiple stacked insulating layers. The electrode portion 120 may be configured to be embedded in each insulating layer of the plurality of insulating portions 110 and may be used to transmit signals and / or power from a main circuit board (not shown) to a semiconductor device. Furthermore, the circuit board 100 may also include a protective layer, a bonding layer, a cover layer, etc., disposed on the electrode portion 120.

[0168] Furthermore, in addition to the content described below, the configurations described in the various embodiments of the present invention can be applied equivalently. Furthermore, in addition to the content described below, the structures based on the various modified examples described above can also be applied equivalently to this embodiment.

[0169] In this example, the circuit board may also include protective films CT1 and CT2, which are spaced apart from the outermost surface of the glass core layer 111 and disposed on the outer surfaces of the laminated insulating portions 112 and 113.

[0170] Protective films CT1 and CT2 can also be located on the outer surface of the protective layer. That is, protective films CT1 and CT2 can be located on the outer surface of the first protective layer and the outer surface of the second protective layer.

[0171] The outermost surface of the glass core layer 111 can be configured to be spaced apart from the outermost surface of the laminated insulating portion 112. Therefore, at least a portion of the upper surface US and the lower surface BS of the glass core layer 111 can be exposed. The structures of the glass core layer and the laminated insulating portion in the second embodiment described above can be applied equivalently. Therefore, the upper surface US of the glass core layer 111 can include an exposed surface. Furthermore, the lower surface BS of the glass core layer 111 can include an exposed surface corresponding to the upper surface.

[0172] Furthermore, at least a portion of the upper surface US and lower surface BS of the glass core layer 111 may not contact the laminated insulating portions 112 and 113. In other words, at least a portion of the upper surface US and lower surface BS of the glass core layer 111 may not overlap with the laminated insulating portions 112 and 113 in the vertical direction (Y-axis direction). The same structure can also be applied to the protective layer.

[0173] Furthermore, protective films CT1 and CT2 may at least partially overlap with the laminated insulating portions 112 and 113 or the protective layers SR1 and Sr2 in the horizontal direction. Furthermore, protective films CT1 and CT2 may overlap with the glass core layer 111 in the vertical direction. Furthermore, protective films CT1 and CT2 may be configured to be spaced apart from the outermost surface of the glass core layer 111 in the horizontal direction.

[0174] The protective films CT1 and CT2 can suppress damage to the laminated insulation and protective layer caused by chamfering equipment, etc.

[0175] Furthermore, the thickness of the cover layer CV can vary depending on its location. For example, the thickness Taa of the cover layer CV at the upper surface of the first protective layer SR1 and the thickness Tab of the cover layer CV at the exposed surface OA1 exposed at the upper surface US can be different from each other. Considering reliability and other factors, the thickness Tab of the cover layer CV at the exposed surface OA1 of the upper surface US can be greater than the thickness Taa of the cover layer CV at the upper surface of the first protective layer SR1.

[0176] Furthermore, in another example, the cover layer CV can be located on the outermost side of the circuit board 100, while the thicknesses Taa and Tab remain constant. For example, the cover layer CV can be disposed along the outer surface of the glass core layer 111, its exposed upper surface, and the outer surface of the laminated insulating portion and / or protective layer, and can have a curved structure corresponding to the shape of the outer surfaces of these components. That is, the cover layer CV can have a shape corresponding to the topology of the components it contacts. For example, the thickness Taa of the cover layer CV at the upper surface of the first protective layer SR1 can be the same as the thickness Tab of the cover layer CV at the exposed surface OA1 of the upper surface US.

[0177] Figure 21 This is a cross-sectional view showing a semiconductor package according to the first embodiment. Figure 22 This is a cross-sectional view showing a semiconductor package according to the second embodiment. Figure 23 This is a cross-sectional view showing a semiconductor package according to a third embodiment, and Figure 24 This is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0178] In the various semiconductor packages described below, the circuit board described above may be located in a portion of the semiconductor package or may correspond to a single substrate.

[0179] Reference Figure 21 The semiconductor package according to the first embodiment may include a first substrate 1100, a second substrate 1200, and a semiconductor device 1300.

[0180] The first substrate 1100 may be or include a "packaging substrate" or a "circuit board". For example, the first substrate 1100 may provide a space in which at least one external substrate can be coupled to the first substrate 1100. The external substrate may be a second substrate 1200 coupled to the first substrate 1100. In addition, the external substrate may be a motherboard included in an electronic device and coupled to the lower part of the first substrate 1100.

[0181] Furthermore, although not shown in the figure, the first substrate 1100 can provide space for mounting at least one semiconductor device therein.

[0182] The first substrate 1100 may include at least one insulating layer and an electrode portion disposed in the at least one insulating layer.

[0183] The second substrate 1200 can be disposed on the first substrate 1100.

[0184] The second substrate 1200 may be an interposer. For example, the second substrate 1200 may provide space for mounting at least one semiconductor device. The second substrate 1200 may be connected to one or more semiconductor devices 1300. For example, the second substrate 1200 may provide space for mounting a first semiconductor device 1310 and a second semiconductor device 1320. The second substrate 1200 may be electrically connected between the first semiconductor device 1310 and the second semiconductor device 1320, and may be electrically connected between the first semiconductor device 1310 and the second semiconductor device 1320 and the first substrate 1100. That is, the second substrate 1200 may be used to provide horizontal electrical interconnections between multiple semiconductor devices and vertical electrical interconnections between semiconductor devices and a package substrate.

[0185] Furthermore, although two semiconductor devices 1310 and 1320 are shown as disposed on the second substrate 1200 in the above example, the present invention is not limited thereto. For example, one semiconductor device may be disposed on the second substrate 1200, or alternatively, three or more semiconductor devices may be disposed thereon.

[0186] The second substrate 1200 may be disposed between one or more semiconductor devices 1300 and the first substrate 1100.

[0187] In one embodiment, the second substrate 1200 may be an active interposer used as a semiconductor device. When the second substrate 1200 is used as a semiconductor device, the semiconductor package according to the embodiment may have a structure in which multiple logic chips are vertically stacked on the first substrate 1100, and may provide the functionality of multiple logic chips. Providing the functionality of logic chips may mean providing the functionality of both active and passive devices. Unlike passive devices, active devices may have nonlinear current-voltage characteristics, and the active interposer may provide the functionality of active devices. Furthermore, the active interposer may perform the functionality of the corresponding logic chip, and may also transmit signals between the second logic chip disposed thereon and the first substrate 1100.

[0188] According to another embodiment, the second substrate 1200 may be a passive interposer. For example, the second substrate 1200 may be used to relay signals between the semiconductor device 1300 and the first substrate 1100, and may provide the functions of passive devices such as resistors, capacitors, and inductors. For example, due to 5G communication, the Internet of Things (IoT), improved image quality, and increased communication speed, the number of terminals in the semiconductor device 1300 has gradually increased. That is, as the number of terminals provided in the semiconductor device 1300 increases, the width of each terminal and the spacing between multiple terminals decrease. In this case, the first substrate 1100 may be connected to the motherboard of the electronic device. Therefore, in order to make the electrodes disposed in the first substrate 1100 have a width and spacing suitable for connection to each of the semiconductor device 1300 and the motherboard, it may be necessary to increase the thickness of the first substrate 1100, or the layer structure of the first substrate 1100 may become complex. Therefore, in the first embodiment, the second substrate 1200 may be disposed between the first substrate 1100 and the semiconductor device 1300. In addition, the second substrate 1200 may include electrodes having fine widths and spacings corresponding to the terminals of the semiconductor device 1300.

[0189] Semiconductor device 1300 can be a logic chip, a memory chip, etc. A logic chip can be a CPU, a GPU, etc. A memory chip can be a stacked memory such as HBM.

[0190] Meanwhile, the semiconductor package according to the first embodiment may include a connection portion.

[0191] For example, a semiconductor package may include a first connection portion 1410 disposed between a first substrate 1100 and a second substrate 1200. The first connection portion 1410 may couple the second substrate 1200 to the first substrate 1100 and electrically connect the first substrate 1100 and the second substrate 1200.

[0192] For example, a semiconductor package may include a second connection portion 1420 disposed between a second substrate 1200 and a semiconductor device 1300. The second connection portion 1420 may couple the semiconductor device 1300 to the second substrate 1200 and electrically connect the semiconductor device 1300 between the second substrate 1200 and the semiconductor device 1300.

[0193] The semiconductor package may include a third connection portion 1430 disposed on the lower surface of the first substrate 1100. The third connection portion 1430 may couple the first substrate 1100 to a motherboard and electrically connect the first substrate 1100 and the motherboard.

[0194] In this configuration, the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 can electrically connect multiple components using at least one joining method selected from wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 are used to electrically connect multiple components, when direct metal-to-metal bonding is used, each connection portion can be understood as an electrical connection portion rather than a separate solder or wire.

[0195] Wire bonding methods can be methods that electrically connect multiple components using conductive wires made of materials such as gold (Au). Alternatively, solder bonding methods can use materials including at least one of tin (Sn), silver (Ag), and copper (Cu) to electrically connect multiple components. Furthermore, direct metal-to-metal bonding methods can be methods that directly bond multiple components to each other by applying heat and pressure to the metal portions of multiple components to induce recrystallization, without intermediate components such as solder, wires, or conductive adhesives. Additionally, direct metal-to-metal bonding methods can be bonding methods for bonding via a second connection portion 1420. In this case, the second connection portion 1420 can be a solder layer formed between the multiple components through recrystallization.

[0196] Specifically, the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 can be coupled together using a thermal compression bonding method. The thermal compression bonding method can be a method of directly joining multiple components together by applying heat and pressure to the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430.

[0197] In this case, in at least one of the first substrate 1100 and the second substrate 1200, the electrode on which the first connection portion 1410, the second connection portion 1420, or the third connection portion 1430 is provided may include a protrusion protruding outward from the insulating layer away from the corresponding substrate. The protrusion may protrude outward from either the first substrate 1100 or the second substrate 1200.

[0198] A protrusion may be referred to as a bump. A protrusion may also be referred to as a post. A protrusion may also be referred to as a pillar. Preferably, the protrusion may be one of the electrodes of the second substrate 1200, on which a second connection portion 1420 for bonding to the semiconductor device 1300 is provided. That is, as the spacing of the terminals of the semiconductor device 1300 becomes finer, a short circuit may occur between the plurality of second connection portions 1420, each of which is connected to a corresponding one of the plurality of terminals of the semiconductor device 1300 by a conductive adhesive such as solder. Therefore, in an embodiment, thermoforming may be performed to reduce the volume of the second connection portion 1420. Therefore, in an embodiment, the electrode of the second substrate 1200 on which the second connection portion 1420 is provided may include a protrusion to ensure alignment accuracy, diffusion characteristics, and diffusion barrier capability to prevent the diffusion of intermetallic compound (IMC) formed between the protrusion and the conductive adhesive such as solder into the interposer and / or substrate.

[0199] In addition, further reference Figure 21 The semiconductor package according to the first embodiment may further include a connecting member 1210.

[0200] The connection member 1210 may be referred to as a bridging substrate. For example, the connection member 1210 may include a redistribution layer. The connection member 1210 can be used to electrically connect multiple semiconductor devices to each other in the horizontal direction. For example, because the area required by semiconductor devices is typically relatively large, the connection member 1210 may include a redistribution layer. Because semiconductor packages and semiconductor devices have circuit patterns with significantly different widths, circuit patterns for electrical connections are needed to act as a buffer. The buffering function may refer to providing a circuit pattern with an intermediate dimension (e.g., width) between the circuit patterns of the semiconductor package and the circuit patterns of the semiconductor device, and the redistribution layer may include this buffering function.

[0201] In this embodiment, the connecting member 1210 may be an organic bridge. For example, the connecting member 1210 may include an organic material. For example, the connecting member 1210 may include an organic substrate comprising an organic material instead of a silicon substrate. The connecting member 1210 may be embedded in the second substrate 1200.

[0202] Therefore, the second substrate 1200 may include a cavity, and the connecting member 1210 may be disposed in the cavity of the second substrate 1200. The connecting member 1210 may electrically connect a plurality of semiconductor devices disposed on the second substrate 1200 in the horizontal direction.

[0203] refer to Figure 22 The semiconductor package according to the second embodiment may include a second substrate 1200 and a semiconductor device 1300. In this case, compared with the semiconductor package according to the first embodiment, the semiconductor package according to the second embodiment may have a structure that omits the first substrate 1100.

[0204] In other words, the second substrate 1200 according to the second embodiment can be used as both an intermediary layer and a packaging substrate.

[0205] The first connection portion 1410 disposed on the lower surface of the second substrate 1200 can couple the second substrate 1200 to the motherboard of the electronic device.

[0206] Reference Figure 23 The semiconductor package according to the third embodiment may include a first substrate 1100 and a semiconductor device 1300.

[0207] Compared to the semiconductor package according to the first embodiment, the semiconductor package according to the third embodiment may have a structure that omits the second substrate 1200.

[0208] In other words, the first substrate 1100 according to the third embodiment can be used as a packaging substrate and can be electrically connected between the semiconductor device 1300 and the motherboard. For this purpose, the first substrate 1100 may include a connection member 1110 configured to electrically connect between a plurality of semiconductor devices. The connection member 1110 may be an organic bridge electrically connecting the plurality of semiconductor devices.

[0209] Reference Figure 24 Compared to the semiconductor package according to the fourth embodiment, the semiconductor package according to the fourth embodiment may further include a third semiconductor device 1330. For this purpose, a fourth connection portion may be further disposed on one surface of the first substrate 1100.

[0210] As described above, the semiconductor package according to the fourth embodiment may have a structure in which semiconductor devices are mounted on each of the upper and lower sides. In this case, the third semiconductor device 1330 may have a structure in which the third semiconductor device 1330 is disposed on the lower surface of the second substrate 1200 in the aforementioned circuit board or semiconductor package.

[0211] Furthermore, the connecting member 1110 can be embedded in the first substrate 1100. The connecting member 1110 can electrically connect the first semiconductor device 1310 and the second semiconductor device 1320 to each other in the horizontal direction.

[0212] Furthermore, the first substrate 1100 may include a conductive coupling portion 1450. The conductive coupling portion 1450 may protrude from the first substrate 1100 toward the second semiconductor device 1320. The conductive coupling portion 1450 may be referred to as a bump, or alternatively as a pillar. The conductive coupling portion 1450 may be disposed on an electrode located at the uppermost side of the first substrate 1100, and has a structure protruding from the electrode.

[0213] The third semiconductor device 1330 may be disposed on the conductive coupling portion 1450. In this case, the third semiconductor device 1330 can be connected to the first substrate 1100 through the conductive coupling portion 1450. Furthermore, the second connection portion 1420 may be disposed between the first semiconductor device 1310, the second semiconductor device 1320, and the third semiconductor device 1330.

[0214] Therefore, the third semiconductor device 1330 can be electrically connected to the first semiconductor device 1310 and the second semiconductor device 1320 through the second connection portion 1420.

[0215] In other words, the third semiconductor device 1330 can be connected to the first substrate 1100 through the conductive coupling portion 1450, and can also be connected to the first semiconductor device 1310 and the second semiconductor device 1320 through the second connection portion 1420.

[0216] In this configuration, the third semiconductor device 1330 can receive power signals and / or electrical power through the conductive coupling portion 1450. Furthermore, the third semiconductor device 1330 can transmit communication signals to and receive communication signals from the first semiconductor device 1310 and the second semiconductor device 1320 through the second connection portion 1420.

[0217] According to the fourth embodiment, the semiconductor package can provide a power signal and / or electrical power to the third semiconductor device 1330 through the conductive coupling portion 1450, thereby providing sufficient power to drive the third semiconductor device 1330 and achieving smooth control of power supply operation.

[0218] Therefore, the embodiments can improve the driving characteristics of the third semiconductor device 1330. That is, the embodiments can solve the problem of insufficient power supplied to the third semiconductor device 1330. Furthermore, the embodiments can allow at least one of a power supply signal, an electrical signal, and a communication signal for the third semiconductor device 1330 to be provided via different paths through the conductive coupling portion 1450 and the second connection portion 1420. Therefore, the embodiments can solve the problem where the communication signal is degraded due to the power supply signal. For example, the embodiments can minimize the mutual interference between the power supply signal and the communication signal.

[0219] Meanwhile, in the fourth embodiment, the third semiconductor device 1330 may be disposed on the first substrate 1100 in a package-on-package (POP) structure in which multiple package substrates are stacked. For example, the third semiconductor device 1330 may be a memory package including a memory chip. Furthermore, the memory package may be coupled to the conductive coupling portion 1450. In this case, the memory package may not be connected to the first semiconductor device 1310 and the second semiconductor device 1320.

[0220] Furthermore, the semiconductor package according to the modified example may include a first substrate 1100 and a first semiconductor device 1310 and a second semiconductor device 1320 disposed on the first substrate 1100, as in the example above. Additionally, the semiconductor package may also include a first connection portion 1410 disposed between the first substrate 1100 and the first semiconductor device 1310 and the second semiconductor device 1320. That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted from the example above.

[0221] Furthermore, when the circuit board of the present invention, having the above-described features, is used in information technology (IT) equipment or home appliances (such as smartphones, server computers, or televisions), it can reliably perform functions such as signal transmission and / or power supply. For example, when the circuit board having the features of the present invention is used as a semiconductor package, the circuit board can safely protect the semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current, electrical short circuits between terminals supplying the semiconductor chip, and open-circuit faults at the terminals. In addition, when the circuit board is used for signal transmission, it can solve noise problems. Therefore, the circuit board having the above-described features of the present invention can help maintain the stable operation of IT equipment or home appliances, and the entire product and circuit board to which the present invention is applied can achieve functional integration or technological synergy.

[0222] When a circuit board with the features of the present invention described above is used in transportation equipment such as vehicles, the circuit board can solve signal distortion in signals transmitted to the transportation equipment. Alternatively, the circuit board can further improve the reliability of the transportation equipment by safely protecting the semiconductor chips configured to control the transportation equipment from external influences and by solving problems such as leakage current, electrical short circuits between terminals supplying the semiconductor chips, and open circuit faults at the terminals. Therefore, the transportation equipment and circuit board to which the present invention is applied can achieve functional integration or technological synergy.

[0223] When a circuit board with the features of the present invention described above is used in transportation equipment such as vehicles, the circuit board can solve signal distortion in signals transmitted to the transportation equipment. Alternatively, the circuit board can further improve the reliability of the transportation equipment by safely protecting the semiconductor chips configured to control the transportation equipment from external influences and by solving problems such as leakage current, electrical short circuits between terminals supplying the semiconductor chips, and open-circuit faults of the terminals. Therefore, the transportation equipment and circuit board to which the present invention is applied can achieve functional integration or technical linkage with each other.

[0224] The features, structures, effects, etc., described in the above embodiments are included in at least one embodiment, and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc., shown in each embodiment can be combined or modified by those skilled in the art to which the embodiments pertain. Therefore, content related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0225] Although embodiments have been described above, these embodiments are merely examples and are not intended to limit the invention. It will be apparent that those skilled in the art can make various modifications and applications not described above without departing from the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be implemented in a modified form. Furthermore, differences associated with such modifications and applications should be interpreted as including within the scope of the embodiments set forth in the appended claims.

Claims

1. A circuit board, comprising: Glass core layer; The core electrode portion disposed in the glass core layer; The laminated insulation portion disposed on the glass core layer; as well as The laminated wire portion is disposed in the laminated insulation portion. The inclination of the outermost surface of the glass core layer is different from the inclination of the outermost surface of the laminated insulating portion.

2. The circuit board according to claim 1, wherein the first tilt angle of the outermost surface of the laminated insulating portion relative to the upper surface of the glass core layer is different from the second tilt angle of the outermost surface of the glass core layer relative to the upper surface of the glass core layer.

3. The circuit board according to claim 2, wherein the first tilt angle is smaller than the second tilt angle.

4. The circuit board of claim 1, wherein the outer surface of the glass core layer comprises a first surface as the outermost surface and a second surface in contact with the first surface and inclined relative to the first surface.

5. The circuit board according to claim 4, wherein the second surface is in contact with the upper or lower surface of the glass core layer.

6. The circuit board according to claim 4, wherein the length of the first surface in the vertical direction is greater than the length of the second surface in the vertical direction.

7. The circuit board according to claim 4, wherein the second surface is located between the upper and lower surfaces of the glass core layer.

8. The circuit board of claim 4, wherein the second surface contacts and is positioned parallel to the outermost surface of the multilayer insulating portion.

9. The circuit board of claim 4, wherein the third tilt angle of the second surface relative to the upper surface of the glass core layer is equal to the first tilt angle of the outermost surface of the laminated insulating portion relative to the upper surface of the glass core layer.

10. The circuit board of claim 4, wherein the third tilt angle of the second surface relative to the upper surface of the glass core layer is different from the second tilt angle of the outermost surface of the laminated insulating portion relative to the upper surface of the glass core layer.

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