Semiconductor device having an oxide layer section in a device region

Abstract

This application describes a semiconductor device having an oxide layer segment in a barrier layer. In some examples, a semiconductor device (300) includes a semiconductor substrate (302), a channel layer (306) above the semiconductor substrate (302), and a barrier layer (310) above the channel layer (306). The semiconductor device (300) further includes an oxide layer (319) comprising a first segment (316B) formed only in a portion of a drain access region (305C) of the semiconductor device (300).

Description

Technical Field

[0001] The disclosed embodiments generally relate to the field of semiconductor devices and their manufacture. More specifically, but not exclusively, the disclosed embodiments relate to III-N semiconductor devices that include oxide layer segments in the selected device region. Background Technology

[0002] Group III nitride materials (also known as III-N materials) possess a unique combination of physical and electrical properties that have been found beneficial in modern microelectronics and optoelectronics. These properties include a wide bandgap, high saturation drift, high breakdown voltage, high thermal conductivity, and robust chemical and thermal stability. Due to these characteristics, III-N materials are considered highly promising for fabricating high-power, high-frequency transistor structures capable of operating in high-temperature and harsh environments. Despite the rapid and continuous development of III-N nitride devices and their fabrication technologies, several shortcomings remain, necessitating further innovations as outlined below. Summary of the Invention

[0003] The following is a simplified overview to provide a basic understanding of some examples of this disclosure. This summary is not a broad overview of the examples and is neither intended to identify key or essential elements of the examples nor to define their scope. In fact, the main purpose of the summary is to present some concepts of this disclosure in a simplified form as a prelude to the more detailed description that will be presented in subsequent sections.

[0004] Examples of this disclosure relate to III-N semiconductor devices that include oxide segments in a selected device region to increase carrier density and / or mobility in a channel formed in a heterojunction structure. In one example, a semiconductor device is disclosed, particularly comprising: a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region; a channel layer over the semiconductor substrate; a barrier layer over the channel layer; a gate stack including a p-doped III-N (p-III-N) layer in the gate region over the barrier layer; and an oxide layer including a first segment in at least a portion of the drain access region.

[0005] In one example, a semiconductor device is disclosed, which in particular includes: a semiconductor substrate having a source region, a gate region, a drain region and a drain access region between the gate region and the drain region; a channel layer over the semiconductor substrate; a barrier layer over the channel layer; and an oxide layer having a first segment included only in a portion of the drain access region.

[0006] In one example, a method for manufacturing a semiconductor device including an oxide layer segment in a selectable device region is disclosed. The method particularly includes: forming a channel layer over a semiconductor substrate, the semiconductor substrate including a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region; forming a barrier layer over the channel layer; forming a gate stack including a p-doped III-N (p-III-N) layer over the barrier layer in the gate region of the semiconductor substrate; and forming an oxide layer including a first segment in at least a portion of the drain access region of the semiconductor substrate.

[0007] In one example, a method for manufacturing a semiconductor device having an oxide layer segment in a selectable device region is disclosed. The method particularly includes: forming a channel layer over a semiconductor substrate, the semiconductor substrate including a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region; forming a barrier layer over the channel layer; and forming an oxide layer that includes a first segment only in a portion of the drain access region of the semiconductor substrate. Attached Figure Description

[0008] In the accompanying figures, embodiments of the present disclosure are illustrated by way of example rather than limitation. Different references to "a" or "an" embodiment in this disclosure do not necessarily refer to the same embodiment, and such references may mean at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not it is explicitly described, such feature, structure, or characteristic may be combined with other embodiments.

[0009] To illustrate one or more exemplary embodiments of this disclosure, the accompanying drawings are incorporated in and form a part of the specification. Various advantages and features of this disclosure are described in the following detailed description, taken in conjunction with the appended claims and with reference to the accompanying drawings, in which:

[0010] Figure 1A-1D Cross-sectional views of semiconductor devices including EMODE GaN devices according to some examples of the present disclosure at various stages of the process flow, wherein an oxide layer may be provided in or over a barrier layer in a selected region of the device;

[0011] Figures 2A-2E Cross-sectional views of semiconductor devices including EMODE GaN devices according to some examples of the present disclosure at various stages of the process flow, wherein an oxide layer may be provided in or over the barrier layer only in a portion of the drain access region of the GaN device.

[0012] Figures 3A-3HCross-sectional views of semiconductor devices including DMODE GaN devices according to some examples of the present disclosure at various stages of the process flow, wherein an oxide layer may be provided in or above the barrier layer only in selected regions of the GaN device;

[0013] Figures 4A-4H Cross-sectional views of semiconductor devices including DMODE GaN devices according to some examples of this disclosure are depicted at various stages of the process flow, wherein an oxide layer may be provided in or above the barrier layer only in a portion of the drain access region of the GaN device; and

[0014] Figure 5 and 6 This is a flowchart of a method for manufacturing a semiconductor device comprising a GaN device having a segmented oxide layer in a barrier layer, according to some examples of the present disclosure. Detailed Implementation

[0015] Examples of this disclosure are described with reference to the accompanying drawings, in which similar reference numerals are generally used to refer to similar elements. The drawings are not drawn to scale and are provided merely for illustrative purposes. Numerous specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, some examples may be practiced without such specific details. In other instances, well-known subsystems, components, structures, and techniques have not been shown in detail to avoid obscuring the understanding of the examples. Therefore, examples of this disclosure may be practiced without such specific components.

[0016] Additionally, terms such as “coupled” and “connected” and their derivatives may be used in the detailed description below, the appended claims, or both. It should be understood that these terms are not necessarily intended to be synonyms with each other. “Coupled” can be used to indicate that two or more elements (which may or may not be in direct physical or electrical contact with each other) cooperate or interact with each other. “Connected” can be used to indicate the establishment of communication, i.e., a communication relationship, between two or more coupled elements. Furthermore, in one or more instances set forth herein, generally, if an element can be programmed to perform or otherwise structurally arranged to perform a certain function, then the element, component, or module can be configured to perform said function.

[0017] Without limitation, examples of this disclosure are set forth below in the context of improving the performance characteristics of semiconductor devices based on group III nitride materials (also known as III-N materials), such as gallium nitride (GaN) devices.

[0018] GaN devices, such as GaN transistors, offer certain performance advantages over silicon, including lower on-state resistance (e.g., drain-source resistance or RDSON), lower switching losses, and improved breakdown voltage. GaN transistors incorporate heteroepitaxial structures with junctions (e.g., heterojunction structures) between materials with different bandgap types (e.g., aluminum gallium nitride (AlGaN) and gallium nitride) to provide lateral two-dimensional electron gas (2DEG) channels for device operation formed within the AlGaN / GaN heteroepitaxial structure. Depletion-mode (DMODE) GaN transistors are normally-on, while enhancement-mode (EMODE) GaN transistors are normally-off. In some instances, EMODE GaN transistors include a gate stack with a p-type doped gallium nitride (p-GaN) layer that depletes the 2DEG channel beneath the gate under zero or negative gate bias. Applying a positive gate voltage enhances the 2DEG channel and turns on the EMODE GaN device to allow current to flow between the source and drain.

[0019] The density and mobility of charge carriers (e.g., electrons) in a 2DEG channel are controlled by a variety of factors, including the Al concentration in AlGaN, the stress in the film, and the layer thickness. While the charge carrier density in a 2DEG channel typically increases with increasing aluminum content and film thickness, there may be physical limitations to the amount of Al that can be increased (e.g., higher Al content leads to higher stress and lower film quality). Furthermore, forming a thicker layer may present manufacturing limitations, such as requiring a longer growth stage, thus increasing cycle time and associated costs. On the other hand, higher 2DEG densities are desirable because they allow for lower on-resistance and a higher maximum on-current (Imax). Additionally, since charge carrier mobility is also related to device performance, higher electron mobility in the 2DEG channel is similarly desirable.

[0020] The examples disclosed herein recognize the aforementioned challenges and provide solutions for advantageously increasing 2DEG electron density, mobility, and / or both in various types of GaN device modes. In some versions of the examples herein, an oxide layer (e.g., an oxide interface layer) is provided only in portions of the barrier layer in different device regions of the GaN device, as will be seen below. This can enhance various electrical parameters of the device, such as reducing the sheet resistance of the 2DEG channel. While the examples provide various structures, materials, and processes that can produce beneficial effects in various device modes, no particular result is required unless expressly stated in the specific claims.

[0021] Refer to the attached diagram. Figure 1A-1DCross-sectional views of a semiconductor device 100 including an EMODE GaN device 101 according to some examples of the present disclosure are depicted at various stages of the process flow, wherein an oxide interface layer may be provided in or over a barrier layer in a selected region of the GaN device 101. Figure 1A This depicts an intermediate stage of a semiconductor device 100 formed on a portion of a semiconductor substrate 102, which may be a silicon wafer, a silicon-on-sapphire wafer, or a silicon carbide wafer, etc. A buffer layer 104 comprising one or more III-N semiconductor material layers is formed on the substrate 102. In some instances where the substrate 102 is implemented as a silicon wafer or a sapphire wafer, the buffer layer 104 may include a nucleation layer having a stoichiometric ratio of aluminum to match the lattice constant of the substrate 102. In some exemplary versions, the buffer layer 104 may further include an aluminum gallium nitride (AlGaN) layer / sublayer with a reduced aluminum content, and in some arrangements, an unintentionally doped (UID) GaN sublayer may be included. For the purposes of this illustration, the various layers / sublayers of the buffer layer 104 are not specifically shown in the accompanying drawings.

[0022] According to the implementation, the buffer layer 104 may have a thickness of about 1 micrometer (µm) to several micrometers (e.g., 3.5 µm to 5.0 µm), and the buffer layer may be formed by a suitable epitaxial process, such as a metal-organic vapor phase epitaxy (MOVPE) process having several operations to form various layers and / or sublayers. Depending on the size of the GaN device 101, the buffer layer 104 is formed to overlap with a region of the substrate 102, in which different regions may be provided relative to the GaN device 101, such as a source region 105A, a gate region 105B, a drain region 105D, and a drain access region 105C between the gate region 105B and the drain region 105D. A channel layer 106 for supporting a 2DEG channel 108 may be formed on or above the buffer layer 104, and the channel layer may be formed by a suitable MOVPE process using gallium-containing gas reagents / sources and nitrogen-containing gas reagents / sources. Although the channel layer 106 may primarily comprise GaN material, in some embodiments, optional trace amounts of other Group III elements, such as aluminum or indium, may be present. Furthermore, in some additional and / or alternative arrangements, the channel layer 106 may be formed as the final portion of the buffer layer 104.

[0023] Continue to refer to Figure 1A A barrier layer 110 comprising a III-N semiconductor material is formed above the channel layer 106 (or on an optional high-bandgap sublayer, if present). In example arrangements, the barrier layer 110 may have a thickness ranging from 1 nanometer (nm) to 60 nm and may contain aluminum and nitrogen. In some versions of this example, the barrier layer 110 may contain gallium with an atomic percentage less than that of aluminum. In some versions, the barrier layer 110 may also contain indium.

[0024] The barrier layer 110 above the channel / buffer stack 104 / 106 can serve as a heterojunction structure to facilitate the formation of a 2DEG channel 108 near the interface between the barrier layer 110 and the channel layer 106. Although the stoichiometry and thickness of the barrier layer 110 can be configured to provide a suitable free charge carrier density (e.g., 3 × 10⁻⁶), the barrier layer 110 can be configured to provide a suitable free charge carrier density. 12 cm -2 Up to 2×10 13 cm -2 The examples described herein can be configured to increase the carrier density of a given heterojunction structure by providing a segmented oxide layer in or above the barrier layer 110 in a selected region of the GaN device 101, as will be described below.

[0025] To achieve the EMODE function, a gate stack 112 comprising a p-doped III-N (p-III-N) layer is formed above the barrier layer 110 in the gate region 105B. The p-III-N layer includes one or more III-N material layers, such as... Figure 1A As shown in the example. In this version, a layer stack including a p-doped GaN layer 114 (e.g., doped with magnesium (Mg) or other p-type dopants), an AlGaN capping layer 115 (e.g., without p-doping), and a silicon nitride (SiN) capping layer 117 can be formed and patterned, for example, using a gate stack mask and appropriate photolithography and etching processes. In some examples, the p-doped GaN layer 114 may contain about 1 × 10⁻⁶ ppm. 20 atoms / cm 3 The peak p-doped concentration can be achieved, and the thickness can range from approximately 50 nm to 200 nm. In some instances, low-pressure chemical vapor deposition (LPCVD) can be used to form the SiN capping layer 117.

[0026] The formation of the gate stack 112, including the p-GaN layer 114, reduces the 2DEG channel 108 in the gate region 105B (e.g., in some cases, it is absent), as... Figure 1A-1D As shown in the example version herein, the source region 105A (where the source terminal or contact will be formed) and the drain region 105D (where the drain terminal or contact will be formed) are asymmetrically arranged relative to the gate region 105B, but this is not necessary. For example, the lateral distance between the gate region 105B and the drain region 105D may be greater than the lateral distance between the gate region 105B and the source region 105A due to the access region (e.g., drain access region 105C) provided between the gate region 105B and the drain region 105D. In some additional and / or alternative arrangements, a source access region may be provided between the source region 105A and the gate region 105B in a similar manner, while still having the source / drain region asymmetry relative to the gate region 105B.

[0027] Additional details regarding the formation of EMODE GaN devices and DMODE GaN devices (which will be further set forth below for the purposes of some examples of this disclosure) can be found in the following U.S. patent applications: (i) U.S. Patent Application Publication No. 2022 / 0130988; (ii) U.S. Patent Application Publication No. 2022 / 0173234; and (iii) U.S. Patent Application Publication No. 2023 / 0094094; each of these U.S. patent application publications is incorporated herein by reference in its entirety for all purposes and may be individually and / or collectively referred to as the “incorporated disclosure”.

[0028] Figure 1B This paper describes the stages of forming an oxide layer 119 (e.g., an oxide interface layer) in or above a barrier layer 110 in a selected region of a GaN device 101 of a semiconductor device 100, according to some examples herein. In one embodiment, the oxide layer 119, also referred to in some examples as a segmented oxide layer, is formed in a plasma-enhanced CVD (PECVD) instrument by a plasma treatment involving nitrous oxide (N₂O). Depending on the configuration, nitrous oxide can be supplied to the reactor chamber at a flow rate of about 1.5 standard liters per minute (slm) to 2.5 slm for about 60 to 90 seconds, wherein the RF power is greater than 600 W and the frequency range is about 10 MHz to 20 MHz. Furthermore, in some arrangements, a chamber pressure of about 300 Pa to 400 Pa and a temperature of about 350°C to 450°C can be maintained during the processing. Figure 1B In this example, plasma processing is applied to all regions of the GaN device 101, namely the source region 105A, the gate region 105B (overlying the gate stack 112), the drain access region 105C, and the drain region 105D. Therefore, except for the portion corresponding to the gate region 105B that lies beneath the gate stack 112, the entire barrier layer 110 is exposed to the reactive plasma material. As will be further explained below, for the purposes of some additional and / or alternative examples herein, the passivation layer prior to plasma processing (where provided) may be patterned to selectively open and thus expose different regions in the barrier layer 110 of the GaN device 101 to the plasma processing in order to form a segmented oxide layer.

[0029] Continue to refer to Figure 1BIn some examples, oxide layer 119 includes a lateral or horizontal segment 116A extending over drain access region 105C and drain region 105D, a lateral or horizontal segment 116B extending over source region 105A, and a horizontal segment 116C over gate stack 112, wherein vertical segments 118A, 118B formed above the respective sidewall surfaces of gate stack 112 extend from horizontal segment 116C to horizontal segments 116A, 116B extending over each side of gate stack 112. Although the thickness of horizontal segments 116C and vertical segments 118A, 118B covering gate stack 112 may vary depending on the morphology of gate stack 112 and / or the composition of underlying material, in some examples herein, the horizontal segments 116A and 116B of oxide layer 119 formed in or over barrier layer 110 may be about 2 nm to 5 nm, or less.

[0030] When an oxide layer is formed on or in the barrier layer 110, the interaction between the plasma material and the surface of the barrier layer 110 may cause variations in the quantum wells formed due to the different band gaps of the materials in the heterojunction structure of the GaN device 101. Such variations in the quantum wells can contribute to increasing the carrier density and / or mobility in the 2DEG channel 108, depending on the plasma chemistry configured in the plasma processing.

[0031] Go to Figure 1C A passivation layer 120 is formed over the GaN device 101. In some embodiments, the passivation layer 120 may include a silicon nitride (SiN) layer with a thickness of about 50 nm to 100 nm formed in an LPCVD process.

[0032] exist Figure 1DThe diagram illustrates a cross-sectional view of a more fully formed semiconductor device 100 containing a GaN device 101. As depicted, a dielectric layer 122 is formed over a passivation layer 120 of the GaN device 101. In some embodiments, the dielectric layer 122 may comprise a PECVD SiN layer with a thickness of about 50 nm to 100 nm. Contact lithography and etching processes may be configured to pattern contact openings in the dielectric layers 122 and 120 over the source region 105A, gate region 105B, and drain region 105D. The source terminal or contact 125A is formed as a horizontal segment 116A extending through the dielectric layers 122, 120, and oxide layer 119 and into the barrier layer 110. Similarly, the drain terminal or contact 125B is formed as a horizontal segment 116B extending through the dielectric layers 122, 120, and oxide layer 119 and into the barrier layer 110. The gate terminal or contact 125C is formed as a horizontal segment 116C extending through the dielectric layers 122, 120 and the oxide layer 119, and into the AlGaN cap 115 of the gate stack 112. The source contact 125A, drain contact 125B and gate contact 125C are conductive and may contain one or more metals, such as titanium, nickel, tungsten or aluminum, or may contain other conductive materials, such as carbon nanotubes or graphene.

[0033] As previously described, due to the presence of the drain access region 105C, the source terminal 125A and the drain terminal 125B are asymmetrically disposed relative to the gate terminal 125C. For the purposes of this example, the drain access region may be a region of the device region disposed between the gate terminal and the drain terminal of the device. Similarly, the source access region (where provided) may be a region of the device region disposed between the gate terminal and the source terminal of the device, which may have a length different from the length of the drain access region (e.g., a length along the X-axis).

[0034] Despite Figure 1D Not shown, but optionally, one or more field plates associated with one or more device terminals (e.g., source terminal 125A, drain terminal 125B, and / or gate terminal 125C) may be provided to mitigate the effects of peak electric fields in the channel layer 106 that may be induced in some high-voltage applications. Furthermore, the source terminal 125A, drain terminal 125B, and / or gate terminal 125C, as well as any optional field plates, may extend into the interlayer dielectric (ILD) and / or pre-metal dielectric (PMD) insulating layer 127 and may be protected by a protective outer coating (PO) of the semiconductor device 100. Figure 1D (Not shown in the text) Coverage.

[0035] Figures 2A-2ECross-sectional views of a semiconductor device 200 including an EMODE GaN device 201 according to some examples of this disclosure are depicted at various stages of the process flow, wherein an oxide layer is provided in or above the barrier layer only in a portion of the drain access region of the GaN device. Figures 2A-2E The process flow stages are basically similar to those described above. Figure 1A-1D The process flow stages, except as noted herein regarding the oxide layer formation stage, are as follows. Therefore, except for the modifications necessary to form an oxide layer only in a portion of the drain access region of GaN device 201, the description of the fabrication of GaN device 101 also applies to the fabrication of GaN device 201. Figure 2A In the intermediate stage, semiconductor device 200 and Figure 1A The semiconductor device 100 is identical to that of the GaN device 201, which includes a source region 205A, a gate region 205B, a drain region 205D, and a drain access region 205C between the gate region 205B and the drain region 205D on a substrate 202. Similar to... Figure 1A In the example, Figure 2A In the stage shown, a buffer layer 204, a channel layer 206 supporting the 2DEG channel 208, and a barrier layer 210 are formed. Similarly, in the gate region 205B of the GaN device 201, a gate stack 212 is formed above the barrier layer 210, wherein the gate stack 212 includes a p-GaN layer 214, an AlGaN cap 215, and a dielectric cap 217, and the gate stack may be patterned similarly to the gate stack 112 described above.

[0036] exist Figure 2B In this process, a dielectric layer 220 is formed over the GaN device 201 as a passivation layer, which may include an LPCVD SiN layer of suitable thickness (e.g., about 50 nm to 100 nm). Openings or apertures with suitable shape factors and dimensions (e.g., rectangular shapes) can be formed in the dielectric layer 220, for example, by patterned etching including wet etching and / or dry etching. Figure 2C As illustrated in the cross-sectional view, an aperture 222 may be formed in the dielectric layer 220, the aperture being laterally spaced 221 from the gate stack 212 to expose a corresponding portion of the barrier layer 210 covering the drain access region 205C. In some embodiments, the aperture 222 may cover at least a portion of the drain access region 205C. In some embodiments, the aperture 222 may extend only over a portion of the drain access region 205C. In some embodiments, multiple apertures 222 covering a portion of the drain access region 205C may be provided through suitable patterning of the dielectric layer 220.

[0037] Figure 2D Depicting using similar Figure 1BThe plasma treatment described in the process involves the formation of an oxide layer 219 over the GaN device 201. Because only the portion of the barrier layer 210 overlying the drain access region 205C is exposed in the orifice 222, the oxide layer 219 may comprise a single segment 231 formed in the orifice 222 (or multiple segments if multiple orifices are provided), which can advantageously influence the carrier density and / or mobility in the 2DEG channel 208. Additional oxide segments formed over the dielectric layer 220 do not have a direct interface with the barrier layer 210 in the remaining region of the GaN device 201, and therefore may not be effective in modulating the carrier parameters in the 2DEG channel 208.

[0038] Figure 2E A cross-sectional view depicting a more fully formed semiconductor device 200 including the GaN device 201. Similar to... Figure 1D The semiconductor device 100 described herein forms a PECVD dielectric layer 229 over a GaN device 201. This PECVD dielectric layer is patterned using similar processes, metallurgy, etc., to form source contacts or terminals 225A, drain contacts or terminals 225B, and gate contacts or terminals 225C. Similarly, the source terminals 225A, drain terminals 225B, and / or gate terminals 225C may be provided with any optional field plates, wherein the terminals and corresponding field plates may extend into the ILD / PMD layer 227 of the semiconductor device 200.

[0039] Similar to the EMODE GaN examples described above, additional and / or alternative examples of this disclosure disclose DMODE GaN examples, in which a similar plasma treatment can be used to form an oxide layer above the barrier layer in the selected region of the DMODE GaN device in order to enhance the carrier density and / or mobility in the 2DEG channel. Figures 3A-3H Cross-sectional views of a semiconductor device 300 including a DMODE GaN device 301 according to some embodiments of the present disclosure are depicted at various stages of the process flow, wherein an oxide layer may be provided in or over the barrier layer in the gate region of the GaN device and / or only in a portion of the drain access region. Except for the fabrication of a DMODE GaN device that does not contain a p-GaN gate stack as a normally-on device in the examples herein, the plasma processing used to form oxide layer segments in the barrier layer of the selected region of the DMODE GaN device is similar to the plasma processing options and process conditions described above. Therefore, with appropriate or related modifications as will be noted below, the plasma processing options and associated process conditions applied in the fabrication of EMODE GaN devices are equally applicable to the fabrication of DMODE GaN devices.

[0040] Figure 3AIntermediate stages of a semiconductor device 300, similar to those described above for semiconductor devices 100 and 200, are depicted. These semiconductor devices include a suitable substrate 302 and one or more III-N layers, which may serve as a buffer layer 304, a channel layer 306 configured to support a 2DEG channel 308, and a barrier layer 310 relative to the GaN device 301 to be formed. Additional details relating to the formation of, for example, a DMODE device of semiconductor device 300, including intermediate stages, can be found in one or more incorporated disclosures as previously described.

[0041] Figure 3B The stage is depicted in which a dielectric layer 320 (e.g., an LPCVD SiN layer with a thickness of about 50 nm to 100 nm) is formed above the barrier layer 310 as a passivation layer.

[0042] Figure 3C The process of patterning dielectric layer 320 (e.g., using suitable photolithography and etching processes, including wet etching and / or dry etching) to form vias 322A and 322B in selected regions of GaN device 301 is described. As illustrated, via 322A is formed over gate region 305B, and via 322B is formed over drain access region 305C disposed between gate region 305B and drain region 305D. In this example, via 322A may also be referred to as a gate via because, during plasma processing, in addition to forming an oxide layer segment at interface 321 of barrier layer 310, a gate dielectric layer and a gate terminal may also be formed in the gate via. Similarly, via 322B may be referred to as a drain access via in which an oxide layer segment may be formed at interface 323 of barrier layer 310 during plasma processing. Depending on the implementation scheme and applicable gate design rules, orifices 322A and 322B may have different sizes and shape factors and may be laterally spaced (e.g., along the X-axis) by a suitable distance 317, thereby forming a mesa structure 315 between the orifices.

[0043] In the version described in this example, the drain access via 322B may expose only a portion of the barrier layer 310 within the drain access region 305C, which is the device region disposed between the gate region 305A and the drain region 305D as previously described. Furthermore, although relative to the source region 305A, in Figure 3C A separate source access region is not shown in the examples, but some additional and / or alternative examples may also include a source access region, which may be patterned to provide an opening for forming oxide layer segments therein in a similar manner.

[0044] Figure 3DThe process of applying plasma treatment to semiconductor device 300 to form oxide layer 319 with a thickness of about 2 nm to 5 nm or less is described, similar to the formation of oxide layers 119 and 219 described above.

[0045] Figure 3E The stage of forming dielectric layer 329 over oxide layer 319 is depicted. In some instances, as an optional embodiment, dielectric layer 329 may comprise an LPCVD SiN layer and may have a thickness suitable for supporting gate field plate formation (e.g., 35 nm to 50 nm).

[0046] Figure 3F The following stages are depicted: the dielectric layer 329 is selectively removed from the bottom of the gate aperture 322A by appropriate mask patterning and etching (e.g., wet etching and / or dry etching), thereby exposing the oxide layer segment 316A overlying the interface 321. Figure 3F The patterning and etching processes implemented during the phase can leave a portion of the dielectric layer 329 on the sidewall of the gate orifice 322A and above the remaining section of the oxide layer 319, including the section remaining above the mesa structure 315 and in the drain access orifice 322B (e.g., oxide section 316B).

[0047] Figure 3G The description depicts the stage of forming a dielectric layer 324 over a topography of a GaN device 301, which includes a gate aperture 322A, a mesa structure 315, and a drain access aperture 322B. In the version of this example, the dielectric layer 324 may have a suitable thickness in the gate aperture 322A, for example, 20 nm to 30 nm, to serve as the gate dielectric layer for the GaN device 301. Furthermore, in some examples, the dielectric layer 324 extending over the mesa structure 315 in the drain access region 305C and / or over the source region 305A may be configured to combine with a dielectric layer 329 to support (optionally) a gate field plate.

[0048] Figure 3HA cross-sectional view depicting a more fully formed semiconductor device 300 including a GaN device 301 is shown. For example, the GaN device 301 includes a gate electrode 325C in a gate aperture 322A of a gate region 305B. The gate electrode 325C extends into a portion of the dielectric layer 324 that can be used as a gate dielectric layer in the gate aperture 322A. Furthermore, contact patterning and etching processes can be configured to form source contacts or terminals 325A in the source region 305A, drain contacts or terminals 325B in the drain region 305D, and gate contacts or terminals (not shown) on the gate electrode 325C. As illustrated, the source contacts 325A extend through horizontal sections of dielectric layers 324, 329, 320 and oxide layer 319 extending above the source region 305 and into the barrier layer 310 of the source region 305A. Similarly, the drain contact 325B extends through the horizontal section of the dielectric layers 324, 329, 320 and the oxide layer 319 above the drain region 305D, and enters the barrier layer 310 of the drain region 305D. Similar to the semiconductor devices 100 and 200 described above, the source contact 325A, drain contact 325B, and gate contact can be formed using similar metals and / or other conductive materials such as carbon nanotubes or graphene. Furthermore, the source terminal 325A, drain terminal 325B, and / or gate electrode 325C may be provided with optional field plates, wherein the terminals and corresponding field plates may extend into the ILD / PMD layer 327 of the semiconductor device 300.

[0049] like Figure 3H As shown, only a portion of the drain access region 305C of the GaN device 301 includes a section of oxide layer 319. Although the gate region 305B may also include a section of oxide layer 319, in other embodiments of this disclosure, this section may be omitted depending on the implementation of plasma processing integration in the manufacturing process.

[0050] Figures 4A-4H Cross-sectional views of a semiconductor device 400 including a DMODE GaN device 401 according to some examples of the present disclosure are shown at various stages of the process flow, wherein an oxide layer may be provided in or over the barrier layer only in a portion of the drain access region of the GaN device 401. Figures 4A-4H The process flow stages are basically similar to those described above. Figures 3A-3H The process flow stages, besides those noted in this article regarding the oxide layer formation stage. Although in Figure 3C During the processing stage, two apertures 322A and 322B are formed in the passivation layer (e.g., dielectric layer 320) covering the barrier layer 310, wherein each aperture exposes the barrier layer 310 in the corresponding device region to form an oxide layer segment therein, but Figure 4CAn example is depicted in the stage where only one aperture (drain access aperture 422B) is formed in the dielectric layer 420 overlying the barrier layer 410 in the drain access region 405C.

[0051] Typically, in addition to forming a separate aperture in the gate region 405B of the GaN device 401 (e.g., Figure 4E Apart from the necessary modifications to the gate aperture 422A shown, the description of the manufacture of GaN device 301 is broadly applicable to the manufacture of GaN device 401. Figure 4A and 4B In the intermediate stage, semiconductor device 400 and Figure 3A , 3B The semiconductor device 300 is the same as that included, and also includes a GaN device 410, which includes a source region 405A, a gate region 405B, a drain region 405D, and a drain access region 405C between the gate region 405A and the drain region 405D on a substrate 402. Similar to... Figure 3A and 3B The stages, such as Figure 4A and 4B As shown in the stage, a buffer layer 404, a channel layer 406 supporting the 2DEG channel 408, a barrier layer 410, and a dielectric layer 420 are formed.

[0052] exist Figure 4C In the stage shown, a drain access via 422B is formed in the dielectric layer 420, thereby exposing the interface 423 of the barrier layer 410 in the drain access region 405C of the GaN device 401. In the version of this example, the drain access via 422B is similar to... Figure 3C It is formed during the patterning and etching processes of the process stage, and may extend only in a portion of the entire drain access region 405C.

[0053] Figure 4D The process of applying plasma treatment to semiconductor device 400 to form oxide layer 419 with a thickness of about 2 nm to 5 nm or less is described, similar to the formation of oxide layers 119, 219, and 319 described above. Figure 4E The description depicts the stage of forming a gate aperture 422A through the oxide layer 419 and dielectric layer 420 in the gate region 405B, which, in addition to forming a mesa structure 415 in the drain access region 405C, also exposes a barrier layer 410 therein. Furthermore, a dielectric layer 429 is formed over the GaN device 401. In the version of this example, the dielectric layer 429 can be formed using a process similar to that described above for forming dielectric layer 329, and can be configured to support optional gate field plate formation in some arrangements.

[0054] Figure 4FThe following stages are depicted: Using appropriate mask patterning and etching (e.g., wet etching and / or dry etching), the dielectric layer 429 is selectively removed from the bottom of the gate aperture 422A, thereby exposing the interface 421 of the barrier layer 410. Figure 4F The patterning and etching processes implemented during the phase can leave a portion of the dielectric layer 429 on the sidewall of the gate orifice 422A and above the remaining portion of the oxide layer 419, including the portion left above the mesa structure 415 and in the drain access orifice 422B.

[0055] Figure 4G The description depicts the stage of forming a dielectric layer 424 over a morphology of a GaN device 401, the morphology including a gate aperture 422A, a mesa structure 415, and a drain access aperture 422B. In the version of this example, the dielectric layer 424 may have a suitable thickness in the gate aperture, for example, 20 nm to 30 nm, to serve as the gate dielectric layer for the GaN device 401. The dielectric layer 424 is in direct contact with the barrier layer 410 in the gate aperture 422A. Furthermore, in a similar manner... Figure 3G In some arrangements of the example, a dielectric layer 424 extending above the mesa structure 415 in the drain access region 405C and / or above the source region 405A may be configured to combine with a dielectric layer 429 to support (optionally) the gate field plate.

[0056] Figure 4H A cross-sectional view depicting a more fully formed semiconductor device 400 including a GaN device 401 is shown. The GaN device is substantially similar to the GaN device 301 described above, except that there is no oxide layer segment in the gate region 405B. Similar to GaN device 301, GaN device 401 includes a gate electrode 425C in the gate aperture 422A of the gate region 405B. The gate electrode 425C extends into the portion of the dielectric layer 424 in the gate aperture 422A that can be used as a contact point with the barrier layer 410. Similar to... Figure 3H The structure shown can be fabricated using contact patterning and etching processes to form source contacts or terminals 425A in the source region 405A, drain contacts or terminals 425B in the drain region 405D, and gate contacts or terminals (not shown) on the gate electrode 425C. Furthermore, similar to... Figure 3H The section of the drain access region 405C of the GaN device 401 in the semiconductor device 300 shown contains only a portion of the oxide layer 419.

[0057] As explained, in Figure 4HIn this configuration, source contact 425A extends through the horizontal section of dielectric layers 424, 429, 420 and oxide layer 419 above source region 405A and enters the barrier layer 410 of source region 405A. Similarly, drain contact 425B extends through the horizontal section of dielectric layers 424, 429, 420 and oxide layer 419 above drain region 405D and enters the barrier layer 410 of drain region 405D. Similar to the semiconductor devices 100, 200, and 300 described above, source contact 425A, drain contact 425B, and gate contact can be formed using similar metals and / or other conductive materials such as carbon nanotubes or graphene. Additionally and / or alternatively, the source terminal 425A, drain terminal 425B, and / or gate electrode 425C may be provided with optional field plates, wherein the terminals and corresponding field plates may extend into the ILD / PMD layer 427 of the semiconductor device 400. Furthermore, similar to... Figure 3H The section of the drain access region 405C of the GaN device 401 in the semiconductor device 300 shown contains only a portion of the oxide layer 419.

[0058] Figure 5 and 6 This is a flowchart of a method for manufacturing a semiconductor device comprising a segmented oxide layer in or above a barrier layer, according to some examples of the present disclosure. Figure 5 Method 500 describes a process for providing one or more oxide layer segments in a selectable region of an EMODE device. At block 502, a channel layer may be formed over a semiconductor substrate, the semiconductor substrate including a source region, a gate region, a drain region, and a drain access region between the gate and drain regions. At block 504, a barrier layer may be formed over the channel layer. At block 504, a gate stack including a p-doped III-N (p-III-N or p-GaN) layer may be formed over the barrier layer in the gate region of the semiconductor substrate, wherein the p-GaN layer may be doped using Mg or other p-type dopants as previously described. At block 506, an oxide layer including a first segment may be formed in at least a portion of the drain access region of the semiconductor substrate. As previously described... Figure 1A-1D and Figures 2A-2E As illustrated in the process stages, some instances can be configured to expose the barrier layer of the GaN device in the entire drain access region or only a portion thereof using a patterned dielectric layer for plasma processing based on selected chemicals and suitable process conditions.

[0059] Figure 6Method 600 describes a process for providing one or more oxide layer segments in the selectable device region of a DMODE device. Similar to block 502 described above, a channel layer may be formed over a semiconductor substrate comprising a source region, a gate region, a drain region, and a drain access region between the gate and drain regions (block 602). Subsequently, a suitable barrier layer may be formed over the channel layer (block 604). In one arrangement, an oxide layer may be formed that includes a segment (e.g., a first segment) only in a portion of the drain access region of the semiconductor substrate (block 606). In another and / or alternative arrangement, a second oxide layer segment may also be formed in the gate region of the semiconductor device. As previously described... Figures 3A-3H and Figures 4A-4H The process stages illustrated herein are similar to the actions and operations described in box 506. Some instances may be configured to expose the barrier layer of the GaN device only in a portion using a patterned dielectric layer for plasma processing based on selected chemicals and suitable process conditions.

[0060] In some instances, plasma treatment of selected portions of the oxide barrier layer can be based on the N₂O chemistry as described above. In addition to the accompanying benefits in several relevant electrical parameters (e.g., on-resistance, channel sheet resistance, contact resistance, etc.), favorable results have also been observed in terms of electron gas density and carrier mobility in the 2DEG channel of the example GaN devices. By way of example only, in some embodiments, an electron gas density approximately 25% higher in the drain access region of the example device has been observed. As another example, in some embodiments, a channel sheet resistance approximately 25% lower has been observed in the example device.

[0061] In additional and / or alternative arrangements, plasma treatment based on oxygen (O2) chemistry can be implemented according to some examples herein, wherein the barrier layer can be selectively exposed in certain regions of the apparatus, similar to the examples described in detail above. According to the implementation, oxygen can be supplied to the reactor chamber of the PECVD tool at a flow rate of about 1.5 slm to 2.5 slm for about 60 to 90 seconds. In versions of this arrangement, both RF power and low-frequency (LF) power can be applied, for example, where the RF power is about 500 W to 600 W with a frequency range of about 10 MHz to 20 MHz, and the LF power is about 300 W with a frequency range of about 300 kHz to 500 kHz. Furthermore, in some arrangements, a chamber pressure of about 300 Pa to 400 Pa and a temperature of about 350 °C to 450 °C can be maintained during a treatment process similar to that based on N2O.

[0062] While various examples of this disclosure have been described above, these examples are presented by way of illustration only and not limitation. Many changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the examples described above. In fact, the scope of this disclosure should be defined by the appended claims and their equivalents.

[0063] For example, in this disclosure and the appended claims, unless otherwise stated and / or specified to the contrary, any one or more of the layers set forth herein may be formed in any number of suitable manners, such as using spin coating, sputtering (e.g., magnetron and / or ion beam sputtering), (thermal) growth techniques, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD). As another example, silicon nitride may be silicon-rich silicon nitride or oxygen-rich silicon nitride. Silicon nitride may contain some oxygen, but not so much that the dielectric constant of the material is significantly different from that of high-purity silicon nitride.

[0064] Furthermore, in at least some additional or alternative embodiments, the functions / actions described in the boxes may not occur in the order shown in the flowchart. For example, depending on the functionality / action involved, two boxes shown consecutively may actually be performed substantially simultaneously, or the boxes may sometimes be performed in reverse order. Additionally, the functionality of a given box in a flowchart and / or block diagram may be divided into multiple boxes, and / or the functionality of two or more boxes in a flowchart and / or block diagram may be at least partially integrated. Also, some boxes in the flowchart may optionally be omitted. Furthermore, although some diagrams include arrows on communication paths to show the main direction of communication, it should be understood that communication may occur in the opposite direction to the depicted arrows. Finally, additional boxes may be added / inserted between the illustrated boxes.

[0065] The order or sequence of actions, steps, functions, components, or blocks illustrated in any of the flowcharts and / or block diagrams depicted in the accompanying drawings of this disclosure may be modified, altered, replaced, customized, or otherwise rearranged within a particular flowchart or block diagram, including the deletion or omission of specific actions, steps, functions, components, or blocks. Furthermore, actions, steps, functions, components, or blocks illustrated in a particular flowchart may be mixed with or otherwise arranged or rearranged with actions, steps, functions, components, or blocks illustrated in another flowchart to achieve additional changes, modifications, and configurations relative to one or more processes for the purpose of practicing the teachings of this disclosure. Similarly, although various examples have been set forth herein, not all features of a particular example are necessarily limited to and / or necessary for this purpose.

[0066] At least some of the above descriptions may contain certain directional terms, such as “upper,” “lower,” “top,” “bottom,” “left,” “right,” “front,” “back,” “vertical,” “horizontal,” etc., which may be used with reference to the orientation of some of the described figures or their illustrative elements. Since components in some instances may be positioned in multiple different orientations, the directional terms are used for illustrative purposes and are by no means limiting. Similarly, references to features referred to as “first,” “second,” etc., do not indicate any particular order, importance, etc., and such references may be interchanged depending on the context, implementation, etc. Furthermore, terms such as “above,” “below,” “under,” etc., relative to the spatial orientation of two components do not necessarily mean that one component is directly above another, or that one component is directly below or under another. Moreover, unless otherwise specifically indicated, the features and / or components of the instances described herein may be combined with each other.

[0067] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or instance. The above specific embodiments should not be construed as implying that any particular component, element, step, action, or function is essential to the scope of the claims. In the context of phrases such as "at least one of A and B" or similar phrases, such phrases should be understood to mean "only A, only B, or both A and B." Unless explicitly stated otherwise, references to singular elements are not intended to mean "one and only one," but rather "one or more." Similarly, depending on the context, phrases such as "a plurality" or "multiple" may mean "one or more" or "at least one." All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference and are intended to be covered by the appended claims.

Claims

1. A semiconductor device comprising: A semiconductor substrate comprising a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region; A channel layer, which is located above the semiconductor substrate; A barrier layer, which is above the channel layer; A gate stack comprising a p-doped III-N layer above the barrier layer in the gate region; as well as An oxide layer that includes a first segment in at least a portion of the drain access region.

2. The semiconductor device of claim 1, wherein the oxide layer comprises a second segment in at least one of the source region and the drain region.

3. The semiconductor device of claim 2, wherein the oxide layer comprises a horizontal segment covering at least a portion of the top surface of the gate stack, and one or more vertical segments covering the respective sidewalls of the gate stack.

4. The semiconductor device of claim 3, further comprising: The source extreme element extends through the first instance of the second segment and enters the barrier layer; The drain terminal extends through the second instance of the second segment and enters the barrier layer; and Gate terminals that extend through the horizontal section and into the capping layer of the gate stack.

5. The semiconductor device of claim 2, further comprising: A dielectric layer is formed over the gate stack, wherein the oxide layer comprises a horizontal section over the dielectric layer and one or more vertical sections covering the respective sidewalls of the dielectric layer formed on the vertical surface of the gate stack.

6. The semiconductor device of claim 5, wherein a first example of the second segment is located over a first lateral portion of the dielectric layer extending over the source region, and a second example of the second segment is located over a second lateral portion of the dielectric layer extending over the drain access region and the drain region, the semiconductor device further comprising: The source terminal extends through the first example of the second segment, the first lateral portion of the dielectric layer, and into the barrier layer; The drain terminal extends through the second example of the second segment, the second lateral portion and into the barrier layer; as well as A gate terminal that extends through the horizontal segment, the dielectric layer above the gate stack, and into the capping layer of the gate stack.

7. The semiconductor device of claim 1, wherein the oxide layer is formed in or above the top surface of the barrier layer.

8. The semiconductor device of claim 1, wherein the oxide layer has a thickness of about 2 to 3 nanometers (nm) or less.

9. A semiconductor device comprising: A semiconductor substrate comprising a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region; A channel layer, which is located above the semiconductor substrate; A barrier layer, which is above the channel layer; as well as An oxide layer comprising a first segment only in a portion of the drain access region.

10. The semiconductor device of claim 9, wherein the oxide layer comprises: A first horizontal segment, located above the dielectric layer above the barrier layer in the source region; and The second horizontal segment is located above the dielectric layer above the barrier layer in the drain region.

11. The semiconductor device of claim 10, wherein the oxide layer further comprises a third horizontal segment of the gate region above the dielectric layer above the barrier layer, and the semiconductor device further comprises: The source terminal extends through the first horizontal segment, the dielectric layer, and into the barrier layer; The drain terminal extends through the second horizontal segment, the dielectric layer, and into the barrier layer; as well as A gate terminal that extends through the third horizontal segment and enters a gate dielectric layer formed in a trench above the barrier layer in the gate region, the gate dielectric layer being in contact with the barrier layer.

12. The semiconductor device of claim 10, wherein the oxide layer further comprises a second segment in a trench above the barrier layer in the gate region, the second segment contacting the barrier layer, and the semiconductor device further comprises: The source terminal extends through the first horizontal segment, the dielectric layer, and into the barrier layer; The drain terminal extends through the second horizontal segment, the dielectric layer, and into the barrier layer; as well as A gate terminal that extends into the gate dielectric layer above the second segment formed in the trench.

13. The semiconductor device of claim 9, wherein the oxide layer is formed in or above the top surface of the barrier layer.

14. The semiconductor device of claim 9, wherein the oxide layer has a thickness of about 2 to 3 nanometers (nm) or less.

15. A method comprising: A channel layer is formed above a semiconductor substrate, the semiconductor substrate including a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region; A barrier layer is formed above the channel layer; A gate stack is formed above the barrier layer in the gate region of the semiconductor substrate, the gate stack comprising a p-doped III-N layer; as well as An oxide layer comprising a first segment is formed in at least a portion of the drain access region formed on the semiconductor substrate.

16. The method of claim 15, wherein the step of forming the oxide layer comprises forming a second segment in at least one of the source region and the drain region.

17. The method of claim 15, wherein the oxide layer is formed in or above the top surface of the barrier layer using nitrous oxide in plasma processing with an RF power greater than 600 W and a frequency range of about 10 MHz to 20 MHz.

18. The method of claim 15, wherein the oxide layer has a thickness of about 2 to 3 nanometers (nm) or less.

19. A method comprising: A channel layer is formed above a semiconductor substrate, the semiconductor substrate including a source region, a gate region, a drain region, and a drain access region between the gate region and the drain region; A barrier layer is formed above the channel layer; as well as An oxide layer is formed comprising a first segment that is only in a portion of the drain access region.

20. The method of claim 19, wherein the step of forming the oxide layer comprises a second segment forming the oxide layer in the gate region.

21. The method of claim 19, wherein the oxide layer is formed in or above the top surface of the barrier layer using nitrous oxide in plasma processing with an RF power greater than 600 W and a frequency range of about 10 MHz to 20 MHz.

22. The method of claim 19, wherein the oxide layer has a thickness of about 2 to 3 nanometers (nm) or less.

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