Thin film resistor integration within copper interconnects

Abstract

In one example, an integrated circuit (IC) (100) includes a dielectric layer (122) above a semiconductor substrate (102), a resistive layer (124) above the dielectric layer (122), a metal interconnect trace (138A) above an end (123A) of the resistive layer (124), a via (134A) extending from the metal interconnect trace (138A) toward the resistive layer (124), and a metal barrier layer (130) between the via (134A) and the resistive layer (124).

Description

[0001] The described implementations generally relate to the field of integrated circuits (ICs) and IC manufacturing. More specifically, but not exclusively, the described implementations relate to thin-film resistor (TFR) integration. Background Technology

[0002] Metal thin-film resistors (TFRs) can be formed using various resistive metals. Nickel-chromium alloy (NiCr) and silicon-chromium alloy (SiCr) are two commonly used resistive metals. These types of TFRs are formed in the back-end process (BEOL) of integrated circuit manufacturing. Because BEOL resistors are formed at a greater distance from the semiconductor substrate, the parasitic capacitance of BEOL resistors is smaller than that of resistors formed in the front-end process (FEOL), which can use polycrystalline silicon, silicides, or n-wells formed in or above the semiconductor substrate.

[0003] Integrating metal TFRs in the BEOL (Body-In-Oriented Online) of the integrated circuit manufacturing process increases costs and production cycles. As the design of interconnects formed in the BEOL continues to improve, microelectronic devices, including metal TFRs and their integration, are also being improved in tandem. Summary of the Invention

[0004] The following is a simplified overview to provide a basic understanding of some examples in this specification. This summary is not a broad overview of the examples, nor does it identify key or essential elements of the examples or define their scope. Rather, the main purpose of this summary is to present some concepts of this specification in a simplified form as a prelude to the more detailed descriptions presented in subsequent sections.

[0005] Examples in this specification relate to one or more TFRs (also known as electronic devices, IC devices, semiconductor devices, etc.) integrated within a BEOL copper interconnect flow. In one example, an IC is described that may include: a dielectric layer above a semiconductor substrate; a resistive layer above the dielectric layer; a metal interconnect trace above the end of the resistive layer; a via extending from the metal interconnect trace toward the resistive layer; and a metal barrier layer located between the via and the resistive layer. In some arrangements, the metal barrier layer may be configured to contact the via and the resistive layer.

[0006] In one example, a method for manufacturing an IC device comprising a TFR is described. The method may, among other steps, include: forming a resistive layer over a semiconductor substrate; forming a first dielectric layer over the resistive layer; forming a metal barrier layer that contacts the resistive layer through an opening in the first dielectric layer; and forming a conductive via extending through a second dielectric layer over the resistive layer to the metal barrier layer, wherein the metal barrier layer may be configured to contact the via and the resistive layer.

[0007] In one example, a method for manufacturing an IC device incorporating a TFR is described. The method may, among other steps, include: forming a first dielectric layer over a semiconductor substrate; forming a resistive layer over the first dielectric layer; forming a second dielectric layer over the resistive layer; patterning the second dielectric layer to form an end trench over an end region of the resistive layer, the remainder of the second dielectric layer covering a resistor body spanning the end regions of the resistive layer; forming a metal barrier layer in the end trench; depositing an interlayer dielectric (ILD) layer over the end trench and the remainder of the second dielectric layer; forming vias in or through the ILD layer, each via falling on the metal barrier layer in the corresponding end trench; and forming a metal interconnect trace located above and electrically in contact with the via, the metal interconnect trace and the via being surrounded by the same barrier material as the metal barrier layer. Attached Figure Description

[0008] The embodiments described in the accompanying figures are illustrated by way of example rather than limitation. Different references to "a" or "an" embodiment in this specification do not necessarily refer to the same embodiment, and such references may mean at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not it is explicitly described, such feature, structure, or characteristic may be combined with other embodiments.

[0009] To illustrate one or more exemplary embodiments of this specification, the accompanying drawings are incorporated in and form a part of this specification. Various advantages and features of this specification are described in the following detailed description, taking into account the appended claims and the accompanying drawings, in which:

[0010] Figures 1A to 1J Cross-sectional views illustrating sequential manufacturing stages of a semiconductor device according to some examples of this specification, in which thin-film resistors can be integrated; and

[0011] Figure 2 and 3 These are flowcharts related to IC manufacturing methods, based on some examples from this specification. Detailed Implementation

[0012] Examples of this specification are described with reference to the accompanying drawings, in which similar reference numerals are generally used to refer to similar elements. The drawings are not drawn to scale and are provided only for illustrative purposes. Numerous specific details, relationships, and methods are set forth below to help understand one or more examples. However, some examples can be practiced without such specific details. In other examples, well-known subsystems, components, structures, and techniques have not been shown in detail to avoid obscuring the understanding of the examples. Therefore, examples of this specification can be practiced without such specific components.

[0013] Furthermore, terms such as “coupled” and “connected” and their derivatives may be used in the detailed description below, the appended claims, or both. These terms are not necessarily synonyms. “Coupled” can be used to indicate that two or more elements (which may or may not be in direct physical or electrical contact with each other) cooperate or interact with each other. “Connected” can be used to indicate the establishment of communication, i.e., a communication relationship, between two or more coupled elements. Additionally, in one or more examples set forth herein, generally, if an element can be programmed to perform a function or otherwise structurally arranged to perform a function, then the element, component, or module can be configured to perform said function.

[0014] Without limitation, examples from this specification will be illustrated below in the context of thin-film resistor (TFR) integration within the BEOL copper interconnect process.

[0015] Thin-film resistors (TFRs) offer low temperature coefficients of resistance (TCR) and have a wide range of applications. For example, due to their low TCR, high-precision analog circuits (e.g., voltage references, digital-to-analog converters and analog-to-digital converters (DAC / ADC), biosensor analog front-ends (AFEs), etc.) can incorporate one or more TFRs. In some baseline processes, TFRs can be formed between metallization layers formed during the BEOL process of a semiconductor device and adjacent metallization layers. This interlayer metal integration of the TFR requires the formation of a TFR head structure, where vias can fall on and contact the TFR film. As interconnect technologies continue to improve, such as those incorporating damascus copper metallization, protecting the TFR film from copper diffusion / migration that can occur in the head structure, potentially impairing the resistivity characteristics of the TFR.

[0016] Examples of this specification advantageously provide TFR arrangements in which the head structure of the TFR (also referred to as the end cap or end structure) is provided with a metal barrier layer configured to mitigate the adverse effects of copper diffusion, which may be induced or exacerbated within a temperature range likely encountered during the process flow. Additionally, examples herein provide end cap barriers comprising material that can also be used to form a barrier layer associated with copper vias used to access the TFR and / or interconnect with metal layers at different levels of a multi-level interconnect scheme. Thus, some examples herein can be configured to enhance the reliability of TFR devices integrated in copper interconnect schemes while facilitating process integration with minimal impact. Furthermore, due to the integration schemes described herein, example TFR structures can be configured with a reduced thickness relative to baseline TFR structures. While the examples can provide materials and processes that advantageously allow the integration of TFRs in various copper-related interconnect schemes, no specific result is required unless expressly stated in the particular claims.

[0017] Figure 1A-1J Cross-sectional views of a semiconductor device 100 (e.g., an IC or discrete device) during a continuous manufacturing phase, according to some examples of this specification, are illustrated, wherein one or more TFRs can be integrated in a BEOL copper interconnect process. In one arrangement, a resistive film or resistive layer, which can be used as a TFR structure having a terminal end (or “head”), can be integrated between two metal layers disposed at different levels of a multi-level interconnect scheme, wherein each terminal end can each include a metal barrier layer containing the same barrier material as that provided for copper vias to facilitate connections to the respective terminal end. In some variations, as an optional embodiment, the terminal end may also include a corresponding dielectric diffusion barrier layer above the metal barrier layer. In yet another arrangement, a subset of the illustrated process phases can be continuously repeated in an iterative process cycle to obtain a TFR arrangement, wherein multiple TFRs integrated at different levels of a multi-level interconnect can be configured as part of the semiconductor device 100.

[0018] For clarity, the illustrated cross-sectional views do not show details of the microelectronic devices and components formed in or on the semiconductor substrate 102 of the semiconductor device 100 as part of the FEOL manufacturing process, such as transistors, isolation regions, lateral diffusion extensions, N-wells, P-wells, deep wells, shallow wells, etc. In representative examples, transistors may include nMOS or pMOS transistors, junction field-effect transistors (JFETs), NPN or PNP bipolar transistors, biCMOS transistors, group III nitride devices, or combinations thereof. Depending on the application, the semiconductor device 100 may represent a device comprising analog circuit systems, digital circuit systems, and / or mixed-signal circuit systems, which can be manufactured using any type or combination of manufacturing techniques and / or technology nodes. For example, semiconductor device 100 can be a device in which different technologies suitable for the corresponding type of product design can be integrated within the same chip or IC device, such as linear BiCMOS or LBC (bipolar-CMOS combination technology, where MOS and bipolar technology can be used for analog functions and CMOS can be used for digital logic design), BCD (bipolar-CMOS-DMOS combination technology, where DMOS can be integrated within an IC device for power and high-voltage sections, the IC device also having analog and digital sections), etc. In some instances, semiconductor device 100 can represent an ADC / DAC converter, where the TFR can be set as part of a resistor ladder network, but is not limited thereto.

[0019] Figure 1A A cross-sectional view of the semiconductor device 100 during the pre-metallization stage (e.g., after various circuit elements are formed on or within the semiconductor substrate 102 in the FEOL process) is depicted. In some instances, the semiconductor substrate 102 may primarily comprise suitably doped silicon as the substrate material; however, in some embodiments, other semiconductor materials such as silicon-on-insulator, Ge, SiGe, GaAs, SiC, GaN, and other group III-V materials may be used, wherein one or more epitaxial layers or single-crystal layers may be formed or disposed as part of the semiconductor substrate 102. Additionally, Figure 1AThe cross-sectional view also depicts one or more polysilicon interconnects or traces 106 formed between the semiconductor substrate 102 and the metal pre-dielectric (PMD) layer 104, which is formed above the semiconductor substrate 102. Alternatively, the polysilicon traces 106 may be used to facilitate connections with structures formed in the BEOL process. Therefore, in some arrangements, the polysilicon traces 106 may be omitted. When polysilicon interconnects 106 are provided, they can have a suitable thickness and can be appropriately siliconized at locations where metal contacts are to be formed through the PMD layer 104 (not specifically shown in the figure). An example silicide circuit used with the polysilicon interconnect 106 may comprise, but is not limited to, depositing metal (e.g., nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), molybdenum (Mo), platinum (Pt), palladium (Pd), tantalum (Ta), etc.), annealing to form a silicide (e.g., using heat, ion energy, laser energy, etc.), then removing the unreacted metal and further annealing to form a silicide material with a low resistivity phase. Although not specifically shown in the figure, the PMD layer 104 may comprise one or more layers and / or sublayers formed of different materials, such as phosphorus-doped silicate glass (PSG), silicon nitride (SiN), or silicon dioxide (SiO2) doped dielectric materials, which may be planarized (e.g., by chemical mechanical polishing (CMP) and / or etching back) to a total thickness of approximately 0.3 micrometers (µm) to 2 µm or greater. In some instances, the PMD layer 104 can be formed by plasma-enhanced chemical vapor deposition (PECVD) and / or by high-density plasma (HDP) deposition.

[0020] Figure 1B The process of forming metal contacts 108 in a PMD layer 104 using contact patterning and etching processes is described for a semiconductor device 100, wherein the contacts 108 can be configured to fall on a polysilicon-silicon interconnect 106. Depending on the embodiment regarding BEOL pre-metallization, contact formation in the PMD layer 104 may include one or more process loops, wherein different contacts 108 can be formed based on the desired connections associated with any upper-level metal structure, which may be formed as part of a multi-level interconnect scheme associated with the semiconductor device 100. Additionally, the contacts 108 may have different shape factors, for example, having highly variable circular, square, or rectangular cross-sections.

[0021] In a non-limiting manner, this document describes several examples of contact formation. In some embodiments, the contact may comprise a titanium adhesive liner formed by a sputtering process. In some embodiments, the contact may comprise a titanium nitride (TiN) or tantalum nitride (TaN) barrier liner, for example, wherein copper is used for contact formation, situated on the adhesive liner. The barrier liner can be formed by reactive sputtering processes, atomic layer deposition (ALD) processes, etc., and can comprise various metal / oxide / nitride compositions. In some embodiments, the contact may comprise a tungsten-filled plug situated on the barrier liner, formed by a reducing metal-organic chemical vapor deposition (MOCVD) process comprising tungsten hexafluoride. In some embodiments, any excess portion of the filler metal, barrier liner, and adhesive liner on the top surface of PMD layer 104 can be removed by a CMP process, an etch-back process, or a combination of both.

[0022] exist Figure 1B In a representative example, contact 108 may include a tungsten plug having a thickness of approximately 0.02 µm to 0.4 µm (e.g., width, diameter, or a similar horizontal dimension along the X-axis) and a height of approximately 0.3 µm to 2 µm, depending on the implementation and consistent with PMD layer 104. Figure 1B The formation of a dielectric layer 116 with a suitable thickness (e.g., approximately 80 nm to 500 nm) is also shown, which may be formed over the PMD layer 104. In some instances, the dielectric layer 116 may serve as an intra-metal or inter-metal dielectric (IMD) layer comprising one or more sublayers and may comprise SiO2, undoped or doped silicate glass, spin-coated glass, fluorosilicate glass, or other low-k dielectric constant materials (e.g., dielectric constant less than about 4), which may be deposited using a suitable baseline procedure. In some instances, the dielectric layer 116 may be planarized, for example, using CMP and / or etch-back. Figure 1BThe process of forming one or more metal interconnect structures 118 in the dielectric layer 116 is further described. In some instances, the metal interconnect structure 118 may be formed as part of the fabrication of a first metal layer (e.g., containing copper), which may be configured as the first metallization level of a multi-level interconnect arrangement of the semiconductor device 100. In some instances, the first metal layer may be referred to as MET1, MT1, or M1, or a term with similar meaning. Where the metal interconnect structures 118 are fabricated as part of an upper metallization level for some instances, they may be referred to as MET2 interconnect structures, MET3 interconnect structures, etc. In such arrangements, one or more interlayer dielectric (ILD) layers and / or associated IMDs may be disposed between the PMD layer 104 and the dielectric layer 116. Regardless of the metallization level of the interconnect structures 118, they can be fabricated in a copper damascus process, wherein the interconnect structures 118 can be surrounded by a suitable barrier layer 120 to enhance the ohmic contact and adhesion of the interconnect structures 118 and to act as a barrier layer to prevent copper from diffusing or migrating into the surrounding dielectric material at the high temperatures that may be encountered during subsequent processing. In some arrangements, the barrier layer 120 may have a thickness of approximately 2 nm. Example diffusion / migration barrier materials may comprise transition metals such as Ta, W, and Ti, and their compositions with nitrogen (N), carbon (C), and / or silicon (Si), thereby producing refractory compounds comprising Ta / TaN, W₂N, TiN, TiC, TaSiN, Si₃N₄, etc. Additional and / or alternative examples herein may comprise barrier materials comprising: platinum group metals (PGMs), such as ruthenium (Ru)-based materials; self-assembled molecular layers (SAMs); and high-entropy alloys (HEAs).

[0023] Figure 1C The process of forming an etch stop layer 112 over a dielectric layer 116 is depicted. This etch stop layer can be used as an IMD layer as described above. In some instances, the etch stop layer 112 can also be used as a dielectric diffusion barrier layer. In some instances, the etch stop layer 112 can have a thickness of approximately 30 nm to 80 nm and can contain materials such as SiCN, SiC, SiCO, SiON, or Si3N4.

[0024] Figure 1DThe stages of forming a dielectric layer 122 over an etch stop layer 112 are described. The dielectric layer 122 may comprise various dielectric materials, including low-k dielectric materials, and may have a thickness of approximately 50 nm to 200 nm. In one embodiment, the dielectric layer 122 may comprise a tetraethyl orthosilicate (TEOS) layer. As will be explained below, according to some examples herein, the dielectric layer 122 may be configured as a “liner” for forming a TFR thereon. In some arrangements, for some example purposes, the liner dielectric layer 122 may be referred to as a first dielectric layer. As used herein, the terms “first dielectric layer,” “second dielectric layer,” etc., may refer to different dielectric layers of a semiconductor device formed after the FEOL process, depending on the type and / or metal level of the implemented TFR integration, and the terms “first dielectric layer,” “second dielectric layer,” etc., are not necessarily limited to… Figure 1D The dielectric layer 122 is shown. For example, in some arrangements, the first dielectric layer may refer to the dielectric layer formed after the formation of the TFR. In some instances, the second dielectric layer may refer to the dielectric layer formed after the formation of dielectric layer 122. In some instances, the second dielectric layer may refer to the dielectric layer formed after the formation of the TFR. In still other instances, terms such as "first dielectric layer," "second dielectric layer," and "third dielectric layer" may refer to various ILDs and / or IMDs formed in the BEOL process, depending on the hierarchy of metal layers arranged in the interconnect arrangement, and do not necessarily imply or limit any particular spatial orientation or hierarchical structure within a multi-level interconnect arrangement.

[0025] Figure 1E The stages for forming a resistive layer 124 over a dielectric layer 122 are described. The resistive layer 124 can be formed using thin-film deposition, patterning, and etching processes, wherein a first terminal portion 123A and a second terminal portion 123B of the resistive layer 124 can be configured to form corresponding end structures thereon, as will be described below. In the version of the examples herein, the terminal regions 123A / 123B may also be referred to as head regions or end regions of the resistive layer 124, wherein one or more electrical connections are made to the resistive material. The resistive layer 124 can be sized to have a suitable form factor, wherein a resistive body 127 with a suitable resistivity extends between the terminal portions 123A and 123B. For example, the resistive layer 124 can have a suitable thickness (e.g., approximately 3 nm to 50 nm or less) and a sufficient resistivity (e.g., greater than 100 μΩ-cm), and can contain various compositions containing at least one transition metal element suitable for TFR formation. In some implementations, the resistive layer 124 (also referred to in some instances as a TFR layer or simply TFR) may contain Si x Cr y C z O wExamples of compositions (in relative atomic percentages) of silicon-chromium (SiCr)-based mixtures, wherein x and y can range from 5% to 50%, while z and w can range from 0% to 50%. In another embodiment, for example, resistive layer 124 may comprise Ni x Cr y C z O w Examples of compositions (in relative atomic percentages) are nickel-chromium (NiCr)-based mixtures, where x and y can range from 5% to 50%, and z and w can range from 0% to 50%. In some instances, the desired resistive material for forming resistive layer 124 may comprise, but is not limited to, SiCr, NiCr, TaN, SiCCr (silicon carbide-chromium), AlNiCr (aluminum-nickel-chromium), or TiNiCr (titanium-nickel-chromium). Typically, such resistive materials may be desirable because they have low TCR (e.g., equal to or less than about 30 ppm / °C) and because resistive bodies containing such materials can tune their resistance using various baseline laser trimming processes.

[0026] Depending on the material used to form the resistive element of the TFR, the resistive layer 124 can be formed in various ways. Without limitation, in some instances, the resistive layer 124 can be deposited using physical vapor deposition (PVD) processes such as evaporation or sputtering. In some embodiments, depositing the resistive layer 124 may include annealing the layer 124 (e.g., first annealing in air at approximately 400°C for about 30 minutes, followed by annealing in a forming gas (e.g., 20% H2, balance N2) at approximately 400°C for about 30 minutes).

[0027] In some additional and / or alternative instances, a high-temperature annealing (HTA) process may be implemented to increase the resistivity of the TFR, such as resistive layer 124. In some arrangements, annealing temperatures of approximately 300°C to 650°C may be applied for shorter or longer periods (e.g., approximately 30 minutes) to increase the resistivity by a factor of three or more. Higher resistivity is generally desired in design layouts because, for a given electrical performance requirement, the size of the TFR can be reduced, thereby saving chip area in the semiconductor device (e.g., semiconductor device 100).

[0028] Figure 1FThe stages of forming a dielectric layer 126 over a resistive layer 124 are depicted. The dielectric layer 126 may comprise a layer with a thickness of approximately 100 nm to 150 nm and may comprise any suitable dielectric material, including low-k dielectric materials. In one embodiment, the dielectric layer 126 may comprise TEOS. Depending on the example, for the purposes of description, the dielectric layer 126 may be referred to as a first dielectric layer or a second dielectric layer. The dielectric layer 126 may be patterned and etched to form or define a pair of openings, also referred to as end trenches or orifices, over the respective terminal portions 123A and 123B of the resistive layer 124, wherein the openings may fall on or in the resistive terminal portions 123A and 123B. The remaining portion of the dielectric layer 126 (e.g., having a thickness of approximately 50 nm to 80 nm) may cover the resistive body 127 to provide protection during subsequent processing, as will be described below. In some arrangements, a TaN barrier layer of suitable thickness (e.g., approximately 30 nm to 100 nm) can be formed in each end trench. In the examples herein, TaN is used to form the corresponding TFR end structure to serve as a diffusion barrier layer between the copper via to be formed in the end structure and the resistor layer 124. Additionally, because TaN has a lower etch rate compared to TEOS, the via etching process involving the formation of both the TFR via and any interlayer vias can be configured to prevent the TFR via from penetrating into the terminal portion (e.g., end through-hole), as will be further explained below. Furthermore, in some arrangements, TaN can also be used as a diffusion barrier layer during the formation of the copper via, thereby promoting a uniform interface between the via and the resistor end, while providing sufficient diffusion barrier capability according to the examples herein.

[0029] Figure 1G-1 The illustration depicts a stage in the semiconductor device 100 in which a metal barrier layer 128 comprising TaN is formed in terminal apertures 199A and 199B, the terminal apertures being formed over corresponding terminal portions 123A and 123B. In an exemplary version herein, the metal barrier layer 128 may be fabricated to contact a resistive layer 124 and vias to be formed thereon in the corresponding terminal apertures 199A and 199B. Reference numerals 125A and 125B refer to intermediate layers of the corresponding terminal structures associated with the resistive layer 124. In another variation, a dielectric diffusion barrier layer 130 may optionally be formed over the metal barrier layer 128 as part of the corresponding terminal structures 125A and 125B, as shown below. Figure 1G-2 As shown. Depending on the implementation, the dielectric diffusion barrier layer 130 may comprise SiN or a combination of SiN and TEOS, with a total thickness ranging from approximately 40 nm to 200 nm. Although subsequent fabrication stages involve the arrangement of the end structures 125A and 125B containing the dielectric diffusion barrier layer 130, these stages are equally applicable with any relevant modifications. Figure 1G-1 The arrangement shown in the figure does not include the dielectric diffusion barrier layer 130 in the end structures 125A and 125B.

[0030] Figure 1H The stages of forming a dielectric layer 132 in a semiconductor device 100 are described. This dielectric layer may be planarized (e.g., CMP and / or etch-back) to have a thickness of approximately 400 nm to 600 nm. In some instances, the dielectric layer 132 may serve as an ILD / IMD layer and may comprise one or more sublayers containing SiO2, undoped or doped silicate glass, spin-coated glass, fluorosilicate glass, or other low-k dielectric constant materials (e.g., dielectric constant less than about 4). In some arrangements, a suitable baseline procedure similar to that described for dielectric layer 116 can be used to form the dielectric layer 132.

[0031] Figure 1I The diagram depicts the stages of forming conductive vias 134A and 134B and corresponding metal interconnect structures 138A and 138B in a semiconductor device 100 using a suitable copper damask process, in via patterning and etching processes, and subsequently in metal patterning and etching processes. As shown, metal interconnect traces 138A and 138B can be formed as part of fabricating a second metal layer (e.g., containing copper), which can be configured as a second metallization level (e.g., MET2, MT2, or M2, or similar terms) in a multi-level interconnect arrangement of the semiconductor device 100. Depending on the implementation within the multi-level interconnect arrangement, the metal interconnect structures 138A and 138B can be configured as terminals and / or interconnect traces that can be appropriately wired.

[0032] In some embodiments, the patterned via apertures may include underlayer anti-reflective coating (BARC) filling and etch-back during photolithography. As part of the copper BEOL process, the via apertures may be filled with copper (or other conductive material), annealed, and polished (e.g., via CMP). In some embodiments, a barrier layer or seed layer may be deposited, which may include a copper diffusion barrier layer containing the same material (e.g., TaN) as the metal barrier layer 128 of the end structures 125A, 125B. Similarly, the damascus formation of the metal interconnect traces 138A and 138B may include the formation of a TaN diffusion barrier layer. As an illustration, Figure 1IReference numeral 136 in the figures refers to a via and interconnect trace diffusion barrier layer, wherein the via diffusion barrier layer 136 contacts the end diffusion barrier layer 128. While the examples herein illustrate a TaN-based embodiment with respect to the end diffusion barrier layer 128 and the via diffusion barrier layer 136, the description is not limited thereto. In some additional and / or alternative examples, material compositions comprising Ta, Ta-Si-N, W, WN, and W-Si-N can be used to form the end diffusion barrier layer 128 and the via diffusion barrier layer 136 relative to a TFR integration scheme.

[0033] In some arrangements, one or more interlayer vias can also be formed during the formation of conductive vias 134A and 134B associated with the TFR end structures 125A and 125B. For example... Figure 1I As shown, an interlayer via 142 can be formed, extending from a metal interconnect trace 140 coplanar with metal interconnect traces 138A and 138B to a lower-level metal interconnect trace, such as copper interconnect structure 118. Similar to conductive vias 134A and 134B (also known as TFR end vias), the formation of the interlayer via 142 may include the formation of a diffusion barrier layer 137. In the example arrangement herein, the via etching process can be configured such that the differential selectivity of etching relative to dielectric layers 122 and 126 on the TaN barrier layer 128 can be used to prevent end punch-through during the formation of end vias 134A and 134B, while the potentially longer interlayer via 142 is also being formed.

[0034] Figure 1J The stages of forming an etch stop layer 144 in a semiconductor device 100 are depicted. This etch stop layer can facilitate the fabrication of additional or next-level metal interconnect structures for a multi-level Cu interconnect scheme associated with the semiconductor device 100. In some instances, the etch stop layer 144 may have a thickness of approximately 30 nm to 80 nm and may contain a material similar to the previously described etch stop layer 112. Depending on the application, one or more additional TFRs having end structures similar to end structures 125A and 125B can be fabricated at the same or different metallization levels, where the TFRs can be configured as, for example, part of a resistive ladder network. Metal interconnect structures (e.g., traces 138A and 138B) disposed at corresponding levels can be configured as horizontal wiring layers, which can be used to provide access and / or connections relative to the TFR resistive layer 124, wherein the horizontal wiring layers can be wired to appropriate electrical nodes associated with the semiconductor device 100, such as bonding pads, etc. (not shown in the figure). Although in Figure 1JNot specifically shown, but the semiconductor device 100 may include a protective capping (PO) layer formed above the topmost metallization layer. Depending on the embodiment, the PO layer may have a total thickness of tens or hundreds of nanometers (nm) to several micrometers (µm), and the PO layer may comprise one or more layers or sublayers of an insulating material (e.g., SiN, SiO, oxynitride, polyimide, etc.), which may be deposited as part of a BEOL process flow.

[0035] although Figure 1A-1J The examples shown illustrate TFR integration schemes within a two-level metal interconnect scheme. However, in some additional and / or alternative examples, metal interconnect structure 118 broadly represents a lower-level (e.g., the (N-1)th level) metal trace, and metal interconnect structures 138A / B and 140 broadly represent higher-level (e.g., the Nth level) metal traces of a multi-level interconnect that can be disposed together with semiconductor device 100. Furthermore, although the examples herein show TFR arrangements in which each terminal region contains a single electrical connection, this specification is not limited thereto. In some versions of the examples, the terminal regions of the TFR may be provided with multiple electrical connections, wherein each electrical connection can be implemented by a corresponding via structure having a blocking metal layer as described above. Additionally, some example TFR arrangements may have one or more electrical connections formed at various locations along the resistive layer, in addition to the electrical connections provided at the corresponding terminal regions of the resistive layer. These one or more electrical connections are configured as “tap” for reference measurements or other purposes (e.g., variable resistor or rheostat applications), wherein these electrical connections can be connected to different nodes of the interconnect circuit.

[0036] Figure 2 and 3 These are flowcharts related to IC manufacturing methods, based on some examples from this specification. Figure 2 The method 200 shown may begin by forming a resistive layer over a semiconductor substrate (box 202), which may involve some aspects of the fabrication process of the resistive layer 124 described above. A first dielectric layer, such as dielectric layer 126, may be formed over the resistive layer, as illustrated in box 204. At box 206, a metal barrier layer may be formed that contacts the resistive layer through an opening in the first dielectric layer, wherein the opening is formed above the end of the resistive layer, which may involve... Figure 1G-1 and Figure 1G-2 This describes some aspects of the end structure formation. At frame 208, a conductive via can be formed, extending through a second dielectric layer above the resistive layer to a metal barrier layer, wherein the metal barrier layer contacts both the conductive via and the resistive layer. This may involve, for example... Figure 1IThis document describes some aspects of the fabrication of vias 134A and 134B. In the illustrative version of this document, the first and second dielectric layers may contain various dielectric materials, depending on the implementation, the voltage level of the application, etc.

[0037] Figure 3 The method 300 shown illustrates a representative process with additional details according to some examples. At block 302, a resistive layer may be formed over the dielectric liner (e.g., the first dielectric layer containing TEOS) above the ILD etch stop layer of the BEOL interconnect level, which may involve Figure 1E Some aspects are shown. At box 304, a second dielectric layer (e.g., containing TEOS) may be formed over the resistive layer, which may involve Figure 1F Some aspects are shown. In some arrangements, a portion of the second dielectric layer remaining after the end trench is formed can be used to cover and protect the resistor body portion of the resistor layer during end fabrication. At block 306, the second dielectric layer can be patterned to form an end trench or opening above the terminal region in the resistor layer, wherein the end trench and the exposed terminal region can be used to form a TFR end and a through-hole therein.

[0038] Compared to Figure 1G-1 and 1G-2 In some aspects, a metal barrier layer (e.g., TaN) can be formed in the end trench, as illustrated in box 308. An optional dielectric layer (e.g., SiN) can be formed over the metal barrier layer in the end trench, as illustrated in box 310. Relative to Figure 1H In some aspects, the ILD layer can be deposited over the end trench and over a second TEOS layer remaining above the TFR body region (box 312). At box 314, a through-hole can be formed through the ILD material in the end trench, the through-hole falling on the metal barrier layer of the corresponding end trench, which may involve... Figure 1I Some aspects. At frame 316, a copper through-hole can be formed in the through-hole opening using a damascus process, wherein the copper through-hole can have a barrier layer comprising the same material as the metal barrier layer of the end trench, which may involve, as described above. Figure 1I In some aspects. Subsequently, the damascus process can be used to form metal interconnect traces at appropriate metal levels to couple to vias, as described above. Figure 1J As described in the text.

[0039] While various examples have been described above, these examples are illustrative only and not intended to be limiting. Many changes may be made to the described examples without departing from the spirit or scope of this specification. Therefore, the breadth and scope of this specification are not limited by any of the foregoing examples. Rather, the scope of this specification is defined in the appended claims and their equivalents.

[0040] For example, in this specification and the appended claims, unless otherwise stated and / or specified to the contrary, any one or more layers set forth herein may be formed in any number of suitable manners, such as using spin coating, sputtering (e.g., magnetron and / or ion beam sputtering), (thermal) growth, or deposition techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD). As another example, silicon nitride may be silicon-rich silicon nitride or oxygen-rich silicon nitride. Silicon nitride may contain some oxygen, but not so much that the dielectric constant of the material differs significantly from that of high-purity silicon nitride.

[0041] Additionally, in at least some additional or alternative embodiments, the functions / actions described in the boxes may not occur in the order shown in the flowchart. For example, depending on the functions / actions involved, two boxes shown consecutively may actually be performed substantially simultaneously, or the boxes may sometimes be performed in reverse order. Furthermore, the function of a given box in a flowchart and / or block diagram may be divided into multiple boxes, and / or the functions of two or more boxes in a flowchart and / or block diagram may be at least partially integrated. Additionally, some boxes in the flowchart may be optionally omitted. Furthermore, although some figures include arrows on communication paths to indicate the primary communication direction, communication may occur in the opposite direction to the depicted arrows. Finally, additional boxes may be added / inserted between the illustrated boxes.

[0042] The order or sequence of actions, steps, functions, components, or blocks illustrated in any of the flowcharts and / or block diagrams depicted in the accompanying drawings of this specification may be modified, altered, replaced, customized, or otherwise rearranged within a particular flowchart or block diagram, including deleting or omitting specific actions, steps, functions, components, or blocks. Furthermore, actions, steps, functions, components, or blocks illustrated in a particular flowchart may be mixed with or otherwise arranged or rearranged with actions, steps, functions, components, or blocks illustrated in another flowchart to allow for additional changes, modifications, and configurations relative to one or more processes for the purpose of practicing the teachings of this specification. Similarly, while various examples have been described herein, not all features of a particular example are necessarily limited to or necessary for that example.

[0043] At least some of the foregoing description may contain specific directional terms, such as “upper,” “lower,” “top,” “bottom,” “left,” “right,” “front,” “rear,” “vertical,” “horizontal,” etc., which may be used with reference to the orientation of some of the accompanying drawings or their illustrative elements. Since components in some instances may be located in multiple different orientations, the directional terms are used for illustrative purposes and are by no means limiting. Similarly, references to features referred to as “first,” “second,” etc., do not indicate any particular order, importance, etc., and such references may be interchanged depending on the context, embodiment, etc. Furthermore, terms such as “above,” “below,” “under,” etc., relative to the spatial orientation of two components do not necessarily mean that one component is directly above, below, or under another component. Additionally, unless otherwise specifically indicated, features and / or components of the instances described herein may be combined with each other.

[0044] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or instance. None of the above detailed descriptions implies that any particular component, element, step, action, or function is so essential that it must be included within the scope of the claims. In the case of phrases such as “at least one of A and B” or similar phrases, such phrases mean “only A,” “only B,” or both A and B.” Unless explicitly stated otherwise, references to singular elements do not mean “one and only one,” but rather “one or more.” Similarly, depending on the context, phrases such as “a plurality” or “multiple” may mean “one or more” or “at least one.” All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference and are covered by the appended claims.

[0045] Within the scope of the claims, modifications may be made in the described examples, and other examples are possible.

Claims

1. An integrated circuit (IC) comprising: The dielectric layer located above the semiconductor substrate; A resistive layer located above the dielectric layer; Metal interconnect traces are located above the ends of the resistive layer; A via extending from the metal interconnect trace toward the resistive layer; as well as A metal barrier layer is located between the via and the resistive layer, and the metal barrier layer is in contact with the via and the resistive layer.

2. The IC of claim 1, wherein the metal barrier layer comprises a barrier material, and the barrier material surrounds the via and the metal interconnect trace.

3. The IC according to claim 1, wherein the metal interconnect traces and the vias are copper damask structures.

4. The IC according to claim 1, wherein the resistive layer comprises silicon-chromium (SiCr).

5. The IC of claim 1, wherein the dielectric layer is a first dielectric layer, and the IC further includes a second dielectric layer located above the first dielectric layer, wherein the via extends through the second dielectric layer and the third dielectric layer to the metal barrier layer.

6. The IC of claim 1, wherein the metal interconnect trace is a first interconnect trace, and the via is a first via, and the IC further comprises: A second interconnect trace that is coplanar with the first interconnect trace; A third interconnect trace located below the second interconnect trace; as well as A second via connects the second interconnect trace and the third interconnect trace, the second via extending through the dielectric layer.

7. The IC of claim 6, wherein the first interconnect trace is a third metal-level trace, and the second interconnect trace is a second metal-level trace.

8. The IC of claim 1, wherein the terminal is a first terminal, the metal interconnect trace is a first interconnect trace, the metal barrier layer is a first metal barrier layer, and the via is a first via, and the IC further comprises: A second metal interconnect trace that is coplanar with the first interconnect trace; A second via extending from the second metal interconnect trace toward the second end of the resistive layer; as well as A second metal barrier layer is located between the second via and the resistive layer.

9. The IC of claim 8, wherein the second metal barrier layer comprises a barrier material, and the barrier material surrounds the second via and the second metal interconnect trace.

10. The IC of claim 9, wherein the blocking material comprises a material selected from the group consisting of TaN, Ta, Ta-Si-N, W, WN, and W-Si-N.

11. A method for forming an integrated circuit, comprising: A resistive layer is formed above a semiconductor substrate; A first dielectric layer is formed above the resistive layer; A metal barrier layer is formed, which contacts the resistive layer through an opening in the first dielectric layer; as well as A conductive via is formed, which extends through a second dielectric layer above the resistive layer to the metal barrier layer, the metal barrier layer being in contact with the conductive via and the resistive layer.

12. The method of claim 11, wherein the metal barrier layer comprises a barrier material, and the barrier material surrounds the conductive via.

13. The method of claim 12, wherein the barrier material comprises a material selected from the group consisting of TaN, Ta, Ta-Si-N, W, WN, and W-Si-N.

14. The method of claim 11, wherein the resistive layer comprises silicon-chromium (SiCr).

15. The method of claim 11, wherein the opening is formed above the end of the resistive layer, and the method further comprises forming a dielectric barrier layer above the metal barrier layer in the opening prior to forming the second dielectric layer.

16. The method of claim 15, wherein the dielectric barrier layer comprises silicon nitride.

17. The method of claim 11, wherein the conductive via is a first conductive via, and the method further comprises forming a second conductive via extending from an upper metal interconnect trace through the second dielectric layer and the first dielectric layer to a metal interconnect trace located below the resistive layer.

18. The method of claim 17, wherein the first conductive via, the second conductive via, and the metal interconnect trace are copper damask structures.

19. The method of claim 11, wherein the first dielectric layer and the second dielectric layer comprise material layers having an etch rate higher than that of the metal barrier layer during via etching.

20. A method comprising: A first dielectric layer is formed above the semiconductor substrate; A resistive layer is formed above the first dielectric layer; A second dielectric layer is formed above the resistive layer; The second dielectric layer is patterned to form an end trench over the end region of the resistive layer, and the remaining portion of the second dielectric layer covers the resistor body spanning between the end regions of the resistive layer; A metal barrier layer is formed in the end groove; An interlayer dielectric (ILD) layer is deposited over the end trench and the remaining portion of the second dielectric layer; Through-holes are formed in or through the ILD layer, each through-hole falling onto the metal barrier layer in a corresponding end trench; and A metal interconnect trace is formed above the via and in electrical contact with the via, the metal interconnect trace and the via being surrounded by the same barrier material as the metal barrier layer.

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