Light detection device

Abstract

This invention reduces dark current and suppresses the decrease in quantum efficiency. The photodetector includes: a semiconductor layer having a thickness in one direction; a photoelectric conversion region disposed in the semiconductor layer and separated by a separation region; and a photoelectric conversion section disposed in the photoelectric conversion region and configured to perform photoelectric conversion from light to signal charge. The separation region includes: a digging section disposed in the semiconductor layer and extending in the one direction; a fixed charge film having a fixed charge and disposed along a side portion of the digging section; and a metal film disposed inside the digging section along the fixed charge film.

Description

Technical Field

[0001] This technology (based on the technology disclosed herein) relates to a light detection device, and more specifically, to a technology effective when used in light detection devices where the photoelectric conversion region is separated from each other by a digging-type separation region. Background Technology

[0002] In image sensors (light detection devices) such as rangefinders or solid-state imaging devices, the photoelectric conversion regions of the semiconductor layer are separated by mined-out separation regions to suppress color mixing between pixels. In this type of image sensor, reducing dark current is a crucial indicator of image quality.

[0003] Patent document 1 discloses a technique for reducing dark current by setting a high concentration of doped regions on the photoelectric conversion region side of the interface between the mining separation region and the photoelectric conversion region to increase the hole density of the interface.

[0004] In addition, Patent Document 2 discloses a technique for reducing dark current by providing a fixed charge film containing a negative fixed charge on the inner side of the excavation section to accumulate holes at the interface between the excavation separation region and the photoelectric conversion region.

[0005] In addition, Patent Document 3 discloses a technique for suppressing dark current generation by embedding a polycrystalline silicon electrode inside the excavation section and applying a negative potential to the polycrystalline silicon electrode to accumulate holes at the interface between the excavation-type separation region and the photoelectric conversion region.

[0006] Citation List

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2022-056360

[0009] Patent Document 2: Japanese Patent Application Publication No. 2013-175494

[0010] Patent Document 3: Japanese Patent Application Publication No. 2022-018088 Summary of the Invention

[0011] The problem the invention aims to solve

[0012] However, in the excavation separation region, when conductive materials such as conductive polycrystalline silicon or metal are embedded inside the excavation section, the conductive materials absorb the light incident on the image sensor, resulting in a decrease in quantum efficiency.

[0013] Furthermore, conductive polysilicon requires heat treatment at temperatures above 500°C to reduce resistance, and the fixed charge film that deactivates at high temperatures is difficult to combine with the technique of setting a polysilicon electrode on the inside of the excavation section and applying a negative potential to the polysilicon electrode to reduce dark current.

[0014] The purpose of this technology is to provide a technique that can reduce dark current and suppress the reduction of quantum efficiency.

[0015] Solution to the problem

[0016] (1) A light detection device according to one aspect of the present technology includes:

[0017] A semiconductor layer having a thickness in one direction;

[0018] A photoelectric conversion region, which is disposed in the semiconductor layer and separated by a separation region; and

[0019] A photoelectric conversion unit is disposed in the photoelectric conversion region and is configured to perform photoelectric conversion from light to signal charge.

[0020] Then, the separation region includes:

[0021] A mining section is disposed in the semiconductor layer and extends in the one direction;

[0022] A fixed charge film having a fixed charge and disposed along the side portion of the excavation section; and

[0023] A metal film is disposed along the fixed charge film on the inner side of the excavation section.

[0024] (2) The optical detection device according to another aspect of the present technology includes:

[0025] A semiconductor layer having a thickness in one direction;

[0026] A photoelectric conversion region, which is disposed in the semiconductor layer and separated by a separation region; and

[0027] A photoelectric conversion unit is disposed in the photoelectric conversion region and is configured to perform photoelectric conversion from light to signal charge.

[0028] Then, the separation region includes:

[0029] A mining section is disposed in the semiconductor layer and extends in the one direction;

[0030] A separation insulating film is disposed on the inner side of the excavated portion along the side portion of the semiconductor layer; and

[0031] A metal film is disposed along the insulating film on the inner side of the excavation section. Attached Figure Description

[0032] Figure 1 This is a chip layout diagram illustrating a configuration example of a solid-state imaging device according to a first embodiment of the present technology.

[0033] Figure 2 This is a block diagram illustrating an example of the configuration of a solid-state imaging device according to a first embodiment of the present technology.

[0034] Figure 3 This is an equivalent circuit diagram illustrating an example of the configuration of a pixel and pixel circuit according to a first embodiment of the present technology.

[0035] Figure 4 It is shown schematically. Figure 1 A plan view of an example of the composition of pixel blocks included in a pixel array section.

[0036] Figure 5 It is an illustrative representation of along Figure 4 The longitudinal section diagram of the structure is taken from the section line a4-a4.

[0037] Figure 6 yes Figure 5 An enlarged longitudinal section view of a portion of the data.

[0038] Figure 7 It is an illustrative representation of along Figure 5 The cross-sectional view of the cross-sectional structure cut by section line a5-a5.

[0039] Figure 8 It is an illustrative representation of along Figure 5 The cross-sectional view of the cross-sectional structure is taken by section line b5-b5.

[0040] Figure 9 It is an illustrative representation of along Figure 5 The cross-sectional view of the cross-sectional structure cut by section line c5-c5.

[0041] Figure 10A It is an illustrative representation of along Figure 1 The longitudinal section diagram of the longitudinal section structure is taken from section line 1a-1a.

[0042] Figure 10B It is an illustrative representation of along Figure 1 The longitudinal section diagram of the longitudinal section structure is taken from section line 1a-1a.

[0043] Figure 11A This is a longitudinal cross-sectional view schematically illustrating the steps in a method for manufacturing a solid-state imaging device according to a first embodiment of the present technology.

[0044] Figure 11B It is shown schematically. Figure 11A The longitudinal section view of the steps following the steps.

[0045] Figure 11C It is shown schematically. Figure 11B The longitudinal section view of the steps following the steps.

[0046] Figure 11D It is shown schematically. Figure 11C The longitudinal section view of the steps following the steps.

[0047] Figure 11E It is shown schematically. Figure 11D The longitudinal section view of the steps following the steps.

[0048] Figure 11F It is shown schematically. Figure 11E The longitudinal section view of the steps following the steps.

[0049] Figure 11G It is shown schematically. Figure 11F The longitudinal section view of the steps following the steps.

[0050] Figure 11H It is shown schematically. Figure 11G The longitudinal section view of the steps following the steps.

[0051] Figure 11I It is shown schematically. Figure 11H The longitudinal section view of the steps following the steps.

[0052] Figure 11J It is shown schematically. Figure 11I The longitudinal section view of the steps following the steps.

[0053] Figure 11K It is shown schematically. Figure 11J The longitudinal section view of the steps following the steps.

[0054] Figure 11L It is shown schematically. Figure 11K The longitudinal section view of the steps following the steps.

[0055] Figure 11M It is shown schematically. Figure 11L The longitudinal section view of the steps following the steps.

[0056] Figure 11N It is shown schematically. Figure 11M The longitudinal section view of the steps following the steps.

[0057] Figure 11O It is shown schematically. Figure 11N The longitudinal section view of the steps following the steps.

[0058] Figure 12 It is a diagram showing a variation 1-1 of the first embodiment of the present invention, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0059] Figure 13 The figure shows variations 1-2 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0060] Figure 14 The figure shows variations 1-3 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0061] Figure 15 The figure shows variations 1-4 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0062] Figure 16 The figure shows variations 1-5 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0063] Figure 17 The figure shows variations 1-6 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0064] Figure 18 The figure shows variations 1-7 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0065] Figure 19 The figure shows variations 1-8 of the first embodiment of the present invention, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0066] Figure 20 The figure shows variations 1-9 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0067] Figure 21 The figure shows variations 1-10 of the first embodiment of the present invention, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0068] Figure 22It is a diagram showing variations 1-11 of the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0069] Figure 23A The figure shows variations 1-12 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0070] Figure 23B It is an illustrative representation of along Figure 23A The cross-sectional view of the cross-sectional structure cut by section line a23-a23.

[0071] Figure 24A It is a diagram showing variations 1-13 of the first embodiment of the present technology, and a plan view schematically showing an example of the composition of a pixel block.

[0072] Figure 24B It is an illustrative representation along Figure 24A The longitudinal section diagram of the longitudinal section structure is taken from section line a24-a24.

[0073] Figure 25 It is a figure showing variations 1-14 of the first embodiment of the present invention, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0074] Figure 26 This is a diagram illustrating a solid-state imaging apparatus according to a second embodiment of the present technology, and is a plan view schematically illustrating an example of the configuration of a pixel block.

[0075] Figure 27 It is an illustrative representation along Figure 26 The longitudinal section diagram of the longitudinal section structure is taken from section line a26-a26.

[0076] Figure 28 It is an illustrative representation along Figure 27 The cross-sectional view of the cross-sectional structure taken by section line a27-a27.

[0077] Figure 29 This is a schematic diagram illustrating a variation 2-1 according to the first embodiment of the present technology, and is schematically shown in relation to... Figure 27 A cross-sectional view of the cross-sectional structure at the same position as section line b27-b27.

[0078] Figure 30 This is a diagram illustrating a solid-state imaging apparatus according to a third embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of a pixel.

[0079] Figure 31It is an illustrative representation along Figure 30 The cross-sectional view of the cross-sectional structure cut by section line a30-a30.

[0080] Figure 32 This is a diagram illustrating a solid-state imaging apparatus according to a fourth embodiment of the present technology, and is a plan view schematically illustrating an example of the configuration of a pixel block.

[0081] Figure 33 It is an illustrative representation along Figure 32 The longitudinal section diagram of the longitudinal section structure taken by section line a32-a32.

[0082] Figure 34 This is a diagram illustrating a solid-state imaging apparatus according to a fifth embodiment of the present technology, and is a plan view schematically illustrating an example of the configuration of a pixel block.

[0083] Figure 35 It is an illustrative representation along Figure 34 The longitudinal section diagram of the longitudinal section structure is taken from section line a34-a34.

[0084] Figure 36 This is a diagram illustrating a solid-state imaging apparatus according to a sixth embodiment of the present technology, and is a plan view schematically illustrating an example of the configuration of a pixel block.

[0085] Figure 37 It is an illustrative representation along Figure 36 The longitudinal section diagram of the longitudinal section structure taken by section line a36-a36.

[0086] Figure 38 This is a schematic longitudinal cross-sectional view illustrating the longitudinal cross-sectional structure of a solid-state imaging device according to the seventh embodiment of the present technology.

[0087] Figure 39 This is a schematic longitudinal cross-sectional view illustrating the longitudinal cross-sectional structure of a solid-state imaging device according to the eighth embodiment of the present technology.

[0088] Figure 40 yes Figure 39 An enlarged longitudinal section view of a portion of the data.

[0089] Figure 41A This is a schematic longitudinal cross-sectional view illustrating the longitudinal cross-sectional structure of a solid-state imaging device according to the ninth embodiment of the present technology.

[0090] Figure 41B It is shown schematically. Figure 41A The following is a longitudinal section diagram of the longitudinal section structure.

[0091] Figure 41C It is shown schematically. Figure 41B The following is a longitudinal section diagram of the longitudinal section structure.

[0092] Figure 42 This is a diagram showing a solid-state imaging apparatus according to a tenth embodiment of the present technology, and is a plan view schematically showing an example of the configuration of pixel blocks included in the pixel array section.

[0093] Figure 43 It is an illustrative representation of along Figure 42 The longitudinal section diagram of the longitudinal section structure is taken from the section line a42-a42.

[0094] Figure 44 yes Figure 43 An enlarged longitudinal section view of a portion of the data.

[0095] Figure 45 It is an illustrative representation of along Figure 43 The cross-sectional view of the cross-sectional structure cut by section line a43-a43.

[0096] Figure 46 It is an illustrative representation of along Figure 43 The cross-sectional view of the cross-sectional structure taken by section line b43-b43.

[0097] Figure 47 It is an illustrative representation of along Figure 43 The cross-sectional view of the cross-sectional structure cut by section line c43-c43.

[0098] Figure 48A It is an illustrative representation of... Figure 1 The longitudinal section diagram of the longitudinal section structure at the same position as section line 1a-1a.

[0099] Figure 48B It is an illustrative representation of... Figure 1 At the same position of section line 1a-1a Figure 48A The following is a longitudinal section diagram of the longitudinal section structure.

[0100] Figure 49A This is a schematic longitudinal cross-sectional view illustrating the steps in a method for manufacturing a solid-state imaging device according to a tenth embodiment of the present technology.

[0101] Figure 49B It is shown schematically. Figure 49A The longitudinal section view of the steps following the steps.

[0102] Figure 49C It is shown schematically. Figure 49B The longitudinal section view of the steps following the steps.

[0103] Figure 49D It is shown schematically. Figure 49C The longitudinal section view of the steps following the steps.

[0104] Figure 49EIt is shown schematically. Figure 49D The longitudinal section view of the steps following the steps.

[0105] Figure 49F It is shown schematically. Figure 49E The longitudinal section view of the steps following the steps.

[0106] Figure 49G It is shown schematically. Figure 49F The longitudinal section view of the steps following the steps.

[0107] Figure 49H It is shown schematically. Figure 49G The longitudinal section view of the steps following the steps.

[0108] Figure 49I It is shown schematically. Figure 49H The longitudinal section view of the steps following the steps.

[0109] Figure 49J It is shown schematically. Figure 49I The longitudinal section view of the steps following the steps.

[0110] Figure 50 This is a diagram showing a variation 10-1 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0111] Figure 51 This is a diagram showing a variation 10-2 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0112] Figure 52 It is a diagram showing a variation 10-3 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0113] Figure 53A It is a diagram showing a variation 10-3 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the steps of the manufacturing method.

[0114] Figure 53B It is shown schematically. Figure 53A The longitudinal section view of the steps following the steps.

[0115] Figure 53C It is shown schematically. Figure 53B The longitudinal section view of the steps following the steps.

[0116] Figure 54This is a diagram showing a variation 10-4 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0117] Figure 55 It is a diagram showing a variation 10-5 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0118] Figure 56 It is a diagram showing a variation 10-6 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0119] Figure 57 It is a diagram showing a variation 10-7 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0120] Figure 58 This is a diagram showing a solid-state imaging device according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0121] Figure 59 It is a diagram showing a variation 11-1 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0122] Figure 60 It is a diagram showing a variation 11-2 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0123] Figure 61 It is a diagram showing a variation 11-3 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0124] Figure 62 It is a diagram showing a variation 11-4 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0125] Figure 63 It is a diagram showing a variation 11-5 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0126] Figure 64It is a diagram showing a variation 11-6 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0127] Figure 65 It is a diagram showing a variation 11-7 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0128] Figure 66 This is a diagram illustrating a schematic configuration of an electronic device according to the twelfth embodiment of the present technology. Detailed Implementation

[0129] The implementation scheme of this technology will be described below with reference to the accompanying drawings.

[0130] Note that in the accompanying drawings referenced in the following description, identical or similar parts are indicated by identical or similar reference numerals. Note that the drawings are schematic, and the relationships between thicknesses and planar dimensions, the thickness ratios of different layers, etc., may differ from actual dimensions. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0131] Furthermore, the accompanying drawings include portions with different dimensional relationships and ratios between the drawings. Additionally, the advantageous effects described in this specification are merely exemplary and not limiting; other effects may also exist.

[0132] Furthermore, the following embodiments illustrate apparatus and methods for embodying the technical concept of this technology, and are not intended to limit the construction to those described below. That is, the technical concept of this technology can be modified in various ways within the scope of the technology described in the appended claims.

[0133] Furthermore, the definitions of directions such as up and down in the following description are merely for illustrative purposes and are not intended to limit the technical concept of this technology. For example, when the object is rotated 90° and observed, up and down will be converted to left and right and read out, while when the object is rotated 180° and observed, up and down will be reversed and read out.

[0134] Furthermore, in the following implementation, an example will be given by the case where the first conductivity type is n-type and the second conductivity type is p-type; however, the conductivity types can be selected to have the opposite relationship, that is, the first conductivity type can be p-type and the second conductivity type can be n-type.

[0135] Furthermore, in the following embodiments, among the three directions orthogonal to each other in space, the first and second directions orthogonal to each other in the same plane are defined as the X direction and the Y direction, respectively, and the third direction orthogonal to each of the first and second directions is defined as the Z direction. Then, in the following embodiments, the thickness direction of the semiconductor layer 21, described later, is defined as the Z direction.

[0136] Furthermore, in the following implementation, the Z direction will be described as "one direction" of this technology.

[0137] Furthermore, in the following embodiments, a plan view refers to the view of semiconductor layer 21 from the Z direction (one direction). A longitudinal section view refers to the view of a section taken along the Z direction (one direction) from a direction orthogonal to the section (X direction or Y direction), and a cross-sectional view refers to the view of a section orthogonal to the Z direction from the Z direction.

[0138] [First Implementation Plan]

[0139] In the first embodiment, as a light detection device, an example of how this technology is applied to a solid-state imaging device as a back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor will be described.

[0140] Furthermore, in the first embodiment, a pixel with a photoelectric conversion unit will be described in each photoelectric conversion region.

[0141] <<Overall Composition of Solid-State Imaging Devices>>

[0142] First, the overall configuration of the solid-state imaging device 1A will be explained.

[0143] like Figure 1 As shown, the solid-state imaging device 1A according to the first embodiment of the present technology is constructed having a semiconductor chip 2 as its main body, the semiconductor chip having a square shape in a two-dimensional planar shape in a planar view. That is, the solid-state imaging device 1A is mounted in the semiconductor chip 2, and the semiconductor chip 2 can be regarded as the solid-state imaging device 1A. Figure 58 As shown, the solid-state imaging device 1A (101) acquires image light (incident light 106) from the subject via optical lens 102, converts the amount of light of the incident light 106 forming an image on the imaging surface into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal.

[0144] like Figure 1As shown, in a two-dimensional plane including mutually orthogonal X and Y directions, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted includes a square pixel array portion 2A disposed in the central part and a peripheral portion 2B disposed outside the pixel array portion 2A to surround the pixel array portion 2A. The semiconductor chip 2 is formed by dividing a semiconductor wafer, including the semiconductor layer 21 described later, into small pieces for each chip formation area during the manufacturing process. Therefore, the configuration of the solid-state imaging device 1A described below is generally similar in the wafer state before the semiconductor wafer is divided into small pieces. Therefore, this technology can be applied to both the state of the semiconductor chip and the state of the semiconductor wafer.

[0145] Note that the solid-state imaging device 1A can be packaged in various forms and mounted on electronic devices, or it can be directly mounted on electronic devices as a chip.

[0146] For example, pixel array section 2A is a receiver of... Figure 58 The optical lens (optical system) 102 shown is a light-receiving surface that converges light. Then, the pixel array section 2A includes an effective pixel region 2A1 and an optical black region 2A2 disposed outside the effective pixel region 2A1 to surround the effective pixel region 2A1 and output an optical reference black level.

[0147] In the pixel array 2A1, multiple pixels 3 (sensor pixels) are arranged in a matrix in a two-dimensional plane including the X and Y directions. In other words, the pixels 3 are repeatedly arranged in the two-dimensional plane along various directions orthogonal to each other in the X and Y directions. The optical black area 2A2 is covered by a light-shielding film 72.

[0148] like Figure 1 As shown, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides of a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 serves as an input / output terminal for electrically connecting the semiconductor chip 2 and an external device to each other. Then, although not shown in the figure, connecting members such as bonding wires or bump electrodes are connected to the respective bonding pads 14.

[0149] <Logic Circuits>

[0150] Semiconductor chip 2 includes, for example Figure 2 The logic circuit 13 shown is as follows. Figure 2As shown, logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, etc. Logic circuit 13 is constructed, for example, using a complementary MOS (CMOS) circuit, which has an n-channel conductive type metal-oxide-semiconductor field-effect transistor (MOSFET) and a p-channel conductive type MOSFET as field-effect transistors.

[0151] Figure 2 The vertical driving circuit 4 shown is, for example, composed of a shift register. The vertical driving circuit 4 sequentially selects the desired pixel driving lines 10, supplies pulses for driving the pixels 3 to the selected pixel driving lines 10, and drives the pixels 3 row by row. That is, the vertical driving circuit 4 sequentially and selectively scans each pixel 3 of the pixel array section 2A row by row in the vertical direction, and supplies the pixel signal from the pixel 3 to the column signal processing circuit 5 via the vertical signal line 11 based on the signal charge generated by the photoelectric conversion section of each pixel 3 according to the amount of received light.

[0152] For example, Figure 2 The column signal processing circuit 5 shown is configured for each column of pixels 3, and performs signal processing such as noise removal on the signal output from the pixel 3 corresponding to a row for each column of pixels. For example, the column signal processing circuit 5 performs signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion to remove fixed-pattern noise inherent in the pixels.

[0153] Figure 2 The horizontal drive circuit 6 shown is, for example, composed of a shift register. The horizontal drive circuit 6 sequentially selects each column signal processing circuit 5 by sequentially outputting horizontal scan pulses to the column signal processing circuit 5, and outputs the pixel signals that have undergone signal processing from each column signal circuit 5 to the horizontal signal line 12.

[0154] Figure 2 The output circuit 7 shown performs signal processing on the pixel signals sequentially supplied from each column signal processing circuit 5 via the horizontal signal line 12, and outputs the resulting pixel signal. For example, buffering, black level adjustment, column change correction, and various types of digital signal processing can be used for signal processing.

[0155] Figure 2 The control circuit 8 shown generates a clock signal or control signal based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal, serving as the reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signal or control signal to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0156] <pixel blocks>

[0157] Semiconductor chip 2 includes Figure 3 The pixel block 15 and pixel circuit (readout circuit) 16 are shown.

[0158] like Figure 3 and Figure 4 As shown, pixel block 15 includes a plurality of pixels 3. Pixel block 15 of the first embodiment includes, but is not limited to, for example... Figure 4 The four pixels shown are arranged in a 2 × 2 pattern (3a, 3b, 3c, and 3d), where two pixels are adjacent to each other in each of the X and Y directions of the planar diagram, forming a single unit. Although in Figure 3 and Figure 4 The image mainly shows a pixel block 15, but as Figure 1 As shown, pixel blocks 15 are repeatedly configured in each of the X and Y directions to construct... Figure 1 The pixel array section 2A shown.

[0159] like Figure 3 As shown, each of the four pixels 3a, 3b, 3c, and 3d included in a pixel block 15 includes common constituent elements. Specifically, each of the four pixels 3a, 3b, 3c, and 3d included in a pixel block 15 includes a photoelectric conversion unit 25 configured to perform photoelectric conversion from light to signal charge, a floating diffusion region FD serving as a charge holding unit to hold (accumulate) the signal charge photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR that transfers the signal charge photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. Furthermore, each of the four pixels 3a, 3b, 3c, and 3d included in a pixel block 15 also includes... Figure 5 The photoelectric conversion region 22 of the semiconductor layer 21 is shown. Then, as... Figure 4 and Figure 5 As shown, each of the photoelectric conversion unit 25, the floating diffusion region FD, and the transmission transistor TR is disposed in the photoelectric conversion region 22. Figure 5 Two pixels, 3a and 3d, are shown among the four pixels 3a, 3b, 3c and 3d included in a pixel block 15.

[0160] (Photoelectric Conversion Unit)

[0161] Figure 3 The photoelectric conversion unit 25 shown includes, for example, a pn junction type photodiode (PD) and generates a signal charge corresponding to the amount of light received. Furthermore, the photoelectric conversion unit 25 temporarily holds (accumulates) the generated signal charge.

[0162] The photoelectric conversion unit 25 has a cathode side electrically connected to the source region of the transmission transistor TR and an anode side electrically connected to a reference potential line (e.g., ground).

[0163] (Transmission transistor)

[0164] Figure 3 The transmission transistor TR shown transfers the signal charge converted by the photoelectric conversion unit 25 to the floating diffusion region FD. The transmission transistor TR has a source region electrically connected to the cathode side of the photoelectric conversion unit 25 and a drain region electrically connected to the floating diffusion region FD. Then, the gate electrode of the transmission transistor TR is electrically connected to... Figure 2 The transmission transistor driving line in the pixel driving line 10 shown.

[0165] (Floating diffusion area)

[0166] Figure 3 The floating diffusion region FD temporarily accumulates and retains the signal charge transmitted from the photoelectric conversion unit 25 via the transmission transistor TR.

[0167] <Pixel Circuit>

[0168] Figure 3 The input side of the pixel circuit (readout circuit) 16 shown is electrically connected to the floating diffusion region FD of pixel 3. For example, the pixel circuit 16 of the first embodiment is provided for each pixel block 15.

[0169] Here, in the first embodiment, as an example, a circuit configuration is used that assigns one pixel circuit 16 to a pixel block 15 comprising four pixels 3 as a unit. However, the assignment of pixel circuit 16 is not limited to the first embodiment. For example, a circuit configuration that assigns one pixel circuit 16 to a pixel block 15 comprising two or more pixels 3 as a unit can be used, or a circuit configuration that assigns one pixel circuit 16 to multiple pixel blocks 15 comprising multiple pixels 3 as a unit can be used. Furthermore, a circuit configuration that assigns one pixel circuit 16 to one pixel 3 can be used.

[0170] Figure 3 The pixel circuit 16 shown reads the signal charge held in the floating diffusion region FD of pixel 3 and outputs a pixel signal based on the read signal charge. In other words, the pixel circuit 6 converts the signal charge converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charge and outputs the pixel signal.

[0171] like Figure 3As shown, the pixel circuit 16 includes, but is not limited to, an amplifying transistor AMP, a selecting transistor SEL, a reset transistor RST, and a switching transistor FDG, which serve as the pixel transistor Q. The pixel transistor Q (AMP, SEL, RST, and FDG) and the aforementioned transmission transistor TR are constructed as insulated-gate field-effect transistors, for example, from metal-oxide-semiconductor field-effect transistors (MOSFETs) with a silicon oxide (SiO2) film as the gate insulating film. Alternatively, metal-insulating-semiconductor FETs (MISFETs) can be used as the pixel transistor Q and the transmission transistor TR, with their gate insulating film formed using a silicon nitride (Si3N4) film or a laminated film such as a silicon nitride film and a silicon oxide film.

[0172] Among the pixel transistors Q (AMP, SEL, RST, and FDG) included in the pixel circuit 16, the select transistor SEL, the reset transistor RST, and the switching transistor FDG are mainly used as switching elements. In addition, the remaining amplifying transistor AMP is mainly used as an amplifying element.

[0173] Figure 3 The amplifying transistor AMP shown has a source region electrically connected to the drain region of the select transistor SEL and a drain region electrically connected to the power line Vdd and the reset transistor RST. Furthermore, the gate electrode of the amplifying transistor AMP is electrically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) and the source region of the switching transistor FDG.

[0174] Figure 3 The selected transistor SEL shown has a source region electrically connected to the vertical signal line 11 (VSL) and a drain region electrically connected to the source region of the amplifying transistor AMP. Furthermore, the gate electrode of the selected transistor SEL is electrically connected to... Figure 2 The selected transistor driving line in the pixel driving line 10 shown.

[0175] Figure 3 The reset transistor RST shown has a source region electrically connected to the drain of the switching transistor FDG and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifying transistor AMP. The gate electrode of the reset transistor RST is then electrically connected to... Figure 2 The reset transistor driving line in the pixel driving line 10 shown.

[0176] like Figure 3 As shown, the switching transistor FDG has a source region electrically connected to the gate electrode of the amplifying transistor AMP and the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d), and a drain region electrically connected to the source region of the reset transistor RST. The gate electrode of the switching transistor FDG is then electrically connected to... Figure 2 The switching transistor driving line in the pixel driving line 10 shown.

[0177] Note that the selection transistor SEL and the switching transistor FDG can be omitted if needed.

[0178] When the select transistor SEL is omitted, the source region of the amplifying transistor AMP is electrically connected to the vertical signal line 11 (VSL). Furthermore, when the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode of the amplifying transistor AMP and the floating diffusion region FD.

[0179] When the transfer transistor TR is turned on Figure 3 The transmission transistor TR shown transmits the signal charge generated by the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0180] When the reset transistor RST is turned on Figure 3 The reset transistor RST shown resets the potential (signal charge) of the floating diffusion region FD to the potential of the power line Vdd.

[0181] Figure 3 The selection transistor SEL shown controls the output timing of the pixel signal from the pixel circuit 16.

[0182] Figure 3 The amplifying transistor AMP shown generates a signal as a pixel signal having a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplifying transistor AMP constitutes a source follower type amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifying transistor AMP amplifies the potential of the floating diffusion region FD and outputs the voltage corresponding to that potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0183] Figure 3 The switching transistor FDG shown controls the charge retention of the floating diffusion region FD and adjusts the amplification factor of the voltage corresponding to the potential amplified by the amplifying transistor AMP.

[0184] During operation of the solid-state imaging apparatus 1A according to the first embodiment, the signal charge generated in the photoelectric conversion section 25 (photoelectric conversion region 22) of pixel 3 is held (accumulated) in the floating diffusion region FD via the transfer transistor TR of pixel 3. Then, pixel circuit 16 reads the signal charge held in the floating diffusion region FD and applies it to the gate electrode of the amplification transistor AMP of pixel circuit 16. The vertical shift register supplies a horizontal line selection control signal to the gate electrode of the selection transistor SEL of pixel circuit 16. Then, the selection control signal is set to a high (H) level, so the selection transistor SEL is turned on to allow current corresponding to the potential of the floating diffusion region FD amplified by the amplification transistor AMP to flow to the vertical signal line 11. In addition, the reset control signal applied to the gate electrode of the reset transistor RST of pixel circuit 16 is set to a high (H) level, so the reset transistor RST is turned on to reset the signal charge accumulated in the floating diffusion region FD.

[0185] Figure 3 Each of the photoelectric conversion unit 25, the transmission transistor TR, and the floating diffusion region FD shown is mounted on the semiconductor layer 21 described later (see reference). Figure 5 Furthermore, although not limited to this, in the first embodiment, for example... Figure 3 The pixel transistors Q (AMP, SEL, RST, and FDG) included in the pixel circuit 16 are also mounted in the semiconductor layer 21 (see reference). Figure 4 ).

[0186] <<Specific Components of Solid-State Imaging Devices>>

[0187] Next, we will refer to Figures 4 to 10B Explain the specific composition of the solid-state imaging device 1A (semiconductor chip 2).

[0188] Figure 4 It is shown schematically. Figure 1 A plan view of an example of the composition of pixel blocks included in a pixel array section.

[0189] Figure 5 It is an illustrative representation along Figure 4 The longitudinal section diagram of the structure is taken from the section line a4-a4.

[0190] Figure 6 yes Figure 5 An enlarged longitudinal section view of a portion of the data.

[0191] Figure 7 It is an illustrative representation along Figure 5 The cross-sectional view of the cross-sectional structure cut by section line a5-a5.

[0192] Figure 8It is an illustrative representation along Figure 5 The cross-sectional view of the cross-sectional structure is taken by section line b5-b5.

[0193] Figure 9 It is an illustrative representation along Figure 5 The cross-sectional view of the cross-sectional structure cut by section line c5-c5.

[0194] Figure 10A It is an illustrative representation along Figure 1 The longitudinal section diagram of the longitudinal section structure is taken from section line 1a-1a.

[0195] Figure 10B It is an illustrative representation along Figure 1 The longitudinal section diagram of the longitudinal section structure is taken from the section line a1-a1.

[0196] Note that in Figure 4 For ease of observation, the illustration of the multilayer wiring layer 51 described later is omitted, and... Figure 5 The illustration of the layer above the first wiring layer 54 in the multilayer wiring layer 50 is omitted.

[0197] also, Figure 1 This is a plan view of semiconductor chip 2 as seen from the light incident surface. Figure 4 This is a plan view taken from the opposite side (multilayer wiring layer side) of the light incident surface of semiconductor chip 2.

[0198] In addition, for ease of observation, Figure 10A and Figure 10B It is shown in a segmented manner along Figure 1 The longitudinal section structure is cut by section line a1-a1. Then, Figure 10A and Figure 10B The longitudinal section relative to Figure 5 The longitudinal section is reversed vertically.

[0199] In addition, Figure 5 , Figure 7 , Figure 8 , Figure 10A and Figure 10B In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0200] like Figure 5As shown, the solid-state imaging device 1A according to the first embodiment includes a semiconductor layer 21, a separation region 31, and a photoelectric conversion region 22. The semiconductor layer 21 has a first facet S1 and a second facet S2 located on opposite sides in a thickness direction (Z direction). The separation region 31 is disposed in the semiconductor layer 21 and extends along the thickness direction (Z direction) of the semiconductor layer 21. The photoelectric conversion region 22 is disposed in the semiconductor layer 21 by being separated by the separation region 31 and includes the first facet S1 and the second facet S2 of the semiconductor layer 21.

[0201] Furthermore, the solid-state imaging device 1A according to the first embodiment also includes a multilayer wiring layer 51 disposed on the first face S1 side of the semiconductor layer 21.

[0202] Furthermore, the solid-state imaging device 1A according to the first embodiment also includes a sealing insulating film 66, a spacer made of low refractive index material 71, a pad insulating film 73, an optical filter layer 74, and a lens layer 75, which are sequentially disposed on the second face S2 side of the semiconductor layer 21.

[0203] In addition, such as Figure 10A and Figure 10B As shown, the solid-state imaging device 1A according to the first embodiment also includes a light-shielding film 72 disposed on the second face S2 side of the semiconductor layer 21 in the optical black region 2A2 of the pixel array section 2A.

[0204] Here, the first facet S1 of the semiconductor layer 21 is also referred to as the main facet or element forming facet, and the second facet S2 is also referred to as the back facet. Then, the solid-state imaging apparatus 1A according to the first embodiment is a back-illuminated type image sensor that uses a photoelectric conversion unit 25 (photodiode PD) disposed in the photoelectric conversion region 22 of the semiconductor layer 21 to perform photoelectric conversion on incident light incident from the second facet S2 side of the semiconductor layer 21. Therefore, in the first embodiment, the second facet S2 of the semiconductor layer 21 can be referred to as the light incident facet.

[0205] <Sealing Insulating Film>

[0206] like Figure 5 and Figure 6 As shown, a sealing insulating film 66 is disposed on the second surface S2 side of the semiconductor layer 21 to cover the photoelectric conversion region 22 and the separation region 31, and to seal the second surface S2 side of the semiconductor layer 21. The sealing insulating film 66 covers the second surface S2 side of the semiconductor layer 21 through the fixed charge film 61, the anti-reflection film 62 and the insulating film 63 described later.

[0207] Here, it goes without saying that the sealing insulating film 66 does not necessarily need to have a sealing function for sealing the second face S2 side of the semiconductor layer 21, and can simply be an insulating film.

[0208] The material of the sealing insulating film 66 is an insulating material containing at least one of Si, N, Al, Hf, Ta, Ti, O, Mg, Sc, Zr, La, Gd or Y. As the sealing insulating film 66, for example, silicon nitride (SiN) film, aluminum oxide (Al2O3) film, silicon oxide (SiO2) film, silicon oxynitride (SiON) film, aluminum oxynitride (AlON) film, silicon aluminum nitride (SiAlN) film, magnesium oxide (MgO), magnesium fluoride (MgF2), silicon alumina (AlSiO) film, hafnium oxide (HfO2) film, hafnium alumina (HfAlO) film, tantalum oxide (Ta2O3) film, titanium oxide (TiO2) film, scandium oxide (Sc2O3) film, zirconium oxide (ZrO2) film, gadolinium oxide (Gd2O3) film, lanthanum oxide (La2O3) film, or yttrium oxide (Y2O3) film can be used, or a laminated structure of these insulating films can also be used. The sealing insulating film 66 of the first embodiment includes, for example, a silicon oxide film with high light transmittance.

[0209] <Spacers and Pad Insulating Film>

[0210] like Figure 5 As shown, spacer 71 is disposed on the side of the sealing insulating film 66 opposite to the semiconductor layer 21 side. Spacer 71 has a lattice-like planar pattern in the plan view, exposing the light-receiving side of each of the plurality of photoelectric conversion regions 22, such that light incident on a given photoelectric conversion region 22 does not leak into adjacent photoelectric conversion regions 22. Spacer 71 has the same lattice-like planar pattern as the separation region 31 described later, and is disposed in the plan view at a position overlapping with the separation region 31. Spacer 71 comprises a low-refractive-index material such as an oxide film or air.

[0211] A pad insulating film 73 is disposed on the side of the sealing insulating film 66 opposite to the semiconductor layer 21 side to cover the sealing insulating film 66 and the spacer 71. The pad insulating film 73 comprises, for example, a silicon oxide film with high light transmittance.

[0212] <Optical filter layer and lens layer>

[0213] like Figure 5 As shown, an optical filter layer 74 is disposed on the side of the pad insulating film 73 opposite to the semiconductor layer 21 side. The optical filter layer 74 performs color separation on incident light incident from the light incident surface side (second surface S2 side) of the solid-state imaging device 1A. Furthermore, for each pixel 3 (for each photoelectric conversion region 22), the optical filter layer 74 includes, but is not limited to, an optical filter section 74a that transmits light of a specific wavelength such as red (R), green (G), or blue (B).

[0214] like Figure 5 As shown, the lens layer 75 is disposed on the side of the optical filter layer 74 opposite to the semiconductor layer 21. Then, for each pixel 3 (for each photoelectric conversion region 22), the lens layer 75 includes a microlens (on-chip lens) 75a that focuses the incident light and effectively guides the focused light into the photoelectric conversion region 22.

[0215] That is, the pixel 3 in the first embodiment includes a photoelectric conversion region 22 and a sealing insulating film 66, a spacer 71, a pad insulating film 73, an optical filter 74a and a microlens 75a disposed on the second face S2 side of the photoelectric conversion region 22.

[0216] <Semiconductor layer>

[0217] like Figure 5 As shown, the semiconductor layer 21 has a separation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21 and a photoelectric conversion region 22 separated by the separation region 31. As the semiconductor layer 21, a Si substrate, a SiGe substrate, an InGaAs substrate, etc., can be used. For example, the first embodiment uses a p-type semiconductor substrate made of single-crystal silicon as the semiconductor layer 21, but it is not limited to this. Figure 4 and Figure 5 As shown, the photoelectric conversion region 22 is separated by a separation region 31 for each pixel 3.

[0218] <Separated Region>

[0219] (Plane shape)

[0220] like Figure 4 As shown in the plan view, the separation region 31 includes a first in-plane extension 31x extending in the X direction and a second in-plane extension 31y extending in the Y direction. The separation region 31 also includes an intersection (intersection point) 31xy where the first in-plane extension 31x and the second in-plane extension 31y intersect each other on the same plane. In a first embodiment, the first in-plane extension 31x and the second in-plane extension 31y are, for example, orthogonal to each other.

[0221] The first plane extension 31x is repeatedly arranged at predetermined intervals in the Y direction. Furthermore, the second plane extension 31y is repeatedly arranged at predetermined intervals in the X direction. That is, in the separation region 31, the planar pattern in the planar view is a grid-like planar pattern.

[0222] like Figure 4 As shown, the separation region 31 corresponding to a photoelectric conversion region 22 has an annular planar pattern (ring planar pattern) that is square in shape in the plan view, and surrounds the photoelectric conversion region 22. On the other hand, as Figure 4As shown, the separation region 31 corresponding to a pixel block 15 is a composite planar pattern with a cross-shaped planar pattern, wherein the first plane extension portion 31x and the second plane extension portion 31y are orthogonally arranged to each other in a square-shaped annular planar pattern.

[0223] like Figure 4 As shown, in the separation region 31 corresponding to a pixel block 15, the intersection (intersection point) 31xy between the first in-plane extension 31x and the second in-plane extension 31y is located at the center of the pixel block 15. Then, the photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c, and 3d) are arranged in a matrix (2 × 2) around the intersection 31xy. That is, the photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c, and 3d) included in a pixel block 15 are adjacent to each other in the X and Y directions in the planar view via the separation region 31.

[0224] (Longitudinal cross-sectional shape)

[0225] like Figure 5 and Figure 6 As shown, the separation region 31 extends in the thickness direction (Z direction) of the semiconductor layer 21 as one direction, and provides electrical and optical separation between two adjacent photoelectric conversion regions 22 in the plan view. Then, the separation region 31 is configured, for example, as a trench type, wherein trenches 32 are formed in the semiconductor layer 21 to separate and isolate the photoelectric conversion regions 22.

[0226] Here, the inner side of the excavation portion 32 formed in the semiconductor layer 21 is filled with a film; however, even after the film is filled therein, the excavation portion 32 is still called that.

[0227] In addition, the shallow excavation section 32 can also be referred to as the hole section or the groove section.

[0228] (Excavation Department)

[0229] like Figure 5 and Figure 6 As shown, the excavation section 32 includes a shallow excavation section (shallow trench) 32a disposed on the first surface S1 side of the semiconductor layer 21 and a deep excavation section (deep trench) 32b extending from the shallow excavation section 32a toward the second surface S2 side of the semiconductor layer 21. In the plan view, its width W2 in the short side direction (refer to...) Figure 6 Narrower than the width W1 of the shallow excavation section 32a in the short side direction (refer to...) Figure 6 The deep-drilled portion 32b of the first embodiment is not limited to this, but is, for example, connected to the shallow-drilled portion 32a and extending from the shallow-drilled portion 32a to the second facet S2 of the semiconductor layer 21. The drilled portion 32 has a grid-like planar pattern similar to the separation region 31 in a plan view.

[0230] Here, the short side direction of each of the shallow excavation section 32a and the deep excavation section 32b refers to the arrangement direction of the two photoelectric conversion regions 22 arranged in a way that separates them from each other in the plan view. In other words, it refers to the separation direction in which the two photoelectric conversion regions 22 are separated from each other.

[0231] (Shallow separation region and deep separation region)

[0232] like Figure 5 and Figure 6 As shown, the separation region 31 includes a shallow separation region 31a disposed in the surface portion on the first face S1 side of the semiconductor layer 21 and a deep separation region 31b extending from the bottom side of the shallow separation region 31a toward the second face S2 side of the semiconductor layer 21. In the plan view, its width W4 in the short side direction is (refer to...) Figure 6 Narrower than the width W3 of the shallow separation region 31a in the short side direction (refer to...) Figure 6 The deep separation region 31b of the first embodiment is not limited thereto, but is, for example, connected to the bottom of the shallow separation region 31a and extends from the bottom of the shallow separation region 31a to the second face S2 of the semiconductor layer 21.

[0233] Here, the direction of the short side of each of the shallow separation region 31a and the deep separation region 31b refers to the arrangement direction of the two photoelectric conversion regions 22 that are arranged in a way that separates them from each other in the plan view. In other words, it refers to the separation direction in which the two photoelectric conversion regions 22 are separated from each other.

[0234] Each of the shallow separation region 31a and the deep separation region 31b is formed in each of the first in-plane extension portion 31x and the second in-plane extension portion 31y. That is, each of the first in-plane extension portion 31x and the second in-plane extension portion 31y of the separation region 31 includes the shallow separation region 31a and the deep separation region 31b.

[0235] Each of the shallow separation region 31a and the deep separation region 31b is not limited thereto, but rather has the same planar pattern, for example, in a planar view. In the first embodiment, each of the shallow separation region 31a and the deep separation region 31b has a grid-like planar pattern.

[0236] Note that the shallow separation region 31a can also be used as a segment separation region separating the element formation region on the first face S1 side of the semiconductor layer 21. In this case, the deep separation region 31b overlaps with the segment separation region in the plan view and, together with the segment separation region, separates the photoelectric conversion region 22.

[0237] <Photoelectric conversion region>

[0238] like Figure 4 As shown in the plan view, the photoelectric conversion region 22 is surrounded by the separation region 31 and has a square planar shape. Specifically, the photoelectric conversion region 22 is surrounded by two first in-plane extension portions 31x extending in the X direction and separated in the Y direction, and two second in-plane extension portions 31y extending in the Y direction and separated in the X direction. Then, the photoelectric conversion region 22 is separated by the first in-plane extension portions 31x and the second in-plane extension portions 31y, and is separated from adjacent photoelectric conversion regions 22.

[0239] like Figure 5 and Figure 6 As shown, the photoelectric conversion region 22 includes a p-type well region 23 disposed in the semiconductor layer 21 across a first face S1 and a second face S2, and an n-type semiconductor region 24 disposed in the p-type well region 23 away from the first face S1 of the semiconductor layer 21.

[0240] Furthermore, the photoelectric conversion region 22 includes a p-type well region 23 and an n-type semiconductor region 24, and also includes a photoelectric conversion section 25 disposed in the semiconductor layer 21 away from the first facet S1 of the semiconductor layer 21.

[0241] In addition, such as Figure 4 and Figure 5 As shown, the photoelectric conversion region 22 also includes a floating diffusion region FD as a charge holding part and a transmission transistor TR. The charge holding part is disposed on the first surface S1 side of the semiconductor layer 21 and holds (accumulates) the signal charge photoelectrically converted by the photoelectric conversion part 25. The transmission transistor TR transmits the signal charge photoelectrically converted by the photoelectric conversion part 25 to the floating diffusion region FD.

[0242] In addition, the photoelectric conversion region 22 also includes a p-type power supply contact region WC disposed on the first face S1 side of the semiconductor layer 21 and at least a portion of the pixel transistor Q included in the pixel circuit 16.

[0243] (p-type trap region)

[0244] like Figure 5 and Figure 6 As shown, in each photoelectric conversion region 22, a p-type well region 23 is disposed across a wide range from the first facet S1 side to the second facet S2 side of the semiconductor layer 21. Furthermore, the p-type well region 23 contacts the separation region 31 along the thickness direction (Z direction) of the semiconductor layer 21. The p-type well region 23 includes a p-type semiconductor region.

[0245] (n-type semiconductor region)

[0246] like Figure 5 and Figure 6As shown, in each photoelectric conversion region 22, an n-type semiconductor region 24 is disposed in a three-dimensional structure within a p-type well region 23. That is, the six faces of the n-type semiconductor region 24, including an upper face, a lower face, and four side faces, are surrounded by the p-type well region 23. Furthermore, the n-type semiconductor region 24 is separated from the first face S1 and the second face S2 of the semiconductor layer 21, as well as the separation region 31. Then, the n-type semiconductor region 24 forms a pn junction with the p-type well region 23 at the six faces of the n-type semiconductor region 24.

[0247] (Photoelectric Conversion Unit)

[0248] like Figure 5 and Figure 6 As shown, a photoelectric conversion unit 25 is disposed in a photoelectric conversion region 22. The photoelectric conversion unit 25 includes a p-type well region 23 and an n-type semiconductor region 24 in the photoelectric conversion region 22. Furthermore, the photoelectric conversion unit 25 is configured as a pn junction photodiode (PD), which includes a pn junction between the p-type well region 23 and the n-type semiconductor region 24.

[0249] The photoelectric conversion unit 25 converts light incident from the second face S2 side (light incident face side) of the semiconductor layer 21 onto the n-type semiconductor region 24 into signal charge in the n-type semiconductor region 24, and temporarily holds (accumulates) the converted signal charge in the pn junction between the p-type well region 23 and the n-type semiconductor region 24. The photoelectric conversion unit 25 is disposed in the semiconductor layer 21 separately from the first face S1 of the semiconductor layer 21. The photoelectric conversion unit 25 is disposed for each photoelectric conversion region 22 (pixel 3).

[0250] In the photoelectric conversion unit 25 of the first embodiment, the well region 23 is p-type and the semiconductor region 24 is n-type, so the signal charge converted by the photoelectric conversion unit 25 is electron.

[0251] (Floating diffusion area)

[0252] like Figure 4 As shown, the floating diffusion region FD of each of the four photoelectric conversion regions 22 (four pixels 3a, 3b, 3c and 3d) included in a pixel block 15 is arranged outside the intersection 31xy in a plan view such that it surrounds the intersection 31xy of the separation region 31 and is adjacent to the intersection 31xy.

[0253] like Figure 4 and Figure 5As shown, the floating diffusion region FD is disposed on the xy side of the intersection 31 of the separation region 31 in the plan view, and is adjacent to the shallow separation region 31a. Then, the floating diffusion region FD is disposed in the p-type well region 23 on the first face S1 side of the semiconductor layer 21, and includes an n-type semiconductor region with an impurity concentration higher than that of the n-type semiconductor region 24. Furthermore, the floating diffusion region FD overlaps with the n-type semiconductor region 24 in the plan view, and is separated from the n-type conductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21.

[0254] (Transmission transistor)

[0255] like Figure 4 and Figure 5 As shown, the transmission transistor TR is disposed on the first face S1 side of the semiconductor layer 21 in the photoelectric conversion region 22. The transmission transistor TR includes a gate electrode 43 disposed on the first face S1 side of the semiconductor layer 21 and a gate insulating film 42 disposed between the gate electrode 43 and the semiconductor layer 21. In addition, the transmission transistor TR also includes an n-type semiconductor region 24 and an n-type floating diffusion region FD serving as source and drain regions, and a p-type well region 23 serving as channel formation region. Although the transmission transistor TR is not limited to this, for example, the transmission transistor TR is configured as a vertical type, wherein the gate electrode 43 extends along the thickness direction (Z direction) of the semiconductor layer 21.

[0256] like Figure 4 As shown, the transmission transistor RT of each of the four photoelectric conversion regions 22 (four pixels 3a, 3b, 3c, and 3d) included in a pixel block 15 is configured to be biased to the intersection 31xy side of the separation region 31 in the plan view. Then, the gate electrode 43 of the transmission transistor TR of each of the four photoelectric conversion regions 22 is disposed outside the n-type floating diffusion region FD in a manner surrounding the intersection 31xy of the separation region 31 in the plan view.

[0257] like Figure 6 As shown, the gate electrode 43 of the transmission transistor TR includes a head 43a and a body 43b. The head 43a is disposed outside the first face S1 of the semiconductor layer 21 through a gate insulating film 42, and the body 43b protrudes from the head 43a into the interior of the semiconductor layer 21 and is adjacent to the semiconductor layer 21 through the gate insulating film 42. Although the gate electrode 43 of the first embodiment is not limited to this, for example, the body 43b is narrower than the head 43a.

[0258] The body 43b of the gate electrode 43 is disposed in the gate trench (gate excavation) 41 of the semiconductor layer 21 through the gate insulating film 42, and reaches the n-type semiconductor region 24. The gate trench 41 extends from the first facet S1 of the semiconductor layer 21 toward the second facet S2.

[0259] The gate insulating film 42 includes, for example, a silicon oxide film. The gate electrode 43 includes, for example, a polysilicon (doped polysilicon) film, in which impurities are introduced to reduce resistance.

[0260] When a gate voltage is applied to the gate electrode 43 and the transfer transistor TR is turned on, a charge transport path (channel) electrically connecting the n-type semiconductor region 24 and the n-type floating diffusion region FD is formed in the p-type well region 23. Furthermore, the signal charge (electrons) photoelectrically converted by the n-type semiconductor region 24 of the photoelectric conversion unit 25 is transported from the n-type semiconductor region 24 to the n-type floating diffusion region FD through the charge transport path.

[0261] (P-type contact area for power supply)

[0262] like Figure 4 and Figure 5 As shown, in each of the four photoelectric conversion regions 22 included in a pixel block 15, the p-type electrical contact region WC is disposed in the plan view outside the other intersection on the opposite side of the intersection 31xy of the separation region 31 located in the center of the pixel block 15. Furthermore, as... Figure 5 As shown, a p-type power supply contact region WC is disposed in the p-type well region 23 on the first face S1 side of the semiconductor layer 21 and is electrically connected to the p-type well region 23. The p-type power supply contact region WC includes a p-type semiconductor region with a higher impurity concentration than the p-type well region 23.

[0263] During operation, a first reference potential (Vss potential) of 0 V is applied to the p-type power supply contact area WC as a reference potential within the solid-state imaging device 1A (in the semiconductor chip 2), and this potential is fixed to the first reference potential during operation.

[0264] (Pixel transistor)

[0265] like Figure 4 As shown, the photoelectric conversion region 22 of each of the four pixels 3 (3a, 3b, 3c, and 3d) included in a pixel block 15 includes one of the pixel transistors Q included in a pixel circuit 16 as described above. In the first embodiment, although not limited thereto, for example, as... Figure 4 As shown, in a pixel block 15, there are four pixels 3 (3a, 3b, 3c and 3d), the photoelectric conversion region 22 of pixel 3a includes an amplifying transistor AMP as a pixel transistor Q, the photoelectric conversion region 22 of pixel 3b includes a selection transistor SEL as a pixel transistor Q, the photoelectric conversion region 22 of pixel 3c includes a switching transistor FDG as a pixel transistor Q, and the photoelectric conversion region 22 of pixel 3d includes a reset transistor RST as a pixel transistor Q.

[0266] In the pixel transistor Q included in the pixel circuit 16, refer to Figure 4 Although not shown in detail, the amplifying transistor AMP includes a gate electrode 44 disposed on the outer side of the first facet S1 of the semiconductor layer 21 and a gate insulating film disposed between the gate electrode 44 and the first facet S1 of the semiconductor layer 21. Furthermore, the amplifying transistor AMP includes a pair of main electrode regions 46a and 46b disposed on both sides of the gate electrode 44 in the gate length direction (direction of gate length Lg) in the semiconductor layer 21 and serving as a source region and a drain region, and a channel formation portion disposed between the pair of main electrode regions 46a and 46b.

[0267] Each of a pair of main electrode regions 46a and 46b includes, for example, an n-type semiconductor region disposed in a p-type well region 23. For example, a channel formation includes a p-type well region 23. The gate insulating film includes, for example, a silicon oxide film. The gate electrode 44 includes, for example, a polysilicon (doped polysilicon) film in which impurities are introduced to reduce resistance.

[0268] Note that, as pixel transistors Q included in pixel circuit 16, each of the select transistor SEL, switching transistor FDG, and reset transistor RST, other than the amplifying transistor AMP, has a similar configuration to the amplifying transistor AMP, therefore, the description of these pixel transistors Q (SEL, FDG, and RST) is omitted.

[0269] Furthermore, although the first embodiment has described the case where a single pixel transistor Q is configured in a photoelectric conversion region 22 as an example, multiple pixel transistors Q having the same function can be configured in a photoelectric conversion region 22, and multiple pixel transistors Q having different functions can also be configured in a photoelectric conversion region 22. Alternatively, the pixel transistor Q may not be configured in the photoelectric conversion region 22. In this case, the pixel transistor Q is configured in another semiconductor layer that overlaps with the semiconductor layer 21 in the planar view.

[0270] <Planar pattern of the photoelectric conversion area>

[0271] like Figure 4 As shown, each of the four pixels 3 (3a, 3b, 3c and 3d) included in a pixel block 15 has a different planar pattern, including the configuration of a transmission transistor TR and a pixel transistor Q in the planar pattern.

[0272] In the first implementation scheme, such as Figure 4As shown, the planar patterns of pixels 3a and 3b arranged in the Y direction are inverted patterns with the boundary between pixels 3a and 3b as the inversion axis. Similarly, the planar patterns of pixels 3c and 3d arranged in the Y direction are inverted patterns with the boundary between pixels 3c and 3d as the inversion axis. Furthermore, the planar patterns of pixels 3a and 3c arranged in the X direction are inverted patterns with the boundary between pixels 3a and 3c as the inversion axis. Also, the planar patterns of pixels 3b and 3d arranged in the X direction are inverted patterns with the boundary between pixels 3b and 3d as the inversion axis.

[0273] <Specific Composition of the Separated Region>

[0274] As described above, the separation region 31 includes a shallow separation region 31a and a deep separation region 31b.

[0275] (Shallow separation region)

[0276] like Figure 5 and Figure 6 As shown, the shallow separation region 31a includes the aforementioned shallow excavation portion 32a and a section insulating film 36 disposed inside the shallow excavation portion 32a, such that the shallow excavation portion 32a is filled.

[0277] (Deeply separated region)

[0278] like Figure 5 and Figure 6 As shown, the deep separation region 31b includes the aforementioned deep excavation section 32b, a fixed charge film 61 provided along the side portion inside the deep excavation section 32b and having a fixed charge, and a metal thin film 64 serving as a conductive film provided along the fixed charge film 60 on the side of the fixed charge film 61 opposite to the side of the deep excavation section 32b inside the deep excavation section 32b.

[0279] In addition, the deep separation region 31b also includes an insulating film 63 disposed between the fixed charge film 61 and the metal film 64, and an insulating film 65 disposed on the side of the metal film 64 opposite to the fixed charge film 61 side.

[0280] Here, the side portion of each of the shallow excavation portion 32a and the deep excavation portion 32b refers to the side portion of the photoelectric conversion region 22 and the side portion of the semiconductor layer 21 located around the shallow excavation portion 32a and the deep excavation portion 32b, respectively.

[0281] Furthermore, the metal thin film 64 of the first embodiment corresponds to a specific example of the “conductive film” of the present technology.

[0282] like Figure 5 and Figure 6As shown, each of the fixed charge film 61 and the insulating film 63 is disposed across the inner side of the deep-drilled portion 32b and the second surface S2 side of the semiconductor layer 21, and overlaps with the second surface S2 of the semiconductor layer 21 in the plan view. On the second surface S2 side of the semiconductor layer 21, the insulating film 63 overlaps with the fixed charge film 61 via the anti-reflective film 62 in the plan view. Each of the fixed charge film 61, the anti-reflective film 62, and the insulating film 63 is disposed on the second surface S2 side of the semiconductor layer 21 in this order.

[0283] like Figure 5 and Figure 6 As shown, each of the fixed charge film 61, the insulating film 63, and the metal film 64 is disposed on two opposing sidewall portions (sidewall portions) along the two sidewall portions (sidewall portions) of the deep excavation portion 32b. Then, each of the fixed charge film 61, the insulating film 63, and the metal film 64 is folded back on the first surface portion S1 side of the semiconductor layer 21, specifically at the bottom of the shallow separation region 31a. Then, the insulating film 65 is disposed such that the space formed by the folded-back metal film 64 is filled.

[0284] That is, on the inner side of the deep excavation section 32b, such as Figure 5 and Figure 8 As shown, each of the following is arranged sequentially from one photoelectric conversion region 22 side to the other photoelectric conversion region 22: fixed charge film 61, insulating film 63, metal film 64, insulating film 65, metal film 64, insulating film 63, and fixed charge film 61.

[0285] (Fixed charge film)

[0286] like Figure 5 and Figure 6 As shown, the fixed charge film 61 is disposed across the interior of the separation region 31 and the exterior of the second surface S2 of the semiconductor layer 21. The fixed charge film 61 inside the separation region 31 is disposed along the inner side and bottom surfaces of the deep-drilled portion 32b; in other words, it is disposed along the side surface of the photoelectric conversion region 22 (the side surface of the semiconductor layer 21) and the bottom of the shallow separation region 31a. The fixed charge film 61 contacts the p-type well region 23 of the photoelectric conversion region 22 along the thickness direction (Z direction) of the semiconductor layer 21. Furthermore, the fixed charge film 61 contacts the p-type well region 23 of the photoelectric conversion region 22 on the second surface S2 side of the semiconductor layer 21.

[0287] like Figure 7 and Figure 8 As shown, the fixed charge film 61 has an annular planar pattern that continuously surrounds the photoelectric conversion region 22 in a planar view.

[0288] Here, in the first embodiment, the signal charge converted by the photoelectric conversion unit 25 is an electron, and the well region 23 in contact with the separation region 31 is a p-type semiconductor region. Therefore, the fixed charge film 61 in the first embodiment has a negative fixed charge.

[0289] The material of the fixed charge film 61 is an insulating material containing at least one of Si, N, Al, Hf, Ta, Ti, O, Ca, Mg, Li, Sr, Sc, Ba, Nb, W, Mo, Zr, La, Gd, or Y. For example, the fixed charge film 61 may include a silicon nitride (SiN) film, an aluminum oxide (Al2O3) film, a silicon oxide (SiO2) film, a silicon oxynitride (SiON) film, an aluminum oxynitride (AlON) film, a silicon aluminum nitride (SiAlN) film, a magnesium oxide (MgO), a silicon aluminum oxide (AlSiO) film, a hafnium oxide (HfO2) film, an aluminum hafnium oxide (HfAlO) film, a tantalum oxide (Ta2O3) film, or a titanium oxide (Ti). The insulating films include O2 films, scandium oxide (Sc2O3) films, zirconium oxide (ZrO2) films, gadolinium oxide (Gd2O3) films, lanthanum oxide (La2O3) films, yttrium oxide (Y2O3), niobium pentoxide (Nb2O5), calcium oxide (CaO), lithium oxide (Li2O), strontium oxide (SrO), barium oxide (BaO), tungsten oxide (WO3), or molybdenum oxide (MoO3) films, or laminated structures of these insulating films. In a first embodiment, for example, an aluminum oxide (Al2O3) film is used as a fixed-charge film 61 with a negative fixed charge.

[0290] The fixed charge film 61 is formed with a film thickness that is shaped along the inner side of the wall of the deep excavation portion 32b. The film thickness of the fixed charge film 61 is preferably about 10 nm, and can be a value in the range of 1 to 100 nm.

[0291] Using the fixed charge film 61, holes (h) are induced on the semiconductor layer 21 side (photoelectric conversion region 22 side) at the interface between the semiconductor layer 21 and the separation region 31 in the photoelectric conversion region 22. + Furthermore, it can ensure pinning at the interface, thereby suppressing the generation of dark current.

[0292] (Anti-reflective film)

[0293] like Figure 5 and Figure 6 As shown, the antireflective film 62 is selectively disposed on the outer side of the second surface portion S2 of the semiconductor layer 21, and not disposed in the separation region 31. Then, on the outer side of the second surface portion S2 of the semiconductor layer 21, the antireflective film 62 is placed between the fixed charge film 61 and the insulating film 63.

[0294] The antireflective film 62 is made of an insulating material containing at least one of Si, N, Al, Hf, Ta, Ti, O, Mg, Sc, Zr, La, Gd, or Y. For example, the antireflective film 62 may include a silicon nitride (SiN) film, an aluminum oxide (Al2O3) film, a silicon oxide (SiO2) film, a silicon oxynitride (SiON) film, an aluminum oxynitride (AlON) film, a silicon aluminum nitride (SiAlN) film, a magnesium oxide (MgO), a magnesium fluoride (MgF2), a silicon aluminum oxide (AlSiO) film, a hafnium oxide (HfO2) film, an aluminum hafnium oxide (HfAlO) film, a tantalum oxide (Ta2O3) film, a titanium oxide (TiO2) film, a scandium oxide (Sc2O3) film, a zirconium oxide (ZrO2) film, a gadolinium oxide (Gd2O3) film, a lanthanum oxide (La2O3) film, or a yttrium oxide (Y2O3) film, or a stacked structure of these insulating films. In the first embodiment, for example, a tantalum oxide (Ta2O3) film is used as an antireflective film 62.

[0295] (Insulating film)

[0296] like Figure 5 and Figure 6 As shown, the insulating film 63 is disposed across the interior of the separation region 31 and the exterior of the second surface S2 of the semiconductor layer 21. The insulating film 63 inside the separation region 31 is disposed along the inner side and bottom surfaces of the deep-drilled portion 32b, separated by a fixed charge film 61; in other words, it is disposed along the side surface of the photoelectric conversion region 22 (the side surface of the semiconductor layer 21) and the bottom of the shallow separation region 31a. The insulating film 63 on the exterior of the second surface S2 of the semiconductor layer 21 covers the photoelectric conversion region 22, separated by an anti-reflective film 62.

[0297] like Figure 7 and Figure 8 As shown, the insulating film 63 has an annular planar pattern that continuously surrounds the photoelectric conversion region 22 in a planar view.

[0298] The insulating film 63 is made of an insulating material containing at least one of Si, N, Al, or Hf. For example, the insulating film 63 may include a silicon nitride (SiN) film, an aluminum oxide (Al2O3) film, a silicon oxide (SiO2) film, a silicon oxynitride (SiON) film, an aluminum oxynitride (AlON) film, a silicon aluminum nitride (SiAlN) film, a silicon aluminum oxide (AlSiO) film, a hafnium oxide (HfO2) film, or an aluminum hafnium oxide (HfAlO) film, or a stacked structure of these insulating films. In the first embodiment, for example, a silicon oxide (SiO2) film is used as the insulating film 63.

[0299] The insulating film 63 is formed with a thickness that is shaped along the inner side of the wall of the deep excavation portion 32b, with the fixed charge film 61 in between. The thickness of the insulating film 63 is preferably about 10 nm, and can be a value in the range of 1 to 500 nm.

[0300] (metal film)

[0301] like Figure 5 and Figure 6 As shown, unlike the fixed charge film 61, the metal thin film 64 is selectively disposed in the separation region 31 and is not extended to the second surface S2 side of the semiconductor layer 21. The metal thin film 64 then folds back at the bottom of the shallow separation region 31a, extends in the thickness direction (Z direction) of the semiconductor layer 21, and terminates on the outer side of the second surface S2 of the semiconductor layer 21. That is, the metal thin film 64 has a U-shaped longitudinal cross-sectional shape in the separation region 31 along the thickness direction (Z direction) of the semiconductor layer 21. The film thickness of the metal thin film 64 is less than the film thickness of the fixed charge film 61 and the film thickness of the insulating film 65.

[0302] like Figure 8 and Figure 9 As shown, the metal thin film 64 has an annular planar pattern (ring planar pattern), wherein the planar shape in the planar view continuously surrounds a photoelectric conversion region 22 in the portion away from the folded-back portion. On the other hand, as Figure 7 As shown, the metal thin film 64 has a lattice-like planar pattern (mesh planar pattern), wherein the planar shape in the planar view continuously surrounds each of the plurality of photoelectric conversion regions 22 in the folded portion. That is, the metal thin film 64 surrounds each of the plurality of photoelectric conversion regions 22 and is integrated across the plurality of photoelectric conversion regions 22.

[0303] The material of the metal thin film 64 includes a metal film or an alloy film of at least one of Ti, W, Ni, N, Ru, Cu, Co, Mo, Rh, Ir, Ag, Nb, or Al, and may also be a stacked structure of these metal films or stacks of these metal films. In a first embodiment, for example, a titanium nitride (TiN) film is used as the metal thin film 64.

[0304] The metal thin film 64 is formed with a thickness that is shaped along the inner side of the wall surface of the deep excavation portion 32b, with the fixed charge film 61 and the insulating film 63 in between. The thickness of the metal thin film 64 is preferably about 5 nm, and can be a value in the range of 0.5 to 10 nm. That is, the thickness of the metal thin film 64 is preferably 10 nm or less.

[0305] A potential is applied (supplied) to the metal film 64. This potential includes a power supply potential supplied from a power generation circuit disposed inside the solid-state imaging device 1A and a power supply potential supplied from outside the solid-state imaging device 1A via bonding pads 14. These power supply potentials include, for example, a first reference potential V1 of "0 V", a second reference potential V2 of a positive potential higher than the first reference potential V1, and a third reference potential V3 of a negative potential lower than the first reference potential difference V1. In the first embodiment, since the well region 23 in contact with the separation region 31 is p-type, a negative potential of, for example, -2.0 V is applied to the metal film 64 as the third reference potential V3. The potential applied to the metal film 64 is maintained during operation of the solid-state imaging device 1A.

[0306] By applying a third reference potential V3 to the metal thin film 64, holes (h+) are induced on the semiconductor layer 21 side of the interface between the semiconductor layer 21 and the separation region 31 in the photoelectric conversion region 22, and pinning at this interface can be ensured, thereby suppressing the generation of dark current.

[0307] Note that, for example, a first reference potential V1 of “0 V” is applied to the p-type well region 23 as a power supply potential, and during the operation of the solid-state imaging device 1A, the p-type well region 23 is fixed at the first reference potential V1.

[0308] By reducing the thickness of the metal thin film 64, the light absorption becomes less than that of the polycrystalline silicon film, thereby suppressing the decrease in quantum efficiency (QE).

[0309] Furthermore, since the metal thin film 64 can be formed by an ALD process at approximately 400°C, the metal thin film 64 can be formed even after the fixed charge film 61 is formed without deactivating the fixed charge in the fixed charge film 61.

[0310] (Insulating film)

[0311] like Figure 5 and Figure 6 As shown, similar to the metal thin film 64, the insulating film 65 extends in the thickness direction (Z direction) of the semiconductor layer 21 and terminates on the outer side of the second facet S2 of the semiconductor layer 21. Furthermore, similar to the metal thin film 64, the insulating film 65 is also selectively disposed in the separation region 31 and is not extended to the second facet S2 side of the semiconductor layer 21.

[0312] The insulating film 65 is made of an insulating material containing at least one of Si, N, Al, or Hf. For example, the insulating film 65 may include a silicon nitride (SiN) film, an aluminum oxide (Al2O3) film, a silicon oxide (SiO2) film, a silicon oxynitride (SiON) film, an aluminum oxynitride (AlON) film, a silicon aluminum nitride (SiAlN) film, a silicon aluminum oxide (AlSiO) film, a hafnium oxide (HfO2) film, or an aluminum hafnium oxide (HfAlO) film, or a stacked structure of these insulating films. In a first embodiment, for example, a silicon oxide (SiO2) film is used as the insulating film 65.

[0313] The insulating film 65 is formed to a thickness such that the space formed by the folded-back metal film 64 is filled by it. The thickness of the insulating film 65 is preferably about 10 nm, and can be a value in the range of 1 to 500 nm.

[0314] <Optical Black Area>

[0315] like Figure 10A and Figure 10B As shown, the optical black region 2A2 of the pixel array section 2A includes a light-shielding film 72 disposed on the second surface S2 side of the semiconductor layer 21, separated by films such as a fixed charge film 61, an anti-reflective film 62, an insulating film 63, and a sealing insulating film 66. Furthermore, the optical black region 2A2 also includes a photoelectric conversion region 22A and a non-photoelectric conversion region 22B disposed in the semiconductor layer 21 and separated by a separation region 31. Unlike the effective pixel region 2A1 of the pixel array section 2A, the optical black region 2A2 does not include an optical filter section 74a or a microlens 75a.

[0316] Each of the photoelectric conversion region 22A and the non-photoelectric conversion region 22B is covered by a light-shielding film 72 disposed on the second face S2 side of the semiconductor layer 21. Figure 10A and Figure 10B In the optical black area 2A2, one photoelectric conversion region 22A and two non-photoelectric conversion regions 22B are shown; however, the number of photoelectric conversion regions 22A and non-photoelectric conversion regions 22B is not limited to... Figure 10A and Figure 10B The quantity in.

[0317] like Figure 10A and Figure 10B As shown, the photoelectric conversion region 22A of the optical black region 2A2 has a similar configuration to the photoelectric conversion region 22 of the effective pixel region 2A1, and includes a photoelectric conversion unit 25. On the other hand, unlike the photoelectric conversion region 22 of the effective pixel region 2A1, the non-photoelectric conversion region 22B does not include the photoelectric conversion unit 25.

[0318] like Figure 10BAs shown, the non-photoelectric conversion region 22B includes a p-type well region 23b disposed in the semiconductor layer 21 across a first face S1 and a second face S2, and a p-type power supply contact region WC1 disposed in the p-type well region 23b on the first face S1 side of the semiconductor layer 21.

[0319] The p-type well region 23b is in contact with the separation region 31 along the thickness direction (Z direction) of the semiconductor layer 21. The p-type well region 23 is formed by a p-type semiconductor region.

[0320] The p-type power supply contact region WC1 is disposed in the p-type well region 23b on the first surface S1 side of the semiconductor layer 21 and is electrically connected to the p-type well region 23b. The p-type power supply contact region WC1 includes a p-type semiconductor region with an impurity concentration higher than that of the p-type well region 23b.

[0321] like Figure 10B As shown, the light-shielding film 72 is electrically and mechanically connected to the p-type well region 23b of the non-photoelectric conversion region 22B and the metal thin film 64 of the separation region 31 through a through-hole 76 disposed on the second face S2 side of the semiconductor layer 21 in the optical black region 2A2.

[0322] A through-hole 76 is disposed across two adjacent non-photoelectric conversion regions 22B, separated by the separation region 31, and overlaps with the p-type well region 23b and the separation region 31 in a plan view. The through-hole 76 then penetrates the sealing insulating film 66, the insulating film 63, the anti-reflective film 62, the fixed charge film 61, etc., and reaches the p-type well region 23b and the metal film 64. That is, the light-shielding film 72 is electrically and mechanically connected to the p-type well region 23b of each of the two adjacent non-photoelectric conversion regions 22B separated by the separation region 31, and is also electrically and mechanically connected to the metal film 64 in the separation region 31 sandwiched between the two non-photoelectric conversion regions 22B.

[0323] W is preferred as the material for the light-shielding film 72, and other metallic materials including at least one of Ti, W, Ni, N, Ru, Cu, Co, Mo or Al can also be used.

[0324] <<Multi-layer wiring>>

[0325] like Figure 5 and Figure 10BAs shown, a multilayer wiring layer 51 is disposed on the first surface S1 side of the semiconductor layer 21. The multilayer wiring layer 51 includes an interlayer insulating film 52 disposed on the first surface S1 side of the semiconductor layer 21 to cover the photoelectric conversion region 22 and the separation region 31, and a first wiring layer 54 disposed on the side of the interlayer insulating layer 52 opposite to the semiconductor layer 21 side. Furthermore, the multilayer wiring layer 51 also includes contact electrodes 53f, 53w, and 53w1 disposed in the interlayer insulating film 52. The first wiring layer 54 includes wirings 54f, 54w, and 54w1.

[0326] For example, high-melting-point metal tungsten (W) can be used as the material for contact electrodes 53f, 53w, and 53w1. For example, a metal material such as aluminum (Al) or copper (Cu), or an alloy material mainly containing Al or Cu, can be used as the material for the first wiring layer 54. For example, a silicon oxide film can be used as the interlayer insulating film 52.

[0327] The gate electrode 44 of the transmission transistor TR and Figure 4 The gate electrode 45 of each of the multiple pixel transistors Q (AMP, SEL, RST, FDG) shown is covered by an interlayer insulating film 52.

[0328] Wiring 54f is electrically connected to the floating diffusion region FD of the photoelectric conversion region 22 via contact electrode 53f disposed in the interlayer insulating film 52. Wiring 54w is electrically connected to the power supply contact region WC of the photoelectric conversion region 22 via contact electrode 53w disposed in the interlayer insulating film 52. Wiring 54w1 is electrically connected to the power supply contact region WC1 of the non-photoelectric conversion region 22B via contact electrode 53w1 disposed in the interlayer insulating film 52.

[0329] <<Electrical Supply>>

[0330] like Figure 10B As shown, the metal film 64 of the optical black region 2A2 is electrically connected to the wiring 54w1 via the light-shielding film 72, the p-type well region 23b, the p-type power supply contact region WC1, and the contact electrode 53w1. The metal film 64 of the optical black region 2A2 is integrated with the metal film 64 of the effective pixel region 2A1 on the folded-back side of the metal film 64. Then, a negative potential of, for example, -2.0 V is applied to the wiring 54w1 as a third reference potential V3. That is, the metal film 64 of the separation region 31 in the effective pixel region 2A1 is electrically connected to the wiring 54w1 (as a conductor of the applied potential) to the third reference potential V3 to which the negative potential is applied.

[0331] Here, the wiring 54w1 of the first embodiment corresponds to a specific example of the “conductor to which a potential is applied” in this technology.

[0332] For example, a first reference potential V1 of "0 V" is applied to... Figure 5 The wiring 54w is shown. Then, the wiring 54w is electrically connected to the p-type well region 23 via the contact electrode 53w and the p-type power supply contact region WC. That is, the p-type well region 23 of the photoelectric conversion region 22 is electrically connected to the wiring 54w, which is subjected to a first reference potential V1 of "0 V".

[0333] Note that in Figure 10B The diagram shows a case where the p-type power supply contact area WC1 is disposed in one of the two non-photoelectric conversion areas 22B connected to the light-shielding film 72; however, the contact electrode 53w1 can be disposed in each of the two non-photoelectric conversion areas 22B, and the wiring 54w1 can be electrically connected to the p-type well area 23b of each of the two non-photoelectric conversion areas 22B.

[0334] <<Manufacturing Methods of Solid-State Imaging Devices>>

[0335] Next, we will refer to Figures 11A~11O This describes a method for manufacturing the solid-state imaging device 1A according to the first embodiment of the present technology. Figures 11A~11O In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0336] In the first embodiment, the formation of the separation region 31, which is specifically included in the manufacturing method of the solid-state imaging device 1A, is described.

[0337] Furthermore, in the first embodiment, the effective pixel region 2A1 specifically concentrated in the pixel array section 2A is described.

[0338] First, such as Figure 11A As shown, a p-type well region 23 and an n-type semiconductor region 24 are formed in the semiconductor layer 21. The p-type well region 23 is formed across the entire region including the photoelectric conversion region 22 and the hole formation region 38 of the semiconductor layer 21. An n-type semiconductor region 24 is formed for each photoelectric conversion region 22. Each of the p-type well region 23 and the n-type semiconductor region 24 can be formed using known photolithography techniques and impurity ion implantation methods. Figure 11A The photoelectric conversion region 22, which has not yet been separated by the separation region 31, is shown.

[0339] Note, refer to Figure 10A and Figure 10B Each of the p-type well region 23 and the n-type semiconductor region 24 is formed in the photoelectric conversion region 22A of the effective pixel region 2A1 and the photoelectric conversion region 22A of the optical black region 2A2. Then, in the non-photoelectric conversion region 22B of the optical black region 2A2, the p-type well region 23 is formed, but the n-type semiconductor region 24 is not formed.

[0340] Here, in the manufacturing of the solid-state imaging device 1A of the first embodiment, a thinning process is performed to reduce the thickness of the semiconductor layer 21 in the Z direction (see reference). Figure 11H During this thinning process, the semiconductor layer 21 is thinned to... Figure 11A The thinning line S2a is shown.

[0341] Next, the excavation formation region 38 on the first face S1 side of the semiconductor layer 21 of the n-type semiconductor region 24 is selectively etched to form Figure 11B The shallow excavation section 32a shown thereafter, as Figure 11B As shown, the shallow punch-hole portion 32a is selectively filled with an insulating film 33. The shallow punch-hole portion 32a is recessed from the first facet S1 of the semiconductor layer 21 toward the second facet S2. The depth of the shallow punch-hole portion 32a is preferably about 150 nm, and can be a value in the range of 50 to 100 nm. The shallow punch-hole portion 32a can be formed using, for example, known photolithography techniques and anisotropic dry etching techniques. Although not shown in detail, the shallow punch-hole portion 32a is formed in a lattice-like planar pattern across the effective pixel region 2A1 and the optical black region 2A2 of the semiconductor layer 21.

[0342] The insulating film 33 is made of an insulating material containing at least one of Si, N, Al, or Hf. For example, the insulating film 33 may include a silicon nitride (SiN) film, an aluminum oxide (Al2O3) film, a silicon oxide (SiO2) film, a silicon oxynitride (SiON) film, an aluminum oxynitride (AlON) film, a silicon aluminum nitride (SiAlN) film, a silicon aluminum oxide (AlSiO) film, a hafnium oxide (HfO2) film, or an aluminum hafnium oxide (HfAlO) film, or a stacked structure of these insulating films.

[0343] Next, a structure is formed on the first face S1 side of the semiconductor layer 21 as shown in the figure. Figure 11C The etching mask M1 is shown, and then the insulating film 33 of the shallow hole 32a and the hole formation region 38 of the semiconductor layer 21 are etched by dry etching to form a deep hole 32b that is deeper than the shallow hole 32a, as shown. Figure 11C As shown. The deep-drilled portion 32b extends from the bottom of the shallow-drilled portion 32a toward the second face S2 side of the semiconductor layer 21 and is integrally formed with the shallow-drilled portion 32a.

[0344] In this process, a mining section 32 is formed, including a shallow mining section 32a and a deep mining section 32b. The mining section 32 is formed in a grid-like planar pattern across the effective pixel region 2A1 and the optical black region 2A2 of the semiconductor layer 21.

[0345] Furthermore, during this process, the photoelectric conversion area 22 is surrounded and separated by the excavation section 32.

[0346] Next, after removing the etch mask M1, the following is formed. Figure 11D The pad insulating film 34 is shown. The pad insulating film 34 is formed across the inner wall surface of the excavation portion 32 and the outer side of the first surface S1 of the semiconductor layer 21. The pad insulating film 34 is formed to have a film thickness that is folded back along the inner wall surface (side surface and bottom surface) of the excavation portion 32.

[0347] The insulating film 34 may include, for example, an insulating film such as a silicon oxide (SiO2) film, a silicon oxynitride (SiON) film, an aluminum oxynitride (AlON) film, a silicon aluminum nitride (SiAlN) film, a silicon aluminum oxide (AlSiO) film, a hafnium oxide (HfO2) film, or an aluminum hafnium oxide (HfAlO) film, or a stacked structure of these insulating films.

[0348] Next, as Figure 11D As shown, a polycrystalline silicon film 35 is formed. The polycrystalline silicon film 35 is formed to a thickness such that the excavated portion 32 is filled by it.

[0349] Next, as Figure 11E As shown, the polysilicon film 35 and the pad insulating film 34 on the first face S1 side of the semiconductor layer 21, as well as the polysilicon film 35, the pad insulating film 34 and the insulating film 33 in the shallow excavation portion 32a, are selectively removed by, for example, an etch-back method.

[0350] During this process, each of the padding insulating film 34 and the polycrystalline silicon film 35 remains in the deep excavation section 32b.

[0351] Next, as Figure 11F As shown, a segment insulating film 36 is selectively formed inside the shallow excavation portion 32a. By forming a segment insulating film 36 on the first facet S1 side of the semiconductor layer 21 to fill the shallow excavation portion 32a, and then selectively removing the segment insulating film 36 on the first facet S1 side of the semiconductor layer 21 using, for example, CMP or etching back, so that the segment insulating film 36 remains in the shallow excavation portion 32a, the segment insulating film 36 of the shallow excavation portion 32a can be formed.

[0352] The material of the segment insulating film 36 is an insulating material containing at least one of Si, N, Al, or Hf. For example, the segment insulating film 36 may include insulating films such as silicon nitride (SiN) film, aluminum oxide (Al2O3) film, silicon oxide (SiO2) film, silicon oxynitride (SiON) film, aluminum oxynitride (AlON) film, aluminum silicon nitride (SiAlN) film, aluminum silicon oxide (AlSiO) film, hafnium oxide (HfO2) film, or hafnium oxide (HfAlO) film, or a laminated structure of these insulating films.

[0353] During this process, a shallow separation region 31a, including a shallow cutout 32a and a segment insulating film 36, is formed on the first surface S1 side of the semiconductor layer 21. The shallow separation region 31a is formed in a grid-like planar pattern across the effective pixel region 2A1 and the optical black region 2A2 of the semiconductor layer 21.

[0354] Next, in the photoelectric conversion region 22, Figure 11G The transmission transistor TR, the n-type floating diffusion region FD, and the p-type power supply contact region WC shown are formed in the surface portion of the first face S1 side of the semiconductor layer 21, and a pixel transistor Q is also formed thereal, although not shown.

[0355] In addition, during this process, refer to Figure 10B A p-type power supply contact region WC1 is formed in the surface portion of the semiconductor layer 21 on the first face S1 side in the non-photoelectric conversion region 22B.

[0356] Next, as Figure 11G As shown, an interlayer insulating film 52, contact electrodes 53f, 53w, and 53w1 (see reference) are formed on the first surface S1 side of the semiconductor layer 21. Figure 10B ) and the multilayer wiring layer 51 of the first wiring layer 54.

[0357] Next, after forming the multi-layer wiring layer 51, as follows Figure 11H As shown, a thinning process is performed, wherein the second face S2 side of the semiconductor layer 21 is cut to the thinning line S2a by, for example, CMP method, to reduce the thickness of the semiconductor layer 21.

[0358] During this process, the deep-drilled portion 32b, the padding insulating film 34, and the polysilicon film 35 extending along the thickness direction (Z direction) of the semiconductor layer 21 are exposed at the first surface S1 of the semiconductor layer 21.

[0359] Next, as Figure 11I As shown, each of the polysilicon film 35 and the insulating pad film 34 in the deep excavation section 32b is removed. Each of the polysilicon film 35 and the insulating pad film 34 is removed by a separate wet chemical treatment.

[0360] Next, as Figure 11J As shown, a fixed charge film 61 is formed. In the first embodiment, the fixed charge film 61 with a negative fixed charge is formed by atomic layer deposition (ALD).

[0361] A fixed charge film 61 is formed across the inner side of the deep-drilled portion 32b and the second facet S2 of the semiconductor layer 21. The fixed charge film 61 is then formed with a film thickness having inner wall faces (side faces and bottom faces) along the inner side of the deep-drilled portion 32b, such that the deep-drilled portion 32b is not filled. In the first embodiment, for example, an alumina (Al2O3) film with a thickness of about 10 nm is formed on the deep-drilled portion 32b, which has a width of about 100 nm, as the fixed charge film 61.

[0362] Next, as Figure 11K As shown, an anti-reflective film 62 is selectively formed on the second facet S2 side of the semiconductor layer 21 by chemical vapor deposition (CVD). CVD can suppress film formation on the inner wall facet of the inner side of the deep-cut portion 32b.

[0363] Next, as Figure 11L As shown, an insulating film 63 is formed using the ALD method. The insulating film 63 is formed across the fixed charge film 61 inside the deep-drilled portion 32b and the anti-reflective film 62 on the second surface S2 side of the semiconductor layer 21. The insulating film 63 is then formed with a film thickness that folds back along the inner wall surfaces (side and bottom surfaces) inside the deep-drilled portion 32b, such that the inner surface of the fixed charge film 61 in the deep-drilled portion 32b is not filled. The insulating film described above can be used as the insulating film 63, or a laminate of these insulating films can be used. In the first embodiment, for example, a silicon oxide (SiO2) film with a thickness of about 10 nm is formed as the insulating film 63. The film thickness of the insulating film 63 can be a value in the range of about 1 to 500 nm.

[0364] Next, as Figure 11M As shown, each of the metal thin film 64 and the insulating film 65 is formed by the ALD method. Each of the metal thin film 64 and the insulating film 65 is formed across the inner side of the deep-drilled portion 32b and the second facet S2 side of the semiconductor layer 21. Then, the metal thin film 64 is formed with a film thickness that folds back along the inner wall facets (side facets and bottom facets) of the inner side of the deep-drilled portion 32b, such that the inner side of the insulating film 63 in the deep-drilled portion 32b is not filled. On the other hand, the insulating film 65 is formed with a film thickness that fills the inner side of the metal thin film 64 in the deep-drilled portion 32b.

[0365] The metal thin film 64 can be any of the aforementioned metal thin films, or a laminate of these metal thin films. In the first embodiment, the metal thin film 64 is, for example, a titanium nitride (TiN) film with a thickness of about 5 nm. The thickness of the metal thin film 64 can be a value in the range of about 0.5 to 10 nm.

[0366] As the insulating film 65, the aforementioned insulating film can be used, or a laminate of these insulating films can be used. In the first embodiment, as the insulating film 65, for example, a silicon oxide (SiO2) film with a thickness of about 10 nm is formed. The film thickness of the insulating film 65 can be a value in the range of about 1 to 500 nm.

[0367] As the metal thin film 64, for example, a titanium nitride (TiN) film can be formed by an ALD process at approximately 400°C, thus allowing the metal thin film 64 to be formed even after the formation of the fixed charge film 61 without deactivating the fixed charge in the fixed charge film 61. Furthermore, with the aforementioned metal film and laminated film, the metal thin film 64 can be formed even after the formation of the fixed charge film 61 without deactivating the fixed charge in the fixed charge film 61.

[0368] Next, as Figure 11N As shown, the insulating film 65 and the metal film 64 on the outer side of the second face S2 of the semiconductor layer 21 are selectively removed, for example, by an etch-back method, such that the metal film 64 selectively remains inside the insulating film 63 in the deep-cut portion 32b, and the insulating film 65 selectively remains inside the metal film 64. The etch-back is performed with an amount sufficient to at least remove the metal film 64 on the second face S2 side of the semiconductor layer 21.

[0369] In this process, a deep separation region 31b is formed, comprising a deep-drilled portion 32b, a fixed charge film 61, an insulating film 63, a metal film 64, and an insulating film 65. The deep separation region 31b is formed in a grid-like planar pattern across the effective pixel region 2A1 and the optical black region 2A2 of the semiconductor layer 21.

[0370] Furthermore, during this process, a separation region 31 is formed, comprising a shallow separation region 31a and a deep separation region 31b. The separation region 31 is formed in a grid-like planar pattern across the effective pixel region 2A1 and the optical black region 2A2 of the semiconductor layer 21.

[0371] Next, as Figure 11O As shown, a sealing insulating film 66 covering the photoelectric conversion region 22 and the separation region 31 is formed on the second surface S2 side of the semiconductor layer 21. The sealing insulating film 66 can be the aforementioned insulating film, or a laminate of these insulating films. In the first embodiment, for example, a silicon oxide (SiO2) film is formed as the sealing insulating film 66.

[0372] Subsequently, by forming spacer 71, light-shielding film 72, padding insulating film 73, optical filter layer 74, lens layer 75, etc. on the second facet S2 side of semiconductor layer 21, a result is obtained. Figure 5 , Figure 6 , Figure 10A and Figure 10B The state shown.

[0373] <<Main Effects of the First Implementation Plan>>

[0374] Next, the main effects of the first implementation plan will be explained.

[0375] The solid-state imaging apparatus 1A according to the first embodiment includes a photoelectric conversion region 22 disposed in a semiconductor layer 21 and separated by a separation region 31, and a photoelectric conversion unit 25 disposed in the photoelectric conversion region 22. The separation region 31 includes a cutout portion 32 extending in the thickness direction (Z direction) of the semiconductor layer 21, a fixed charge film 61 having a fixed charge and disposed along a side portion inside the cutout portion 32, and a metal thin film 64 serving as a conductive thin film disposed along the fixed charge film 62 inside the cutout portion 32. As the metal thin film 64, for example, a titanium nitride (TiN) film can be formed by an ALD process at approximately 400°C, etc., so that even after the fixed charge film 61 is formed, the metal thin film 64 can be formed without deactivating the fixed charge in the fixed charge film 61.

[0376] Therefore, according to the solid-state imaging device 1A of the first embodiment, by applying a third reference potential V3 (negative potential) to the metal thin film 64, holes (h) are induced on the semiconductor layer 21 side of the interface between the semiconductor layer 21 of the photoelectric conversion region 22 and the separation region 31. + Furthermore, it ensures pinning at the interface, thereby suppressing the generation of dark current. In addition, according to the solid-state imaging device 1A of the first embodiment, a fixed charge film 61 is used to induce holes (h) on the semiconductor layer 21 side of the interface between the semiconductor layer 21 of the photoelectric conversion region 22 and the separation region 31. + Furthermore, it can ensure pinning at the interface, thereby suppressing the generation of dark current.

[0377] That is, the solid-state imaging device 1A according to the first embodiment has both the effect of suppressing dark current by fixing the potential of the metal thin film 64 and the effect of suppressing dark current by fixing the charge film 61, thus significantly reducing dark current.

[0378] Furthermore, by reducing the thickness of the metal thin film 64, the light absorption becomes less than that of the polycrystalline silicon film, thereby suppressing the reduction in quantum efficiency.

[0379] Therefore, the solid-state imaging device 1A according to the first embodiment can reduce dark current and suppress the decrease in quantum efficiency.

[0380] <<Variations on the First Implementation Plan>>

[0381] <Variation Example 1-1>

[0382] Figure 12 This is a longitudinal cross-sectional view of a variation 1-1 according to the first embodiment of the present technology, schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0383] like Figure 12 As shown, in Modification 1-1, the polarity of the photoelectric conversion unit 25 is reversed relative to the first embodiment described above.

[0384] That is, the well region 23 is n-type and the semiconductor region 24 is p-type. Then, the photoelectric conversion unit 25 of Modified Example 1-1 is constructed as a pn-junction type photodiode including the pn junction between the p-type semiconductor region 24 and the n-type well region 23. Then, the signal charge photoelectrically converted by the photoelectric conversion unit 25 of Modified Example 1-1 is a hole.

[0385] Then, in modified example 1-1, the fixed charge film 61 has a positive fixed charge, and the potential applied to the metal thin film 64 is a positive potential of the second reference potential V2 (e.g., 2.0 V).

[0386] In the case of Variation 1-1, the material of the fixed charge film 61 is an insulating material containing at least one of Si, N, Al, Hf, Ta, Ti, O, Ca, Mg, Li, Sr, Sc, Ba, Nb, W, Mo, Zr, La, Gd, or Y. For example, the fixed charge film 61 may include a silicon nitride (SiN) film, an aluminum oxide (Al2O3) film, a silicon oxide (SiO2) film, a silicon oxynitride (SiON) film, an aluminum oxynitride (AlON) film, a silicon aluminum nitride (SiAlN) film, a magnesium oxide (MgO), a silicon aluminum oxide (AlSiO) film, a hafnium oxide (HfO2) film, an aluminum hafnium oxide (HfAlO) film, a tantalum oxide (Ta2O3) film, or a titanium oxide (Ti). O2) film, scandium oxide (Sc2O3) film, zirconium oxide (ZrO2) film, gadolinium oxide (Gd2O3) film, lanthanum oxide (La2O3) film, yttrium oxide (Y2O3), niobium pentoxide (Nb2O5), calcium oxide (CaO), lithium oxide (Li2O), strontium oxide (SrO), barium oxide (BaO), tungsten oxide (WO3) or molybdenum oxide (MoO3) film, or a stacked structure of these insulating films.

[0387] Since the polarity of the charge in the fixed charge film 61 can vary depending on the adjacent insulating film material and metal material, the material of the fixed charge film 61 with a positive fixed charge can be the same as the material of the fixed charge film with a negative fixed charge.

[0388] This technology can also be applied to variant 1-1, and can achieve similar effects to the first embodiment described above.

[0389] <Variations 1-2>

[0390] Figure 13 The figure shows variations 1-2 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0391] like Figure 13 As shown, the difference between Modification 1-2 and the first embodiment described above lies in the configuration of the separation region 31. Specifically, the separation region 31 in Modification 1-2 further includes a dielectric film (high-k film) 67 with a higher relative permittivity (k) than silicon oxide, disposed between the fixed charge film 61 and the insulating film 63. Similar to each of the fixed charge film 61, the insulating film 63, and the metal film 64, the dielectric film 67 is folded back at the bottom of the shallow separation region 31a on the first facet S1 side of the semiconductor layer 21, spanning the inner side of the deep excavation portion 32b and the second facet S2 side of the semiconductor layer 21, and overlaps with the second facet S2 of the semiconductor layer 21 in the plan view. In Modification 1-2, for example, an HfO2 film is used as the dielectric film 67.

[0392] In variations 1-2, the separation region 31 has a stacked structure, including, for example, an Al2O3 film with a high fixed charge as a fixed charge film 61, an HfO2 film with a high dielectric constant as a dielectric film 67, and a SiO2 film with high thermal stability as an insulating film 63. With this stacked structure, in addition to hole induction from the fixed charge, the electric field from the metal thin film 64 is more easily transferred to the semiconductor layer of the photoelectric conversion region, thereby further increasing the hole density induced at the interface between the separation region 31 and the semiconductor layer 21 of the photoelectric conversion region 22, and significantly reducing the dark current.

[0393] Therefore, this technology can also be applied to variations 1-2, and can achieve similar effects to the first embodiment described above.

[0394] Note that variations 1-2 can be combined with variations 1-1 described above.

[0395] <Variations 1-3>

[0396] Figure 14 The figure shows variations 1-3 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0397] like Figure 14 As shown, the difference between Modification 1-3 and Modification 1-2 above is that the arrangement order of the fixed charge film 61 and the dielectric film 67 is reversed.

[0398] That is, in modified examples 1-3, the dielectric film 67 is disposed between the deep excavation section 32b and the fixed charge film 61.

[0399] This technology can also be applied to variations 1-3, and can achieve similar effects to the first embodiment described above.

[0400] Furthermore, variations 1-3 can also be combined with variations 1-1 described above.

[0401] <Variations 1-4>

[0402] Figure 15 The figure shows variations 1-4 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0403] like Figure 15 As shown, in Modification 1-4, a La2O3 film 67a is used instead of an HfO2 film as the dielectric film 67 in the separation region 31 of Modification 1-2.

[0404] This technology can also be applied to variations 1-4, and can achieve similar effects to the first embodiment described above.

[0405] Furthermore, variations 1-4 can also be combined with the above-described variations 1-1.

[0406] <Variations 1-5>

[0407] Figure 16 The figure shows variations 1-5 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0408] like Figure 16 As shown, the separation region 31 of modifications 1-5 also includes a gap 65a disposed on the side of the insulating film 65 opposite to the metal film 64 side. In other words, the separation region 31 of modifications 1-5 also includes a gap (cavity) 65a surrounded by the insulating film 65.

[0409] This technology can also be applied to variations 1-5, and can achieve similar effects to the first embodiment described above.

[0410] Furthermore, since the separation region 31 of the modified examples 1-5 has a gap 65a, the crack resistance caused by the stress caused by the difference in the coefficient of thermal expansion between the film material inside the deep excavation region 32b and the semiconductor layer 21 around the deep excavation region 32b can be improved compared with the case where the deep excavation region 32b is completely filled by the insulating film 65.

[0411] Furthermore, variations 1-5 can also be combined with the above-described variations 1-1.

[0412] <Variations 1-6>

[0413] Figure 17 The figure shows variations 1-6 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0414] like Figure 17 As shown, in modifications 1-6, the metal thin film 64 has a stacked structure in which multiple metal material films are stacked. The metal thin film 64 in modifications 1-6 has a two-layer structure, such as a TiN film / W film. By using a low-resistance metal material film as the second layer, the potential of the negative bias voltage can be stabilized. Furthermore, similar effects can be obtained in stacked structures such as TiN film / Ru film or TiN film / Cu film.

[0415] This technology can also be applied to variations 1-6, and can achieve similar effects to the first embodiment described above.

[0416] Furthermore, variations 1-6 can also be combined with the above-described variations 1-1.

[0417] <Variations 1-7>

[0418] Figure 18 The figure shows variations 1-8 of the first embodiment of the present invention, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0419] like Figure 18 As shown, the photoelectric conversion region 22 of Variations 1-7 further includes a pinning layer (semiconductor region) 26, which is disposed between the deep separation region 31b of the separation region 31 and the well region 23, which is a semiconductor region, and has the same conductivity type as the well region 23 but a higher impurity concentration. Since the well region 23 is p-type in the first embodiment described above, the pinning layer 26 of Variations 1-7 is also p-type. If the well region 23 is n-type, as in Variation 1-1, the pinning layer 26 is also n-type.

[0420] The pinning layer 26 is disposed along the thickness direction (Z direction) of the semiconductor layer 21 on the semiconductor layer 21 side of the interface between the deep separation region 31b and the semiconductor layer 21 of the photoelectric conversion region 22. The pinning layer 26 can be formed in the manufacturing process of the solid-state imaging device 1A by introducing p-type impurities from the inside of the deep excavation section 32b using the PLAD method or solid-state diffusion method before the formation of the fixed charge film 61. Boron (B) is preferably used as the p-type impurity, but gallium (Ga) or aluminum (Al) can also be used.

[0421] Note that when the photoelectric conversion unit 25 performs photoelectric conversion on holes that serve as signal charges, arsenic (As) is preferably used as an n-type impurity, but phosphorus (P) or antimony (Sb) can also be used.

[0422] This technology can also be applied to variations 1-7, and can achieve similar effects to the first embodiment described above.

[0423] Furthermore, since the photoelectric conversion region 22 of the modified examples 1-7 also includes a pinning layer 26, the number of holes induced at the interface between the deep separation region 31b and the semiconductor layer 21 of the photoelectric conversion region 22 increases, and the effect of reducing dark current can be further improved.

[0424] <Variations 1-8>

[0425] Figure 19 The figure shows variations 1-8 of the first embodiment of the present invention, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0426] like Figure 19 As shown, the separation region 31 in modifications 1-8 further includes a pinning layer 37, which is disposed between the side portion of the deep excavation section 32b and the fixed charge film 61, and has the same conductivity type as the well region 23 but a higher impurity concentration. Since the well region 23 is p-type in the first embodiment described above, the pinning layer 37 in modifications 1-8 is also p-type. If the well region 23 is n-type, as in modification 1-1, the pinning layer 37 is also n-type.

[0427] The pinning layer 37 is disposed along the thickness direction (Z direction) of the semiconductor layer 21 on the side of the semiconductor layer 21 at the interface between the deep separation region 31b and the semiconductor layer 21 of the photoelectric conversion region 22. The pinning layer 26 can be formed in the manufacturing process of the solid-state imaging device 1A by epitaxial growth of an epitaxial layer introducing p-type impurities on the side surface of the semiconductor layer 21 inside the deep excavation region 32b before the formation of the fixed charge film 61.

[0428] Note that when the photoelectric conversion unit 25 performs photoelectric conversion on holes that serve as signal charges, arsenic (As) is preferably used as an n-type impurity, but phosphorus (P) or antimony (Sb) can also be used.

[0429] This technology can also be applied to variations 1-8, and can achieve similar effects to the first embodiment described above.

[0430] Furthermore, since the separation region 31 of the modified examples 1-7 also includes a pinning layer 37, the number of holes induced at the interface between the deep separation region 31b and the semiconductor layer 21 of the photoelectric conversion region 22 increases, and the effect of reducing dark current can be further improved.

[0431] <Variations 1-9>

[0432] Figure 20 The figure shows variations 1-9 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0433] like Figure 20 As shown, in modifications 1-9, the deep separation region 31b and the shallow separation region 31a are spaced apart. Then, in modifications 1-9, the fixed charge film 61 is provided across the side and bottom portions of the semiconductor layer 21 inside the deep-cut portion 32b. In modifications 1-9, the deep separation region 31b can be considered as a separation region 31 formed by processing from the second surface S2 side of the semiconductor layer 21. Then, the shallow separation region 31a in modifications 1-9 can be used as a segment separation region separating the element formation region on the first surface S1 side of the semiconductor layer 21. In the case of modifications 1-9, when the deep-cut portion 32b is formed, the etching amount in the thickness direction (Z direction) of the semiconductor layer 21 is small, thus suppressing damage to the crystal structure of the semiconductor layer 21 due to etching (defect generation).

[0434] This technology can also be applied to variations 1-9, and can achieve similar effects to the first embodiment described above.

[0435] Furthermore, variations 1-9 can also be combined with variations 1-1 described above.

[0436] <Variations 1-10>

[0437] Figure 21 The figure shows variations 1-10 of the first embodiment of the present invention, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0438] like Figure 21 As shown, in variations 1-10, the metal thin film 64 terminates inside the second facet S2 of the semiconductor layer 21 and is more recessed than the second facet S2 of the semiconductor layer 21. However, in the thickness direction (Z direction) of the semiconductor layer 21, the metal thin film 64 needs to cover more than 30% of the depth direction (Z direction) of the deep-cut portion 32b. By making the metal thin film 64 more recessed inside the semiconductor layer 21 than the second facet S2 of the semiconductor layer 21, light absorption of the metal thin film 64 can be suppressed, thereby improving quantum efficiency.

[0439] This technology can also be applied to variations 1-10, and can achieve similar effects to the first embodiment described above.

[0440] Furthermore, variations 1-10 can also be combined with the above-described variations 1-1.

[0441] <Variation Example 1-11>

[0442] Figure 22 It is a diagram showing variations 1-11 of the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0443] like Figure 21 As shown, in variations 1-11, the thickness of the metal thin film 64 is greater on the second face side of the semiconductor layer than on the first face side of the semiconductor layer 21. In other words, the metal thin film 64 in variations 1-11 is thinner on the second face side S2 of the semiconductor layer 21 and gradually thickens towards the first face side S1. Since the light absorption is greater on the light-incident face side (second face side S2) of the semiconductor layer 21, an improvement in quantum efficiency can be expected by increasing the thickness of the metal thin film as it moves from the second face side to the first face side of the semiconductor layer 21.

[0444] This technology can also be applied to variations 1-11, and can achieve similar effects to the first embodiment described above.

[0445] Furthermore, variations 1-11 can also be combined with the above-described variations 1-1.

[0446] <Variations 1-12>

[0447] Figure 23A The figure shows variations 1-12 of the first embodiment of the present invention, and is a schematic longitudinal cross-sectional view showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0448] Figure 23B It is an illustrative representation along Figure 23A The cross-sectional view of the cross-sectional structure cut by section line a23-a23.

[0449] like Figure 23A and Figure 23BAs shown, in variations 1-12, a metal gate 77 with a lattice-like planar pattern is provided on the light-incident surface (second surface S2 side) of the semiconductor layer 21. The metal gate 77 is disposed between the sealing insulating film 66 and the pad insulating film 73. The metal gate 77 is then formed into the same shape as the lattice-like planar pattern of the separation region 31 and overlaps with the separation region 31 in the planar view. The metal gate 77 then penetrates the sealing insulating film 66 and is electrically and mechanically connected to the metal film 64 of the separation region 31. The metal gate 77 is inserted between the two metal films 64 folded back inside the deep excavation portion 62b and is connected to the metal films 64.

[0450] By setting such a metal gate 77, color mixing can be reduced and the controllability of the potential applied to the metal thin film 64 can be improved. As the material of the metal gate 77, tungsten (W) is preferred, and metals including at least one of Ti, W, Ni, N, Ru, Cu, Co, Mo or Al can also be used.

[0451] This technology can also be applied to variations 1-12, and can achieve similar effects to the first embodiment described above.

[0452] Furthermore, variations 1-12 can also be combined with variations 1-1 described above.

[0453] <Variation Example 1-13>

[0454] Figure 24A It is a diagram showing variations 1-13 of the first embodiment of the present technology, and is a plan view schematically showing a configuration example of a pixel block.

[0455] Figure 24B It is an illustrative representation along Figure 24A The longitudinal section diagram of the longitudinal section structure is taken from section line a24-a24.

[0456] like Figure 24A and Figure 24B As shown, in Modification 1-13, a relay electrode 78 is provided in the shallow separation region 31a of the separation region 31. In the intersection of the in-plane extension 31x and the out-of-plane extension 31y of the separation region 31, the relay electrode 78 is positioned in the plan view at the intersection other than the intersection 31xy adjacent to the floating diffusion region FD. The relay electrode 78 is embedded, for example, in the shallow separation region 31a.

[0457] like Figure 24BAs shown, the shallow separation region 31a in Modifications 1-13 includes a shallow excavation section 32a, a section insulating film 36, and a relay electrode 78. The relay electrode 78 is then insulated and isolated from the semiconductor layer 21 by the section insulating film 36. The relay electrode 78 is then electrically and mechanically connected to the metal film 64 of the deep separation region 31b at the bottom side of the shallow separation region 31a. The relay electrode 78 is then electrically connected to the wiring 54m disposed in the first wiring layer 54 via a contact electrode 53m disposed in the interlayer insulating film 52. In Modifications 1-13, the voltage of the metal film 64 can be controlled by applying a potential (e.g., a third reference potential V3) to the wiring 54m.

[0458] As the relay electrode 78, for example, a polycrystalline silicon film with impurities introduced (added) to reduce resistance can be used. In variations 1-13, the wiring 54m and the relay electrode 78 correspond to a specific example of the “conductor to which a potential is applied” in this technology.

[0459] This technology can also be applied to variations 1-13, and can achieve similar effects to the first embodiment described above.

[0460] Furthermore, variations 1-13 can also be combined with variations 1-1 described above.

[0461] Note that in variations 1-13, the relay electrode 78 is disposed at the intersection of the separation regions 31; however, the relay electrode 78 may also be disposed in the middle portion between the two intersections of the separation regions 31.

[0462] Furthermore, despite Figure 24A The diagram shows one relay electrode 78, but it is preferable to provide multiple relay electrodes 78.

[0463] Furthermore, in variations 1-13, it has been described that the relay electrode 78 is embedded in the shallow separation region 31a; however, the relay electrode 78 may also be disposed across the inner and outer sides of the shallow separation region 31a, such that a portion of the relay electrode 78 protrudes from the shallow separation region 31a.

[0464] <Variation Example 1-14>

[0465] Figure 25 It is a figure showing variations 1-14 of the first embodiment of the present invention, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0466] like Figure 25As shown, Modifications 1-14 are modifications of Modifications 1-13 described above, wherein the relay electrode 78 is omitted, and the contact electrode 53m is directly connected to the metal film 64 of the deep separation region 31b. In Modifications 1-14, the contact electrode 53m penetrates each of the interlayer insulating film 52, the segment insulating film 36, the fixed charge film 61, and the insulating film 63, and is electrically and mechanically connected to the metal film 64.

[0467] In variations 1-14, the voltage of the metal film 64 can also be controlled by applying a potential (e.g., a third reference potential V3) to the wiring 54m.

[0468] This technology can also be applied to variations 1-14, and can achieve similar effects to the first embodiment described above.

[0469] Furthermore, variations 1-14 can also be combined with the above-described variations 1-1.

[0470] [Second Implementation Plan]

[0471] In the second embodiment, an example of how this technology is applicable to solid-state imaging devices including interpolated phase difference pixels will be given.

[0472] Figure 26 This is a diagram illustrating a solid-state imaging apparatus according to a second embodiment of the present technology, and is a plan view schematically illustrating a configuration example of a pixel block.

[0473] Figure 27 It is an illustrative representation along Figure 26 The longitudinal section diagram of the longitudinal section structure is taken from section line a26-a26.

[0474] Figure 28 It is an illustrative representation along Figure 27 The cross-sectional view of the cross-sectional structure taken by section line a27-a27.

[0475] Notice, Figure 27 It shows one pixel, while Figure 28 It shows the relationship with Figure 26 A corresponding pixel block contains four pixels.

[0476] In addition, Figure 27 and Figure 28 In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0477] The solid-state imaging device 1B according to the second embodiment of the present technology has a configuration that is substantially similar to that of the solid-state imaging device 1A according to the first embodiment, except for the configuration of the pixels 3. Other configurations are substantially similar to those of the first embodiment.

[0478] like Figure 4 and Figure 5 As shown, the pixel 3 of the first embodiment described above has a configuration in which a photoelectric conversion unit 25 (PD) is disposed in a photoelectric conversion region 22.

[0479] In comparison, such as Figures 26-28 As shown, in the second embodiment, pixel 3 is configured as a phase difference pixel, which detects the phase difference between two photoelectric conversion units 25 disposed in a photoelectric conversion region 22. This technology can also be applied to a solid-state imaging device 1B that includes such a phase difference pixel.

[0480] like Figures 26-28 As shown, the photoelectric conversion region 22 of the second embodiment includes a first photoelectric conversion cell 22L and a second photoelectric conversion cell 22R disposed in semiconductor layers 21 that are adjacent to each other in the X direction in a plan view. In addition, the photoelectric conversion region 22 of the second embodiment also includes a separation barrier 39 disposed between the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R in a plan view, and extending in the thickness direction (Z direction) of the semiconductor layer 21.

[0481] Each of the first photoconversion cell 22L and the second photoconversion cell 22R is separated by a separation region 31 and a separation barrier 39, and includes a p-type well region 23, an n-type semiconductor region 24, a photoconversion unit 25, a transmission transistor TR, an n-type floating diffusion region FD, a p-type power supply contact region WC, and a pixel transistor Q.

[0482] like Figure 26 and Figure 28 As shown in the plan view, the separation barriers 39 protrude into the interior of the photoelectric conversion region 22 from the middle portion of each of the two first in-plane extension portions 31x extending in the X direction on both sides of the photoelectric conversion region 22 in the Y direction, and are spaced apart from each other in the Y direction. That is, in the photoelectric conversion region 22 of the second embodiment, the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R that are adjacent to each other in the X direction are selectively separated by two separation barriers 39 protruding into the interior of the photoelectric conversion region 22 from the middle portion of each of the two first in-plane extension portions 31x extending in the X direction.

[0483] like Figures 26-28 As shown, each of the two separation barriers 39 is connected to and integrated with the separation region 31, and has a similar configuration to the separation region 31. That is, each of the two separation barriers 39 includes a shallow separation region 31a and a deep separation region 31b. Therefore, similar to the separation region 31, each of the two separation barriers 39 also includes a digging section 32, a fixed charge film 61, an insulating film 63, a metal film 64, and an insulating film 65.

[0484] Autofocus

[0485] In the electronic device including the solid-state imaging device 1B of the second embodiment, the signal charge of two photoelectric conversion units 25 and 25 disposed in a photoelectric conversion region 22 is read out for each pixel 3, and the phase difference is detected.

[0486] When the image is in focus, there is no difference in the amount of signal charge accumulated in the two photoelectric conversion units 25 included in a photoelectric conversion region 22. In contrast, when the image is out of focus, a difference arises between the amount of signal charge Q1 accumulated in one of the two photoelectric conversion units 25 and the amount of signal charge Q2 accumulated in the other photoelectric conversion unit 25. Furthermore, when the image is out of focus, the electronic device performs operations such as moving the objective lens to align Q1 and Q2 with each other. This is autofocus.

[0487] <Flow of signal charge>

[0488] In the photoelectric conversion region 22 of the second embodiment, the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R are partially isolated from each other, except for the region between the two separation barriers 39. Then, the p-type well region 23 of each of the first photoelectric conversion cells 22L and the second photoelectric conversion cell 22R is connected between the two separation barriers 39. Therefore, the p-type well region 23 between the separation barriers 39 serves as an overflow path.

[0489] Then, a first barrier can be formed in the well region 23 between the two separation barriers 39. When the transmission transistor TR of the first photoconversion cell 22L does not transfer signal charge from the photoconversion section 25 to the floating diffusion region FD, a second barrier higher than the first barrier can be formed. Furthermore, when the transmission transistor TR of the second photoconversion cell 22R does not transfer signal charge from the photoconversion section 25 to the floating diffusion region FD, a second barrier higher than the first barrier can be formed.

[0490] Then, the photoelectric conversion sections 25 and 25 of the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R can independently accumulate signal charge up to the height of the first barrier. Then, when the accumulated signal charge exceeds the height of the first barrier, the signal charge flows from one of the photoelectric conversion sections 25 of the first photoelectric conversion cell 26L and the second photoelectric conversion cell 22R to the other via the overflow path between the two separation barriers 39.

[0491] The solid-state imaging device 1B according to the second embodiment can perform image plane phase difference detection while reducing dark current and suppressing quantum efficiency reduction.

[0492] <<Variations on the Second Implementation Plan>>

[0493] <Variation Example 2-1>

[0494] Figure 29 This is a schematic diagram illustrating a variation 2-1 according to the second embodiment of the present technology, and is schematically shown in relation to... Figure 27 A cross-sectional view of the cross-sectional structure at the same location as section line b27-b27. Figure 29 In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0495] like Figure 29 As shown, in variant 2-1, the configuration of the separation barrier 39 is different.

[0496] That is, such as Figure 29 As shown, the separation barrier 39 in Modification 2-1 includes a fixed charge film but not a metal film. In Modification 2-1, the fixed charge film is disposed across the separation region and the separation barrier. On the other hand, the metal film is selectively disposed in the separation region 31 but not in the separation barrier 39.

[0497] This technology can also be applied to variant 2-1, and can achieve similar effects to the second embodiment described above.

[0498] Furthermore, since the separation barrier 39 of Modified Example 2-1 does not include the metal thin film 64, the metal thin film does not absorb light at the separation barrier, which can suppress the reduction of quantum efficiency compared with the second embodiment.

[0499] [Third Implementation Plan]

[0500] Figure 30 This is a diagram illustrating a solid-state imaging apparatus according to a third embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of a pixel.

[0501] Figure 31 It is an illustrative representation along Figure 30 The cross-sectional view of the cross-sectional structure cut by section line a30-a30.

[0502] Notice, Figure 30 It shows one pixel, while Figure 31 The image shows four pixels contained within a single pixel block.

[0503] In addition, Figure 30 and Figure 31 In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0504] like Figure 30 and Figure 31As shown, the solid-state imaging device 1C according to the third embodiment of the present technology has a configuration that is basically similar to that of the solid-state imaging device 1B according to the second embodiment described above, and differs in the following aspects.

[0505] That is, such as Figure 30 and Figure 31 As shown, the solid-state imaging device 1C according to the third embodiment of the present technology is a solid-state imaging device 1B of the second embodiment and a modification of Examples 1-12. Figure 23A and 23B The combination of metal gate 77 shown. Similar to the modifications 1-12 described above, the metal gate 77 of the third embodiment is also disposed between the sealing insulating film 66 and the pad insulating film 73 on the light incident surface side (second surface S2 side) of the semiconductor layer 21, and is formed in a lattice-like planar pattern with the same shape as the lattice-like planar pattern of the separation region 31, and overlaps with the separation region 31 in the planar view. Then, the metal gate 77 of the third embodiment also penetrates the sealing insulating film 66, and is electrically and mechanically connected to the metal film 64 of the separation region 31. The metal gate 77 of the third embodiment is also inserted between the two metal films 64 folded back inside the deep excavation portion 62b, and is connected to the metal film 64.

[0506] In the third implementation scheme, such as Figure 30 and Figure 31 As shown, the metal gate 77 is not positioned to overlap with the separation barrier 39 in the planar view. This configuration helps to suppress the reduction in quantum efficiency compared to when the metal gate 77 is positioned to overlap with the separation barrier 39 in the planar view.

[0507] According to the solid-state imaging device 1C of the third embodiment, image plane phase difference detection can be performed while reducing dark current and color mixing and improving quantum efficiency.

[0508] [Fourth Implementation Plan]

[0509] Figure 32 This is a diagram illustrating a solid-state imaging apparatus according to a fourth embodiment of the present technology, and is a plan view schematically illustrating a configuration example of a pixel block.

[0510] Figure 33 It is an illustrative representation along Figure 32 The longitudinal section diagram of the structure, taken from section line a32-a32. Figure 33 In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0511] like Figure 32 and Figure 33As shown, the solid-state imaging device 1C according to the fourth embodiment of the present technology has a configuration that is basically similar to that of the solid-state imaging device 1B according to the second embodiment described above, but differs in the configuration of the photoelectric conversion region.

[0512] That is, such as Figure 32 and Figure 33 As shown, the photoelectric conversion region 22 of the fourth embodiment includes a separation barrier 39D, replacing the one described in the second embodiment. Figures 26-28 Separation barrier 39 is shown.

[0513] like Figure 32 As shown in the plan view, a separation barrier 39D is disposed between the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R. Then, in the plan view, the separation barrier 39D is spaced apart from each of the two first in-plane extension portions 31x extending in the X direction on both sides of the photoelectric conversion region 22 in the Y direction, and extends in the Y direction. That is, in the photoelectric conversion region 22 of the fourth embodiment, the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R, which are adjacent to each other in the X direction, are spaced apart from each of the first in-plane extension portions 31x extending in the X direction and are selectively separated by the separation barrier 39D extending in the Y direction.

[0514] like Figure 33 As shown, unlike the separation barrier 39 of the second embodiment described above, the separation barrier 39D includes a deep separation region 31b1. The deep separation region 31b1 has a configuration substantially similar to that of the deep separation region 31b, but does not include a metal film. That is, the separation barrier 39D includes a cut-out portion 32b, a fixed charge film 61, an insulating film 63, and an insulating film 65.

[0515] The separation barrier 39D extends from the second facet S2 side of the semiconductor layer 21 towards the first facet S1 side, and is spaced apart from the first facet S1. Then, in the plan view, a floating diffusion region FD is provided in the surface portion of the semiconductor layer on the first facet side that overlaps with the separation barrier 39D. The floating diffusion region FD is shared by the first photoconversion cell 22L and the second photoconversion cell 22R.

[0516] In this way, by separating the separation barrier 39D from the first facet S1 of the semiconductor layer, the floating diffusion region FD can be shared by each of the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R, and the number of contacts and wiring capacitance can be reduced, thereby improving the conversion efficiency of the solid-state imaging device 1D. Then, by improving the conversion efficiency, the influence of random noise is reduced, thereby improving image quality.

[0517] [Fifth Implementation Plan]

[0518] Figure 34 This is a diagram illustrating a solid-state imaging apparatus according to a fifth embodiment of the present technology, and is a plan view schematically illustrating a configuration example of a pixel block.

[0519] Figure 35 It is an illustrative representation along Figure 34 The longitudinal section diagram of the structure, taken from section line a34-a34. Figure 35 In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0520] like Figure 34 and Figure 35 As shown, the solid-state imaging device 1E according to the fifth embodiment of the present technology has a configuration that is basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, but differs in the configuration of the pixel blocks.

[0521] That is, such as Figure 34 and Figure 35 As shown, the pixel block 15 in the fifth embodiment includes a floating diffusion region FDX, replacing the first embodiment described above. Figure 4 The floating diffusion region FD is shown. The floating diffusion region FDX is located in the center of pixel block 15 in the planar view and is shared by the four pixels 3 (3a, 3b, 3c and 3d) included in pixel block 15. Similar to the floating diffusion region FD, the floating diffusion region FDX includes an n-type semiconductor region with an impurity concentration higher than that of the n-type semiconductor region 24.

[0522] like Figure 34 As shown, in the separation region 31 corresponding to a pixel block 15, each of the first in-plane extension portion 31x and the second in-plane extension portion 31y located within the square-shaped annular planar pattern is divided into two separate parts at the center of the pixel block 15, and there is no separation region at the center of the pixel block 15. Then, each of the divided first in-plane extension portion 31x and the second in-plane extension portion 31y is set to surround the floating diffusion region FDX outside the floating diffusion region in the planar diagram.

[0523] In the fifth embodiment, since the four pixels 3 included in a pixel block 15 share a floating diffusion region FDX, the number of contacts can be reduced.

[0524] This technology can also be applied to the solid-state imaging device 1E according to the fifth embodiment, and can achieve similar effects to the solid-state imaging device 1A of the first embodiment described above.

[0525] [Sixth Implementation Plan]

[0526] Figure 36This is a diagram illustrating a solid-state imaging apparatus according to a sixth embodiment of the present technology, and is a plan view schematically illustrating a configuration example of a pixel block.

[0527] Figure 37 It is an illustrative representation along Figure 36 The longitudinal section diagram of the structure, taken from section line a36-a36. Figure 37 In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0528] like Figure 36 and Figure 37 As shown, the solid-state imaging device 1F according to the sixth embodiment of the present technology has a configuration that is basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, and also includes a relay conductive pad 46.

[0529] The relay conductive pad 46 is disposed in the center of the pixel block 15 in the plan view. Then, the relay conductive pad 46 is disposed across four photoelectric conversion regions 22 and separation regions 31 on the first surface S1 side of the semiconductor layer 21, and is electrically and mechanically connected to the floating diffusion region FD of each of the four photoelectric conversion regions 22. The relay conductive pad 46 is then electrically connected to the wiring 54f via contact electrode 53f. For example, a polycrystalline silicon film doped with impurities to reduce resistance can be used as the relay conductive pad 46.

[0530] In the sixth embodiment, since the four floating diffusion regions FD share a single contact electrode 53f, the number of contacts can be reduced.

[0531] This technology can also be applied to the solid-state imaging device 1F according to the sixth embodiment, and can achieve similar effects to the solid-state imaging device 1A of the first embodiment described above.

[0532] [Seventh Implementation Plan]

[0533] In the seventh embodiment, an example will be described of the application of this technology to, for example, a two-level stacked solid-state imaging device in which two semiconductor layers are stacked in two levels, as a stacked light detection device in which semiconductor layers are stacked in multiple levels.

[0534] Figure 38 This is a schematic longitudinal cross-sectional view illustrating the longitudinal structure of a solid-state imaging device according to the seventh embodiment of the present technology. Figure 38 In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0535] like Figure 38 As shown, the solid-state imaging device 1G according to the seventh embodiment of the present technology has a configuration that is basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, and has the following different configurations.

[0536] That is, such as Figure 38 As shown, the solid-state imaging apparatus 1G according to the seventh embodiment further includes a semiconductor layer 120 disposed on the first surface S1 side of the semiconductor layer 21 through an insulating layer 110, and an insulating layer 125 disposed on the side of the semiconductor layer 120 opposite to the insulating layer 110 side. Then, in the solid-state imaging apparatus 1G of the seventh embodiment, unlike the first embodiment described above, the pixel circuit 16 (see...) Figure 3 The pixel transistor Q included in the image is disposed in the semiconductor layer 120. Figure 38 In the diagram, the amplifying transistor AMP and the switching transistor FDG are shown as examples of the pixel transistor Q.

[0537] like Figure 38 As shown, each of the photoelectric conversion unit 25, the transmission transistor TR, and the floating diffusion region FD is disposed on the side of the semiconductor layer 21, which is different from the semiconductor layer 120. The solid-state imaging device 1G of the seventh embodiment includes semiconductor layer 21 and semiconductor layer 120 stacked in the thickness direction (Z direction) of semiconductor layer 21 in one direction, separated by an insulating layer 110.

[0538] Here, in the seventh embodiment, semiconductor layer 21 corresponds to a specific example of the "first semiconductor layer" of the present technology, and semiconductor layer 120 corresponds to a specific example of the "second semiconductor layer" of the present technology.

[0539] In addition, such as Figure 38 As shown, the solid-state imaging device 1G according to the seventh embodiment also includes a conductive path 130 electrically connecting the floating diffusion region FD disposed on the semiconductor layer 21 side and the amplification transistor AMP and the switching transistor FDG disposed in the semiconductor layer 120.

[0540] Furthermore, the solid-state imaging device 1G according to the seventh embodiment also includes a relay conductive pad 46 disposed on the first face S1 side of the semiconductor layer 21 across the photoelectric conversion region 22 and the separation region 31 and electrically connected to the floating diffusion region FD of the photoelectric conversion region 22.

[0541] The conductive path 130 includes a relay conductive pad 46 disposed across the photoelectric conversion region 22 and the separation region 31 on the first face S1 side of the semiconductor layer 21 and electrically connected to the floating diffusion region FD of the photoelectric conversion region 22; and a through contact electrode 132 extending from the insulating layer 125 to the relay conductive pad 46 and connected to the relay conductive pad 46 in the stacking direction (Z direction) of the semiconductor layers 21 and 120. Furthermore, the conductive path 130 includes a contact electrode 133 embedded in the insulating layer 125 and connected to the gate electrode 44 of the amplifying transistor AMP; a contact electrode 134 embedded in the insulating layer 125 and connected to the main electrode region 45a serving as the source region of the switching transistor FDG; and a wiring 135 disposed on the side of the insulating layer 125 opposite to the semiconductor layer 120 side and electrically and mechanically connected to each of the through contact electrodes 132, 133, and 134.

[0542] For example, wiring 135 can be made of metal film such as aluminum (Al) or copper (Cu), or an alloy film mainly containing Al or Cu.

[0543] For example, a silicon oxide film can be used as the insulating layer 125.

[0544] The insulating layer 110 includes, for example, two insulating films 111 and 112. As the two insulating films 111 and 112, silicon oxide films can be used, for example.

[0545] As the semiconductor layer 120, a Si substrate, a SiGe substrate, an InGaAs substrate, etc. can be used. For example, the seventh embodiment uses a p-type semiconductor substrate made of single-crystal silicon as the semiconductor layer 120, but it is not limited to this.

[0546] Through contact electrode 132 is electrically insulated and isolated from semiconductor layer 120. For each of through contact electrode 132, contact electrode 133 and contact electrode 134, a high melting point metal film such as titanium (Ti) or tungsten (W) can be used, for example.

[0547] For example, a polycrystalline silicon film with impurities added to reduce resistance can be used as the relay conductive pad 46.

[0548] In the solid-state imaging device 1G according to the seventh embodiment, similar effects to those of the solid-state imaging device 1A according to the first embodiment can also be obtained. That is, this technology can also be applied to a two-stage stacked solid-state imaging device 1G in which the two semiconductor layers 21 and 120 are stacked in two stages.

[0549] Note that, although not shown, this technique can also be applied to multi-level stacked solid-state imaging devices in which three or more semiconductor layers are stacked in multiple levels.

[0550] [Eighth Implementation Plan]

[0551] In the eighth embodiment, an explanation will be given of the case where a two-dimensional material film is used as a conductive thin film.

[0552] Figure 39 This is a schematic longitudinal cross-sectional view illustrating the longitudinal structure of a solid-state imaging device according to the eighth embodiment of the present technology. Figure 39 In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0553] Figure 40 yes Figure 39 An enlarged longitudinal section view of a portion of the data.

[0554] like Figure 39 and Figure 40 As shown, the solid-state imaging device 1H according to the eighth embodiment of the present technology has a configuration that is basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, but differs in the configuration of the separation region.

[0555] That is, such as Figure 39 and Figure 40 As shown, the separation region 31 of the eighth embodiment includes a two-dimensional material membrane 64H, replacing the one described in the first embodiment. Figure 5 and Figure 6 The metal thin film 64 is shown. The two-dimensional material film 64H corresponds to a specific example of the "conductive film" of this technology. That is, the conductive film comprises the two-dimensional material film 64H.

[0556] Similar to the metal thin film 64 of the first embodiment, but unlike the fixed charge film 61, the two-dimensional material film 64H is selectively disposed in the separation region 31 and is not extended to the second facet S2 side of the semiconductor layer 21. Then, the two-dimensional material film 64H folds back at the bottom of the shallow separation region 31a, extends in the thickness direction (Z direction) of the semiconductor layer 21, and terminates on the outside of the second facet S2 of the semiconductor layer 21. That is, similar to the metal thin film 64 of the first embodiment, the two-dimensional material film 64H also has a U-shaped longitudinal cross-sectional shape in the separation region 31 along the thickness direction (Z direction) of the semiconductor layer 21.

[0557] Two-dimensional material membranes

[0558] Although not shown in detail, similar to the metal thin film 64 of the first embodiment, the two-dimensional material film 64H has an annular planar pattern (ring planar pattern), wherein the planar shape in the planar view continuously surrounds the periphery of a photoelectric conversion region 22 in the portion away from the folded-back portion. Then, similar to the metal thin film 64 of the first embodiment, the two-dimensional material film 64H has a lattice planar pattern (mesh planar pattern), wherein the planar shape in the planar view continuously surrounds the periphery of each of the plurality of photoelectric conversion regions 22 in the folded-back portion. That is, similar to the metal thin film 64 of the first embodiment, the two-dimensional material film 64H also surrounds the periphery of each of the plurality of photoelectric conversion regions 22 and is integrated across the plurality of photoelectric conversion regions 22.

[0559] The two-dimensional material film 64H is formed from a two-dimensional material with a stacked structure in which unit layers of a two-dimensional structure are stacked. Due to its two-dimensional structure, the two-dimensional material exhibits high carrier mobility.

[0560] Examples of two-dimensional materials include monolayered materials or compounds similar to monolayered materials, or transition metal dichalcogenides.

[0561] Monolayered materials or compounds similar to monolayered materials are compounds having a two-dimensional crystal structure composed of covalent bonds in which unit layers are stacked and bonded to each other by van der Waals forces. Examples of such compounds include graphene, black phosphorus, silicene, or hexagonal boron nitride (hBN). Two-dimensional material films 64H can be formed as a monolayer of one of these compounds, or as a stack of multiple of these compounds.

[0562] In addition, examples of single-atom layered materials include graphene or phosphorene.

[0563] Transition metal dichalcogenides are compounds represented by the formula MX2. In MX2, M is a transition metal element, such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ge, Zr, Nb, Mo, Ru, Rh, Pd, Sn, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, or Pb, and X is a chalcogenide, such as S, Se, or Te. More specifically, examples of transition metal dichalcogenides include CrS2, CrSe2, CrTe2, HfS2, HfSe2, HfTe2, MoS2, MoSe2, MoTe2, NiS2, NiSe2, SnS2, SnSe2, TiS2, TiSe2, TiTe2, WS2, WSe2, WTe2, ZeTe2, ZrS2, ZrSe2, or ZrTe2, etc. Two-dimensional material film 64H can be formed as a single layer of one of these compounds, or as a multilayer film of multiple of these compounds.

[0564] In particular, the two-dimensional material film 64H preferably includes any one of the following two-dimensional materials: MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, ZeTe2, HfSe2, HfTe2, graphene, or phosphorene.

[0565] <Various Properties of Graphene>

[0566] (Optical properties)

[0567] The transmittance of single-layer graphene is approximately 97%.

[0568] The transmittance of four-layer graphene is approximately 90%.

[0569] Logically speaking, 100 - 2.3N (where N is the number of layers)

[0570] (Electrical characteristics)

[0571] Four-layer graphene: Compared to TiN, the film thickness is less than half and the resistivity is 1 / 10.

[0572] Single-layer graphene: film thickness 0.34 nm, sheet resistance approximately 600 Ω / sq, resistivity approximately 0.0204 mΩ·cm

[0573] Four-layer graphene: film thickness 1.8 nm, sheet resistance approximately 377 Ω / sq, resistivity approximately 0.0606 mΩ·cm

[0574] TiN: 5 nm thick, resistivity approximately 0.6 mΩ·cm

[0575] Polycrystalline silicon: 60 nm thick, resistivity approximately 5 mΩ·cm

[0576] <<Main Effects of the Eighth Implementation Plan>>

[0577] The two-dimensional material film 64H can be formed by a film-forming process at approximately 400°C. Therefore, even after the formation of the fixed charge film 61, the two-dimensional material film 64H can be formed without deactivating the fixed charge in the fixed charge film 61.

[0578] Therefore, in the solid-state imaging apparatus 1H according to the eighth embodiment, by applying a third reference potential V3 to the two-dimensional material film 64H, holes (h) are induced on the semiconductor layer 21 side of the interface between the semiconductor layer 21 of the photoelectric conversion region 22 and the separation region 31. + Furthermore, it ensures pinning at the interface, thereby suppressing the generation of dark current. In addition, in the solid-state imaging device 1H according to the eighth embodiment, using the fixed charge film 61, holes (h) are induced on the semiconductor layer 21 side of the interface between the semiconductor layer 21 of the photoelectric conversion region 22 and the separation region 31. + Furthermore, it can ensure pinning at the interface, thereby suppressing the generation of dark current.

[0579] That is, in the solid-state imaging device 1H according to the eighth embodiment, since it has both the effect of suppressing dark current by fixing the potential of the two-dimensional material film 64H and the effect of suppressing dark current by fixing the charge film 61, the dark current can be significantly reduced.

[0580] Furthermore, by reducing the thickness of the two-dimensional material film 64H, the light absorption becomes less than that of the polycrystalline silicon film, thereby suppressing the reduction in quantum efficiency.

[0581] Therefore, in the solid-state imaging device 1H according to the eighth embodiment, dark current can also be reduced and the reduction in quantum efficiency can be suppressed.

[0582] Note that the thickness of the two-dimensional material film 64H is preferably less than 5 nm.

[0583] <<Variations on the Eighth Implementation Plan>>

[0584] The two-dimensional material film 64H is not limited to the eighth embodiment described above. It can also be used to replace the metal thin film 64 in the second to eighth embodiments and the ninth embodiment described below.

[0585] Furthermore, in the above-mentioned modified examples (modified examples 1-1 to 1-14 and modified example 2-1), a two-dimensional material film 64H can also be used to replace the metal thin film 64.

[0586] [Ninth Implementation Plan]

[0587] Figure 41A This is a schematic longitudinal cross-sectional view illustrating the longitudinal cross-sectional structure of a solid-state imaging device according to the ninth embodiment of the present technology.

[0588] Figure 41B It is shown schematically. Figure 41A The following is a longitudinal section diagram of the longitudinal section structure.

[0589] Figure 41C It is shown schematically. Figure 41B The following is a longitudinal section diagram of the longitudinal section structure.

[0590] Note that, for easier observation, Figures 41A-41C The longitudinal cross-sectional structure from the effective pixel region of the pixel array to the optical black region 2A2 is shown in a segmented manner. Then, Figures 41A-41C The longitudinal section relative to the first embodiment described above Figure 5 The longitudinal section is reversed vertically.

[0591] In addition, Figures 41A-41C In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0592] like Figures 41A-41C As shown, the solid-state imaging device 1I according to the ninth embodiment of the present technology has a configuration that is basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, except for the configuration of the optical black region 2A2. Other configurations are basically similar to those of the first embodiment described above.

[0593] That is, such as Figures 41A-41C As shown, the optical black region 2A2 of this technology includes the first embodiment described above. Figure 10B Wiring 54w1 shown (refer to) Figure 41C As a conductor to which a potential is applied and which is electrically connected to the metal thin film 64, it also includes the modifications 1-13 described above. Figure 24B The wiring shown is 54m (refer to). Figure 41B Then, similar to the above-described modifications 1-13, a relay electrode 78 serving as a conductor is provided in the shallow separation region 31a of the separation region 31 (see reference). Figure 41B In the ninth embodiment, relay electrode 78, wiring 54m, and wiring 54w1 correspond to a specific example of the “conductor to which a potential is applied” in this technology.

[0594] Although not shown in detail, the relay electrode 78 of the ninth embodiment is also disposed at the intersection of the first in-plane extension 31x and the second in-plane extension 31y of the separation region 31. The relay electrode 78 is then embedded in, for example, a shallow separation region 31a.

[0595] like Figure 41BAs shown, the shallow separation region 31a of the ninth embodiment includes a shallow excavation section 32a, a segment insulating film 36, and a relay electrode 78. The relay electrode 78 is then insulated and isolated from the semiconductor layer 21 by the segment insulating film 36. The relay electrode 78 is then electrically and mechanically connected to the metal film 64 of the deep separation region 31b at the bottom side of the shallow separation region 31a. The relay electrode 78 is then electrically connected to the wiring 54m disposed in the first wiring layer 54 via a contact electrode 53m disposed in the interlayer insulating film 52. A negative potential, for example -2.0 V, is then applied to the wiring 54w1 as a third reference potential V3. That is, the metal film 64 of the separation region 31 in the optical black region 2A2 is electrically connected to each of the wiring 54w1 and wiring 54m, which are conductors with applied negative potentials and the third reference potential V3.

[0596] This technology can also be applied to the solid-state imaging device 1I according to the ninth embodiment, and can achieve similar effects to the solid-state imaging device 1A of the first embodiment described above.

[0597] Furthermore, since the metal film 64 of the separation region 31 in the optical black region 2A2 is electrically connected to each of the wirings 54w1 and 54m of the third reference potential V3 to which a negative potential is applied, the potential supply to the metal film 64 of the separation region 31 in the effective pixel region can be stabilized compared to the first embodiment.

[0598] Note that in the ninth embodiment, it has been described that the metal film 64 of the separation region 31 in the optical black region 2A2 is electrically connected to each of the wires 54w1 and 54m to which the applied potential is applied; however, the electrical connection between the metal film 64 and the wires 54w1 may be omitted.

[0599] [Tenth Implementation Plan]

[0600] In the tenth embodiment, a description will be given of a configuration specifically designed to suppress dark current by fixing the potential of the metal thin film 64.

[0601] Figure 42 This is a diagram showing a solid-state imaging apparatus according to a tenth embodiment of the present technology, and is a plan view schematically showing an example of the configuration of pixel blocks included in the pixel array section.

[0602] Figure 43 It is an illustrative representation along Figure 42 The longitudinal section diagram of the longitudinal section structure is taken from the section line a42-a42.

[0603] Figure 44 yes Figure 43 An enlarged longitudinal section view of a portion of the data.

[0604] Figure 45 It is an illustrative representation along Figure 43 The cross-sectional view of the cross-sectional structure cut by section line a43-a43.

[0605] Figure 46 It is an illustrative representation along Figure 43 The cross-sectional view of the cross-sectional structure taken by section line b43-b43.

[0606] Figure 47 It is an illustrative representation along Figure 43 The cross-sectional view of the cross-sectional structure cut by section line c43-c43.

[0607] Figure 48A It is an illustrative representation of... Figure 1 The longitudinal section diagram of the longitudinal section structure at the same position as section line 1a-1a.

[0608] Figure 48B It is an illustrative representation of... Figure 1 At the same position of section line 1a-1a Figure 48A The following is a longitudinal section diagram of the longitudinal section structure.

[0609] Note that, compared with the first implementation scheme described above... Figure 4 and Figure 5 Similarly, in Figure 42 For ease of observation, the diagram of the multi-layer wiring layer 51 has been omitted. Figure 43 The illustration of the layer above the first wiring layer 54 included in the multilayer wiring layer 51 is omitted.

[0610] also, Figure 42 This is a plan view taken from the opposite side of the light incident surface (multilayer wiring layer side) of semiconductor chip 2.

[0611] In addition, for ease of observation, Figure 48A and Figure 48B It is shown in a segmented manner with Figure 1 The longitudinal section structure at the same position as section line a1-a1. Then, Figure 10A and Figure 10B The longitudinal section relative to Figure 43 The longitudinal section is reversed vertically.

[0612] In addition, Figure 43 and Figures 45-48B In the image, the shading lines representing the cross-sections have been partially omitted for easier observation.

[0613] The solid-state imaging device 1J according to the tenth embodiment of the present technology is substantially similar in configuration to the solid-state imaging device 1A according to the first embodiment, but differs in the following configurations.

[0614] That is, the solid-state imaging device 1J according to the tenth embodiment of this technology includes Figure 42 and Figure 43 The separation region 31J shown is used in place of the first embodiment described above. Figure 4 and Figure 5 The separation region 31 is shown. Then, depending on the configuration of the separation region 31J, the configuration between the second face S2 of the semiconductor layer 21 and the optical filter layer 74 is also different.

[0615] <Separated Region>

[0616] like Figure 42 and Figure 43 As shown, the separation region 31J of the tenth embodiment has a configuration substantially similar to that of the insulating region 31 according to the first embodiment described above, and the main difference lies in the configuration of the longitudinal section along the thickness direction (Z direction) of the semiconductor layer 21. Since the planar pattern of the separation region 31J is substantially similar to that of the separation region 31 according to the first embodiment described above, the description of the planar pattern of the separation region 31J is omitted.

[0617] like Figure 43 and Figure 44 As shown, the separation region 31J extends in the thickness direction (Z direction) of the semiconductor layer 21 as one direction, and provides electrical and optical separation between two adjacent photoelectric conversion regions 22 in the plan view. Then, the separation region 31J is constructed, for example, as a trench type, wherein trenches 32 are formed in the semiconductor layer 21 to separate and isolate the photoelectric conversion regions 22.

[0618] Here, as described in the first embodiment above, the inside of the excavation portion 32 formed in the semiconductor layer 21 is filled with a film; however, even after the film is filled therein, the excavation portion 32 is still referred to as such.

[0619] In addition, the excavation section 32 can also be called the hole section or the groove section.

[0620] (Excavation Department)

[0621] like Figure 43 and Figure 44 As shown, the excavation section 32 includes a shallow excavation section (shallow excavation section) 32a disposed on the first surface S1 side of the semiconductor layer 21 and a deep excavation section (deep trench section) 32b extending from the shallow excavation section 32a toward the second surface S2 side of the semiconductor layer 21. In the plan view, its width W2 in the short side direction (refer to...) Figure 44 Narrower than the width W1 of the shallow excavation section 32a in the short side direction (refer to...) Figure 44The deep-drilling section 32b of the tenth embodiment is not limited to this, but is, for example, connected to the shallow-drilling section 32a and extending from the shallow-drilling section 32a to the second facet S2 of the semiconductor layer 21. The drilling section 32 has a grid-like planar pattern similar to the separation region 31J in a plan view.

[0622] Here, as described in the first embodiment above, the short side direction of each of the shallow excavation section 32a and the deep excavation section 32b refers to the constitutive direction of the two photoelectric conversion regions 22 arranged in a way that separates them from each other in the plan view. In other words, it refers to the separation direction in which the two photoelectric conversion regions 22 are separated from each other.

[0623] (Shallow separation region and deep separation region)

[0624] like Figure 42 and Figure 43 As shown, the separation region 31J includes a shallow separation region 31a disposed in the surface portion on the first face S1 side of the semiconductor layer 21 and a deep separation region 31b extending from the bottom side of the shallow separation region 31a toward the second face S2 side of the semiconductor layer 21. In the plan view, its width W4 in the short side direction (refer to...) Figure 44 Narrower than the shallow separation region 31a in the short side direction W3 (refer to) Figure 6 The deep separation region 31b of the tenth embodiment is not limited to this, but is, for example, connected to the bottom of the shallow separation region 31a and extends from the bottom of the shallow separation region 31a to the second face S2 of the semiconductor layer 21.

[0625] Here, as described in the first embodiment above, the short side direction of each of the shallow separation region 31a and the deep separation region 31b refers to the constitutive direction of the two photoelectric conversion regions 22 arranged in a way that separates them from each other in the plan view. In other words, it refers to the separation direction in which the two photoelectric conversion regions 22 are separated from each other.

[0626] Similar to the first embodiment described above, each of the shallow separation region 31a and the deep separation region 31b is formed in each of the first in-plane extension portion 31x and the second in-plane extension portion 31y. That is, each of the first in-plane extension portion 31x and the second in-plane extension portion 31y of the separation region 31J includes a shallow separation region 31a and a deep separation region 31b.

[0627] Each of the shallow separation region 31a and the deep separation region 31b is not limited thereto, but rather has the same planar pattern, for example, in a planar view. In the tenth embodiment, each of the shallow separation region 31a and the deep separation region 31b has a grid-like planar pattern.

[0628] Note that the shallow separation region 31a can also be used as a segment separation region separating the element formation region on the first face S1 side of the semiconductor layer 21. In this case, the deep separation region 31b overlaps with the segment separation region in the plan view and, together with the segment separation region, separates the photoelectric conversion region 22.

[0629] <Specific Composition of the Separated Region>

[0630] Next, we will give a detailed description of the specific structure of the separation region 31J.

[0631] like Figure 43 and Figure 44 As shown, the separation region 31J includes a digging section 32 having a shallow digging section 32a and a deep digging section 32b, a separation insulating film 81 disposed on the inner side of the digging section 32 along the side portion of the semiconductor layer 21 (photoelectric conversion region 22), and a metal thin film 64 serving as a conductive film disposed on the side of the separation insulating film 81 opposite to the digging section 32 side.

[0632] Furthermore, the separation region 31J also includes an insulating film 65 disposed on the side of the metal film 64 opposite to the separation insulating film 81 side, and a section insulating film 36 disposed on the side of the separation insulating film 81 opposite to the digging section 32 side. The section insulating film 36 is disposed in the shallow digging section 32a through the separation insulating film 81. Each of the metal film 64 and the insulating film 65 is disposed in the deep digging section 32b mainly through the separation insulating film 81.

[0633] Here, the separation region 31J in the tenth embodiment does not include the region in the first embodiment described above. Figure 5 and Figure 6 The fixed charge film 61 is shown. Then, the separation region 31J of the tenth embodiment includes a separation insulating film 81, replacing the one described in the first embodiment. Figure 5 and Figure 6 The insulating film 63 shown.

[0634] (Separating the insulating film)

[0635] like Figure 43 and Figure 44As shown, the separating insulating film 81 extends across the shallow excavation portion 32a and the deep excavation portion 32b included in the excavation portion 32, and is disposed along the side portion of the semiconductor layer 21 on the inner side of each of the shallow excavation portion 32a and the deep excavation portion 32b. Then, in the thickness direction (Z direction) of the semiconductor layer 21, the separating insulating film 81 terminates at the first surface S1 side of the semiconductor layer 21 and terminates at the second surface S2 side of the semiconductor layer 21. Then, in the plan view, the separating insulating film 81 is disposed on the side portion side of each of the two semiconductor layers 21 (photoelectric conversion regions 22) located opposite each other across the excavation portion 32. Then, with the first embodiment described above... Figure 5 and Figure 6 Unlike the fixed charge film 61 and insulating film 63 shown, the separation insulating film 81 is selectively disposed in the separation region 31J in the plan view and is not led out to the second face S2 side of the semiconductor layer 21.

[0636] The separating insulating membrane 81 comprises at least one of a silicon oxide (SiO) film or a silicon nitride (SiN) film. The separating insulating membrane 81 of the tenth embodiment is not limited thereto, but rather as follows: Figure 43 and Figure 44 As shown, a silicon oxide film 81a and a silicon nitride film 81b are sequentially disposed, for example, from the side portion of the semiconductor layer 21 inside the mining section 32 toward the metal thin film 64. The silicon oxide film 81a is disposed on the side portion of the semiconductor layer 21, spanning both the shallow mining section 32a and the deep mining section 32b, inside each of them. The silicon nitride film 81b is disposed on the side of the silicon oxide film 81a opposite to the semiconductor layer 21 side, spanning both the shallow mining section 32a and the deep mining section 32b, inside each of them.

[0637] The separating insulating film 81 is formed with a film thickness that follows the wall shape along the inner side of the excavation portion 32. The film thickness of the separating insulating film 81 is preferably 20 nm or less. In the tenth embodiment, for example, each of the silicon oxide film 81a and the silicon nitride film 81b is formed with a film thickness of approximately 10 nm. The silicon oxide film 81a and the silicon nitride film 81b have different etching rates.

[0638] As described above, the separation insulating film 81 is disposed across the shallow excavation portion 31a and the deep excavation portion 32b. In other words, the separation insulating film 81 is disposed across the first facet S1 and the second facet S2 of the semiconductor layer 21. During the manufacturing process of the solid-state imaging device, this separation insulating film 81 can be easily formed by forming a film from the first facet S1 side (transistor forming facet side) of the semiconductor layer 21, which is opposite to the second facet S2 side (light incident facet side).

[0639] (metal film)

[0640] like Figure 43 and Figure 44 As shown, the metal thin film 64 extends in the thickness direction (Z direction) of the semiconductor layer 21. Then, the metal thin film 64 folds back at the bottom of the shallow separation region 31a (specifically, the bottom surface of the segment insulating film 36) on the first surface S1 side of the semiconductor layer 21, and terminates at the outer side of the second surface S2 side of the semiconductor layer 21. The metal thin film 64 is then disposed on the side surface of each of the two semiconductor layers 21 (photoelectric conversion regions 22) located opposite each other across the cutout portion 32. That is, similar to the first embodiment described above, the metal thin film 64 of the tenth embodiment also has a U-shaped longitudinal cross-sectional shape of the separation region 31J along the thickness direction (Z direction) of the semiconductor layer 21. Furthermore, similar to the first embodiment described above... Figure 5 and Figure 6 Unlike the fixed charge film 61 shown, the metal thin film 64 of the tenth embodiment is selectively disposed in the separation region 31J in the plan view and is not led out to the second face S2 side of the semiconductor layer 21.

[0641] The metal thin film 64 is folded back at the bottom of the shallow separation region 31a (the bottom surface of the segment insulating film 36). Unlike the separation insulating film 81 described above, this metal thin film 64 can be easily formed by forming a film from the second surface S2 side (light incident surface side) of the semiconductor layer 21 during the manufacturing process of the solid-state imaging device.

[0642] like Figure 46 and Figure 47 As shown, the metal thin film 64 has an annular planar pattern (ring planar pattern), wherein the planar shape in the planar view continuously surrounds a photoelectric conversion region 22 in the portion away from the folded-back portion. On the other hand, as Figure 45 As shown, the metal thin film 64 has a lattice-like planar pattern (mesh planar pattern), wherein the planar shapes in the planar view continuously surround each of the plurality of photoelectric conversion regions in the folded-back portion. That is, in the tenth embodiment, the metal thin film 64 also surrounds each of the plurality of photoelectric conversion regions 22 and is integrated across the plurality of photoelectric conversion regions 22. Furthermore, in the tenth embodiment, although not limited thereto, a titanium nitride (TiN) film, for example, is used as the metal thin film 64.

[0643] The metal thin film 64 is formed with a thickness that is separated from the insulating film 81 and has a shape along the inner side wall of the deep excavation portion 32b. The thickness of the metal thin film 64 is preferably about 5 nm, and can be in the range of 0.5 nm to 10 nm. That is, for the metal thin film 64, 10 nm or less is preferred.

[0644] Towards Figure 44 The metal film 64 shown is supplied with a potential. Also in the tenth embodiment, since the trap region 23 in contact with the separation region 31J is p-type, a negative potential of, for example, -2.0 V is applied to the metal film 64 as a third reference potential V3. The potential applied to the metal film 64 is maintained during operation of the solid-state imaging device 1J.

[0645] By applying a third reference potential V3 to the metal thin film 64, holes (h) are induced on the semiconductor layer 21 side of the interface between the semiconductor layer 21 of the photoelectric conversion region 22 and the separation region 31J. + Furthermore, it can ensure pinning at the interface, thereby suppressing the generation of dark current.

[0646] Similarly, in the tenth embodiment, similar to the first embodiment described above, for example, a first reference potential V1 of “0 V” is applied to the p-type well region 23 as a power supply potential, and during the operation of the solid-state imaging device 1J, the p-type well region 23 is fixed at the first reference potential V1.

[0647] (Insulating film)

[0648] like Figure 43 and Figure 44 As shown, the insulating film 65 extends in the thickness direction (Z direction) of the semiconductor layer 21. The insulating film 65 terminates at the folded-back portion of the metal film 64 on the first surface S1 side of the semiconductor layer 21, and terminates on the outer side of the second surface S2 side of the semiconductor layer 21. Similar to the metal film 64, the insulating film 65 is also selectively disposed in the separation region 31 and is not extended to the second surface S2 side of the semiconductor layer 21. Then, inside the cutout portion 32, the insulating film 65 is disposed between two spaced-apart metal films 64.

[0649] (Shallow separation region and deep separation region)

[0650] like Figure 43 and Figure 44 As shown, the shallow separation region 31a of the tenth embodiment includes a shallow excavation section 32a contained in the excavation section 32, a separation insulating film 81 disposed on the inner side of the shallow excavation section 32 along the side portion of the semiconductor layer 21 (photoelectric conversion region 22), and a section insulating film 36 disposed on the side of the separation insulating film 81 opposite to the shallow excavation section 32a side to fill the shallow excavation section 32a.

[0651] like Figure 43 and Figure 44As shown, the deep separation region 31b of the tenth embodiment includes a deep excavation section 32b contained in the excavation section 32, a separation insulating film 81 disposed along the side portion of the semiconductor layer 21 (photoelectric conversion region 22) inside the deep excavation section 32b, a metal thin film 64 disposed along the separation insulating film 81 on the side opposite to the semiconductor layer 21 side, and an insulating film 65 disposed on the side of the metal thin film 64 opposite to the separation insulating film 81 side to fill the deep excavation section 32b. In the tenth embodiment, for example, a silicon oxide (SiO2) film is used as the insulating film 65.

[0652] The insulating film 65 is formed to a thickness such that the space formed by the folded-back metal film 64 is filled by it. The thickness of the insulating film 65 is preferably about 10 nm, and can be a value in the range of 1 to 500 nm.

[0653] <The structure between the second face of the semiconductor layer and the optical filter layer>

[0654] like Figure 43 and Figure 44 As shown, on the second surface S2 side of the semiconductor layer 21, a fixed charge film 61, an anti-reflection film 62, and a sealing insulating film 66 are sequentially disposed starting from the second surface S2 side of the semiconductor layer 21. Each of the fixed charge film 61 and the anti-reflection film 62 is selectively disposed in the photoelectric conversion region 22, but not in the separation region 31J, in the plan view. On the other hand, the sealing insulating film 66 is disposed across the photoelectric conversion region 22 and the separation region 31J in the plan view.

[0655] <Optical Black Area>

[0656] like Figure 48A and Figure 48B As shown, the optical black region 2A2 of the pixel array section 2A includes a light-shielding film 72 disposed on the second surface S2 side of the semiconductor layer 21, separated by films such as a fixed charge film 61, an anti-reflective film 6, and a sealing insulating film 66. Furthermore, the optical black region 2A2 also includes a photoelectric conversion region 22A and a non-photoelectric conversion region 22B disposed in the semiconductor layer 21 and separated by a separation region 31J. Unlike the effective pixel region 2A1 of the pixel array section 2A, the optical black region 2A2 does not include an optical filter section 74a or a microlens 75a.

[0657] Each of the photoelectric conversion region 22A and the non-photoelectric conversion region 22B is covered by a light-shielding film 72 disposed on the second face S2 side of the semiconductor layer 21. Figure 48A and Figure 48B In the optical black area 2A2, one photoelectric conversion region 22A and two non-photoelectric conversion regions 22B are shown; however, the number of photoelectric conversion regions 22A and non-photoelectric conversion regions 22B is not limited to... Figure 48A and Figure 48B The quantity in.

[0658] like Figure 48A and Figure 48B As shown, the photoelectric conversion region 22A of the optical black region 2A2 has a similar configuration to the photoelectric conversion region 22 of the effective pixel region 2A1, and includes a photoelectric conversion unit 25. On the other hand, unlike the photoelectric conversion region 22 of the effective pixel region 2A1, the non-photoelectric conversion region 22B does not include the photoelectric conversion unit 25.

[0659] like Figure 48B As shown, the non-photoelectric conversion region 22B includes a p-type well region 23b disposed in the semiconductor layer 21 across a first face S1 and a second face S2, and a p-type power supply contact region WC1 disposed in the p-type well region 23b on the first face S1 side of the semiconductor layer 21.

[0660] The p-type well region 23b is in contact with the separation region 31J along the thickness direction (Z direction) of the semiconductor layer 21. The p-type well region 23 is formed by a p-type semiconductor region.

[0661] The p-type power supply contact region WC1 is disposed in the p-type well region 23b on the first surface S1 side of the semiconductor layer 21 and is electrically connected to the p-type well region 23b. The p-type power supply contact region WC1 includes a p-type semiconductor region with an impurity concentration higher than that of the p-type well region 23b.

[0662] like Figure 48B As shown, the light-shielding film 72 is electrically and mechanically connected to the p-type well region 23b of the non-photoelectric conversion region 22B and the metal thin film 64 of the separation region 31 through a through-hole 76 disposed on the second face S2 side of the semiconductor layer 21 in the optical black region 2A2.

[0663] A through-hole 76 is disposed across two adjacent non-photoelectric conversion regions 22B, separated by the separation region 31, and overlaps with the p-type well region 23b and the separation region 31 in a plan view. The through-hole 76 then penetrates the sealing insulating film 66, the anti-reflective film 62, the fixed charge film 61, etc., and reaches the p-type well region 23b and the metal film 64. That is, the light-shielding film 72 is electrically and mechanically connected to the p-type well region 23b of each of the two adjacent non-photoelectric conversion regions 22B separated by the separation region 31, and is also electrically and mechanically connected to the metal film 64 in the separation region 31 sandwiched between the two non-photoelectric conversion regions 22B.

[0664] W is preferred as the material for the light-shielding film 72, and other metallic materials including at least one of Ti, W, Ni, N, Ru, Cu, Co, Mo or Al can also be used.

[0665] <<Electrical Supply>>

[0666] like Figure 10B As shown, the metal film 64 of the optical black region 2A2 is electrically connected to the wiring 54w1 via the light-shielding film 72, the p-type well region 23b, the p-type power supply contact region WC1, and the contact electrode 53w1. The metal film 64 of the optical black region 2A2 is integrated with the metal film 64 of the effective pixel region 2A1 on the folded-back side of the metal film 64. Then, a negative potential of, for example, -2.0 V is applied to the wiring 54w1 as a third reference potential V3. That is, the metal film 64 of the separation region 31J in the effective pixel region 2A1 is electrically connected to the wiring 54w1 (as a conductor of the applied potential) to the third reference potential V3 to which the negative potential is applied.

[0667] Here, in the tenth embodiment, wiring 54w1 corresponds to a specific example of the “conductor to which a potential is applied” in this technology.

[0668] For example, a first reference potential V1 of "0 V" is applied to... Figure 43 The wiring 54w is shown. Then, the wiring 54w is electrically connected to the p-type well region 23 via the contact electrode 53w and the p-type power supply contact region WC. That is, in the tenth embodiment, similar to the first embodiment described above, the p-type well region 23 of the photoelectric conversion region 22 is electrically connected to the wiring 54w, which is subjected to a first reference potential V1 of "0 V".

[0669] Note that in Figure 10B The diagram shows a case where the p-type power supply contact area WC1 is disposed in one of the two non-photoelectric conversion areas 22B connected to the light-shielding film 72; however, the contact electrode 53w1 can be disposed in each of the two non-photoelectric conversion areas 22B, and the wiring 54w1 can be electrically connected to the p-type well area 23b of each of the two non-photoelectric conversion areas 22B.

[0670] <<Manufacturing Methods of Solid-State Imaging Devices>>

[0671] Next, we will refer to Figures 49A-49J This describes a method for manufacturing a solid-state imaging device 1J according to the tenth embodiment of this technology.

[0672] In the tenth embodiment, the formation of the separation region 31J, which is specifically concentrated in the manufacturing method of the solid-state imaging device 1J, is described.

[0673] First, in a manner similar to the first implementation scheme described above, such as Figure 49AAs shown, a trench 32 is formed extending from the first surface S1 of the semiconductor layer 21 toward the second surface S2, and a photoelectric conversion region 22 is formed by the trench 32. The trench 32 includes a shallow trench 32a formed on the first surface S1 of the semiconductor layer 21 and a deep trench 32b extending from the bottom of the shallow trench 32a toward the second surface S2 of the semiconductor layer 21. The width W2 of the short side of the deep trench 32b is narrower than the width W1 of the short side of the shallow trench 32a.

[0674] Next, as Figure 49B As shown, a separation insulating film 81 is formed from the first surface S1 side (transistor forming surface side) of the semiconductor layer 21, opposite to the second surface S2 side (light incident surface side). The separation insulating film 81 is formed across the wall surface of the semiconductor layer 21 inside the excavation portion 32 and the first surface S1 of the semiconductor layer 21. The separation insulating film 81 includes, for example, a silicon oxide film 81a formed on the semiconductor layer 21 side and a silicon nitride film 81b formed on the side of the silicon oxide film 81a opposite to the semiconductor layer 21 side. Each of the silicon oxide film 81a and the silicon nitride film 81b is formed to a film thickness that is folded back along the wall surface of the semiconductor layer 21 inside the excavation portion 32. Each of the silicon oxide film 81a and the silicon nitride film 81b is formed by the ALD method, which forms films with good film quality even at thin film thicknesses.

[0675] In the multilayer wiring layer 51 described later (see reference) Figure 49E A separation insulating film 81, comprising a silicon oxide film 81a and a silicon nitride film 81b, is formed prior to the formation of the multilayer wiring layer 51. When the separation insulating film 81 is formed after the formation of the multilayer wiring layer 51, it needs to be formed at a temperature lower than the melting temperature (below 400°C) of the wiring included in the multilayer wiring layer 51, resulting in a decrease in the film quality of the separation insulating film 81. Therefore, by forming the separation insulating film 81 before the multilayer wiring layer 51, as in the manufacturing process of the tenth embodiment, a separation insulating film 81 with good film quality can be formed at high temperatures, without being limited by the temperature imposed by the multilayer wiring layer 51. In particular, this effect on film quality is most significant for the silicon oxide film 81a.

[0676] In this process, since a separation insulating film 81, including a silicon oxide film 81a and a silicon nitride film 81b, is formed from the first face S1 side (transistor forming face side) of the semiconductor layer 21, even in a mining section 32 that includes shallow mining sections 32a and deep mining sections 32b with different widths (W1 and W2) in the short side direction, a separation insulating film 81 extending continuously across the shallow mining section 32a and the deep mining section 32b can be formed on the side face of the semiconductor layer 21 inside the mining section 32.

[0677] Next, after forming the separation insulating film 81, as... Figure 49C As shown, a polycrystalline silicon film 35 is formed on the first surface S1 side of the semiconductor layer 21, including the inner side of the excavation portion 32. The polycrystalline silicon film 35 is formed to a thickness such that the excavation portion having the separation insulating film 32 is filled therein.

[0678] Next, each of the polysilicon film 35 on the first face S1 side of the semiconductor layer 21 and the separation insulating film 32, as well as the polysilicon film 35 of the shallow cut portion 32a included in the cut portion 32, is selectively removed by, for example, etching back or CMP. Thereafter, as... Figure 49D As shown, a section insulating film 36 is selectively formed on the inner side of the shallow excavation section 32a, separated by a separation insulating film 81.

[0679] By forming an insulating film on the first facet S1 side of the semiconductor layer 21 to fill the shallow cutout portion 32a, and then selectively removing the insulating film on the first facet S1 side of the semiconductor layer 21 by, for example, CMP or etching back, so that the insulating film remains in the shallow cutout portion 32a, a segment insulating film 36 can be formed inside the shallow cutout portion 32a. As described in the first embodiment above, the segment insulating film 36 uses a film containing at least one of Si, N, Al, or Hf.

[0680] During this process, a shallow separation region 31a, including a shallow cutout region 32a and a segment insulating film 36, is formed on the surface portion of the first facet S1 of the semiconductor layer 21. The shallow separation region 31a is formed in a grid-like planar pattern across the effective pixel region 2A1 and the optical black region 2A2 of the semiconductor layer 21.

[0681] Next, in the photoelectric conversion region 22, Figure 49E The transmission transistor TR, the n-type floating diffusion region FD, and the p-type power supply contact region WC shown are formed in the surface portion of the first face S1 side of the semiconductor layer 21, and a pixel transistor Q is also formed thereal, although not shown.

[0682] In addition, during this process, refer to Figure 48B A p-type power supply contact region WC1 is formed in the surface portion of the semiconductor layer 21 on the first face S1 side in the non-photoelectric conversion region 22B.

[0683] Next, as Figure 49E As shown, an interlayer insulating film 52, contact electrodes 53f, 53w, and 53w1 (see reference) are formed on the first surface S1 side of the semiconductor layer 21. Figure 48B ) and the multilayer wiring layer 51 of the first wiring layer 54.

[0684] During this process, the separation insulating film 81 has been formed on the inner side of the excavation section 32.

[0685] Next, after forming the multi-layer wiring layer 51, as follows Figure 49F As shown, a thinning process is performed, wherein the second face S2 side of the semiconductor layer 21 is cut to the thinning line S2a by, for example, CMP method, to reduce the thickness of the semiconductor layer 21.

[0686] During this process, the deep-drilled portion 32b extending along the thickness direction (Z direction) of the semiconductor layer 21 and the polycrystalline silicon film 35 are exposed at the first surface S1 of the semiconductor layer 21.

[0687] Furthermore, during this process, a digging portion 32 is formed, which includes a shallow digging portion 32a and a deep digging portion 32b and extends across the first facet S1 and the second facet S2 of the semiconductor layer 21. A separation insulating film 81 extending across the first facet S1 and the second facet S2 of the semiconductor layer 21 is formed on the side portion of the semiconductor layer 21 inside the digging portion 32.

[0688] Next, as Figure 49G As shown, the polysilicon film 35 of the deep excavation section 32b is removed. The polysilicon film 35 is removed by wet chemical treatment.

[0689] In this process, the silicon nitride film 81b serves as an etching stop film and can suppress the reduction (thinning) of the film thickness of the silicon oxide film 81a.

[0690] Next, as Figure 49H As shown, a fixed charge film 61 and an anti-reflective film 62 with negative fixed charges are sequentially and selectively formed on the first surface S1 side of the semiconductor layer 21. Then, as... Figure 49H As shown, a metal thin film 64 and an insulating film 65 are formed. A fixed-charge film 61 with a negative fixed charge is formed, for example, by an ALD method. An anti-reflective film 62 is formed, for example, by a CVD method.

[0691] Each of the metal thin film 64 and the insulating film 65 is formed across the inner side of the deep-drilled portion 32b and the second face S2 side of the semiconductor layer 21. The metal thin film 64 is then formed with a film thickness that folds back along the inner wall face (side face and bottom face) of the deep-drilled portion 32b, such that the inner side (deep-drilled portion 32b side of the separating insulating film 81) in the deep-drilled portion 32b is not filled. On the other hand, the insulating film 65 is formed with a film thickness that fills the inner side of the metal thin film 64 in the deep-drilled portion 32b.

[0692] The metal thin film 64 can be any of the aforementioned metal thin films, or a laminate of these metal thin films. Similarly, in the tenth embodiment, as in the first embodiment described above, the metal thin film 64 is, for example, a titanium nitride (TiN) film with a thickness of approximately 5 nm. The thickness of the metal thin film 64 can be in the range of approximately 0.5 to 10 nm.

[0693] As the insulating film 65, the aforementioned insulating film can be used, or a laminate of these insulating films can be used. Similarly, in the tenth embodiment, as in the first embodiment described above, as the insulating film 65, for example, a silicon oxide (SiO2) film with a thickness of about 10 nm is formed. The film thickness of the insulating film 65 can be a value in the range of about 1 to 500 nm.

[0694] As the metal thin film 64, for example, a titanium nitride (TiN) film can be formed by an ALD process at approximately 400°C. Therefore, even after the fixed charge film 61 is formed, the metal thin film 64 can be formed without deactivating the fixed charge in the fixed charge film 61 on the second facet S2 side of the semiconductor layer 21 in the photoelectric conversion region 22. Furthermore, with the aforementioned metal film and laminated film, the metal thin film 64 can be formed even after the fixed charge film 61 is formed without deactivating the fixed charge in the fixed charge film 61.

[0695] Next, as Figure 49I As shown, the insulating film 65 and the metal film 64 on the outer side of the second face S2 of the semiconductor layer 21 are selectively removed, for example, by an etch-back method, such that the metal film 64 selectively remains inside the separated insulating film 81 in the deep-cut section 32b, and the insulating film 65 selectively remains inside the metal film 64. The etch-back is performed with an etch-back amount sufficient to at least remove the metal film 64 on the second face S2 side of the semiconductor layer 21.

[0696] During this process, a deep separation region 31b is formed, comprising a deep excavation section 32b, a separation insulating film 81, a metal thin film 64, and an insulating film 65. The deep separation region 31b is formed in a grid-like planar pattern across the effective pixel region 2A1 and the optical black region 2A2 of the semiconductor layer 21.

[0697] Furthermore, during this process, a separation region 31J is formed, comprising a shallow separation region 31a and a deep separation region 31b. The separation region 31J is formed in a grid-like planar pattern across the effective pixel region 2A1 and the optical black region 2A2 of the semiconductor layer 21.

[0698] Next, as Figure 49J As shown, a sealing insulating film 66 covering the photoelectric conversion region 22 and the separation region 31J, as well as the photoelectric conversion region 22A and the non-photoelectric conversion region 22B of the optical black region 2A2, are formed on the second surface S2 side of the semiconductor layer 21. The sealing insulating film 66 can be the aforementioned insulating film, or a laminate of these insulating films. In the tenth embodiment, for example, a silicon oxide (SiO2) film is formed as the sealing insulating film 66.

[0699] Subsequently, by forming spacer 71, light-shielding film 72, padding insulating film 73, optical filter layer 74, lens layer 75, etc. on the second facet S2 side of semiconductor layer 21, a result is obtained. Figure 43 , Figure 44 , Figure 48A and Figure 48B The state shown.

[0700] <<Main Effects of the Tenth Implementation Plan>>

[0701] Next, the main effects of the tenth implementation plan will be explained.

[0702] The solid-state imaging apparatus 1J according to the first embodiment includes a separation region 31J. The separation region 31J then includes a cutout portion 32 extending in the thickness direction (Z direction) of the semiconductor layer 21, a separation insulating film 81 disposed on the inner side of the cutout portion 32 along the side portion of the semiconductor layer 21, and a metal thin film 64 serving as a conductive film disposed on the inner side of the cutout portion 32 along the separation insulating film 81 on the side opposite to the side of the cutout portion 32.

[0703] Then, by applying a third reference potential V3 (negative potential) to the metal thin film 64, holes (h) are induced on the semiconductor layer 21 side of the interface between the semiconductor layer 21 of the photoelectric conversion region 22 and the separation insulating film 81 of the separation region 31J. + Furthermore, it can ensure pinning at the interface, thereby suppressing the generation of dark current.

[0704] Here, in the separation region 31J, by reducing the film thickness of the separation insulating film 81, the effectiveness of the negative bias voltage is improved, and the effect of suppressing dark current can be further enhanced. However, in order to reduce the film thickness of the separation insulating film 81, it is necessary to form a high-quality film and ensure insulation resistance.

[0705] In the formation of the insulating film 81, there are cases where it is carried out after the formation of the multilayer wiring layer 51 in the manufacturing process of the solid-state imaging device and cases where it is carried out before the formation of the multilayer wiring layer 51.

[0706] When forming a separation insulating film 81 after forming a multilayer wiring layer 51, the separation insulating film 81 needs to be formed at a temperature lower than the melting temperature (below 400°C) of the wiring included in the multilayer wiring layer 51, making it difficult to form a high-quality film. This is particularly significant when an oxide film is formed by the ALD method.

[0707] On the other hand, if the separation insulation film 81 is formed before the formation of the multilayer wiring layer 51, the film can be formed at high temperature without being limited by the temperature of the melting temperature of the wiring included in the multilayer wiring layer 51, thereby forming a high-quality separation insulation film 81.

[0708] In the manufacturing process of the tenth embodiment, as described above, since the separation insulation film 81 is formed before the formation of the multilayer wiring layer 51, the film can be formed at high temperature without being limited by the temperature of the melting temperature of the wiring included in the multilayer wiring layer 51, thereby forming a high-quality separation insulation film 81.

[0709] Therefore, according to the solid-state imaging device 1J of the tenth embodiment, the separating insulating film 81 can be made thinner, which improves the effectiveness of the negative bias voltage when the third reference potential V3 is applied to the metal thin film 64 compared with the first embodiment described above, and can further enhance the effect of suppressing dark current by fixing the potential of the metal thin film 64. In the first embodiment described above, after the formation of the multilayer wiring layer 51, a fixed charge film 61 and an insulating film 63 (see reference) are formed in the separating region 31. Figure 11J and 11L ).

[0710] Furthermore, in the tenth embodiment, since the separation insulating film 81 is formed from the first face S1 side (transistor forming face side) of the semiconductor layer 21 opposite to the second face S2 side (light incident face side), the separation insulating film 81, which extends continuously across the first face S1 and the second face S2 of the semiconductor layer 21, can be easily disposed on the side face of the semiconductor layer 21 inside the excavation portion 32.

[0711] Specifically, the excavation portion 32 in the tenth embodiment has a longitudinal cross-sectional shape, which includes a shallow excavation portion 32a disposed on the first facet S1 side of the semiconductor layer 21 and a deep excavation portion 32b extending from the shallow excavation portion 32a toward the second facet S2 of the semiconductor layer 21 and having a width W2 in the short side direction in the plan view that is narrower than the width W1 of the shallow excavation portion 32a in the short side direction. Therefore, when the separation insulating film 81 is formed from the second facet S2 side of the semiconductor layer 21, it is difficult to provide a separation insulating film 81 that extends continuously across the first facet S1 and the second facet S2 of the semiconductor layer 21 on the side surface of the semiconductor layer 21 inside the excavation portion 32.

[0712] Furthermore, since the metal thin film 64 included in the separation region 31J of the tenth embodiment has a smaller light absorption than that of a polycrystalline silicon film by reducing the film thickness, the reduction in quantum efficiency can be suppressed.

[0713] Therefore, the solid-state imaging device 1J according to the tenth embodiment, similar to the solid-state imaging device 1A of the first embodiment described above, can reduce dark current and suppress the decrease in quantum efficiency.

[0714] Furthermore, the solid-state imaging device 1J according to the first embodiment includes a fixed-charge film 61 having a fixed charge and disposed on the second face S2 side of the semiconductor layer 21 to overlap with the photoelectric conversion region 22 on the light incident face side (second face S2 side) of the photoelectric conversion region 22. Using the fixed-charge film 61, holes (h) are induced on the photoelectric conversion region 22 side of the interface between the photoelectric conversion region 22 and the fixed-charge film 61. + Furthermore, it can ensure pinning at the interface, thereby suppressing the generation of dark current at the light incident surface of the photoelectric conversion region 22.

[0715] <<Variations on the Tenth Implementation Plan>>

[0716] <Variation Example 10-1>

[0717] Figure 50 This is a diagram showing a variation 10-1 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0718] The main difference in variant 10-1 lies in the composition of the separation region 31J.

[0719] That is, such as Figure 50 As shown, in the separation region 31J of Modified Example 10-1, a fixed charge film 61 is disposed between the separation insulating film 81 and the metal thin film 64. Specifically, the separation region 31J of Modified Example 10-1 includes a mining section 32 having a shallow mining section 32a and a deep mining section 32b, and a separation insulating film 81 disposed along the side surface of the semiconductor layer 21 inside the mining section 32. Furthermore, the separation region 31J of Modified Example 10-1 also includes a metal thin film 64, which serves as a conductive film, disposed along the separation insulating film 81 on the side opposite to the mining section 32 inside the mining section 32, and a fixed charge film 61 disposed between the separation insulating film 81 and the metal thin film 64 inside the mining section 32. The fixed charge film 61 is disposed across the second surface S2 side of the semiconductor layer 21 and the inside of the mining section 32. Then, similar to the metal thin film 64, the fixed charge film 61 located inside the excavation section 32 is folded back on the first face S1 side of the semiconductor layer 21 and is provided on the side face of each of the two semiconductor layers 21 (photoelectric conversion regions 22) located on opposite sides of the excavation section 32.

[0720] This technology can also be applied to variant 10-1, and can achieve similar effects to the first embodiment described above.

[0721] Furthermore, since the fixed charge film 61 located inside the excavation section 32 does not directly contact the semiconductor layer 21, the fixed charge of the fixed charge film 61 does not function; however, the amount of fixed charge of the fixed charge film 61 varies due to the bias voltage applied to the metal thin film 64, and the risk of changes in dark current characteristics caused by such changes in the amount of fixed charge can be avoided.

[0722] <Variation Example 10-2>

[0723] Figure 51 This is a diagram showing a variation 10-2 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0724] like Figure 51 As shown, variant example 10-2 omits the tenth embodiment described above. Figure 43 and Figure 44 The fixed charge film 61 is shown. That is, the anti-reflective film 62 and the sealing insulating film 66 are disposed on the second surface S2 of the photoelectric conversion region 22 in this order, and the anti-reflective film 62 is in contact with the second surface S2 of the photoelectric conversion region 22.

[0725] This technique can also be applied to variations 10-2, and can achieve similar effects to the tenth embodiment described above.

[0726] <Variation Example 10-3>

[0727] Figure 52 This is a diagram showing a variation 10-3 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0728] like Figure 52 As shown, the main difference in variant 10-3 lies in the composition of the separation region 31J.

[0729] That is, such as Figure 52As shown, in the separation region 31J of Modification 10-3, the metal thin film 64 extends across the first facet S1 and the second facet S2 of the semiconductor layer 21, similar to the separation insulating film 81. Specifically, the separation region 31J of Modification 10-3 includes a separation insulating film 81 extending across the shallow digging portion 32a and the deep digging portion 32b included in the digging portion 32 and disposed along the side portion of the semiconductor layer 21 on the inner side of each of the shallow digging portion 32a and the deep digging portion 32b, and a metal thin film 64 disposed along the separation insulating film 81 on the side of the separation insulating film 81 opposite to the digging portion 32 side and extending across the first facet S1 and the second facet S2 of the semiconductor layer 21. Then, the separation region 31J of Modification 10-3 also includes an insulating film 82 that extends along the metal thin film 64 on the side of the metal thin film 64 opposite to the separation insulating film 81 side and is disposed across the first facet S1 and the second facet S2 of the semiconductor layer 21. The insulating film 82 is disposed across the shallow excavation section 32a and the deep excavation section 32b included in the excavation section 32, corresponding to the section insulating film 36 in the shallow excavation section 32a and corresponding to the insulating film 65 in the deep excavation section 32b.

[0730] The separation region 31J of variant example 10-3 can be formed by the following manufacturing method.

[0731] That is, by implementing the same process as the first implementation scheme described above to form such Figure 49B As shown, until after the separation of insulating film 81, as Figure 53A As shown, similar to the separation of insulating film 81, a metal thin film 64 is formed from the first face S1 side of semiconductor layer 21.

[0732] A metal thin film 64 is formed across the inner side of the excavation section 32 and the first surface S1 side of the semiconductor layer 21. Then, the metal thin film 64 is formed to have a film thickness that folds back along the inner wall surface (side surface and bottom surface) of the excavation section 32, such that the inner side of the separation insulating film 81 in the excavation section 32 (the side of the separation insulating film 81 opposite to the excavation section 32 side) is not filled.

[0733] Next, as Figure 53B As shown, an insulating film 82 is formed on the first surface S1 side of the semiconductor layer 21, including the inner side of the excavation section 32. The insulating film 36 is formed to a thickness such that the side of the metal thin film 64 opposite to the side of the separating insulating film 81 is filled with it.

[0734] Next, each of the insulating film 36, the metal film 64, and the separation insulating film 81 on the first face S1 side of the semiconductor layer 21 is selectively removed by, for example, etching back or CMP, and as Figure 53C As shown, each of the insulating film 36, the metal film 64, and the separation insulating film 81 is selectively retained on the inside of the excavation section 32.

[0735] Subsequently, the separation region 31J of variant example 10-3 is formed by performing the thinning process shown in Figure 49.

[0736] Note that the insulating film 82 is disposed across the shallow excavation section 32a and the deep excavation section 32b included in the excavation section 32, corresponding to the section insulating film 36 in the shallow excavation section 32a and corresponding to the insulating film 65 in the deep excavation section 32b.

[0737] This technique can also be applied to variations 10-3, and can achieve similar effects to the tenth embodiment described above.

[0738] <Variation Example 10-4>

[0739] Figure 54 This is a diagram showing a variation 10-4 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0740] Modification 10-4 differs in the composition of the separation insulating film 81 included in the separation region 31J.

[0741] That is, such as Figure 54 As shown, in the separation region 31J of Modified Example 10-4, the separation insulating film 81 is formed as a single layer of silicon oxide film 81a.

[0742] This technique can also be applied to variations 10-4, and can achieve similar effects to the tenth embodiment described above.

[0743] <Variation Example 10-5>

[0744] Figure 55 It is a diagram showing a variation 10-5 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0745] Modification 10-5 differs in the composition of the separation insulating film 81 included in the separation region 31J.

[0746] That is, such as Figure 55 As shown, in the separation region 31J of modified example 10-5, the separation insulating film 81 is formed as a single layer of silicon nitride film 81b.

[0747] This technique can also be applied to variations 10-5, and can achieve similar effects to the tenth embodiment described above.

[0748] <Variation Example 10-6>

[0749] Figure 56It is a diagram showing a variation 10-6 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0750] The difference in variant 10-6 lies in the composition of the separation region 31J.

[0751] That is, such as Figure 56 As shown, in the separation region 31J of Modification 10-6, a silicon oxide film 83 is provided between the silicon nitride film 81b and the metal film 64 of the separation insulating film 81. Specifically, the separation region 31J of Modification 10-6 includes a mining portion 32 having a shallow mining portion 32a and a deep mining portion 32b, and a separation insulating film 81 provided along the side portion of the semiconductor layer 21 inside the mining portion 32. Then, the separation region 31J of Modification 10-6 also includes a silicon oxide film 83 provided along the separation insulating film 81 on the side of the separation insulating film 81 opposite to the mining portion 32 side inside the mining portion 32, a metal film 64 serving as a conductive film provided along the silicon oxide film 81 on the side of the silicon oxide film 83 opposite to the mining portion 32 side inside the mining portion 32, and an insulating film 65 provided along the metal film on the side of the metal film 64 opposite to the silicon oxide film 82 side. Similar to the metal thin film 64, the silicon oxide film 83 is folded back on the first face S1 side of the semiconductor layer 21 and is disposed on the side face of each of the two semiconductor layers 21 (photoelectric conversion regions 22) located on opposite sides of each other across the excavation portion 32.

[0752] This technique can also be applied to variations 10-6, and can achieve similar effects to the tenth embodiment described above.

[0753] <Variation Example 10-7>

[0754] Figure 57 It is a diagram showing a variation 10-7 according to the tenth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region and the photoelectric conversion region.

[0755] Modification 10-7 is a combination of the above-mentioned Modification 10-1 and Modification 10-4, and is used as the configuration of the separation region 31J.

[0756] That is, such as Figure 57 As shown, the separation region 31J of Modification 10-7 includes the separation insulating film 81 (a single layer of silicon oxide film) of Modification 10-4, in place of the separation insulating film 81 of Modification 10-1.

[0757] This technique can also be applied to variations 10-7, and can achieve similar effects to the tenth embodiment described above.

[0758] <Other variations>

[0759] Note that, as a combination of variations, variation 10-5 can also be combined with variation 10-1.

[0760] Furthermore, any one of Modification 10-2, Modification 10-4, Modification 10-5 and Modification 10-6 can also be combined with Modification 10-3.

[0761] [Eleventh Implementation Plan]

[0762] In the eleventh embodiment, a description of a separated insulating film comprising a dielectric film (high-k film) having a higher relative permittivity (k) than silicon oxide will be given.

[0763] Figure 58 This is a diagram showing the solid-state imaging device 1K according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region 31K and the photoelectric conversion region 22.

[0764] Figure 58 The solid-state imaging device 1K according to the eleventh embodiment of the present technology shown has a configuration that is basically similar to that of the solid-state imaging device 1J according to the tenth embodiment described above, but differs in the configuration of the separation insulating film included in the separation region 31J.

[0765] That is, the separation region 31J according to the eleventh embodiment of this technology includes Figure 58 The shown separation insulating film 85 is used instead of the tenth embodiment described above. Figure 44 The insulating film 81 is shown. Since the other components are roughly similar to those in the tenth embodiment described above, the description of the components other than the separating insulating film 85 is omitted here.

[0766] like Figure 58 As shown, the above-mentioned separated insulating film 81 (refer to...) Figure 44 Similarly, the separating insulating film 85 extends across the shallow excavation portion 32a and the deep excavation portion 32b included in the excavation portion 32, and is disposed along the side portion of the semiconductor layer 21 on the inner side of each of the shallow excavation portion 32a and the deep excavation portion 32b. Then, in the thickness direction (Z direction) of the semiconductor layer 21, the separating insulating film 85 terminates at the first surface portion S1 of the semiconductor layer 21 on the first surface portion S1 side, and terminates at the second surface portion S2 of the semiconductor layer 21 on the second surface portion S2 side. Then, in the plan view, the separating insulating film 85 is disposed on the side portion side of each of the two semiconductor layers 21 (photoelectric conversion regions 22) located on opposite sides of each other across the excavation portion 32.

[0767] like Figure 58As shown, the separating insulating film 85 of the eleventh embodiment includes a dielectric film (high-k film) 85b with a dielectric constant (k) higher than that of silicon oxide. However, the separating insulating film 85 of the eleventh embodiment is not limited to this, but may include, for example, a silicon oxide film 85a and a dielectric film 85b with a dielectric constant higher than that of silicon oxide film 85a. The silicon oxide film 85a is disposed on the side portion of the semiconductor layer 21, spanning the shallow and deep portions 32a and 32b, on the inner side of each of the shallow and deep portions 32a and 32b. The dielectric film 85b is disposed on the side of the silicon oxide film 85a opposite to the semiconductor layer 21 side, spanning the shallow and deep portions 32a and 32b, on the inner side of each of the shallow and deep portions 32a and 32b. That is, the separation insulating film 85 in the eleventh embodiment includes a silicon oxide film 85a and a dielectric film 85b sequentially disposed from the side portion of the semiconductor layer 21 inside the excavation portion 32 toward the metal thin film 64.

[0768] Here, the dielectric constant (k) of silicon oxide is approximately 3.9. Examples of dielectric films 85b with a higher dielectric constant (k) than silicon oxide include silicon nitride (Si3N4) films, aluminum oxide (Al2O3) films, hafnium oxide (HfO2) films, and lanthanum oxide (LaO) films. The dielectric constant (k) of silicon nitride (Si3N4) films is approximately 7. The dielectric constant (k) of aluminum oxide (Al2O3) films is approximately 10. The dielectric constant (k) of hafnium oxide (HfO2) films is approximately 25. The dielectric constant (k) of lanthanum oxide (LaO) is approximately 27. In the eleventh embodiment, for example, a hafnium oxide (HfO2) film is used as the dielectric film 85b. The dielectric constant (k) of these silicon nitride (Si3N4) films, aluminum oxide (Al2O3) films, hafnium oxide (HfO2) films, etc., can be changed by altering the film formation conditions.

[0769] As described above, the solid-state imaging apparatus 1k according to the eleventh embodiment includes a separation region 31J. The separation region 31J then includes a cutout portion 32 extending in the thickness direction (Z direction) of the semiconductor layer 21, a separation insulating film 85 disposed on the inner side of the cutout portion 32 along the side portion of the semiconductor layer 21, and a metal thin film 64 disposed on the inner side of the cutout portion 32 along the separation insulating film 85 on the side of the separation insulating film 85 opposite to the side of the cutout portion 32.

[0770] Then, by applying a third reference potential V3 (negative potential) to the metal thin film 64, holes (h) are induced on the semiconductor layer 21 side of the interface between the semiconductor layer 21 of the photoelectric conversion region 22 and the separation insulating film 85 of the separation region 31J. + Furthermore, it can ensure pinning at the interface, thereby suppressing the generation of dark current.

[0771] Furthermore, since the separation insulating film 85 according to the eleventh embodiment includes a dielectric film 85b with a dielectric constant (k) higher than that of silicon oxide, the number of holes (h) induced on the semiconductor layer 21 side of the interface between the semiconductor layer 21 of the photoelectric conversion region 22 and the separation insulating film 85 of the separation region 31J is reduced compared to the case without the dielectric film 85b. + The increased density further ensures pinning at the interface and further suppresses the generation of dark current. Therefore, the solid-state imaging device 1K according to the eleventh embodiment achieves both improved reliability and improved dark current.

[0772] In the eleventh embodiment, a hafnium oxide (HfO2) film is used as an example of a dielectric film 85b with a higher dielectric constant (k) than silicon oxide; however, in dielectric films with a higher dielectric constant (k) than silicon oxide (high-k films), it is more preferable to use a material that causes a positive flat band shift due to dipoles, such as an aluminum oxide (Al2O3) film, to achieve both improved reliability and dark current.

[0773] With the aforementioned tenth implementation plan Figure 49B Similar to the separation insulating film 81 shown, the separation insulating film 85 of the eleventh embodiment is preferably formed at a high temperature before the formation of the multilayer wiring layer 51, without being limited by the temperature of the melting temperature of the wiring included in the multilayer wiring layer 51, so as to deactivate the fixed charge.

[0774] Similar to silicon nitride film 81b, in the tenth embodiment described above... Figure 49G During the removal of the polycrystalline silicon film 35 shown, the dielectric film 85b can also be used as an etching stop film.

[0775] Note that, in addition to the silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, and hafnium oxide (HfO2) film mentioned above, examples of dielectric films 85 with a higher dielectric constant (k) than silicon oxide include the following:

[0776] Examples include silicon oxynitride (SiON) films, aluminum oxynitride (AlON) films, aluminum silicon nitride (SiAlN) films, magnesium oxide (MgO), aluminum silicon oxide (AlSiO) films, hafnium oxide (HfAlO) films, tantalum oxide (Ta2O3) films, titanium oxide (TiO2) films, scandium oxide (Sc2O3) films, zirconium oxide (ZrO2) films, gadolinium oxide (Gd2O3) films, lanthanum oxide (La2O3) films, yttrium oxide (Y2O3), niobium pentoxide (Nb2O5), calcium oxide (CaO), lithium oxide (Li2O), strontium oxide (SrO), barium oxide (BaO), tungsten oxide (WO3), or molybdenum oxide (MoO3).

[0777] Furthermore, the dielectric film 85, which has a higher dielectric constant (k) than silicon oxide, can be an insulating material including at least one of Si, N, Al, Hf, Ta, Ti, O, Mg, Sc, Zr, La, Gd, or Y.

[0778] Furthermore, in the tenth embodiment described above, by changing the film-forming conditions of the silicon nitride film 81b included in the separated insulating film 81, it can be used as a dielectric film with a higher dielectric constant (k) than silicon oxide.

[0779] <<Variations on the Eleventh Implementation Plan>>

[0780] <Variation Example 11-1>

[0781] Figure 59 This is a diagram showing a variation 11-1 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region 31J and the photoelectric conversion region 22.

[0782] like Figure 59 As shown, Modification 11-1 omits the above-described eleventh embodiment. Figure 58 The fixed charge film 61 is shown. That is, the anti-reflective film 62 and the sealing insulating film 66 are disposed on the second surface S2 of the photoelectric conversion region 22 in this order, and the anti-reflective film 62 is in contact with the second surface S2 of the photoelectric conversion region 22.

[0783] This technique can also be applied to variant 11-1, and can achieve similar effects to the eleventh embodiment described above.

[0784] <Variation Example 11-2>

[0785] Figure 60 This is a diagram showing a variation 11-2 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region 31J and the photoelectric conversion region 22.

[0786] like Figure 60 As shown, in variant 11-2, dielectric films 85b and 85c of different materials are provided, which are dielectric films with a higher dielectric constant (k) than silicon oxide.

[0787] That is, the separation insulating film 85 in Modification 11-2 includes a silicon oxide film 85a and dielectric films 85b and 85c sequentially disposed from the side portion of the semiconductor layer 21 inside the excavation portion 32 toward the metal thin film 64.

[0788] A silicon oxide film 85a is disposed on the side portion of the semiconductor layer 21, spanning the shallow and deep portions 32a and 32b, with the inner side of each of the shallow and deep portions 32a and 32b. A dielectric film 85b is disposed on the side of the silicon oxide film 85a opposite to the semiconductor layer 21, spanning the inner side of each of the shallow and deep portions 32a and 32b. A dielectric film 85c is disposed on the side of the dielectric film 85b opposite to the semiconductor layer 21, spanning the inner side of each of the shallow and deep portions 32a and 32b.

[0789] In variations 11-2, for example, similar to the eleventh embodiment described above, a hafnium oxide (HfO2) film is used as the dielectric film 85b, and for example, an aluminum oxide (Al2O3) film is used as the dielectric film 85c.

[0790] This technique can also be applied to variations 11-2, and can achieve similar effects to the eleventh embodiment described above.

[0791] Furthermore, since the alumina (Al2O3) film is a material that causes a positive flat band shift due to dipoles, holes (h) induced on the semiconductor layer 21 side of the interface between the semiconductor layer 21 of the photoelectric conversion region 22 and the separation insulating film 85 of the separation region 31J are generated. + Density can be increased.

[0792] Note that since lanthanum oxide (LaO) film is a material that causes a negative flat band shift, it is effective when the conductivity types of semiconductor regions 23 and 24 of semiconductor layer 21 are exchanged, i.e., when semiconductor region 23 is n-type and semiconductor region 24 is p-type, when lanthanum oxide film is used as dielectric film 85c.

[0793] Note that in variant 11-2, two dielectric films with a dielectric constant (k) higher than that of silicon oxide are provided; however, three or more dielectric films with a dielectric constant (k) higher than that of silicon oxide may also be provided.

[0794] <Variation Example 11-3>

[0795] Figure 61 This is a diagram showing a variation 11-3 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region 31J and the photoelectric conversion region 22.

[0796] like Figure 61 As shown, Modification 11-3 has a configuration that is basically similar to that of Modification 10-3 described above, and uses... Figure 58 The separation region 85 shown replaces the above-described variant 10-3. Figure 52The separation region 81 is shown. That is, in the separation region 31J of the modified example 11-3, similar to the separation insulating film 85, the metal thin film 64 extends across the first facet S1 and the second facet S2 of the semiconductor layer 21.

[0797] This technique can also be applied to variations 11-2, and can achieve similar effects to the eleventh embodiment described above.

[0798] <Variation Example 11-4>

[0799] Figure 62 It is a diagram showing a variation 11-4 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region 31J and the photoelectric conversion region 22.

[0800] Modification 10-4 differs in the composition of the separation insulating film 85 included in the separation region 31J.

[0801] That is, such as Figure 62 As shown, the separation insulating film 85 included in the separation region 31J of Modified Examples 11-4 includes a single layer of dielectric film 85b with a dielectric constant (k) higher than that of silicon oxide.

[0802] This technique can also be applied to variations 11-4, and can achieve similar effects to the eleventh embodiment described above.

[0803] <Variation Example 11-5>

[0804] Figure 63 This is a diagram showing a variation 11-5 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region 31J and the photoelectric conversion region 22.

[0805] The difference in variant 11-5 lies in the composition of the separation region 31J.

[0806] That is, such as Figure 63As shown, in the separation region 31J of Modification 11-5, a silicon oxide film 86 is provided between the dielectric film 85b of the separation insulating film 85 and the metal film 64. Specifically, the separation region 31J of Modification 11-5 includes a mining portion 32 having a shallow mining portion 32a and a deep mining portion 32b, and a separation insulating film 85 provided along the side portion of the semiconductor layer 21 inside the mining portion 32. Then, the separation region 31J of Modification 11-5 also includes a silicon oxide film 86 provided along the separation insulating film 85 on the side of the separation insulating film 85 opposite to the mining portion 32 side inside the mining portion 32, a metal film 64 provided along the silicon oxide film 86 on the side of the silicon oxide film 86 opposite to the separation insulating film 85 side inside the mining portion 132, and an insulating film 65 provided along the metal film 64 on the side of the metal film 64 opposite to the silicon oxide film 86 side. Similar to the metal thin film 64, the silicon oxide film 86 is folded back on the first face S1 side of the semiconductor layer 21 and is disposed on the side face of each of the two semiconductor layers 21 (photoelectric conversion regions 22) located on opposite sides of each other across the excavation portion 32.

[0807] This technique can also be applied to variations 11-5, and can achieve similar effects to the eleventh embodiment described above.

[0808] In addition, the withstand voltage between the semiconductor layer 21 of the photoelectric conversion region 22 and the metal thin film 64 of the separation region 31J can be improved.

[0809] Furthermore, hydrogen can be supplied from the silicon oxide film 86 by forming a silicon oxide film 86 using the ALD method.

[0810] <Variation Example 11-6>

[0811] Figure 64 It is a diagram showing a variation 11-6 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region 31J and the photoelectric conversion region 22.

[0812] like Figure 64 As shown, Modification 11-6 has a configuration basically similar to that of Modification 10-1 described above, and uses... Figure 58 The separation region 85 shown replaces the above-described variant 10-1. Figure 50 The separation region 81 is shown. That is, in the separation region 31J of the modified examples 11-6, the fixed charge film 61 is disposed between the separation insulating film 85 and the metal film 64.

[0813] A fixed charge film 61 is disposed across the second face S2 side of the semiconductor layer 21 and the inner side of the excavation portion 32. Then, similar to the metal thin film 64, the fixed charge film 61 located inside the excavation portion 32 is folded back at the first face S1 side of the semiconductor layer 21 and disposed on the side face of each of the two semiconductor layers 21 (photoelectric conversion regions 22) that are opposite to each other across the excavation portion 32.

[0814] This technique can also be applied to variations 11-6, and can achieve similar effects to the eleventh embodiment described above.

[0815] Furthermore, since the fixed charge film 61 located inside the excavation section 32 does not directly contact the semiconductor layer 21, the fixed charge of the fixed charge film 61 does not function; however, the amount of fixed charge of the fixed charge film 61 varies due to the bias voltage applied to the metal thin film 64, and the risk of changes in dark current characteristics caused by such changes in the amount of fixed charge can be avoided.

[0816] <Variation Example 11-7>

[0817] Figure 65 This is a diagram showing a variation 11-7 according to the eleventh embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the separation region 31J and the photoelectric conversion region 22.

[0818] like Figure 65 As shown, Modification 11-7 is a combination of Modification 11-4 and Modification 11-6 above, and is used as a configuration of the separation region 31J.

[0819] That is, in the separation region 31J of the modified examples 11-7, the fixed charge film 61 is disposed between the separation insulating film 85 and the metal film 64, which are composed of a single layer of dielectric film 85b with a dielectric constant (k) higher than that of silicon oxide.

[0820] This technique can also be applied to variations 11-7, and can achieve similar effects to the eleventh embodiment described above.

[0821] <Other variations>

[0822] Note that, as a combination of variations, variation 11-3 can also be combined with variation 11-2.

[0823] Furthermore, any one of Modification 10-3, Modification 10-4, and Modification 10-6 can also be combined with Modification 10-5.

[0824] [Twelfth Implementation Plan]

[0825] <<Examples of Electronic Device Applications>>

[0826] This technology (the technology disclosed herein) can be applied to various electronic devices, such as imaging devices like digital still cameras or digital video cameras, mobile phones with imaging capabilities, or other devices with imaging capabilities.

[0827] Figure 66 This is a diagram illustrating a schematic configuration of an electronic device (e.g., a camera) according to a twelfth embodiment of the present technology.

[0828] like Figure 66 As shown, the electronic device 200 includes a solid-state imaging device 201, an optical lens 202, a shutter device 203, a drive circuit 204, and a signal processing circuit 205. The electronic device 200 illustrates an embodiment in which solid-state imaging devices 1A to 1D, 1J, and 1K according to the first to eleventh embodiments of the present technology, and their variations, are used as solid-state imaging device 201 in an electronic device (e.g., a camera).

[0829] Optical lens 202 forms an image of the image light (incident light 206) from the subject on the imaging surface of solid-state imaging device 201. Therefore, signal charge accumulates in solid-state imaging device 201 over a certain period. Shutter device 203 controls the illumination and blocking periods of solid-state imaging device 201. Drive circuit 204 supplies drive signals for controlling the transmission operation of solid-state imaging device 201 and the shutter operation of shutter device 203. Charge transfer in solid-state imaging device 201 is performed by the drive signal (timing signal) supplied from drive circuit 204. Signal processing circuit 205 performs various types of signal processing on the signal (pixel signal (image signal)) output from solid-state imaging device 201. The processed video signal is stored in a storage medium such as a memory or output to a monitor.

[0830] With this configuration, the image quality performance of the electronic device 200 according to the tenth embodiment can be improved because dark current is reduced and quantum efficiency is suppressed in the solid-state imaging device 201.

[0831] Note that the electronic device 200, which can be applied to one of the above embodiments of the solid-state imaging device, is not limited to a camera, and the solid-state imaging device can also be applied to other electronic devices. For example, the solid-state imaging device can be applied to imaging devices such as camera modules of mobile devices such as mobile phones or tablet terminals.

[0832] Furthermore, this technology is applicable not only to the aforementioned solid-state imaging devices used as image sensors, but also to the entire range of light detection devices, including distance measuring sensors (also known as ToF (Time-of-Flight) sensors). A distance measuring sensor is a sensor that emits illumination light towards an object, detects the reflected light from the object's surface, and calculates the distance to the object based on the time it takes for the illumination light to travel from emission to return as reflected light. The aforementioned pixel transistors can also be used in this distance measuring sensor.

[0833] Note that this technology can have the following configuration.

[0834] (1) A light detection device, comprising:

[0835] A semiconductor layer having a thickness in one direction;

[0836] A photoelectric conversion region, which is disposed in the semiconductor layer and separated by a separation region; and

[0837] A photoelectric conversion unit is disposed in the photoelectric conversion region and configured to perform photoelectric conversion from light to signal charge, wherein

[0838] The separation region includes

[0839] A mining section, which is disposed in the semiconductor layer and extends in the one direction.

[0840] A fixed charge film, having a fixed charge and disposed along the side portion of the excavation section, and

[0841] A metal film is disposed along the fixed charge film on the inner side of the excavation section.

[0842] (2) The photodetector according to (1), wherein the metal film is electrically connected to a conductor to which a potential is applied.

[0843] (3) The optical detection device according to (1) or (2), wherein

[0844] The signal charge is an electron.

[0845] The fixed charge is a negative fixed charge, and

[0846] The potential applied to the metal film is a negative potential.

[0847] (4) The optical detection device according to (1) or (2), wherein

[0848] The signal charge is a hole.

[0849] The fixed charge is a positive fixed charge, and

[0850] The potential applied to the metal film is a positive potential.

[0851] (5) The light detection device according to any one of (1) to (4), wherein each of the fixed charge film and the metal film is disposed on each of the two side faces of the excavation portion located on opposite sides of each other.

[0852] (6) The light detection device according to any one of (1) to (5), wherein

[0853] The semiconductor layer has a first facet and a second facet located on opposite sides of each other in the one direction, and

[0854] Each of the fixed charge film and the metal film is folded back on the first face side of the semiconductor layer.

[0855] (7) The light detection device according to any one of (1) to (6), wherein the metal film terminates on the outer side of the second face of the semiconductor layer.

[0856] (8) The photodetector according to (6), wherein the metal film terminates on the inside of the second face of the semiconductor layer.

[0857] (9) The optical detection device according to (6), wherein

[0858] The excavation unit includes:

[0859] A shallow excavation portion is disposed on the first face side of the semiconductor layer; and

[0860] The deep portion extends from the shallow portion side toward the second surface side of the semiconductor layer, and in the plan view, its width in the short side direction is narrower than the width of the shallow portion in the short side direction.

[0861] Each of the fixed charge film and the metal film is selectively disposed in the deep excavation section.

[0862] (10) The optical detection device according to (9), wherein

[0863] The separation area also includes a section of insulating film disposed in the shallow excavation section, and

[0864] The fixed charge film is disposed across the side portion of the deep excavation section and the bottom portion of the section insulating film.

[0865] (11) The optical detection device according to (9), wherein

[0866] The deep excavation section is spaced apart from the shallow excavation section, and

[0867] The fixed charge film is disposed across the side and bottom portions of the deep excavation section.

[0868] (12) The light detection device according to any one of (1) to (11), wherein the separation region further includes an insulating film disposed between the fixed charge film and the metal film.

[0869] (13) The light detection device according to any one of (1) to (12), wherein the separation region further comprises an insulating film disposed on the side of the metal film opposite to the fixed charge film side.

[0870] (14) According to the photodetector of (13), the separation region further includes a gap disposed on the side of the embedded insulating film opposite to the metal film side.

[0871] (15) The light detection apparatus according to any one of (1) to (14), wherein

[0872] The photoelectric conversion region further includes:

[0873] A first semiconductor region of a first conductivity type, which is spaced apart from the separation region and the first face of the semiconductor layer, and is included in the photoelectric conversion section;

[0874] A second semiconductor region of a second conductivity type is disposed between the separated region and the first semiconductor region; and

[0875] A third semiconductor region of the second conductivity type is disposed between the separation region and the second semiconductor region, and has an impurity concentration higher than that of the second semiconductor region.

[0876] (16) The light detection apparatus according to any one of (1) to (15), wherein

[0877] The photoelectric conversion region further includes:

[0878] A first semiconductor region of a first conductivity type, spaced apart from the separation region and the first facet of the semiconductor layer, and included in the photoelectric conversion section; and

[0879] A second semiconductor region of a second conductivity type is disposed between the separated region and the first semiconductor region, and

[0880] The separation region also includes a third semiconductor region of a second conductivity type, which is disposed between the side portion of the excavation section and the fixed charge film, and has an impurity concentration higher than that of the second semiconductor region.

[0881] (17) The light detection device according to any one of (1) to (16), wherein the fixed charge film comprises a single-layer film or a multilayer film.

[0882] (18) The photodetector according to any one of (1) to (17), wherein the fixed charge film comprises at least one of Si, N, Al, Hf, Ta, Ti, O, Ca, Mg, Li, Sr, Sc, Ba, Nb, W, Mo, Zr, La, Gd or Y.

[0883] (19) The photodetector according to any one of (1) to (18), wherein the thickness of the fixed charge film is 100 nm or less.

[0884] (20) The light detection device according to any one of (1) to (19), wherein the metal film comprises a single-layer metal film or a multi-layer metal film.

[0885] (21) The photodetector according to any one of (1) to (20), wherein the metal film comprises at least one of Ti, W, Ni, N, Ru, Cu, Co, Mo, Rh, Ir, Ag, Nb or Al.

[0886] (22) The photodetector according to any one of (1) to (21), wherein the thickness of the metal film is 10 nm or less.

[0887] (23) According to the photodetector of (6), the thickness of the metal film on the first face side of the semiconductor layer is greater than the thickness on the second face side of the semiconductor layer.

[0888] (24) The optical detection device according to (1), wherein the metal film comprises a two-dimensional material film.

[0889] (25) The photodetector according to (24), wherein the two-dimensional material film comprises at least one of C, Mo, W, Zr, Sn, Hf, Ge, S, Se or Te.

[0890] (26) The photodetector according to (24) or (25), wherein the thickness of the two-dimensional material film is less than 5 nm.

[0891] (27) The photodetector according to any one of (1) to (26), wherein the photoelectric conversion region further includes at least a charge holding part and a transmission transistor, wherein the charge holding part holds the signal charge photoelectrically converted by the photoelectric conversion part, and the transmission transistor transmits the signal charge photoelectrically converted by the photoelectric conversion part to the charge holding part.

[0892] (28) The light detection apparatus according to any one of (1) to (27), further comprising, when the semiconductor layer is defined as a first semiconductor layer:

[0893] A second semiconductor layer is configured to overlap with the first semiconductor layer in the one direction; and

[0894] A pixel circuit reads out the signal charge held in the charge holding section and outputs a pixel signal based on the read-out signal charge, wherein...

[0895] The pixel transistors included in the pixel circuit are disposed in the second semiconductor layer.

[0896] (29) The light detection apparatus according to any one of (1) to (28), wherein

[0897] The photoelectric conversion region further includes a separation barrier portion connected to the separation region, and a first photoelectric conversion cell and a second photoelectric conversion cell separated by the separation barrier portion.

[0898] Each of the first photoelectric conversion cell and the second photoelectric conversion cell includes the photoelectric conversion section, the transmission transistor, and the charge holding section.

[0899] The separation barrier includes the excavation section, the fixed charge film, and the conductive film.

[0900] (30) The photodetector according to (13), wherein the thickness of the metal film is less than the thickness of the insulating film.

[0901] (31) A light detection device, comprising:

[0902] A semiconductor layer having a thickness in one direction;

[0903] A photoelectric conversion region, which is disposed in the semiconductor layer and separated by a separation region; and

[0904] A photoelectric conversion unit is disposed in the photoelectric conversion region and configured to perform photoelectric conversion from light to signal charge, wherein

[0905] The separation region includes

[0906] A mining section, which is disposed in the semiconductor layer and extends in the one direction.

[0907] A separation insulating film is provided on the inner side of the excavated portion along the side portion of the semiconductor layer, and

[0908] A metal film is disposed along the insulating film on the inner side of the excavation section.

[0909] (32) The photodetector according to (31), wherein the metal film is electrically connected to a conductor to which an applied potential is applied.

[0910] (33) The photodetector according to (31) or (32), wherein the thickness of the separating insulating film is less than 20 nm.

[0911] (34) The photodetector according to any one of (31) to (33), wherein the separating insulating film comprises at least one of silicon oxide film or silicon nitride film.

[0912] (35) The light detection device according to any one of (31) to (34), wherein each of the separating insulating film and the metal film is disposed on the side side of each of the two semiconductor layers located on opposite sides of each other across the excavation portion.

[0913] (36) The light detection apparatus according to any one of (31) to (35), wherein

[0914] The semiconductor layer has a first facet and a second facet located on opposite sides of each other in the one direction, and

[0915] The excavation section and the separating insulating film are disposed across the first and second faces of the semiconductor layer.

[0916] (37) According to the photodetector of (36), wherein the metal film is folded back on the first face side of the semiconductor layer.

[0917] (38) The photodetector according to (36), wherein the metal film is disposed across the first and second facets of the semiconductor layer.

[0918] (39) The light detection apparatus according to any one of (31) to (35), wherein

[0919] The semiconductor layer has a first facet and a second facet located on opposite sides of each other in one direction.

[0920] The photoelectric conversion region further includes a charge holding section and a transmission transistor. The charge holding section is disposed on the first face side, and the transmission transistor transmits the signal charge photoelectrically converted by the photoelectric conversion section to the charge holding section.

[0921] The photoelectric conversion unit performs photoelectric conversion on light incident from the second face side of the semiconductor layer.

[0922] (40) The optical detection device according to (39), wherein

[0923] The photoelectric conversion region includes a first face and a second face, and

[0924] A fixed charge film with a fixed charge is disposed on the second surface side of the photoelectric conversion region.

[0925] (41) The light detection device according to any one of (31) to (40), wherein the separation region further includes a fixed charge film having a fixed charge and disposed between the separation insulating film and the metal film.

[0926] (42) The light detection device according to any one of (31) to (41), wherein the separation region further includes an insulating film disposed on the side of the metal film opposite to the separation insulating film side.

[0927] (43) The optical detection device according to any one of (31) to (42), wherein the thickness of the metal film is less than the thickness of the insulating film.

[0928] (44) The photodetector according to any one of (31) to (43), wherein the thickness of the metal film is 10 nm or less.

[0929] (45) The optical detection device according to (31), wherein

[0930] The semiconductor layer has a first facet and a second facet located on opposite sides of each other in one direction.

[0931] The excavation unit includes:

[0932] A shallow excavation portion is disposed on the first face side of the semiconductor layer; and

[0933] The deep portion extends from the shallow portion side toward the second surface side of the semiconductor layer, and in the plan view, its width in the short side direction is narrower than the width of the shallow portion in the short side direction.

[0934] The separating insulating membrane is disposed across the shallow excavation section and the deep excavation section.

[0935] (46) The photodetector according to (21), wherein the separating insulating film comprises a silicon oxide film and a silicon nitride film.

[0936] (47) The photodetector according to (31), wherein the separating insulating film comprises a dielectric film with a higher relative permittivity than silicon oxide.

[0937] (48) The photodetector according to (47), wherein the dielectric film comprises at least one of Si, N, Al, Hf, Ta, Ti, O, Mg, Sc, Zr, La, Gd or Y.

[0938] (49) An electronic device comprising:

[0939] The light detection device according to any one of (1) to (48);

[0940] An optical lens that forms an image of the light from the subject on the imaging surface of the light detection device; and

[0941] A signal processing circuit that performs signal processing on the signal output from the optical detection device.

[0942] The scope of this technology is not limited to the exemplary embodiments illustrated and described, but also includes all embodiments that produce effects equivalent to those obtained by this technology. Furthermore, the scope of this technology is not limited to the combination of features of the invention as defined by the claims, but can be defined by any desired combination of specific features among all disclosed features.

[0943] List of reference numerals

[0944] 1A, 1B, 1C, 1D, 1J, 1K Solid-state imaging devices

[0945] 2 Semiconductor chips

[0946] 2A pixel array section

[0947] 2A1 effective pixel area

[0948] 2A2 Optical Black Area

[0949] 2B Peripheral Department

[0950] 3, 3a, 3b, 3c, 3d pixels (sensor pixels)

[0951] 4 Vertical drive circuit

[0952] 5-column signal processing circuits

[0953] 6. Horizontal drive circuit

[0954] 7 Output Circuit

[0955] 8. Control Circuit

[0956] 10-pixel drive line

[0957] 11 Vertical signal lines

[0958] 12 Horizontal Signal Lines

[0959] 13 Logic Circuits

[0960] 14. Bonding pads

[0961] 15-pixel block

[0962] 16-pixel circuit

[0963] 17-pixel block formation area

[0964] 21 Semiconductor layer

[0965] 22, 22A Photoelectric conversion region

[0966] 22B Non-photoelectric conversion region

[0967] 22L First Photoconversion Cell

[0968] 22R Second Photoelectric Conversion Cell

[0969] 23,23b p-type trap region

[0970] 24 n-type semiconductor region

[0971] 25. Photoelectric conversion unit

[0972] 26 pinned layers

[0973] 31, 31J Separation Region

[0974] 31a Shallow separation region

[0975] 31b Deep separation region

[0976] 31x Extension in the first plane

[0977] 31xy intersection

[0978] 31y Extension in the second plane

[0979] 32 Excavation Department

[0980] 32a Shallow Excavation Section

[0981] 32b Deep Excavation Department

[0982] 33 Insulating film

[0983] 34. Pad Insulation Film

[0984] 35 Polycrystalline silicon film

[0985] 36-section insulating film

[0986] 37 Stapling layers

[0987] 38. Excavation area

[0988] 39 Separation Barrier

[0989] 41 Gate trench

[0990] 42 Gate insulating film

[0991] 43. Gate electrode

[0992] 43a Head

[0993] 43b Torso

[0994] 44 Gate electrode

[0995] 45a, 45b Main electrode regions

[0996] 46 Relay conductive pads

[0997] 51 Multilayer Wiring

[0998] 52-layer interlayer insulating film

[0999] 53f, 53m, 53w, 53w1 contact electrodes

[1000] 54 Wiring Layer

[1001] 54f, 54m, 54w, 54w1 wiring

[1002] 61 Fixed charge film

[1003] 62 Anti-reflective film

[1004] 63 Insulating film

[1005] 64. Metal thin film (conductive film)

[1006] 64H two-dimensional material membrane

[1007] 65 Insulating film

[1008] 65a Void

[1009] 66 Sealed insulating film

[1010] 67 Dielectric film

[1011] 71 Spacer

[1012] 72 shading film

[1013] 73. Pad Insulation Film

[1014] 74 Optical Filtering Layer

[1015] 74a Optical Filtering Unit

[1016] 75 Lens Layer

[1017] 75a Microlens (On-Chip Lens)

[1018] 76 Connecting holes

[1019] 77 Metal Grid

[1020] 78 Relay Electrode

[1021] 81 Separation of insulating film

[1022] 81a silicon oxide film

[1023] 81b silicon nitride film

[1024] 82 Insulating film

[1025] 83 Silica film

[1026] 85 Separation of insulating film

[1027] 85a silicon oxide film

[1028] 85b, 85c dielectric films

[1029] 86 Silica film

[1030] 110 Insulation Layer

[1031] 120 Semiconductor Layer

[1032] 130 Conductive Path

[1033] 132 Through-contact electrode

[1034] Contact electrodes 133 and 134

[1035] 135 wiring

[1036] 200 electronic devices

[1037] 201 Solid-State Imaging Device

[1038] 202 Optical Lenses (Optical Systems)

[1039] 203 shutter mechanism

[1040] 204 drive circuit

[1041] 205 Signal Processing Circuit

[1042] 206 Incident light

[1043] AMP amplification transistor

[1044] FD n-type floating diffusion region

[1045] M1 Etching Mask

[1046] PD photodiode

[1047] Q pixel transistor

[1048] RST reset transistor

[1049] SEL selects transistors

[1050] S1 First Face

[1051] S2 Second Face

[1052] TR Transmission Transistor

[1053] WC, WC1 p-type power supply contact area

[1054] V1 First reference potential

[1055] V2 Second reference potential

[1056] V3 Third Reference Potential

Claims

1. A light detection device, comprising: A semiconductor layer having a thickness in one direction; A photoelectric conversion region is disposed in the semiconductor layer and separated by a separation region; and A photoelectric conversion unit is disposed in the photoelectric conversion region and configured to perform photoelectric conversion from light to signal charge, wherein The separation region includes A mining section, which is disposed in the semiconductor layer and extends in the one direction. A fixed charge film, having a fixed charge and disposed along the side portion of the excavation section, and A metal film is disposed along the fixed charge film on the inner side of the excavation section.

2. The photodetector according to claim 1, wherein the metal film is electrically connected to the conductor to which the potential is applied.

3. The optical detection device according to claim 2, wherein... The signal charge is an electron. The fixed charge is a negative fixed charge, and The potential applied to the metal film is a negative potential.

4. The optical detection device according to claim 1, wherein each of the fixed charge film and the metal film is disposed on each of the two side faces of the excavation portion located on opposite sides of each other.

5. The optical detection device according to claim 4, wherein... The semiconductor layer has a first facet and a second facet located on opposite sides of each other in the one direction, and Each of the fixed charge film and the metal film is folded back on the first face side of the semiconductor layer.

6. The photodetector according to claim 5, wherein the metal film terminates on the outer side of the second facet of the semiconductor layer.

7. The photodetector according to claim 5, wherein the metal film terminates inside the second facet of the semiconductor layer.

8. The optical detection device according to claim 5, wherein The excavation unit includes: A shallow excavation section is disposed on the first face side of the semiconductor layer; and The deep portion extends from the shallow portion side toward the second surface side of the semiconductor layer, and in the plan view, its width in the short side direction is narrower than the width of the shallow portion in the short side direction. Each of the fixed charge film and the metal film is selectively disposed in the deep excavation section.

9. The optical detection device according to claim 8, wherein... The separation area also includes a section of insulating film disposed in the shallow excavation section, and The fixed charge film is disposed across the side portion of the deep excavation section and the bottom portion of the section insulating film.

10. The photodetector according to claim 1, wherein the separation region further includes an insulating film disposed between the fixed charge film and the metal film.

11. The photodetector according to claim 1, wherein the separation region further comprises an insulating film disposed on the side of the metal film opposite to the fixed charge film side.

12. The photodetector according to claim 11, wherein the thickness of the metal film is less than the thickness of the insulating film.

13. The optical detection device according to claim 1, wherein... The photoelectric conversion region further includes: A first semiconductor region of a first conductivity type, which is spaced apart from the separation region and the first face of the semiconductor layer, and is included in the photoelectric conversion section; A second semiconductor region of a second conductivity type is disposed between the separation region and the first semiconductor region; and A third semiconductor region of the second conductivity type is disposed between the separation region and the second semiconductor region, and has an impurity concentration higher than that of the second semiconductor region.

14. The photodetector according to claim 1, wherein the thickness of the metal film is less than 10 nm.

15. The photodetector according to claim 5, wherein the thickness of the metal film on the first face side of the semiconductor layer is greater than the thickness on the second face side of the semiconductor layer.

16. The optical detection device according to claim 1, wherein the metal film comprises a two-dimensional material film.

17. The photodetector according to claim 16, wherein the two-dimensional material film comprises at least one of C, Mo, W, Zr, Sn, Hf, Ge, S, Se or Te.

18. The photodetector according to claim 16, wherein the thickness of the two-dimensional material film is less than 5 nm.

19. The photodetector according to claim 1, wherein the photoelectric conversion region further includes at least a charge holding section and a transmission transistor, the charge holding section holding the signal charge photoelectrically converted by the photoelectric conversion section, and the transmission transistor transmitting the signal charge photoelectrically converted by the photoelectric conversion section to the charge holding section.

20. The photodetector according to claim 1, further comprising, when the semiconductor layer is defined as a first semiconductor layer: A second semiconductor layer is configured to overlap with the first semiconductor layer in the one direction; and A pixel circuit reads out the signal charge held in the charge holding section and outputs a pixel signal based on the read-out signal charge, wherein... The pixel transistors included in the pixel circuit are disposed in the second semiconductor layer.

21. A light detection device, comprising: A semiconductor layer having a thickness in one direction; A photoelectric conversion region is disposed in the semiconductor layer and separated by a separation region; and A photoelectric conversion unit is disposed in the photoelectric conversion region and configured to perform photoelectric conversion from light to signal charge, wherein The separation region includes A mining section, which is disposed in the semiconductor layer and extends in the one direction. A separating insulating film is disposed on the inner side of the excavated portion along the side portion of the semiconductor layer, and A metal film is disposed along the insulating film on the inner side of the excavation section.

22. The photodetector according to claim 21, wherein the metal film is electrically connected to a conductor to which an applied potential is applied.

23. The photodetector according to claim 21, wherein the thickness of the separating insulating film is less than 20 nm.

24. The photodetector according to claim 21, wherein the separating insulating film comprises at least one of a silicon oxide film or a silicon nitride film.

25. The photodetector according to claim 21, wherein each of the separating insulating film and the metal film is disposed on the side portion of each of the two semiconductor layers located on opposite sides of each other across the excavation portion.

26. The optical detection device according to claim 21, wherein... The semiconductor layer has a first facet and a second facet located on opposite sides of each other in the one direction, and The excavation section and the separating insulating film are disposed across the first and second faces of the semiconductor layer.

27. The photodetector according to claim 26, wherein the metal film is folded back on the first face side of the semiconductor layer.

28. The photodetector according to claim 26, wherein the metal film is disposed across a first facet and a second facet of the semiconductor layer.

29. The optical detection device according to claim 21, wherein... The semiconductor layer has a first facet and a second facet located on opposite sides of each other in one direction. The photoelectric conversion region further includes a charge holding section and a transmission transistor. The charge holding section is disposed on the first face side, and the transmission transistor transmits the signal charge photoelectrically converted by the photoelectric conversion section to the charge holding section. The photoelectric conversion unit performs photoelectric conversion on light incident from the second face side of the semiconductor layer.

30. The optical detection device according to claim 29, wherein... The photoelectric conversion region includes a first face and a second face, and A fixed charge film with a fixed charge is disposed on the second surface side of the photoelectric conversion region.

31. The photodetector according to claim 21, wherein the separation region further includes a fixed charge film having a fixed charge and disposed between the separation insulating film and the metal film.

32. The photodetector according to claim 21, wherein the separation region further comprises an insulating film disposed on the side of the metal film opposite to the separation insulating film side.

33. The photodetector according to claim 21, wherein the thickness of the metal film is less than the thickness of the insulating film.

34. The photodetector according to claim 21, wherein the thickness of the metal film is less than 10 nm.

35. The optical detection device according to claim 21, wherein... The semiconductor layer has a first facet and a second facet located on opposite sides of each other in one direction. The excavation unit includes: A shallow excavation section is disposed on the first face side of the semiconductor layer; and The deep portion extends from the shallow portion side toward the second surface side of the semiconductor layer, and in the plan view, its width in the short side direction is narrower than the width of the shallow portion in the short side direction. The separating insulating membrane is disposed across the shallow excavation section and the deep excavation section.

36. The photodetector according to claim 21, wherein the separating insulating film comprises a silicon oxide film and a silicon nitride film.

37. The photodetector according to claim 21, wherein the separating insulating film comprises a dielectric film with a higher relative permittivity than silicon oxide.

38. The photodetector according to claim 37, wherein the dielectric film comprises at least one of Si, N, Al, Hf, Ta, Ti, O, Mg, Sc, Zr, La, Gd or Y.

Images