Display device, light emitting device, and method of manufacturing display device

Abstract

A display device, a light-emitting element, and a method for manufacturing the display device are provided. The display device includes: a substrate on which pixel electrodes are disposed; a light-emitting element disposed on the pixel electrodes and including an element rod and contact electrodes disposed on one surface and a side surface of the element rod; a connecting electrode electrically connecting the contact electrodes and the pixel electrodes; and a common electrode disposed on the light-emitting element. The element rod may include: a first element rod including a first semiconductor layer and an active layer, and the side surface of the first element rod having a first tilt angle; a second element rod disposed on the first element rod, and the side surface of the second element rod having a second tilt angle; and a third element rod disposed on the second element rod, and the side surface of the third element rod having a third tilt angle.

Description

Technical Field

[0001] This disclosure relates to a display device, a light-emitting element, and a method for manufacturing a display device. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel display devices, such as liquid crystal displays, field emission displays, and light-emitting displays.

[0003] Light-emitting displays include organic light-emitting displays and micro-light-emitting displays. Organic light-emitting displays use organic light-emitting diodes (OLEDs) as light-emitting elements, while micro-light-emitting displays use micro-light-emitting diodes (hereinafter referred to as micro-light-emitting elements) as light-emitting elements. Because micro-light-emitting diodes are made of inorganic materials, they have fewer degradation problems and therefore a longer lifespan compared to organic light-emitting diodes. Summary of the Invention

[0004] Technical issues

[0005] The aspects and features of this disclosure are to provide a display device, a light-emitting element, and a method for manufacturing the display device that can prevent short circuits between the common electrode and the contact electrode.

[0006] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0007] Technical solution

[0008] According to an aspect of this disclosure, a display device includes: a substrate on which a pixel electrode is disposed; a light-emitting element disposed on the pixel electrode and including an element rod and contact electrodes disposed on one side and a side surface of the element rod; a connecting electrode electrically connecting the contact electrodes and the pixel electrode; and a common electrode disposed on the light-emitting element, wherein the element rod includes: a first element rod including a first semiconductor layer and an active layer and having a side surface having a first tilt angle; a second element rod disposed on the first element rod and having a side surface having a second tilt angle; and a third element rod disposed on the second element rod and having a side surface having a third tilt angle, wherein the light-emitting element further includes: a first protective layer disposed on one side and a side surface of the first element rod and on a side surface of the second element rod; a reflective layer disposed on the first protective layer and on one side and a side surface of the first element rod and on a side surface of the second element rod; and a second protective layer disposed on a side surface of the second element rod, a side surface of the third element rod, and an edge of the top surface of the third element rod.

[0009] The contact electrode is disposed on one side of the first element rod on the reflective layer and extends to the side of the first element rod and the side of the second element rod.

[0010] The contact electrode is disposed on the side of the second element rod between the reflective layer and the second protective layer, wherein one end of the reflective layer on the side of the second element rod is completely surrounded by the first protective layer and the contact electrode.

[0011] The first protective layer, reflective layer, and contact electrode are not located on the side of the third element rod.

[0012] The third semiconductor layer has an uneven structure.

[0013] The second protective layer extends from the side of the third element rod and is disposed at the edge of the uneven structure of the third semiconductor layer.

[0014] The second protective layer thins inward from the top surface of the third semiconductor layer.

[0015] The display device further includes an organic pattern layer disposed on a pixel electrode and on the lower surface of a light-emitting element, wherein a connecting electrode is disposed on one side of the pixel electrode, the side of the organic pattern layer, and the side of the first contact electrode of the light-emitting element.

[0016] The first protective layer has one or more openings defined on one side of the first element bar, wherein contact electrodes are electrically connected to the element bar exposed by the openings.

[0017] The contact electrode has higher conductivity and lower reflectivity than the reflective layer.

[0018] The second dip angle is smaller than the first dip angle and the third dip angle.

[0019] The second tilt angle is between 60 and 80 degrees.

[0020] The width of the second element bar increases toward the third element bar, and the width of the third element bar is wider than the width of the first element bar.

[0021] The light-emitting element includes: an element rod in which a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer are stacked sequentially and divided into a first element rod, a second element rod, and a third element rod according to an angle; a first protective layer disposed on one side and the side surface of the first element rod and on the side surface of the second element rod; a reflective layer disposed on the second protective layer and on one side and the side surface of the first element rod and on the side surface of the second element rod; a contact electrode disposed on one side of the first element rod on the reflective layer and extending to the side surface of the first element rod and the side surface of the second element rod; and a second protective layer disposed on the side surface of the second element rod, the side surface of the third element rod, and the edge of the top surface of the third element rod.

[0022] The third semiconductor layer has an uneven structure, wherein the second protective layer is disposed at the edge of the uneven structure of the third semiconductor layer.

[0023] The second protective layer thins inward from the top surface of the third semiconductor layer.

[0024] The second dip angle is smaller than the first dip angle and the third dip angle, wherein the second dip angle is between 60 degrees and 80 degrees.

[0025] According to another aspect of this disclosure, a method for manufacturing a display device is provided, comprising: forming a third semiconductor material layer, a second semiconductor material layer, an active material layer, and a first semiconductor material layer on a growth substrate; forming a first element bar having a first tilt angle by etching the active material layer and the first semiconductor material layer using a first mask; forming a second element bar having a second tilt angle by etching the second semiconductor material layer and the third semiconductor material layer using a second mask; forming a first protective layer, a reflective layer, and a contact electrode covering the third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer; forming a third element bar having a third tilt angle by etching a portion of the second element bar using a third mask; and forming a second protective layer disposed on the side surface of the second element bar and the side surface of the third element bar, wherein the second protective layer extends from the side surface of the third element bar and is disposed between the edge gap between the third element bar and the protective layer.

[0026] The method includes: transferring a light-emitting element comprising a first element rod, a second element rod, and a third element rod to a circuit board having a pixel electrode; and forming a connecting electrode connecting the contact electrode and the pixel electrode.

[0027] Transferring light-emitting elements to a circuit board having pixel electrodes includes: forming an organic pattern layer on the pixel electrodes as a pseudo-adhesive layer; arranging a plurality of light-emitting elements on the organic pattern layer, and fixing the light-emitting elements by curing the organic pattern layer.

[0028] Details of the implementation methods are included in the detailed description and accompanying drawings.

[0029] Beneficial effects

[0030] According to the display device and its manufacturing method according to the embodiment, short circuits between the common electrode and the contact electrode of the light-emitting element can be minimized.

[0031] However, the effects of the embodiments according to this disclosure are not limited to those exemplified above, and various other effects are incorporated herein. Attached Figure Description

[0032] Figure 1 This is a perspective view of a display device according to an embodiment.

[0033] Figure 2 This is a layout diagram of a display device according to an embodiment.

[0034] Figure 3 This is a block diagram of a display device according to an embodiment.

[0035] Figure 4 This is an equivalent circuit diagram of a sub-pixel according to the implementation method.

[0036] Figure 5 This is a layout diagram showing the pixels of a display area according to one embodiment.

[0037] Figure 6 This illustrates a corresponding embodiment. Figure 5 A cross-sectional view of the display panel along line I1-I1'.

[0038] Figure 7 This illustrates an embodiment. Figure 6 A detailed cross-sectional view of region A.

[0039] Figure 8 This illustrates an embodiment according to another method. Figure 6 A detailed cross-sectional view of region A.

[0040] Figure 9 This illustrates an embodiment according to another method. Figure 6 A detailed cross-sectional view of region A.

[0041] Figure 10 This is a layout diagram showing the pixels of a display area according to one embodiment.

[0042] Figure 11 It shows the corresponding Figure 10 A cross-sectional view of an example of the display panel section along line I2-I2'.

[0043] Figure 12 It is shown in detail Figure 11 A cross-sectional view of an example of region B in the diagram.

[0044] Figure 13 This is a flowchart illustrating a method for manufacturing a display device according to one embodiment.

[0045] Figures 14 to 22 This is a cross-sectional view showing a method of manufacturing a display device according to an embodiment; Figure 23 It is shown in detail Figure 22 A view of an example of region C in the image; Figures 24 to 29 This is a cross-sectional view further illustrating a method of manufacturing a display device according to an embodiment; Figure 30 This is an exemplary view of a smartwatch including a display device according to an embodiment; Figure 31 This is an exemplary view of a virtual reality device including a display device according to an embodiment; Figure 32 and Figure 33 This is an exemplary view of a virtual reality device including a display device according to an embodiment; Figure 34 This is an exemplary view showing a vehicle instrument cluster and a central dashboard including a display device according to an embodiment; and Figure 35 This is an exemplary view of a transparent display device including a display device according to an embodiment. Detailed Implementation

[0046] The advantages and features of the present invention, as well as methods for implementing them, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. These embodiments are provided only to ensure that the disclosure of the present invention is complete and do not limit common knowledge in the art to which this invention pertains. The present invention is provided to fully inform those skilled in the art of its scope, and the invention is defined only by the scope of the claims.

[0047] When an element or layer is referred to as being "on" another element or layer, it includes cases where the element or layer is directly on top of or interposed with another element. Throughout this specification, the same reference numerals denote the same elements. The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the drawings used to explain embodiments are illustrative, and the invention is not limited to the details shown.

[0048] Features of each of the various embodiments of the present invention may be partially or wholly connected or combined with each other, various interlocks and drives are technically possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

[0049] The embodiments will be described in detail below with reference to the accompanying drawings.

[0050] Figure 1 This is a perspective view of a display device according to an embodiment.

[0051] refer to Figure 1The display device 10 is a device for displaying moving images and / or still images. The display device 10 can be used as a display screen in portable electronic devices and various products such as televisions, laptop computers, monitors, billboards and / or Internet of Things (IoT) devices, such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-books, portable multimedia players (PMPs), navigation devices and ultra-mobile PCs (UMPCs).

[0052] The display device 10 may be a light-emitting display, such as an organic light-emitting display using organic light-emitting diodes (OLEDs), a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including inorganic semiconductors, or a micro-light-emitting display or nano-light-emitting display using micro-light-emitting diodes or nano-light-emitting diodes (LEDs). The following description will primarily focus on the case where the display device 10 is a micro-light-emitting display or a nano-light-emitting display, but this disclosure is not limited thereto. For ease of description, micro-LEDs or nano-LEDs will be referred to as light-emitting elements.

[0053] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply unit 500.

[0054] The display panel 100 can be formed as a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. Each corner where the short side extending in the first direction DR1 meets the long side extending in the second direction DR2 can be rounded to have an appropriate curvature (e.g., a predetermined curvature), or it can be a right angle. The planar shape of the display panel 100 is not limited to a quadrilateral shape, but can also be other polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 can be formed as a flat surface, but this disclosure is not limited thereto. For example, the display panel 100 may include curved portions formed at the left and right ends and having constant or varying curvatures. Furthermore, the display panel 100 can be formed as flexible, such that it can be curved, bent, folded, and / or rolled up.

[0055] The substrate SUB of the display panel 100 (see, for example, see...) Figure 6 It can include the main region MA and the sub-region SBA.

[0056] The main region MA may include a display region DA for displaying an image and a non-display region NDA disposed around the display region DA along its edge or periphery. The display region DA may include multiple pixels for displaying the image. Each pixel may include multiple sub-pixels. For example, each pixel may include a first sub-pixel that emits light of a first color, a second sub-pixel that emits light of a second color, and a third sub-pixel that emits light of a third color, but this disclosure is not limited thereto.

[0057] The subregion SBA can protrude from one side of the main region MA in the second direction DR2. Although the subregion SBA is in Figure 1 The display panel 100 is unfolded, but it can be bent. In this case, the sub-region SBA can be placed on the lower surface of the display panel 100. When the sub-region SBA is bent, it can overlap with the main region MA on the third third direction DR3, which is the thickness direction of the display panel 100. The display driving circuit 250 can be disposed in the sub-region SBA.

[0058] The display driving circuit 250 can generate signals and voltages for driving the display panel 100. The display driving circuit 250 can be formed as an integrated circuit (IC) and attached to the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, and / or ultrasonic bonding method. However, this disclosure is not limited thereto. For example, the display driving circuit 250 can also be attached to the circuit board 300 using a chip-on-film (COF) method.

[0059] Circuit board 300 can be attached to one end of a sub-region SBA of display panel 100. Therefore, circuit board 300 can be electrically connected to display panel 100 and display driving circuit 250. Display panel 100 and display driving circuit 250 can receive digital video data, timing signals, and driving voltages through circuit board 300. Circuit board 300 can be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as chip on film (COF).

[0060] The power supply unit 500 can generate multiple panel driving voltages based on the power supply voltage from an external source. The power supply unit 500 can be formed as an integrated circuit (IC) and attached to the circuit board 300 using the COF method.

[0061] Figure 2 This is a layout diagram of the display device 10 according to the embodiment. Figure 2 This shows the state where the subregion SBA is expanded without bending.

[0062] refer to Figure 2 The display panel 100 may include a main area MA and a sub-area SBA.

[0063] The main region MA may include a display area DA for displaying the image and a non-display area NDA surrounding the display area DA. The display area DA may occupy most of the main region MA. The display area DA may be located in the center of the main region MA.

[0064] The display area DA may include multiple pixels PX for displaying an image, and each of the pixels PX may include multiple subpixels SPX. Pixel PX may be defined as the smallest group of subpixels that can represent a white grayscale level.

[0065] The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can be an area outside the display area DA. The non-display area NDA can surround the display area DA. The non-display area NDA can be an edge area of ​​the display panel 100.

[0066] The first scan driver SDC1 and the second scan driver SDC2 can be located in the non-display area NDA. The first scan driver SDC1 can be located on one side (e.g., the left side) of the display panel 100, and the second scan driver SDC2 can be located on the other side (e.g., the right side) of the display panel 100. However, this disclosure is not limited thereto.

[0067] Each of the first scan driver SDC1 and the second scan driver SDC2 can be electrically connected to the display driver circuit 250 via a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 can receive a scan control signal from the display driver circuit 250, generate a scan signal according to the scan control signal, and output the scan signal to the scan line.

[0068] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be less than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and placed below the display panel 100. In this case, the sub-region SBA may overlap with the main region MA in the third direction DR3.

[0069] The sub-region SBA can include the connection region CA, the pad region PA, and the bend region BA.

[0070] The connecting area CA is a region that protrudes from one side of the main area MA in the second direction DR2. One side of the connecting area CA can contact the non-display area NDA of the main area MA, and the other side of the connecting area CA can contact the curved area BA.

[0071] The pad area PA is the area where the pads PD and the display driving circuit 250 are located. The display driving circuit 250 can be attached to the driving pads of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be attached to the pads PD of the pad area PA using a conductive adhesive member such as anisotropic conductive film. One side of the pad area PA can contact the curved area BA.

[0072] The bending region BA is a flexible region. When the bending region BA is bent, the pad region PA can be placed below the connector region CA and the main region MA. The bending region BA can be positioned between the connector region CA and the pad region PA. One side of the bending region BA can contact the connector region CA, and the other side of the bending region BA can contact the pad region PA.

[0073] Figure 3 This is a block diagram of the display device 10 according to an embodiment.

[0074] refer to Figure 3 The display area DA includes multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, and multiple data lines DL.

[0075] Pixels PX can be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, pixels PX can be arranged along the rows and columns of a matrix along the first direction DR1 and the second direction DR2. Scan lines SL and emit control lines EL can extend along the first direction DR1 and can be arranged along the second direction DR2. Data lines DL can extend along the second direction DR2 and can be arranged along the first direction DR1. Scan lines SL include multiple write scan lines GWL, multiple initialization scan lines GIL, and multiple bias scan lines GBL.

[0076] Each sub-pixel SPX can be connected to one of the write scan lines GWL, one of the initialization scan lines GIL, one of the bias scan lines GBL, one of the emission control lines EL, and one of the data lines DL. In some embodiments, each sub-pixel SPX can be connected to one of the control scan lines. Each sub-pixel SPX can receive the data voltage of the data line DL according to the write scan signal of the write scan line GWL, and can emit light from the light-emitting element according to the data voltage.

[0077] The non-display area NDA includes a first scan driver SDC1, a second scan driver SDC2, and a display driver circuit 250.

[0078] The first scan driver SDC1 and the second scan driver SDC2 may each include a write scan signal output unit 611, an initialization scan signal output unit 612, a bias scan signal output unit 613, and a transmit control signal output unit 614. The write scan signal output unit 611, the initialization scan signal output unit 612, the bias scan signal output unit 613, and the transmit control signal output unit 614 may each receive a scan timing control signal SCS from the timing controller 251.

[0079] The write scan signal output unit 611 can generate write scan signals according to the scan timing control signal SCS of the timing controller 251, and sequentially output the write scan signals to the write scan line GWL.

[0080] The initialization scan signal output unit 612 can generate an initialization scan signal according to the scan timing control signal SCS, and sequentially output the initialization scan signal to the initialization scan line GIL.

[0081] The bias scan signal output unit 613 can generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL. The transmit control signal output unit 614 can generate a transmit control signal according to the scan timing control signal SCS, and sequentially output the transmit control signal to the transmit control line EL.

[0082] The display driver circuit 250 includes a timing controller 251 and a data driver 252.

[0083] Data driver 252 can receive digital video data DATA and data timing control signal DCS from timing controller 251. Data driver 252 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to data line DL. In this case, sub-pixels SPX can be selected by the write scan signals of the first scan driver SDC1 and the second scan driver SDC2, and the data voltage can be supplied to the selected sub-pixel SPX.

[0084] The timing controller 251 can receive digital video data DATA and timing signals from an external source. Based on the timing signals, the timing controller 251 can generate a scan timing control signal SCS and a data timing control signal DCS for controlling the display panel 100. The timing controller 251 can output the scan timing control signal SCS to the first scan driver SDC1 and the second scan driver SDC2. The timing controller 251 can also output the digital video data DATA and the data timing control signal DCS to the data driver 252.

[0085] The power supply unit 500 can generate multiple panel driving voltages based on the power supply voltage from the outside. For example, the power supply unit 500 can generate a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VINT, and a fourth power supply voltage VAINT, and supply them to the display panel 100.

[0086] Figure 4 This is an equivalent circuit diagram of the sub-pixel SPX according to the implementation method.

[0087] refer to Figure 4 According to the implementation method, the sub-pixel SPX can be connected to scan lines GWL, GIL, and GBL, emission control line EL, and data line DL. For example, the sub-pixel SPX can be connected to the write scan line GWL, the initialization scan line GIL, the bias scan line GBL, the emission control line EL, and the data line DL.

[0088] According to the embodiment, the sub-pixel SPX includes a driving transistor DT, a switching element, a capacitor C1, and a light-emitting element LE. The switching element includes a first transistor ST1 to a sixth transistor ST6.

[0089] The driving transistor DT includes a gate electrode, a conductive layer, and a second electrode. The driving transistor DT controls the drain-source current Ids (hereinafter referred to as the "driving current") flowing between the conductive layer and the second electrode according to the data voltage applied to the gate electrode.

[0090] The light-emitting element LE1 can be a micro-LED.

[0091] The light-emitting element LE1 emits light according to the driving current Ids. The amount of light emitted from the light-emitting element LE is proportional to the driving current Ids. The anode of the light-emitting element LE can be connected to the conductive layer of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode can be connected to the second power supply line VSL to which a second supply voltage is applied.

[0092] A capacitor C1 is formed between the second electrode of the driving transistor DT and a first power supply line VDL to which a first supply voltage is applied. The first supply voltage can be at a higher level than the second supply voltage. One electrode of capacitor C1 can be connected to the second electrode of the driving transistor DT, and the other electrode can be connected to the first power supply line VDL.

[0093] like Figure 4 As shown, the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT can all be formed as p-type metal-oxide-semiconductor field-effect transistors (MOSFETs). In this case, the active layer of each of the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT can be made of polysilicon.

[0094] The gate electrodes of the first transistor ST1 and the second transistor ST2 can be connected to the write scan line GWL, the gate electrode of the third transistor ST3 can be connected to the initialization scan line GIL, the gate electrode of the fourth transistor ST4 can be connected to the bias scan line GBL, and the gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 can be connected to the emitter control line EL. Since the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, they can conduct when a gate-low voltage scan signal and a gate-low voltage emitter control signal are applied to the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emitter control line EL, respectively. One electrode of the third transistor ST3 can be connected to the applied gate-low voltage emitter control signal. Figure 3 The third supply voltage VINT in the first initialization voltage line VIL, and one electrode of the fourth transistor ST4 can be connected to the applied voltage. Figure 3 The second initialization voltage line VAIL is the fourth power supply voltage VAINT. Figure 3 The third supply voltage VINT and Figure 3 The fourth supply voltage, VAINT, can be a different voltage. Furthermore, Figure 3 The third supply voltage VINT and Figure 3 The fourth supply voltage VAINT can be at a voltage level that is lower than the first supply voltage VDD and higher than the second supply voltage VSS.

[0095] Optionally, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed as p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 can be formed as n-type MOSFETs. The active layer of each of the p-type MOSFETs (DT, ST2, ST4, ST5, and ST6) can be made of polysilicon, and the active layer of each of the n-type MOSFETs (ST1 and ST3) can be made of oxide semiconductor. In this case, because the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can be turned on in response to a scan signal with a high gate voltage, and the third transistor ST3 can be turned on in response to an initial scan signal with a high gate voltage. On the other hand, because the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, they can be turned on in response to a scan signal with a low gate voltage and an emitter control signal.

[0096] Optionally, the fourth transistor ST4 can be formed as an n-type MOSFET, while the remaining transistors DT, ST1, ST2, ST3, ST5, and ST6 can be formed as p-type MOSFETs. In this case, the active layer of the fourth transistor ST4 can be formed of oxide semiconductor, and the active layer of each of the remaining transistors DT, ST1, ST2, ST3, ST5, and ST6 can be formed of polysilicon. Furthermore, the fourth transistor ST4 can be turned on when a scan signal with a high gate voltage is applied, while the remaining transistors DT, ST1, ST2, ST3, ST5, and ST6 can be turned on when a scan signal with a low gate voltage and a transmit control signal are applied.

[0097] Optionally, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can all be formed as n-type MOSFETs. In this case, the active layers of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can be formed of oxide semiconductor, and they can be turned on when a scan signal and a transmit control signal with a high gate voltage are applied.

[0098] Figure 5 This is a layout diagram showing the pixels of the display area according to an embodiment.

[0099] refer to Figure 5 Each of the plurality of pixels PX in the display area DA may include three sub-pixels SPX1, SPX2, and SPX3, but this disclosure is not limited thereto and may include four sub-pixels. Each of the plurality of pixels PX includes three sub-pixels SPX1, SPX2, and SPX3, which include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0100] Multiple pixels PX can be arranged in a matrix. In each of the multiple pixels PX, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged along the first direction DR1.

[0101] When each of the multiple pixels PX comprises three sub-pixels SPX1, SPX2, and SPX3, the first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 can emit light of a third color. Here, the first color light can be light in the red wavelength band, the second color light can be light in the green wavelength band, and the third color light can be light in the blue wavelength band. For example, the blue wavelength band can refer to light with a dominant peak wavelength in the wavelength band approximately 370nm to 460nm, the green wavelength band can refer to light with a dominant peak wavelength in the wavelength band approximately 480nm to 560nm, and the red wavelength band can refer to light with a dominant peak wavelength in the wavelength band approximately 600nm to 750nm.

[0102] Optionally, when each of the multiple pixels PX comprises four sub-pixels, the first sub-pixel can emit light of a first color, the second and fourth sub-pixels can emit light of a second color, and the third sub-pixel can emit light of a third color. Alternatively, the first sub-pixel can emit light of the first color, the second sub-pixel can emit light of the second color, the third sub-pixel can emit light of the third color, and the fourth sub-pixel can emit light of a fourth color. In this case, the fourth color light can be white light.

[0103] The first sub-pixel SPX1 includes a first pixel electrode PXE1, multiple light-emitting elements LE, and a first light conversion layer QDL1. The second sub-pixel SPX2 includes a second pixel electrode PXE2, multiple light-emitting elements LE, and a second light conversion layer QDL2. The third sub-pixel SPX3 includes a third pixel electrode PXE3, multiple light-emitting elements LE, and a light-transmitting layer TPL.

[0104] Each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2.

[0105] The light-emitting element LE can have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2.

[0106] As will be described later, the light-emitting element LE may include a first element bar ( Figure 7 LD1 in the middle), the second element rod ( Figure 7 LD2 in the middle) and the third element rod ( Figure 7The first element rod LD1, the second element rod LD2, and the third element rod LD3 each conform to the planar shape of the light-emitting element LE. For example, the first element rod LD1, the second element rod LD2, and the third element rod LD3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2.

[0107] The length of the short side LD2-2 of the element rod LD is approximately 13 μm to 11 μm, and the length of the long side LD2-1 is 20 μm to 22 μm, and can be 23 μm to 26 μm. Furthermore, the length of the short side LD1-1 of the first element rod LD can be approximately 6 μm to 7 μm, and the length of the long side LD1-2 can be 20 μm to 22 μm, but this is only an example and not a limitation.

[0108] Based on the light conversion efficiency of the first light conversion layer QDL1 and the second light conversion layer QDL2, the areas of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be set. In other words, the lower the light conversion efficiency, the larger the sub-pixel area can be.

[0109] For example, such as Figure 5 As shown, when the light conversion efficiency of the second light conversion layer QDL2 is lower than that of the first light conversion layer QDL1, the area of ​​the second pixel electrode PXE2 can be larger than the area of ​​the first pixel electrode PXE1, and the area of ​​the first pixel electrode PXE1 can be larger than the area of ​​the third pixel electrode PXE3.

[0110] Each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to at least one transistor via pixel connection holes (CT1 / CT2 / CT3). For example, each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to a fourth transistor of the corresponding sub-pixel. Figure 4 The first electrode and the sixth transistor (ST4) in the middle Figure 4 The second electrode of ST6 in the middle.

[0111] Multiple light-emitting elements (LEs) can be disposed on each of pixel electrodes PXE1, PXE2, and PXE3. The same number of LEs can be disposed on each of pixel electrodes PXE1, PXE2, and PXE3. For example, one LE can be disposed on each of pixel electrodes PXE1, PXE2, and PXE3. Multiple LEs can emit light of a third color, i.e., light in the blue wavelength band, but this disclosure is not limited thereto. When the LEs of the first sub-pixel SPX1 emit light of a first color, the LEs of the second sub-pixel SPX2 emit light of a second color, and the LEs of the third sub-pixel SPX3 emit light of a third color, the light conversion layers QDL1 and QDL2 and the light-transmitting layer TPL can be omitted.

[0112] The first light conversion layer QDL1 can completely overlap with the first pixel electrode PXE1 and multiple light-emitting elements LE of the first sub-pixel SPX1. The area of ​​the first light conversion layer QDL1 can be larger than the area of ​​the first pixel electrode PXE1. The first light conversion layer QDL1 can convert or shift the peak wavelength of the incident light to another specific peak wavelength and emit it. For example, the first light conversion layer QDL1 can convert or shift the third light emitted from the multiple light-emitting elements LE of the first sub-pixel SPX1 into the first light.

[0113] The second light conversion layer QDL2 can completely overlap with the multiple light-emitting elements LE of the second sub-pixel SPX2 and the second pixel electrode PXE2. The area of ​​the second light conversion layer QDL2 can be larger than the area of ​​the second pixel electrode PXE2. The second light conversion layer QDL2 can convert or shift the peak wavelength of the incident light to another specific peak wavelength and emit it. For example, the second light conversion layer QDL2 can convert or shift the third light emitted from the multiple light-emitting elements LE of the second sub-pixel SPX2 into second light.

[0114] The light-transmitting layer TPL can completely overlap with the multiple light-emitting elements LE of the third sub-pixel SPX3 and the third pixel electrode PXE3. The light-transmitting layer TPL can transmit incident light as is. For example, the light-transmitting layer TPL can directly transmit third light emitted from the multiple light-emitting elements LE of the third sub-pixel SPX3.

[0115] Figure 6 This shows the corresponding implementation method. Figure 5 A cross-sectional view of the display panel along line I1-I1'. Figure 7 This illustrates an embodiment. Figure 6 A detailed cross-sectional view of region A. Figure 8 and Figure 9 This illustrates one or more other embodiments. Figure 6 A detailed cross-sectional view of region A.

[0116] refer to Figure 6 and Figure 7 The substrate SUB can be made of an insulating material such as glass or polymer resin. If the substrate SUB is made of polymer resin, it can be a stretchable, flexible substrate. Polymer resins can be acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0117] A barrier film (BR) can be disposed on a substrate (SUB). The barrier film (BR) is a film that protects the transistors of the thin-film transistor layer (TFTL) from the influence of moisture permeating through the substrate (SUB), which is susceptible to moisture penetration. The barrier film (BR) can be composed of multiple inorganic films stacked alternately. For example, the barrier film (BR) can be formed as a multilayer of alternating inorganic films selected from one or more of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide layers.

[0118] The thin-film transistor TFT1 can be disposed on the barrier film BR. The thin-film transistor TFT1 can be... Figure 4 The fourth transistor ST4 or the sixth transistor ST6 shown is illustrated. The thin-film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0119] The first active layer ACT1 of the thin-film transistor TFT1 can be disposed on the barrier film BR. The first active layer ACT1 of the thin-film transistor TFT1 may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, and / or amorphous silicon. Optionally, the first active layer ACT1 of the thin-film transistor TFT1 may include an oxide semiconductor, including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) and / or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0120] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region overlapping the first gate electrode G1 on a third-direction DR3, where DR3 is the thickness direction of the substrate SUB. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions on the third-direction DR3 that do not overlap with the first gate electrode G1. The first source region S1 and the first drain region D1 may be conductive regions in which the semiconductor material is doped with ions.

[0121] The first gate insulating film 131 can be disposed on the first channel region CHA1, the first source region S1, the first drain region D1, and the barrier film BR of the thin film transistor TFT1.

[0122] A first gate metal layer may be disposed on the first gate insulating film 131. The first gate metal layer may include the first gate electrode G1 and the first capacitor electrode CAE1 of the thin-film transistor TFT1. The first gate electrode G1 may overlap with the first active layer ACT1 on the third-direction DR3. Figure 6 In the diagram, the first gate electrode G1 and the first capacitor electrode CAE1 are shown as spaced apart from each other (e.g., spaced apart), but the first gate electrode G1 and the first capacitor electrode CAE1 may be connected to each other.

[0123] The second gate insulating film 132 can be disposed on the first gate electrode G1, the first capacitor electrode CAE1 and the first gate insulating film 131 of the thin film transistor TFT1.

[0124] A second gate metal layer can be disposed on the second gate insulating film 132. The second gate metal layer may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 on the third-direction DR3. Because the second gate insulating film 132 has a suitable dielectric constant (e.g., a predetermined dielectric constant), the capacitor ( Figure 4 C1 in the figure can be formed by a first capacitor electrode CAE1, a second capacitor electrode CAE2 and a second gate insulating film 132 disposed between them.

[0125] The first interlayer insulating film 141 can be disposed on the second capacitor electrode CAE2 and the second gate insulating film 132.

[0126] A first data metal layer may be disposed on a first interlayer insulating film 141. The first data metal layer may include a first source connection electrode PCE1. The first source connection electrode PCE1 may be connected to the first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 that penetrates the first gate insulating film 131, the second gate insulating film 132 and the first interlayer insulating film 141.

[0127] The first organic film 160 can be disposed on the first source connection electrode PCE1 and the first interlayer insulating film 141 to flatten the step caused by the thin film transistor TFT1.

[0128] A second data metal layer may be disposed on the first organic film 160. The second data metal layer may include a second source connection electrode PCE2. The second source connection electrode PCE2 may be connected to the first source connection electrode PCE1 through a second pixel contact hole PCT2 penetrating the first organic film 160.

[0129] The second organic film 180 can be disposed on the second source connection electrode PCE2 and the first organic film 160.

[0130] The barrier film BR, the first gate insulating film 131, the second gate insulating film 132, and the first interlayer insulating film 141 can be formed from inorganic films such as silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and / or aluminum oxide layers.

[0131] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer can be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or alloys thereof.

[0132] The first organic membrane 160 and the second organic membrane 180 can be formed from organic membranes such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0133] The light-emitting element layer can be disposed on the second organic film 180. The light-emitting element layer may include pixel electrodes PXE1, PXE2 and PXE3, a common electrode CE, a light-emitting element LE and an organic layer 190.

[0134] The pixel electrode layer can be disposed on the second organic film 180.

[0135] The pixel electrode layer may include pixel electrodes PXE1, PXE2, and PXE3. The pixel electrode layer may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or alloys thereof. For example, the pixel electrode layer may be made of copper (Cu) with low sheet resistance to reduce the resistance of each of the pixel electrodes PXE1, PXE2, and PXE3.

[0136] An organic layer 210 (hereinafter referred to as an organic patterned layer, to distinguish it from the organic films 180 and 190 disposed on the entire surface of the underlying structure) may be disposed on each of the pixel electrodes PXE1, PXE2, and PXE3. The organic patterned layer 210 temporarily fixes and / or adheres multiple light-emitting elements (LEs) to prevent them from tilting or flipping during the transfer of the multiple light-emitting elements (LEs) to the display panel. That is, the organic patterned layer 210 may be a film used to temporarily adhere the multiple light-emitting elements (LEs) to each of the pixel electrodes PXE1, PXE2, and PXE3. To facilitate temporary adhesion, the thickness of the organic patterned layer 210 may be greater than the thickness of each of the pixel electrodes PXE1, PXE2, and PXE3.

[0137] The organic pattern layer 210 can be a photosensitive organic film such as a photoresist. Optionally, the organic pattern layer 210 can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0138] The organic patterned layer 210 can be disposed on the bottom surface of the contact electrode CTE.

[0139] Multiple light-emitting elements (LEs) can be disposed on the organic pattern layer 210. Figure 6 The diagram shows a vertical micro-LED, each of a plurality of light-emitting elements LE extending along a third direction DR3. A vertical micro-LED is defined as an LED having a structure in which a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a third semiconductor layer USE are arranged sequentially along a third direction DR3, which is a vertical direction.

[0140] Each of the plurality of light-emitting elements (LEs) can be formed of an inorganic material such as gallium nitride (GaN). Each of the plurality of light-emitting elements (LEs) can have a length of several to several hundred μm in a first direction DR1, a length in a second direction DR2, and a length in a third direction DR3. For example, each of the plurality of light-emitting elements (LEs) can have a length of approximately 100 μm or less in the first direction DR1, the second direction DR2, and the third direction DR3.

[0141] Each of the light-emitting elements (LEs) may include a current spreading layer (CSL), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a third semiconductor layer (USE), a shell layer (OSL), and a contact electrode (CTE). In some embodiments, the current spreading layer (CSL) may be omitted from each of the light-emitting elements (LEs).

[0142] A current spreading layer (CSL) is disposed on the contact electrode (CTE) and serves to increase light extraction efficiency. The CSL can be formed from a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO) to allow light to pass through.

[0143] The first semiconductor layer SEM1 can be disposed on the current spreading layer CSL (or on the contact electrode CTE if the current spreading layer CSL is omitted), the active layer MQW can be disposed on the first semiconductor layer SEM1, the second semiconductor layer SEM2 can be disposed on the active layer MQW, and the third semiconductor layer USE can be disposed on the second semiconductor layer SEM2.

[0144] The first semiconductor layer SEM1 can be made of GaN doped with a first conductivity type dopant such as Mg, Zn, Ca, Sr, Ba, etc. (e.g., p-type dopant).

[0145] The first semiconductor layer SEM1 can be electrically connected to the pixel electrode PXE of each sub-pixel SPX. For example, the first semiconductor layer SEM1 can be electrically connected to the pixel electrode PXE of each sub-pixel SPX through the current spreading layer CSL and the contact electrode CTE.

[0146] The active layer MQW can be disposed on the first semiconductor layer SEM1. The active layer MQW can emit light by causing electron-hole pairs to recombine based on the electrical signals applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0147] The active layer MQW can include materials having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material with a multiple quantum well structure, it can have a structure in which multiple well layers and barrier layers are stacked alternately. In this case, the well layers can be formed of InGaN, and the barrier layers can be formed of GaN and / or AlGaN, but are not limited thereto. Optionally, the active layer MQW can have a structure in which semiconductor materials with high bandgap energy and semiconductor materials with low bandgap energy are stacked alternately, and can include other group III to group V semiconductor materials depending on the wavelength range of the emitted light.

[0148] When the active layer MQW includes InGaN, the color of the emitted light can vary depending on the indium (In) content. For example, as the indium (In) content increases, the wavelength band of the light emitted by the active layer can shift to the red wavelength band, and as the indium (In) content decreases, the wavelength band of the light emitted by the active layer can shift to the blue wavelength band. For example, the indium (In) content in the active layer MQW of a light-emitting element LE that emits third light (light in the blue wavelength band) can be approximately 10 wt% to 20 wt%.

[0149] The second semiconductor layer SEM2 can be disposed on the active layer MQW. The second semiconductor layer SEM2 can be doped with a dopant of a second conductivity type, such as Si, Ge, Sn, etc. For example, the second semiconductor layer SEM2 can be n-GaN doped with n-type Si.

[0150] An electron blocking layer can be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer can be a layer that suppresses or prevents excessive electron flow into the active layer MQW. For example, the electron blocking layer can be AlGaN and / or p-AlGaN doped with p-type Mg. The electron blocking layer can be omitted.

[0151] A superlattice layer can be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer can be a layer used to alleviate stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer can be formed of InGaN and / or GaN. The superlattice layer can be omitted.

[0152] The third semiconductor layer USE may have an uneven structure on its top surface. For example, the third semiconductor layer USE may be an undoped semiconductor grown on a patterned sapphire substrate (PSS). The third semiconductor layer USE may be a material that is not doped to be n-type or p-type. In embodiments, the third semiconductor layer USE may be undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and / or InN, but is not limited to these.

[0153] The current spreading layer CSL, the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer USE of the light-emitting element LE can be referred to as the element rod LD.

[0154] The element bar LD may include a first element bar LD1, a second element bar LD2, and a third element bar LE3, which are divided according to the change of the tilt angle of the side.

[0155] The first element rod LD1 may include a first sidewall SS1 having a first tilt angle θ1. The first tilt angle θ1 of the first sidewall SS1 may be formed as follows: Figures 7 to 9 The 90 degrees shown is not limited to this. For example, the first tilt angle θ1 can be 70 degrees or greater and less than 90 degrees. The first tilt angle θ1 is the angle between the extension of the contact surface between the second semiconductor layer SEM2 and the first element rod LD1 and the second element rod LD2 and the first sidewall SS1 of the first element rod LD1.

[0156] The height of the first element bar LD1 can be the lowest among the three element bars LD1, LD2, and LD3. That is, the height of the first element bar LD1 is lower than the height of the second element bar LD2 and the height of the third element bar LD3.

[0157] The first element bar LD1 may include a first semiconductor layer SEM1 and an active layer MQW.

[0158] The second element rod LD2 is disposed on the first element rod LD1.

[0159] The height of the second component rod LD2 can be the highest among the component rods LD1, LD2 and LD3.

[0160] The second element rod LD2 may include a second sidewall SS2 having a second tilt angle θ2. The second tilt angle θ2 of the second sidewall SS2 may be 60 degrees or greater and 80 degrees or less. Furthermore, the second tilt angle θ2 may be less than the first tilt angle θ1. Therefore, the second sidewall SS2 may be formed as a regular cone. The width of the second element rod LD2 increases towards the top (i.e., towards the third element rod LE3). The second tilt angle θ2 is the angle between the extension of the contact surface between the second element rod LD2 and the third element rod LD3 and the second sidewall SS2 of the second element rod LD2.

[0161] like Figure 8 As shown, the areas of the surfaces of the first element bar LD1 and the second element bar LD2 facing each other can match each other, but are not limited to this.

[0162] like Figure 9 As shown, the areas of the surfaces of the first element bar LD1 and the second element bar LD2 facing each other can be mismatched, such that the first element bar LD1 and the second element bar LD2 can be formed with steps.

[0163] The second element rod LD2 may include a second semiconductor layer SEM2.

[0164] The third element rod LD3 can be disposed on the second element rod LD2. The third element rod LD3 may include a third sidewall SS3 having a third tilt angle θ3. The third tilt angle θ3 of the third sidewall SS3 can be as follows: Figure 7 The angle shown is 90 degrees, but it is not limited to this. For example, the third tilt angle θ3 can be 70 degrees or greater and less than 90 degrees.

[0165] The third element rod LD3 may include a portion of the third semiconductor layer USE. In one or more other embodiments, the third element rod LD3 may include a portion of the second semiconductor layer SEM2 and the third semiconductor layer USE.

[0166] When the total height of the element rods LD is 6 μm, the height of the first element rod LD1 can be in the range of 0.5 μm to 1.2 μm, the height of the second element rod LD2 can be in the range of 2.3 μm to 2.7 μm, and the height of the third element rod LD3 can be in the range of 1.5 μm to 2.3 μm, but this is for illustrative purposes only and is not limited thereto.

[0167] Each of the plurality of light-emitting elements (LEs) can be formed by growing on a semiconductor substrate (such as a silicon substrate and / or a sapphire substrate). The plurality of light-emitting elements (LEs) can be transferred directly from the semiconductor substrate to the pixel electrodes PXE1, PXE2, and PXE3 of the display panel 100. Alternatively, the plurality of light-emitting elements (LEs) can be transferred to the pixel electrodes PXE1, PXE2, and PXE3 of the display panel 100 by an electrostatic method using an electrostatic head and / or by an imprinting method using an elastic polymer material such as PDMS and / or silicon as a transfer substrate.

[0168] The outer shell layer OSL can be disposed on at least one side of the first element bar LD1, one side of the second element bar LD2, and one side of the third element bar LD3. For example, the outer shell layer OSL is disposed on at least one side of the current spreading layer CSL, the first semiconductor layer SEM1, the second semiconductor layer SEM2, the active layer MQW, and the third semiconductor layer USE. The outer shell layer OSL may include a first protective layer INS1, a first reflective layer RF1, and a second protective layer INS2.

[0169] The first protective layer INS1 and the second protective layer INS2 may include materials with insulating properties, such as inorganic insulating materials like silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiOxNy), aluminum oxide (AlxOy), aluminum nitride (AlN), etc.

[0170] The first protective layer INS1 can be disposed on at least one side of the current spreading layer CSL, the first semiconductor layer SEM1, the second semiconductor layer SEM2, the active layer MQW, and the third semiconductor layer USE.

[0171] The first protective layer INS1 may include one or more openings on one side of the current spreading layer CSL. For example, the first protective layer INS1 may include a first opening OP1 and a second opening OP2 that are spaced apart from each other (e.g., spaced apart).

[0172] At least a portion of the current spreading layer CSL can be exposed through the first opening OP1 and the second opening OP2.

[0173] In this embodiment, the first protective layer INS1 can be made of a single layer or multiple layers of a material with insulating properties. The first protective layer INS1 can prevent electrical short circuits that may occur when the active layer MQW is in direct contact with the electrode through which the electrical signal is transmitted to the element rod LD. Furthermore, because the first protective layer INS1 covers the outer peripheral surface of the active layer MQW and protects the outer surface (e.g., the outer peripheral surface) of the element rod LD, it can reduce or prevent a decrease in luminous efficiency.

[0174] The first reflective layer RF1 may be disposed on the first protective layer INS1 to surround one surface LD-B of the element rod LD, the side surfaces of the first element rod LD1 and the second element rod LD2. The first reflective layer may not be disposed on the side surface of the third element rod LD.

[0175] The first reflective layer RF1 may comprise a conductive and highly reflective metallic material (e.g., reflectivity greater than 90%). The first reflective layer RF1 may comprise, for example, aluminum (Al), chromium (Cr), and / or silver (Ag) and / or alloys thereof, and may comprise a single layer or multiple layers. Multiple layers may be, for example, two layers of titanium / aluminum, two layers of nickel / aluminum, two layers of silver / aluminum-silicon alloy, etc. The first reflective layer RF1 allows light emitted from the light-emitting element LE to be emitted upwards.

[0176] The first reflective layer RF1 can use an omnidirectional reflector (ODR), but is not limited to it. An omnidirectional reflector is a reflector that maintains high reflectivity over a wide wavelength range and a wide angle of incidence. The first reflective layer RF1 can have a reflectivity of 90% or higher in the visible range.

[0177] The contact electrode CTE can be disposed on the first reflective layer RF1, the entire bottom and side of the first element rod LD1, and the side of the second element rod LD2. The contact electrode CTE can be formed to cover one end of the first reflective layer RF1 disposed on the side of the second element rod LD2.

[0178] One end of the contact electrode CTE can be arranged in a straight line aligned with the side surface of the third element rod LD3, but this disclosure is not limited thereto. For example, as Figure 9 As shown, the side surface of the third element rod LD3 can be disposed further outward at one end of the contact electrode CTE. When the side surface of the third element rod LD3 is disposed further outward at one end of the contact electrode CTE, the height of the third element rod LD3 can be reduced.

[0179] The contact electrode CTE can contact the current spreading layer CSL exposed by the first opening OP1 and the second opening OP. When the current spreading layer CSL is omitted, the contact electrode CTE can contact the first semiconductor layer SEM1.

[0180] Since the contact electrode CTE is located on the outermost side of one surface of the first element rod LD1, it can be disposed on the organic pattern layer 210. The contact electrode CTE can include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0181] The second protective layer INS2 may be disposed on at least a portion of the side surface of the component rod LD. For example, the second protective layer INS2 may be disposed on the side surface of the second component rod LD2 and the third component rod LD3, and may extend from the side surface of the third component rod LD3, and may be at least partially disposed on the top surface of the third component rod LD3. For example, the second protective layer INS2 may be disposed at the edge of the top surface of the third component rod LD3. The second protective layer INS2 may be disposed along an irregular portion of the top surface of the third component rod LD3. The second protective layer INS2 may be configured to thin from the outer side to the inner side of the top surface of the third component rod LD3.

[0182] Therefore, the contact area CTA between the common electrode CE and the third element rod LD3 on the plane can be smaller than the area LD3A of the third element rod LD3. Furthermore, on the plane (e.g., in a planar view), the area LEA of the third element rod LD3 can be the same as the area LEA of the light-emitting element LE; therefore, the contact area CTA between the common electrode CE and the third element rod LD3 can be the same as the area LEA of the third element rod LD3.

[0183] The second protective layer INS2 can cover and protect at least one end of the contact electrode CTE.

[0184] The connecting electrode BE connects the contact electrode CTE of the light-emitting element LE to one of the pixel electrodes PXE1, PXE2, and PXE3. The connecting electrode BE can be connected to any of the exposed pixel electrodes PXE1, PXE2, and PXE3 through a connecting hole penetrating the organic patterning layer 210. Furthermore, the connecting electrode BE can be disposed on the top surface of the organic patterning layer 210 and the side surface of the contact electrode CTE. Alternatively, the connecting electrode BE can be disposed on a portion of the side surface of the light-emitting element LE. For example, the connecting electrode BE can be disposed on the contact electrode CTE on the side surface of the first element bar LD1.

[0185] The connecting electrode BE can include any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the connecting electrode BE can be made of a transparent conductive material (TCO) that transmits light, such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0186] The third organic layer 190 may be configured to cover a portion of the side surface of the plurality of light-emitting elements LE. Furthermore, the third organic layer 190 may be configured to cover the connecting electrode BE.

[0187] The top surface of each of the multiple light-emitting elements LE can be exposed without being covered by the third organic layer 190.

[0188] The third organic layer 190 can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0189] The common electrode CE can be disposed on the top surface of each of the multiple light-emitting elements LE and on the top surface of the third organic layer 190. The common electrode CE can be a common layer formed together in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The common electrode CE can be made of a transparent conductive material (TCO) that can transmit light, such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0190] Meanwhile, pixel electrodes PXE1, PXE2, and PXE3 can be referred to as anode electrodes or first electrodes, and the common electrode CE can be referred to as cathode electrodes or second electrodes.

[0191] The first capping layer CAP1 can be placed on the common electrode CE.

[0192] A light-blocking layer BM, a first light conversion layer QDL1, a second light conversion layer QDL2, and a light-transmitting layer TPL can be disposed on a first capping layer CAP1. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL can be formed by separating the light-blocking layer BM. Therefore, the first light conversion layer QDL1 can be disposed on the first capping layer CAP1 in the first sub-pixel SPX1, the second light conversion layer QDL2 can be disposed on the first capping layer CAP1 in the second sub-pixel SPX2, and the light-transmitting layer TPL can be disposed on the first capping layer CAP1 in the third sub-pixel SPX3. The light-blocking layer BM may not overlap with any of the multiple light-emitting elements LE.

[0193] The first light conversion layer QDL1 can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element LE into first light (light in the red wavelength band). The first light conversion layer QDL1 may include a first base resin BRS1 and first wavelength conversion particles WCP1. The first base resin BRS1 may include a light-transmitting organic material. The first wavelength conversion particles WCP1 can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element LE into first light (light in the red wavelength band).

[0194] The second light conversion layer QDL2 can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element LE into second light (light in the green wavelength band). The second light conversion layer QDL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 may include a light-transmitting organic material. The second wavelength conversion particles WCP2 can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element LE into second light (light in the green wavelength band).

[0195] The light-transmitting layer (TPL) may include light-transmitting organic materials.

[0196] For example, the first base resin BRS1, the second base resin BRS2, ​​and the light-transmitting layer TPL may include epoxy-based resins, acrylic-based resins, calorie-based resins, or imide-based resins. The first wavelength conversion particle WCP1 and the second wavelength conversion particle WCP2 may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials.

[0197] The light-blocking layer BM may include a first light-blocking layer BM1 and a second light-blocking layer BM2 stacked sequentially. The length of the first light-blocking layer BM1 in the first direction DR1 or the length in the second direction DR2 may be greater than the length of the second light-blocking layer BM2 in the first direction DR1 or the second direction DR2. The first light-blocking layer BM1 and the second light-blocking layer BM2 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. The first light-blocking layer BM1 and the second light-blocking layer BM2 may include a light-blocking material to prevent light from the light-emitting element LE from one sub-pixel from propagating to adjacent sub-pixels. For example, the first light-blocking layer BM1 and the second light-blocking layer BM2 may include an inorganic black pigment such as carbon black or an organic black pigment.

[0198] The second capping layer CAP2 can be disposed on the first capping layer CAP1 and the light blocking layer BM. The second capping layer CAP2 can be disposed on the side and top surface of the light blocking layer BM. That is, the second capping layer CAP2 can be disposed on the side of the first light blocking layer BM1 and on the side and top surface of the second light blocking layer BM2.

[0199] The second reflective layer RF2 can be disposed between the light-blocking layer BM and the first light conversion layer QDL1, between the light-blocking layer BM and the second light conversion layer QDL2, and between the light-blocking layer BM and the light-transmitting layer TPL. The second reflective layer RF2 can be disposed on the side of the first light-blocking layer BM1 and the side of the second light-blocking layer BM2, on the second capturing layer CAP2. The second reflective layer RF2 is used to reflect light propagating laterally from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL.

[0200] The second reflective layer RF2 may include a highly reflective metallic material, such as aluminum (Al). The thickness of the second reflective layer RF2 may be approximately 0.1 μm.

[0201] Optionally, the second reflective layer RF2 may comprise M pairs of the first and second layers with different refractive indices (M is an integer of 2 or greater) to function as a distributed Bragg reflector (DBR). In this case, the M first layers and M second layers may be arranged alternately. The first and second layers may be formed of inorganic films (e.g., silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide).

[0202] The third capping layer CAP3 can be disposed on the second capping layer CAP2, the second reflective layer RF2, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL.

[0203] The first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3 can be formed from inorganic films such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL can be encapsulated by the first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3.

[0204] A fourth organic membrane 193 may be disposed on the third capping layer CAP3. Multiple color filters CF1, CF2, and CF3 may be disposed on the fourth organic membrane 193. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0205] The first color filter CF1, disposed in the first sub-pixel SPX1, can transmit first light (light in the red wavelength band) and absorb or block third light (light in the blue wavelength band). Therefore, the first color filter CF1 can transmit the first light (light in the red wavelength band) that has been converted by the first light conversion layer QDL1 from the third light (light in the blue wavelength band) emitted from the light-emitting element LE, and absorb or block the third light (light in the blue wavelength band) that has not been converted by the first light conversion layer QDL1. Therefore, the first sub-pixel SPX1 can emit the first light (light in the red wavelength band).

[0206] The second color filter CF2, disposed in the second sub-pixel SPX2, can transmit second light (light in the green wavelength band) and absorb or block third light (light in the blue wavelength band). Therefore, the second color filter CF2 can transmit the second light (light in the green wavelength band) emitted from the light-emitting element LE that has been converted by the second light conversion layer QDL2, and absorb or block the third light (light in the blue wavelength band) that has not been converted by the second light conversion layer QDL2. Thus, the second sub-pixel SPX2 can emit second light (light in the green wavelength band).

[0207] The third color filter CF3, located in the third sub-pixel SPX3, can transmit third light (light in the blue wavelength band). Therefore, the third color filter CF3 can transmit third light (light in the blue wavelength band) emitted from the light-emitting element LE that passes through the light-transmitting layer TPL. Thus, the third sub-pixel SPX3 can emit third light (light in the blue wavelength band).

[0208] The first color filter CF1, the second color filter CF2, and the third color filter CF3, which are superimposed on the third-direction DR3, can overlap with the light-blocking layer BM on the third-direction DR3.

[0209] The fifth organic membrane 194 can be disposed on multiple color filters CF1, CF2 and CF3 for planarization.

[0210] The fourth organic membrane 193 and the fifth organic membrane 194 can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0211] According to an embodiment, the second protective layer INS2 is configured to cover at least one end of the contact electrode CTE to prevent short circuit between the pixel electrode PXE and the common electrode CE.

[0212] Figure 10 This is a layout diagram showing the pixels of a display area according to one embodiment.

[0213] Figure 10 Implementation methods and Figure 5 The difference in the implementation is that the first sub-pixel SPX1 further includes a first common electrode CE1, the second sub-pixel SPX2 further includes a second common electrode CE2, the third sub-pixel SPX3 further includes a third common electrode CE3, and the light-emitting element LE is a flip-chip microLED. Figure 10 In the implementation method, omission and Figure 5 The descriptions of the implementation methods overlap.

[0214] refer to Figure 10Each of the pixel electrodes PXE1, PXE2, and PXE3, and the common electrodes CE1, CE2, and CE3, can have a rectangular planar shape. The area of ​​the first pixel electrode PXE1 can be the same as the area of ​​the first common electrode CE1, the area of ​​the second pixel electrode PXE2 can be the same as the area of ​​the second common electrode CE2, and the area of ​​the third pixel electrode PXE3 can be the same as the area of ​​the third common electrode CE3, but the embodiments of this disclosure are not limited thereto.

[0215] In the first sub-pixel SPX1, the first pixel electrode PXE1 and the first common electrode CE1 can be arranged to be spaced apart in the second direction DR2. In the second sub-pixel SPX2, the second pixel electrode PXE2 and the second common electrode CE2 can be arranged to be spaced apart in the second direction DR2. In the third sub-pixel SPX3, the third pixel electrode PXE3 and the third common electrode CE3 can be arranged to be spaced apart in the second direction DR2.

[0216] The first common electrode CE1 can be connected to the second power line VSL, and the second supply voltage VSS is applied to the second power line VSL through the first common connection hole CT4. The second common electrode CE2 can be connected to the second power line VSL through the second common connection hole CT5. The third common electrode CE3 can be connected to the second power line VSL through the third common connection hole CT6. Therefore, the second supply voltage VSS can be applied to each of the common electrodes CE1, CE2, and CE3.

[0217] Figure 11 It shows the corresponding Figure 10 A cross-sectional view of an example of the display panel section along line I2-I2'. Figure 12 It is shown in detail Figure 11 A cross-sectional view of an example of region B in the diagram.

[0218] Figure 11 and Figure 12 Implementation methods and Figure 6 and Figure 7 The difference in implementation is that the light-emitting element LE is a flip-chip microLED. Figure 11 and Figure 12 In the implementation method, omission and Figure 6 and Figure 7 The descriptions of the implementation methods overlap.

[0219] refer to Figure 11 and Figure 12 The light-emitting element LE can be a flip-chip microLED. A flip-chip microLED is an LED in which contact electrodes CTE1 and CTE2 are formed on one side (e.g., the bottom side) of the light-emitting element LE.

[0220] A pixel electrode layer, including pixel electrodes PXE1, PXE2 and PXE3 and common electrodes CE1, CE2 and CE3, can be disposed on the second organic film 180.

[0221] Each of the light-emitting elements (LEs) may include a current spreading layer (CSL), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a third semiconductor layer (USE), and a shell layer (OSL). In one embodiment, the current spreading layer (CSL) may be omitted from each of the light-emitting elements (LEs). In one embodiment, each of the light-emitting elements (LEs) may also include contact electrodes (CTE1 and CTE2). For example, the first contact electrode (CTE1) may be electrically connected to the current spreading layer (CSL), and the second contact electrode (CTE2) may also include a second contact electrode (CTE2) that contacts the first contact electrode (CTE1) and the second semiconductor layer (SEM2). In one embodiment, when the current spreading layer (CSL) is omitted, the first contact electrode (CTE1) may be electrically connected to the first semiconductor layer (SEM1).

[0222] The light-emitting element (LE) has a trench HCTE on one surface that passes through a current spreading layer (CSL), a first semiconductor layer (SEM1), and an active layer (MQW), and exposes a second semiconductor layer (SEM2). A second contact electrode (CTE) can be connected to the second semiconductor layer (SEM2) via the trench HCTE defined to pass through the current spreading layer (CSL), the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2).

[0223] The outer shell layer OSL can be disposed on one side and the side surface of the component rod LD. The outer shell layer OSL may include a first protective layer INS1, a first reflective layer RF1, and a second protective layer INS2.

[0224] The first protective layer INS1 may include a first opening OP1 and a second opening OP2 on one side of the first component rod LD1. The first opening OP1 and the second opening OP2 may be arranged spaced apart from each other. The first opening OP1 may be located on one side of the first component rod LD1, and the second opening OP2 may be arranged to overlap with the bottom of the trench HCTE. For example, the second semiconductor layer SEM2 may be exposed through the second opening OP2 of the first protective layer INS1 that overlaps with the trench HCTE.

[0225] The first reflective layer RF1 may include a 1-1 reflective layer RF1-1 and a 1-2 reflective layer RF1-2. Furthermore, the ends of the 1-1 reflective layer RF1-1 and the 1-2 reflective layer RF1-2 may be spaced apart from each other. The 1-1 reflective layer RF1-1 and the 1-2 reflective layer RF1-2 are not electrically connected.

[0226] In one embodiment, the 1-1 reflective layer RF1-1 may be disposed on the current spreading layer CSL exposed through the first opening OP1 of the first protective layer INS1. The 1-1 reflective layer RF1-1 is electrically connected to the current spreading layer CSL.

[0227] In one embodiment, the 1-2 reflective layer RF1-2 may be disposed on the second semiconductor layer SEM2 exposed through the second opening OP2 of the first protective layer INS1 and extend to the side of the trench HCTE. The 1-2 reflective layer RF1-2 (e.g., via the second contact electrode CTE2) is electrically connected to the second semiconductor layer SEM2.

[0228] In one embodiment, the first contact electrode CTE1 may be disposed on the pixel electrode PXE of each sub-pixel SPX (e.g., an organic pattern layer 210 is interposed therebetween). For example, in one embodiment, the first contact electrode CTE1 may be disposed between the pixel electrode PXE of each sub-pixel SPX and the light-emitting element LE.

[0229] A first contact electrode CTE1 is disposed on a first reflective layer RF1 to follow the first reflective layer RF1, such as a 1-1 reflective layer RF1-1. One end of the first contact electrode CTE1 is disposed on one surface of the light-emitting element LE and is electrically connected to the current spreading layer CSL through a first opening OP1. In an embodiment, the 1-1 reflective layer RF1-1 can be electrically connected to the current spreading layer CSL through the first contact electrode CTE1 on the first opening OP1. One end of the first contact electrode CTE1 extends along one side of the light-emitting element LE and can be configured to cover the 1-1 reflective layer RF1-1.

[0230] The first contact electrode CTE1 can electrically connect the first semiconductor layer SEM1 of the light-emitting element LE to the pixel electrode PXE of each sub-pixel SPX via the first connection electrode BE1, which will be described later.

[0231] In one embodiment, the second contact electrode CTE2 can be disposed on the common electrode CE of each sub-pixel SPX (e.g., an organic pattern layer 210 is interposed therebetween). For example, in one embodiment, the second contact electrode CTE2 can be disposed between the common electrode CE of each sub-pixel SPX and the light-emitting element LE. The second contact electrode CTE2 is disposed on the first reflective layer RF1 to follow the first reflective layer RF1, such as a 1-2 reflective layer RF1-2. One end of the second contact electrode CTE2 can be disposed on one surface of the light-emitting element LE and extend to the side of the slot HCTE. The second contact electrode CTE2 is electrically connected to the second semiconductor layer SEM2 through the second opening OP2. In one embodiment, the 1-2 reflective layer RF1-2 can be electrically connected to the second semiconductor layer SEM2 through the second contact electrode CTE2 on the second opening OP2. One end of the second contact electrode CTE2 extends along one side of the light-emitting element LE and can be configured to cover the 1-2 reflective layer RF1-2.

[0232] Furthermore, one end of the first contact electrode CTE1 and the second contact electrode CTE2 can be spaced apart from each other. The first contact electrode CTE1 and the second contact electrode CTE2 are not electrically connected.

[0233] The second contact electrode CTE2 can connect the second semiconductor layer SEM2 of the light-emitting element LE to the common electrode CE of each sub-pixel SPX via the second connection electrode BE2.

[0234] The first contact electrode CTE1 and the second contact electrode CTE2 may comprise a metal, metal oxide, and / or another conductive material having a higher conductivity than the first reflective layer RF1. For example, the first contact electrode CTE1 and the second contact electrode CTE2 may comprise gold (Au), copper (Cu), and / or chromium (Cr).

[0235] The second protective layer INS2 can be disposed on at least a portion of the side surface of the element rod LD. For example, the second protective layer INS2 can be disposed on the side surfaces of the second element rod LD2 and the third element rod LD3, and can extend from the side surface of the third element rod LD3, and can be disposed at least partially on one side of the third element rod LD3. For example, the second protective layer INS2 can be disposed partially along the uneven portion of the third element rod LD3. Therefore, the contact area CTA between the third element rod LD3 and the common electrode CE in the plane can be smaller than the area LD3A of the third element rod LD3. Furthermore, in the plane (e.g., in a planar view), the area LEA of the third element rod LD3 can be the same as the area LEA of the light-emitting element LE, so the contact area CTA can be smaller than the area LEA of the light-emitting element LE.

[0236] The second protective layer INS2 can cover and protect one end of the first contact electrode CTE1 and one end of the second contact electrode CTE2.

[0237] The connecting electrode BE may include a first connecting electrode BE1 and a second connecting electrode BE2.

[0238] The first connecting electrode BE1 connects the first contact electrode CTE1 to one of the pixel electrodes PXE1, PXE2, and PXE3. Furthermore, the first connecting electrode BE1 can be disposed on the top and side surfaces of the organic pattern layer 210. Additionally, the first connecting electrode BE1 can be disposed on a portion of the side surface of the light-emitting element LE on the first contact electrode CTE1. For example, the first connecting electrode BE1 can be disposed on a portion of the first contact electrode CTE1.

[0239] The second connecting electrode BE2 connects the second contact electrode CTE2 to one of the common electrodes CE1, CE2, and CE3. Furthermore, the second connecting electrode BE2 can be disposed on the top and side surfaces of the organic patterned layer 210. Alternatively, the second connecting electrode BE2 can be disposed on a portion of the side surface of the light-emitting element LE on the second contact electrode CTE2. For example, the second connecting electrode BE2 can be disposed on a portion of the second contact electrode CTE2.

[0240] Each of the first connecting electrode BE1 and the second connecting electrode BE2 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu). Optionally, each of the first connecting electrode BE1 and the second connecting electrode BE2 may be made of a transparent conductive material (TCO) capable of transmitting light, such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0241] Figure 13 This is a flowchart illustrating a method for manufacturing a display device according to one embodiment. Figures 14 to 29 This is a cross-sectional view showing a method of manufacturing a display device according to one embodiment.

[0242] Figures 14 to 29 The structure is shown as a cross-sectional view according to the formation order of each layer of the display device. Figures 14 to 29 The light-emitting element and the light-emitting element layer are mainly shown. Figure 6 The formation of LEL in the text can be roughly divided into two categories: Figure 7 The sectional view in the text. In the following text, it will be combined with... Figure 13 describe Figures 14 to 29 The method for manufacturing a display device is shown.

[0243] refer to Figure 14Multiple semiconductor material layers, namely USEL, SEM2L, MQWL, and SEM1L, and a current spreading material layer, CSLL, are stacked and patterned on a growth substrate BSUB to form a multi-layer semiconductor stack. Figure 13 (S110 in the middle)

[0244] First, a growth substrate BSUB is prepared. The growth substrate BSUB can be a sapphire substrate (Al2O3) or a silicon wafer comprising silicon. However, the invention is not limited thereto, and in one embodiment, the case where the growth substrate BSUB is a sapphire substrate is described as an example.

[0245] Multiple semiconductor material layers, SEM3L, SEM2L, SLTL, MQML, EBLL, and SEM1L, are formed on a growth substrate BSUB. Multiple semiconductor material layers can be formed by epitaxial growth using seed crystals. Methods for forming semiconductor material layers include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), type-two thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), etc., and are preferably formed by MOCVD. However, it is not limited to these methods.

[0246] Within the range of conventionally selectable materials used to form the subject material, there are no particular limitations on the precursor materials used to form multiple semiconductor material layers. In one example, the precursor material may be a metal precursor comprising alkyl groups such as methyl or ethyl groups. For example, it may be a compound such as trimethylgallium (Ga(CH3)3), trimethylaluminum (Al(CH3)3), or triethyl phosphate ((C2H5)3PO4), but is not limited thereto.

[0247] Specifically, a third semiconductor material layer USEL is formed on the growth substrate BSUB. Although the accompanying drawings show a further stacked third semiconductor material layer USEL, the process is not limited to this, and multiple layers can be formed. The third semiconductor material layer USEL can be disposed on the uneven structure of the growth substrate BSUB. Therefore, an uneven portion is also formed on one surface of the third semiconductor layer USEL that contacts the uneven structure of the growth substrate BSUB. The uneven structure of the third semiconductor layer USEL corresponds to the uneven structure of the growth substrate BSUB. For example, an upwardly convex uneven portion is formed on one surface of the third semiconductor layer USEL that contacts an upwardly convex uneven portion of the growth substrate BSUB. The uneven portion can be one of, but is not limited to, a hemispherical shape, a conical shape, a truncated cone shape, a pyramidal shape, a truncated pyramidal shape, and a cylindrical shape.

[0248] The third semiconductor material layer USEL can be configured to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the growth substrate BSUB. For example, the third semiconductor material layer USEL may include an undoped semiconductor, which may be an n-type or p-type undoped material. In embodiments, the third semiconductor material layer USEL may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0249] Using the method described above, a second semiconductor material layer SEM2L, an active material layer MQWL, and a first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer USEL. In another modified example, a superlattice material layer can be formed between the second semiconductor material layer SEM2L and the active material layer MQWL. Furthermore, an electron blocking material layer can be formed between the active material layer MQWL and the first semiconductor material layer SEM1L. A current spreading material layer CSLL can be further formed on the first semiconductor material layer SEM1L. The current spreading material layer CSLL can be made of a light-transmitting transparent metal material (TCO), such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0250] refer to Figure 15 The active material layer MQWL and the first semiconductor material layer SEM1L can be etched using a first mask to form a first element rod LD1 with a first tilt angle θ1. Figure 13 (S120 in the middle)

[0251] For example, a first mask is used to dry-etch at least the current spreading layer CSL, the first semiconductor material layer SEM1L, and the active material layer MQWL. At this point, a portion of the second semiconductor layer SEM2 can be further etched.

[0252] During dry etching, as the etching depth increases, the processing time increases, and the plasma exposure time of the semiconductor material layers increases, which may increase damage to the active layer. Therefore, in this embodiment, instead of etching the first semiconductor material layer SEM1L, the active material layer MQWL, the second semiconductor material layer SEM2L, and the third semiconductor material layer USEL all at once, only a portion corresponding to approximately 1 / 10 of the total semiconductor material layers—the current spreading material layer CSLL, the first semiconductor material layer SEM1L, the active material layer MQWL, and the second semiconductor material layer SEM2L—is etched. This reduces or minimizes damage to the active layer. Subsequent wet etching can then be performed.

[0253] refer to Figure 16 and Figure 17A second mask can be used to etch the second semiconductor material layer SEM2L and the third semiconductor material layer USEL to form a second element rod LD2' with a second tilt angle θ2. Figure 13 (S130 in the middle).

[0254] For example, refer to Figure 16 A dielectric material such as ZAZ (ZrO2 / Al2O3 / ZrO2) is applied to the first element rod LD1 for winding.

[0255] Then, the second element rod LD2 is formed using a photolithography process. The photolithography process involves applying a photoresist (PR) to a substrate and passing light through a mask with the desired pattern to form the desired structure. For example, the photoresist PR2 can be formed as a coil wrapped around the first element rod LD1. The photoresist PR2 can have the shape of a square pillar whose width narrows towards the top. The tilt angle θM of the photoresist PR2 can be greater than 60 degrees and less than or equal to 80 degrees.

[0256] A second mask is used to pattern the second semiconductor material layer SEM2L and the third semiconductor material layer USEL. For example, the second semiconductor material layer SEM2L and the third semiconductor material layer USEL can be formed into the second semiconductor layer SEM2 and the third semiconductor layer USEL using a dry etching process. Depending on the shape of the photoresist PR, the width can increase from the second semiconductor layer SEM2 to the third semiconductor layer USEL. The tilt angle of the second element rod LD2 can be formed to correspond to the tilt angle θM of the photoresist PR, being greater than 60 degrees and less than or equal to 80 degrees. Through this process, each light-emitting element can be separated from each other.

[0257] refer to Figures 18 to 20 This can form a first protective layer INS1 covering the third semiconductor layer USE, the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1, and the current spreading layer CSL, as well as a first reflective layer RF1 covering the third semiconductor layer USE, the second semiconductor layer SEM2, and the active layer MQW. Figure 13 (S140 in the middle)

[0258] For example, refer to Figure 18 A first protective material layer INS1L is formed on the growth substrate BSUB to cover the first element rod LD1, the second semiconductor layer SEM2, and the third semiconductor layer USE. The first protective material layer INS1L can be formed as an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not limited thereto.

[0259] refer to Figure 19A first reflective material layer is formed on the first protective material layer INS1L to cover the first element rod LD1, the second semiconductor layer SEM2, and the third semiconductor layer USE. The first reflective material layer can be deposited by processes such as sputtering, but is not limited thereto.

[0260] Next, the first reflective layer RF1 can be formed by etching a portion of the first reflective material layer using a third mask via a photolithography process. For example, the first reflective material layer disposed on the third semiconductor layer USE can be removed. A wet etching process can be used to etch the first reflective material layer, but it is not limited to this.

[0261] refer to Figure 20 A portion of the first reflective layer RF1 is etched onto the top surface of the first element rod LD1 using a fourth mask, and one or more openings OP1 and OP2 overlapping the first protective material layer INS1L can be formed using the reflective layer RF1 as a mask. The first opening OP1 and the second opening OP2 can be formed to be spaced apart from each other. The openings OP1 and OP2 can be formed by a dry etching process, but are not limited thereto.

[0262] In this process, a portion of the top surface of the current spreading layer (CSL) can be exposed.

[0263] refer to Figures 21 to 23 Forming the contact electrode CTE and the third element rod LD3 ( Figure 13 (S150 in the middle).

[0264] For example, refer to Figure 21 A conductive material layer CTEL is formed on the entire surface of a multi-layer semiconductor stack and a growth substrate BSUB. The conductive material layer CTEL can be deposited by processes such as sputtering, but is not limited to these.

[0265] refer to Figure 22 The contact electrode CTE is formed by etching a portion of the conductive material layer CTEL using a fifth mask. For example, a photoresist is formed to cover the entire conductive material layer CTEL to be the contact electrode CTE, and the portion of the conductive material layer CTEL not covered by the photoresist is etched using a fifth mask to form the contact electrode CTE. One end of the contact electrode CTE can be formed to have a minimum length that completely covers the first reflective layer RF1. One end of the contact electrode CTE is spaced apart from the growth substrate BSUB. The photoresist can be removed by an ashing process, but is not limited to this.

[0266] Next, the third element rod LD3 is formed using the contact electrode CTE as a mask. The portion without the contact electrode CTE becomes the third element rod LD3, and the second element rod surrounded by the contact electrode CTE ( Figure 21The portion of LD2' becomes the second element rod LD2. The sides of the contact electrode CTE and the third element rod LD3 can be aligned and matched with each other.

[0267] In other implementations, a separate mask can be used instead of the contact electrode CTE as a mask. When using a separate mask, such as... Figure 9 As described, one end of the contact electrode and the side surface of the third element rod LD3 may have a step difference.

[0268] Figure 23 yes Figure 22 A magnified view of region C. (e.g.) Figure 23 As shown, in the wet etching process for forming the third element rod LD3, a partial gap may form between the growth substrate BSUB and the third semiconductor layer USE at the edge of the third semiconductor layer USE. The extent of gap widening can be adjusted by the wet etching time and etching material.

[0269] In one implementation, the contact area between the third semiconductor layer USE and the growth substrate BSUB is reduced by forming a gap between the growth substrate BSUB and the third semiconductor layer USE, which requires less energy in the subsequent laser lift-off (LLO) process for separating the growth substrate BSUB.

[0270] refer to Figure 24 and Figure 25 This forms a second protective layer, INS2. Figure 13 (S160 in the middle).

[0271] refer to Figure 24 A second protective material layer INS2L is applied to the entire growth substrate BSUB. Sputtering methods can be used for application, but are not limited to this. When forming the second protective material layer INS2L, it can be used to fill the gap between the growth substrate BSUB and the third semiconductor layer USE.

[0272] refer to Figure 25 A portion of the second protective material layer INS2L is selectively etched to form the second protective layer INS2.

[0273] For example, a sixth mask can be used to etch a second protective material layer INS2L disposed on the top and side surfaces of the first element rod LD1 to form a second protective layer INS2 disposed on the side surface of the second element rod LD2, the side surface of the third element rod LD3, and at least a portion of the third element rod LD3 and the growth substrate BSUB.

[0274] refer to Figure 26 and Figure 27The light-emitting element (LE) is transferred to the pixel electrode (PXE) on the circuit board. Figure 13 (S170 in the middle)

[0275] Will Figure 26 The light-emitting element (LE) of the growth substrate BSUB fabricated in the process is transferred to the target substrate. In one embodiment, for ease of illustration, the target substrate is described as a circuit board, but it is not limited thereto. For example, the target substrate may be a relay substrate.

[0276] The light-emitting element LE of the growth substrate BSUB is aligned at the desired location on the target substrate. For example, an organic pattern layer 210 is formed on the pixel electrode PXE, and the light-emitting element LE is disposed on the organic pattern layer 210.

[0277] The organic pattern layer 210 can be a photosensitive organic layer such as a photoresist. Optionally, the organic pattern layer 210 can be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. The thickness of the organic pattern layer 210 can be thicker than the thickness of the pixel electrode layer.

[0278] A portion of the light-emitting element (LE) disposed on the organic pattern layer 210 can be temporarily fixed by embedding it in the organic pattern layer 210. For example, a portion of the contact electrode (CTE) of multiple light-emitting elements (LEs) can be embedded and fixed in the organic pattern layer 210.

[0279] Thus, when the organic pattern layer 210 is a photosensitive organic layer such as a photoresist, at least a portion of each of a plurality of light-emitting elements LEs can be inserted into the organic pattern layer 210 after soft baking at a first temperature. The organic pattern layer 210 can then be fully cured at a second temperature higher than the first temperature. The first temperature can be approximately 100 degrees Celsius, and the second temperature can be approximately 230 degrees Celsius, but embodiments of this disclosure are not limited thereto. In the first curing, the first temperature is insufficient to fully cure the organic pattern layer 210, so the organic pattern layer 210 can have fluidity. On the other hand, a second curing is performed at the second temperature for approximately 30 minutes, and the organic pattern layer 210 can be fully cured. The fully cured organic pattern layer 210 does not have fluidity. The light-emitting elements LEs embedded when they have fluidity after the initial curing can be fully fixed to the organic pattern layer 210 after the second curing.

[0280] Then, the light-emitting elements (LEs) can be separated from the growth substrate (BSUB). The growth substrate (BSUB) is separated from each of the third semiconductor layers (USE) of the multiple light-emitting elements (LEs).

[0281] Laser lift-off (LLO) can be used to separate the grown substrate BSUB. LLO uses a laser, and a KrF excimer laser (248 nm wavelength) can be used as the source. The excimer laser operates at approximately 550 mJ / cm². 2 Up to 950mJ / cm 2 Irradiation can be carried out within a range of energy densities, and the incident area can range from 50×50μm² to 1×1cm². 2 Within, but not limited to, the growth substrate BSUB can be separated from the light-emitting element LE by irradiating the growth substrate BSUB with a laser.

[0282] In this way, after the stripping process, a cleaning process can be performed to remove contaminants from the light-emitting element. For example, Cl2 can be used in the cleaning process, in which HCl or the like may be formed. In this way, even if HCl is formed, the reflective layer RF1 will not be exposed in the light-emitting element LE according to one embodiment, thus minimizing damage to the reflective layer RF1. For example, if one end of the reflective layer RF1, made of aluminum (Al), silver (Ag), or the like, is exposed, not only the exposed reflective layer but also a large portion of the reflective layer may be damaged due to penetration of the exposed reflective layer.

[0283] Subsequently, refer to Figure 28 and Figure 29 This forms the connecting electrode BE and the common electrode CE. Figure 13 (S180 in the middle).

[0284] For example, refer to Figure 28 After forming a conductive material layer on the circuit board, a portion of the conductive material layer can be removed using a photolithography process to form the connection electrode BE connecting the contact electrode CTE of the light-emitting element LE and the pixel electrodes PXE1, PXE2, and PXE3. The connection electrode BE is formed on the contact electrode CTE, and the second protective layer INS2 and the connection electrode BE can be on the side of the light-emitting element LE without overlapping each other.

[0285] The connecting electrode BE can be used as a bonding metal for bonding the pixel electrode PXE and the light-emitting element LE.

[0286] refer to Figure 29 A third organic layer 190 is formed on a growth substrate BSUB on which no light-emitting elements LE are disposed. The third organic layer 190 can fill the space between the light-emitting elements LE and can be formed to cover the side surfaces of the light-emitting elements LE. The third organic layer 190 can be formed below the height of the light-emitting elements LE. Therefore, the top surface of the light-emitting elements LE can be exposed.

[0287] The common electrode CE covers the light-emitting element LE and the third organic layer 190, and can be formed to be in direct contact with them. The common electrode CE can be formed continuously throughout the display area. The common electrode CE can be formed along an irregular portion of the top surface of the third semiconductor SEM3 of the light-emitting element LE.

[0288] Figure 30 This is an exemplary view of a smartwatch that includes a display device according to an embodiment.

[0289] refer to Figure 30 The display device 10_1 according to the embodiment can be applied to a smartwatch 1000_1, which is a type of smart device.

[0290] Figure 31 and Figure 32 This is an exemplary view of a virtual reality (VR) device that includes a display device according to an embodiment.

[0291] refer to Figure 31 and Figure 32 According to the embodiment, the head-mounted display device 1000_2 includes a first display device 10_2, a second display device 10_3, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0292] The first display device 10_2 provides an image to the user's left eye, and the second display device 10_3 provides an image to the user's right eye. Each of the first display device 10_2 and the second display device 10_3 is substantially aligned with a reference. Figure 1 and Figure 2 The display device 10 described is the same. Therefore, the description of the first display device 10_2 and the second display device 10_3 will be omitted.

[0293] The first optical component 1510 may be disposed between the first display device 10_2 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_3 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0294] The intermediate frame 1400 can be disposed between the first display device 10_2 and the control circuit board 1600, and can also be disposed between the second display device 10_3 and the control circuit board 1600. The intermediate frame 1400 supports and fixes the first display device 10_2, the second display device 10_3, and the control circuit board 1600.

[0295] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_2 and the second display device 10_3 via connectors. The control circuit board 1600 can convert image sources received from external sources into digital video data DATA, and transmit the digital video data DATA to the first display device 10_2 and the second display device 10_3 via connectors.

[0296] The control circuit board 1600 can transmit digital video data DATA corresponding to a left image optimized for the user's left eye to the first display device 10_2, and digital video data DATA corresponding to a right image optimized for the user's right eye to the second display device 10_3. Optionally, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_2 and the second display device 10_3.

[0297] The display device housing 1100 houses a first display device 10_2, a second display device 10_3, an intermediate frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is positioned to cover the opening surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for placing the user's left eye and a second eyepiece 1220 for placing the user's right eye. Although in Figure 33 and Figure 34 The first eyepiece 1210 and the second eyepiece 1220 are provided separately, but the embodiments described in this specification are not limited to this. The first eyepiece 1210 and the second eyepiece 1220 can also be combined into one.

[0298] The first eyepiece 1210 can be aligned with the first display device 10_2 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_3 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_2 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_3 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0299] The headband 1300 secures the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively positioned over the user's left and right eyes. When the display device housing 1200 is made lightweight and compact, the head-mounted display device 1000_2 may include, for example... Figure 33 The eyeglass frame shown is not the headband 1300.

[0300] In addition, the head-mounted display device 1000_2 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0301] Figure 33 This is an exemplary view of a VR device including a display device according to an embodiment. Figure 33 A VR device 1000_3, which has been equipped with a display device 10_4 according to an embodiment, is shown.

[0302] refer to Figure 33 The VR device 1000_3 according to the embodiment can be a device in the form of glasses. The VR device 1000_3 according to the embodiment may include a display device 10_4, a left lens 10a, a right lens 10b, a support frame 20, eyeglass temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0303] exist Figure 33 The example shown is a glasses-type display device including temples 30a and 30b. That is, the VR device 1000_3 according to the embodiment is not limited to... Figure 35 The device shown can be applied in various forms to various other electronic devices.

[0304] The display device housing 50 may include a display device 10_4 and a reflective member 40. The image displayed on the display device 10_4 can be reflected by the reflective member 40 and provided to the user's right eye through the right lens 10b. Therefore, the user can view the VR image displayed on the display device 10_4 through their right eye.

[0305] Despite Figure 33 The display device housing 50 is located at the right end of the support frame 20, but the embodiments described herein are not limited to this. For example, the display device housing 50 may also be located at the left end of the support frame 20. In this case, the image displayed on the display device 10_4 can be reflected by the reflective member 40 and provided to the user's left eye through the left lens 10a. Therefore, the user can view the VR image displayed on the display device 10_4 through their left eye. Alternatively, the display device housing 50 may be located at both the right and left ends of the support frame 20. In this case, the user can view the VR image displayed on the display device 10_4 through both their left and right eyes.

[0306] Figure 34This is an exemplary view showing a vehicle instrument cluster and a central dashboard including a display device according to an embodiment. Figure 34 Vehicles in which display devices 10_a to 10_e according to embodiments have been applied are shown.

[0307] refer to Figure 34 The display devices 10_a to 10_c according to the embodiments can be applied to the instrument cluster of a vehicle, the central instrument panel of a vehicle, or the central information display (CID) installed on the instrument panel of a vehicle. Furthermore, the display devices 10_d and 10_e according to the embodiments can be applied to interior mirror displays that replace the side mirrors of a vehicle.

[0308] Figure 35 This is an exemplary view of a transparent display device including a display device according to an embodiment.

[0309] refer to Figure 35 The display device 10_5 according to the embodiment can be applied to a transparent display device. A transparent display device can transmit light while displaying an image IM. Therefore, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10_5, but also view the object RS or background located behind the transparent display device. When the display device 10_5 is applied to a transparent display device, the substrate of the display device 10_5 may include a light-transmitting portion, or may be made of a light-transmitting material.

Claims

1. A display device, comprising: Substrate, with pixel electrodes located on the substrate; A light-emitting element is provided on the pixel electrode, and includes an element rod and contact electrodes on one side and the side of the element rod; Connecting electrodes, electrically connecting the contact electrodes and the pixel electrodes; as well as The common electrode is located on the light-emitting element. The component rod includes: The first element bar includes a first semiconductor layer and an active layer and has a side having a first tilt angle; The second element rod is on the first element rod and has a side surface with a second tilt angle; and The third element rod is on the second element rod and has a side with a third tilt angle. The light-emitting element further includes: A first protective layer is provided on one and the sides of the first component rod and on the side of the second component rod. A reflective layer, on the first protective layer, and on one and the sides of the first element rod and on the sides of the second element rod; and The second protective layer is located on the side surface of the second element rod, the side surface of the third element rod, and the edge of the top surface of the third element rod.

2. The display device according to claim 1, wherein, The contact electrode is on one side of the first element rod on the reflective layer and extends to the side of the first element rod and the side of the second element rod.

3. The display device according to claim 1, wherein, The contact electrode is located on the side of the second element rod between the reflective layer and the second protective layer. Wherein, on the side of the second element rod, one end of the reflective layer is surrounded by the first protective layer and the contact electrode.

4. The display device according to claim 1, wherein, The first protective layer, the reflective layer, and the contact electrode are not on the side of the third element rod.

5. The display device according to claim 1, wherein, The third semiconductor layer of the element rod has an uneven structure.

6. The display device according to claim 5, wherein, The second protective layer extends from the side of the third element bar and is located at the edge of the uneven structure of the third semiconductor layer.

7. The display device according to claim 1, wherein, The second protective layer thins inward from the top surface of the third semiconductor layer of the component rod.

8. The display device according to claim 1, further comprising an organic pattern layer on the pixel electrode and on the lower surface of the light-emitting element. in, The connecting electrode is located on one side of the pixel electrode, the side of the organic pattern layer, and the side of the first contact electrode of the contact electrode of the light-emitting element.

9. The display device according to claim 1, wherein, The first protective layer has one or more openings defined on one side of the first element bar. The contact electrode is electrically connected to the element rod exposed by the opening.

10. The display device according to claim 1, wherein, The contact electrode has higher conductivity and lower reflectivity than the reflective layer.

11. The display device according to claim 1, wherein, The second tilt angle is smaller than the first tilt angle and the third tilt angle.

12. The display device according to claim 11, wherein, The second tilt angle is between 60 degrees and 80 degrees.

13. The display device according to claim 1, wherein, The width of the second element bar increases toward the third element bar, and the width of the third element bar is wider than the width of the first element bar.

14. A light-emitting element, comprising: The component rod, wherein a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer are stacked sequentially and divided into a first component rod, a second component rod and a third component rod according to the tilt angle; A first protective layer is provided on one and the sides of the first component rod and on the side of the second component rod. A reflective layer, on the first protective layer, and on one side and the side surface of the first element rod and on the side surface of the second element rod; A contact electrode is located on one side of the first element rod on the reflective layer and extends to the side of both the first and second element rods; and The second protective layer is located on the edge of the side surface of the second element rod, the side surface of the third element rod, and the top surface of the third element rod.

15. The light-emitting element according to claim 14, wherein, The third semiconductor layer has an uneven structure. The second protective layer is located at the edge of the uneven structure of the third semiconductor layer.

16. The light-emitting element according to claim 14, wherein, The second protective layer thins inward from the top surface of the third semiconductor layer.

17. The light-emitting element according to claim 14, wherein, The second tilt angle of the second element rod is smaller than the first tilt angle of the first element rod and the third tilt angle of the third element rod. The second tilt angle is between 60 degrees and 80 degrees.

18. A method of manufacturing a display device, comprising: A third semiconductor material layer, a second semiconductor material layer, an active material layer, and a first semiconductor material layer are formed on a growth substrate; A first element bar with a first tilt angle is formed by etching the active material layer and the first semiconductor material layer using a first mask; A second element bar with a second tilt angle is formed by etching the second semiconductor material layer and the third semiconductor material layer using a second mask. A first protective layer, a reflective layer, and a contact electrode are formed covering the third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer; A third element bar with a third tilt angle is formed by etching a portion of the second element bar using a third mask; and A second protective layer is formed on the side surface of the second element rod and the side surface of the third element rod. The second protective layer extends from the side of the third element rod and lies between the edge gap between the third element rod and the second protective layer.

19. The method of claim 18, further comprising: The light-emitting element, including the first element bar, the second element bar, and the third element bar, is transferred to a circuit board having pixel electrodes; as well as A connecting electrode is formed to connect the contact electrode and the pixel electrode.

20. The method according to claim 19, wherein, Transferring the light-emitting element to the circuit board having the pixel electrode includes: An organic patterned layer is formed on the pixel electrode as a pseudo-adhesive layer; and Multiple light-emitting elements are arranged on the organic pattern layer, and the light-emitting elements are fixed by curing the organic pattern layer.

Images