Integrated device comprising a metallized portion

Abstract

An integrated device includes: a die substrate; die interconnects coupled to the die substrate; an encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnects; a plurality of pad interconnects coupled to the die interconnects; and a plurality of metallized interconnects, wherein one or more metallized interconnects from the plurality of metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Nonprovisional Application Serial No. 18 / 611,416, filed March 20, 2024, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0003] Various features are involved in integrated devices. Background Technology

[0004] Integrated devices are configured to perform various electrical functions. The performance of an integrated device and how it performs these functions will depend on the arrangement of interconnects. There is a continuous need to improve the performance of integrated devices while simultaneously reducing their overall size. Summary of the Invention

[0005] Various features are involved in integrated devices.

[0006] One example provides an integrated device comprising: a die substrate; die interconnects coupled to the die substrate; an encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnects; a plurality of pad interconnects coupled to the die interconnects; and a plurality of metallized interconnects, wherein one or more metallized interconnects from the plurality of metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects.

[0007] Another example provides a package including a first integrated device comprising: a die substrate; die interconnects coupled to the die substrate; an encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnects; a plurality of pad interconnects coupled to the die interconnects; and a plurality of metallized interconnects, wherein one or more metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects; and a second integrated device coupled to the first integrated device via a plurality of solder interconnects.

[0008] Another example provides a device including a die substrate; die interconnects coupled to the die substrate; an encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnects; a plurality of pad interconnects coupled to the die interconnects; and a plurality of metallized interconnects, wherein one or more metallized interconnects from the plurality of metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects. Attached Figure Description

[0009] Various features, characteristics, and advantages may become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0010] Figure 1 A cross-sectional view of an exemplary integrated device is shown.

[0011] Figure 2 A cross-sectional view of an exemplary integrated device is shown.

[0012] Figure 3 A cross-sectional view of an exemplary integrated device is shown.

[0013] Figure 4 A cross-sectional plan view of an exemplary integrated device is shown.

[0014] Figure 5 A cross-sectional plan view of an exemplary integrated device is shown.

[0015] Figure 6 An exemplary plan view of the spoke configuration is shown.

[0016] Figure 7 An exemplary plan view of the spoke configuration is shown.

[0017] Figure 8 An exemplary plan view illustrating the arrangement of interconnects is shown.

[0018] Figure 9 An exemplary plan view illustrating the arrangement of interconnects is shown.

[0019] Figure 10 An exemplary plan view illustrating the arrangement of interconnects is shown.

[0020] Figure 11 A cross-sectional view of an exemplary integrated device is shown.

[0021] Figure 12 A cross-sectional view of an exemplary integrated device is shown.

[0022] Figures 13A to 13I An exemplary process for manufacturing integrated devices is illustrated.

[0023] Figure 14 An exemplary flowchart illustrating a method for manufacturing integrated devices is shown.

[0024] Figure 15 A cross-sectional plan view of an exemplary integrated device is shown.

[0025] Figure 16A cross-sectional plan view of an exemplary package including several integrated devices is shown.

[0026] Figures 17A to 17C An exemplary process for manufacturing a package that includes several integrated devices is illustrated.

[0027] Figure 18 An exemplary flowchart illustrating a method for manufacturing a package comprising several integrated devices is shown.

[0028] Figure 19 Examples are provided of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0029] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0030] This disclosure describes an integrated device comprising: a die substrate; die interconnects coupled to the die substrate; an encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnects; a plurality of pad interconnects coupled to the die interconnects; and a plurality of metallized interconnects, wherein one or more metallized interconnects from the plurality of metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects. In some embodiments, the integrated device provides a reduced and / or minimized number of metal layers for the metallized interconnects in a compact form factor, while providing improved performance for the integrated device.

[0031] Exemplary integrated device

[0032] Figure 1A cross-sectional view of an integrated device 100 is illustrated. The integrated device 100 includes a die-substrate base 102 and die interconnects 104. The die-substrate base 102 includes a die-substrate 120, an active region 122, and a plurality of through-substrate vias 121. The active region 122 and the plurality of through-substrate vias 121 can be considered as part of the die-substrate 120. The plurality of through-substrate vias 121 may include plated vias. The active region 122 may include a plurality of logic cells, a plurality of transistors, and / or a plurality of filters. Different implementations may use different types of transistors, such as field-effect transistors (FETs), planar FETs, finned FETs, and gate-all-around FETs. In some implementations, a front-end process (FEOL) may be used to fabricate the active region 122 of the die-substrate 120.

[0033] The die substrate 120 may include silicon (Si). The die substrate 120 may include bulk silicon. The bulk silicon may include a monolithic silicon substrate. A plurality of through-substrate vias 121 may extend through the die substrate 120. Different embodiments may have different thicknesses of the die substrate 120.

[0034] The die interconnect 104 includes at least one dielectric layer 140 and at least one die metallization layer (e.g., die metal 0, die metal 1) having a plurality of die interconnects 142. The die interconnect 104 is coupled to a die substrate base 102. The plurality of die interconnects 142 are coupled to an active region 122 of the die substrate base 102. The plurality of die interconnects 142 may be coupled to a plurality of through-substrate vias 121. The die interconnect 104 may also include a plurality of pad interconnects 101 and a passivation layer 106. In some embodiments, a back-to-end (BEOL) process may be used to manufacture the die interconnect 104. The die interconnect 104 may be a BEOL die interconnect. The die interconnect 104 may be an on-die interconnect.

[0035] The integrated device 100 includes a passivation layer 106, a plurality of pad interconnects 101, a plurality of metallized interconnects 103, a plurality of metallized interconnects 105, a plurality of metallized interconnects 107, a plurality of under-bump metallized interconnects 109, a plurality of solder interconnects 110, an encapsulation layer 112, and a solder mask layer 108. The passivation layer 106 may be disposed on the die interconnects 104. The plurality of solder interconnects 110 may be a plurality of solder bumps (e.g., solder bump interconnects).

[0036] Multiple pad interconnects 101 may include pad interconnects 101a, 101b, 101c, and 101d. Multiple metallized interconnects 103 may include metallized interconnect 103a. Multiple metallized interconnects 105 may include metallized interconnects 105a, 105b, and 105c. Multiple metallized interconnects 107 may include metallized interconnects 107a and 107b. Multiple under-bump metallized interconnects 109 may include under-bump metallized interconnects 109a, 109b, 109c, and 109d. In some specific implementations, a back-to-back (BEOL) process can be used to manufacture a passivation layer 106, multiple pad interconnects 101, multiple metallized interconnects 103, multiple metallized interconnects 105, multiple metallized interconnects 107, multiple under-bump metallized interconnects 109, an encapsulation layer 112, and / or a solder mask layer 108.

[0037] Multiple pad interconnects 101 may be coupled to multiple die interconnects 142. The multiple pad interconnects 101 may include aluminum (Al). The multiple die interconnects 142 may include copper (Cu). The multiple die interconnects 142 may include a different material than the multiple pad interconnects 101. A passivation layer 106 may be located over at least one dielectric layer 140. The passivation layer 106 may be coupled to and contact the top surface of at least one dielectric layer 140. The passivation layer 106 may be located over at least a portion of the multiple pad interconnects 101. The passivation layer 106 may include a different material than the at least one dielectric layer 140.

[0038] Metallized interconnect 103a may be coupled to and contact pad interconnect 101a. Metallized interconnect 107a may be coupled to and contact pad interconnect 101b and pad interconnect 101c. Metallized interconnect 107b may be coupled to and contact pad interconnect 101d. Multiple metallized interconnects 103 may include copper. Multiple metallized interconnects 107 may include copper. Multiple metallized interconnects 103 may be located in at least one cavity of passivation layer 106. Multiple metallized interconnects 103 may include via metallized interconnects, pad metallized interconnects, and / or trace metallized interconnects. Multiple metallized interconnects 103 may be located above the surface of passivation layer 106. Multiple metallized interconnects 107 may be located in at least one cavity of passivation layer 106. Multiple metallized interconnects 107 may include via metallized interconnects, pad metallized interconnects, and / or trace metallized interconnects. Multiple metallized interconnects 107 may be located above the surface of the passivation layer 106. The thickness of the trace metallized interconnects from the multiple metallized interconnects 107 may be greater than the thickness of the trace metallized interconnects from the multiple metallized interconnects 103. The thickness of the metallized pad interconnects from the multiple metallized interconnects 107 may be greater than the thickness of the metallized pad interconnects from the multiple metallized interconnects 103. The thickness of the metallized pad interconnects (e.g., formed by metallized interconnects 103 and 105) may be greater than the thickness of the trace metallized interconnects (e.g., formed by metallized interconnects 103). The thickness of the metallized trace interconnects (e.g., formed by metallized interconnects 103) may be less than the thickness of the pad metallized interconnects (e.g., formed by metallized interconnects 103 and 105). The metallized interconnect 107a includes a first pad metallized interconnect 107a-1, a second pad metallized interconnect 107a-2, and a trace metallized interconnect 107a-3. The first pad metallized interconnect 107a-1 is coupled to the second pad metallized interconnect 107a-2 via the trace metallized interconnect 107a-3. The trace metallized interconnect 107a-3 has the same thickness as the first pad metallized interconnect 107a-1 and / or the same thickness as the second pad metallized interconnect 107a-2. However, in some specific embodiments, the trace metallized interconnect 107a-3 may have a thickness less than the thickness of the first pad metallized interconnect 107a-1 and / or less than the thickness of the second pad metallized interconnect 107a-2. The first pad metallized interconnect 107a-1 is vertically overlapped and / or vertically aligned with the pad interconnect 101b and the under-bump metallized interconnect 109c. The second pad metallized interconnect 107a-2 is vertically overlapped and / or vertically aligned with the pad interconnect 101c and the under-bump metallized interconnect 109d.

[0039] Multiple metallized interconnects 105 may be coupled to and contact multiple metallized interconnects 103. Metallized interconnect 105a may be coupled to and contact metallized interconnect 103a. Metallized interconnect 105b may be coupled to and contact metallized interconnect 103a. Metallized interconnect 105c may be coupled to and contact metallized interconnect 103a. The multiple metallized interconnects 105 may include copper. The multiple metallized interconnects 105 may include via metallized interconnects, pad metallized interconnects, and / or trace metallized interconnects.

[0040] The encapsulation layer 112 may laterally surround at least a portion of the plurality of metallized interconnects 103, at least a portion of the plurality of metallized interconnects 105, and / or at least a portion of the plurality of metallized interconnects 107.

[0041] Encapsulation layer 112 may be located above passivation layer 106. Encapsulation layer 112 may comprise a material different from passivation layer 106. Encapsulation layer 112 may comprise molding material, resin, and / or epoxy resin. Encapsulation layer 112 may be a component for encapsulation. Encapsulation layer 112 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Encapsulation layer 112 may also be coupled to the sidewalls of die substrate base 102 and / or die interconnect 104. For example, encapsulation layer 112 may be coupled to and contact the sidewalls of at least one dielectric layer 140 and / or the sidewalls of die substrate 120.

[0042] The solder mask 108 is coupled to and contacts the encapsulation layer 112. At least a portion of the solder mask 108 may be located above the encapsulation layer 112. The solder mask 108 may include a material different from that of the encapsulation layer 112.

[0043] Under-bump metallized interconnect 109a is coupled to and contacts metallized interconnect 105a. Under-bump metallized interconnect 109b is coupled to and contacts metallized interconnect 105c. Under-bump metallized interconnect 109c is coupled to and contacts metallized interconnect 107a. Under-bump metallized interconnect 109d is coupled to and contacts metallized interconnect 107a. Under-bump metallized interconnect 109e is coupled to and contacts metallized interconnect 107b. The plurality of under-bump metallized interconnects 109 may include copper. A portion of the plurality of under-bump metallized interconnects 109 may be located within a cavity of solder mask 108. A portion of the plurality of under-bump metallized interconnects 109 may be located above the surface of solder mask 108.

[0044] Multiple solder interconnects 110 are coupled to and contact multiple under-bump interconnects 109. Solder interconnect 110a may be coupled to and contact under-bump interconnect 109a. Solder interconnect 110b may be coupled to and contact under-bump interconnect 109b. Solder interconnect 110c may be coupled to and contact under-bump interconnect 109c. Solder interconnect 110d may be coupled to and contact under-bump interconnect 109d. Solder interconnect 110e may be coupled to and contact under-bump interconnect 109e.

[0045] In some embodiments, electrical paths to and / or from the active region 122 may include at least one die interconnect from a plurality of die interconnects 142, and at least one through-substrate via from a plurality of through-substrate vias 121. In some embodiments, electrical paths to and / or from the active region 122 may include at least one die interconnect from a plurality of die interconnects 142, at least one pad interconnect from a plurality of pad interconnects 101, at least one metallized interconnect from a plurality of metallized interconnects 103, at least one metallized interconnect from a plurality of metallized interconnects 105, at least one under-bump metallized interconnect from a plurality of under-bump metallized interconnects 109, and / or at least one solder interconnect from a plurality of solder interconnects 110.

[0046] In some embodiments, the electrical path to and / or from the active region 122 may include at least one die interconnect from a plurality of die interconnects 142, and at least one through-substrate via from a plurality of through-substrate vias 121. In some embodiments, the electrical path to and / or from the active region 122 may include at least one die interconnect from a plurality of die interconnects 142, at least one pad interconnect from a plurality of pad interconnects 101, at least one metallized interconnect from a plurality of metallized interconnects 107, at least one under-bump metallized interconnect from a plurality of under-bump metallized interconnects 109, and / or at least one solder interconnect from a plurality of solder interconnects 110.

[0047] In some specific implementations, pad interconnect 101a, metallized interconnect 103a, metallized interconnect 105a, metallized interconnect 105b, metallized interconnect 105c, under-bump metallized interconnect 109a, under-bump metallized interconnect 109b, solder interconnect 110a and / or solder interconnect 110b may be part of an electrical path configured for a first power supply.

[0048] In some specific implementations, pad interconnects 101b, 101c, metallized interconnects 107a, under-bump metallized interconnects 109c, under-bump metallized interconnects 109d, solder interconnects 110c and / or solder interconnects 110d may be portions of an electrical path configured for a second power supply. The second power supply may be different from the first power supply.

[0049] In some specific implementations, pad interconnects 101d, metallized interconnects 107b, under-bump metallized interconnects 109e, and / or solder interconnects 110e may be part of an electrical path configured for a signal (e.g., an input / output signal).

[0050] Figure 1 Examples illustrate a vertically overlapping and / or vertically aligned under-bump metallized interconnect 109c with a pad interconnect 101b. A vertically overlapping and / or vertically aligned under-bump metallized interconnect 109d with a pad interconnect 101c. A vertically overlapping and / or vertically aligned under-bump metallized interconnect 109e with a pad interconnect 101d. A vertically overlapping and / or vertically aligned metallized interconnect 107b with both under-bump metallized interconnect 109e and pad interconnect 101d. Metallized interconnect 107b includes a first pad metallized interconnect 107a-1, a second pad metallized interconnect 107a-2, and a trace metallized interconnect 107a-3. The first pad metallized interconnect 107a-1 is coupled to the second pad metallized interconnect 107a-2 via the trace metallized interconnect 107a-3. The first pad metallized interconnect 107a-1 of the metallized interconnect 107a vertically overlaps with the under-bump metallized interconnect 109c and the pad interconnect 101b. The second pad metallized interconnect 107a-2 of the metallized interconnect 107a vertically overlaps with the under-bump metallized interconnect 109d and the pad interconnect 101c. The trace metallized interconnect 107a-3 has the same thickness as the first pad metallized interconnect 107a-1 and / or the same thickness as the second pad metallized interconnect 107a-2. However, in some specific embodiments, the trace metallized interconnect 107a-3 may have a thickness less than the thickness of the first pad metallized interconnect 107a-1 and / or less than the thickness of the second pad metallized interconnect 107a-2.

[0051] A first interconnect (e.g., a first metallized interconnect) vertically aligned with a second interconnect (e.g., a second metallized interconnect) can mean that the center of the first interconnect can be vertically aligned with the center of the second interconnect. Vertical alignment of two or more pad interconnects helps reduce and / or minimize the number of metal layers required to route electrical signals because less fan-out or redistribution of interconnects in the lateral direction is needed. Fewer interconnects mean fewer metal layers are required to accommodate them. Additionally, using thinner trace metallized interconnects helps keep pad metallized interconnects closer together, and thus allows for more interconnects to be provided in a given area and / or region of the metallized portion.

[0052] Figure 1 An example of an integrated device 100 with a compact form factor while still providing high-density interconnects is illustrated. For example, the integrated device 100 may include a minimum number of metal layers on the die interconnects 104, which reduces the overall size of the integrated device 100. For example, a spoke configuration where adjacent pad interconnects can share a common interconnect and / or be coupled via the common interconnect allows the pad interconnects to be closer to each other, as shorting between these adjacent pad interconnects is less of a concern. Furthermore, because the integrated device 100 can be manufactured by a single supplier, it can be manufactured more cost-effectively than other similar integrated devices. For example, multiple metallized interconnects 103, multiple metallized interconnects 105, multiple metallized interconnects 107, and / or multiple under-bump metallized interconnects 109 can be manufactured as part of the process for manufacturing the die interconnects 104, which helps reduce the overall cost of the integrated device 100.

[0053] Another advantage is that by reducing the number of metal layers used for multiple metallized interconnects, a smaller and tighter pitch can be provided for the metallized interconnects and / or under-bump metallized interconnects. In some specific embodiments, the pitch of the metallized interconnects and / or the pitch of the under-bump metallized interconnects can range from about 10 micrometers to 40 micrometers. This may be made possible because the metallized interconnects for power supply configurations do not occupy too much space (e.g., due to the use of a spoke configuration). Metallized interconnects and / or under-bump metallized interconnects with these pitches can be configured to provide electrical paths for signals (e.g., input / output signals). The above advantages apply to any integrated device described in this disclosure.

[0054] Figure 2An example of integrated device 200 is illustrated. Integrated device 200 is similar to integrated device 100 and may include similar components arranged and / or configured in a similar manner to integrated device 100. However, integrated device 200 may include additional components and / or components arranged and / or configured differently. Integrated device 200 includes a die substrate base 102 and die interconnects 104. Die substrate base 102 includes a die substrate 120, an active region 122, and a plurality of through-substrate vias 121. Active region 122 may include a plurality of logic cells, a plurality of transistors, and / or a plurality of filters. Die substrate 120 may include silicon (Si). Die substrate 120 may include bulk silicon. Bulk silicon may include a monolithic silicon. The plurality of through-substrate vias 121 may extend through die substrate 120. Different specific embodiments may have different thicknesses of die substrate 120.

[0055] The die interconnect 104 includes at least one dielectric layer 140 and a plurality of die interconnects 142. The die interconnect 104 is coupled to a die substrate base 102. The plurality of die interconnects 142 are coupled to an active region 122 of the die substrate base 102. The plurality of die interconnects 142 may be coupled to a plurality of through-substrate vias 121. The die interconnect 104 may also include a plurality of pad interconnects 101 and a passivation layer 106.

[0056] The integrated device 200 includes multiple metallized interconnects 103, multiple metallized interconnects 105, multiple under-bump metallized interconnects 109, multiple solder interconnects 110, and an encapsulation layer 112.

[0057] Multiple pad interconnects 101 may include pad interconnects 101a, 101b, 101c, and 101d. Multiple metallized interconnects 103 may include metallized interconnects 103a, 103b, and 103c. Multiple metallized interconnects 105 may include metallized interconnects 105a, 105b, 105c, 105d, and 105e. Multiple under-bump metallized interconnects 109 may include under-bump metallized interconnects 109a, 109b, 109c, 109d, and 109e. In some specific implementations, a back-to-back (BEOL) process can be used to manufacture the passivation layer 106, multiple pad interconnects 101, multiple metallized interconnects 103, multiple metallized interconnects 105, multiple under-bump metallized interconnects 109, and encapsulation layer 112.

[0058] like Figure 2As shown, a plurality of pad interconnects 101 may be coupled to a plurality of die interconnects 142. The plurality of pad interconnects 101 may include aluminum (Al). The plurality of die interconnects 142 may include copper (Cu). The plurality of die interconnects 142 may include a material different from the plurality of pad interconnects 101. A passivation layer 106 may be located over at least one dielectric layer 140. The passivation layer 106 may be coupled to and contact the top surface of at least one dielectric layer 140. The passivation layer 106 may be located over at least a portion of the plurality of pad interconnects 101. The passivation layer 106 may include a material different from the at least one dielectric layer 140.

[0059] like Figure 2 As further shown, metallized interconnect 103a may be coupled to and contact pad interconnect 101a. Metallized interconnect 103b may be coupled to and contact pad interconnect 101b and pad interconnect 101c. Metallized interconnect 103c may be coupled to and contact pad interconnect 101d. The plurality of metallized interconnects 103 may include copper.

[0060] Multiple metallized interconnects 105 may be coupled to and contact multiple metallized interconnects 103. Metallized interconnect 105a may be coupled to and contact metallized interconnect 103a. Metallized interconnect 105b may be coupled to and contact metallized interconnect 103a. Metallized interconnect 105c may be coupled to and contact metallized interconnect 103a. Metallized interconnect 105d may be coupled to and contact metallized interconnect 103b. Metallized interconnect 105f may be coupled to and contact metallized interconnect 103b. Metallized interconnect 105e may be coupled to and contact metallized interconnect 103c. The multiple metallized interconnects 105 may include copper. The multiple metallized interconnects 105 may include via metallized interconnects, pad metallized interconnects, and / or trace metallized interconnects.

[0061] Under-bump metallized interconnect 109a is coupled to and contacts metallized interconnect 105a. Under-bump metallized interconnect 109b is coupled to and contacts metallized interconnect 105c. Under-bump metallized interconnect 109c is coupled to and contacts metallized interconnect 105d. Under-bump metallized interconnect 109d is coupled to and contacts metallized interconnect 105d. Under-bump metallized interconnect 109e is coupled to and contacts metallized interconnect 105e.

[0062] Figure 3Examples include: Under-bump metallized interconnect 109c vertically overlapping and / or vertically aligned with pad interconnect 101b; Under-bump metallized interconnect 109d vertically overlapping and / or vertically aligned with pad interconnect 101c; Metallized interconnect 105d (which may be a pad metallized interconnect) vertically overlapping and / or vertically aligned with both under-bump metallized interconnect 109c and pad interconnect 101b; Metallized interconnect 105f (which may be a pad metallized interconnect) vertically overlapping and / or vertically aligned with both under-bump metallized interconnect 109d and pad interconnect 101c; and Metallized interconnect 105d coupled to Metallized interconnect 105f via Metallized interconnect 103b. The thickness of the trace metallized interconnect 103b-3 of the metallized interconnect 103b may be less than the combined thickness of the metallized interconnect 105d and the first pad metallized interconnect 103b-1 of the metallized interconnect 103b. The thickness of the trace metallized interconnect 103b-3 of the metallized interconnect 103b may be less than the combined thickness of the metallized interconnect 105f and the second pad metallized interconnect 103b-2 of the metallized interconnect 103b.

[0063] Multiple solder interconnects 110 are coupled to and contact multiple under-bump interconnects 109. Solder interconnect 110a may be coupled to and contact under-bump interconnect 109a. Solder interconnect 110b may be coupled to and contact under-bump interconnect 109b. Solder interconnect 110c may be coupled to and contact under-bump interconnect 109c. Solder interconnect 110d may be coupled to and contact under-bump interconnect 109d. Solder interconnect 110e may be coupled to and contact under-bump interconnect 109e.

[0064] Figure 3 An example of an integrated device 300 is illustrated. Integrated device 300 is similar to integrated device 100 and may include similar components arranged and / or configured in a similar manner to integrated device 100. However, integrated device 300 may include additional components and / or components arranged and / or configured differently. Integrated device 300 includes a die substrate base 102 and die interconnects 104. Die substrate base 102 includes a die substrate 120, an active region 122, and a plurality of through-substrate vias 121. Active region 122 may include a plurality of logic cells, a plurality of transistors, and / or a plurality of filters. Die substrate 120 may include silicon (Si). Die substrate 120 may include bulk silicon. Bulk silicon may include a monolithic silicon. The plurality of through-substrate vias 121 may extend through die substrate 120. Different specific embodiments may have different thicknesses of die substrate 120.

[0065] The die interconnect 104 includes at least one dielectric layer 140 and a plurality of die interconnects 142. The die interconnect 104 is coupled to a die substrate base 102. The plurality of die interconnects 142 are coupled to an active region 122 of the die substrate base 102. The plurality of die interconnects 142 may be coupled to a plurality of through-substrate vias 121. The die interconnect 104 may also include a plurality of pad interconnects 101 and a passivation layer 106.

[0066] The integrated device 300 includes a plurality of metallized interconnects 107, a plurality of under-bump metallized interconnects 109, a plurality of solder interconnects 110, and an encapsulation layer 112. The plurality of pad interconnects 101 include pad interconnects 101a, 101b, 101c, and 101d. The plurality of metallized interconnects 107 include metallized interconnects 107a, 107b, and 107c. The plurality of under-bump metallized interconnects 109 include under-bump metallized interconnects 109a, 109b, 109c, 109d, and 109e.

[0067] like Figure 3 As shown, metallized interconnect 107c is coupled to and contacts pad interconnect 101a. Metallized interconnect 107a is coupled to and contacts pad interconnect 101b and pad interconnect 101c. Metallized interconnect 107b is coupled to and contacts pad interconnect 101d. Under-bump metallized interconnect 109a may be coupled to and contacts metallized interconnect 107c. Under-bump metallized interconnect 109b may be coupled to and contacts metallized interconnect 107c. Under-bump metallized interconnect 109c may be coupled to and contacts metallized interconnect 107a. Under-bump metallized interconnect 109d may be coupled to and contacts metallized interconnect 107a. Under-bump metallized interconnect 109e may be coupled to and contacts metallized interconnect 107b.

[0068] like Figure 3 As further shown, solder interconnect 110a can be coupled to and contact under-bump metallized interconnect 109a. Solder interconnect 110b can be coupled to and contact under-bump metallized interconnect 109b. Solder interconnect 110c can be coupled to and contact under-bump metallized interconnect 109c. Solder interconnect 110d can be coupled to and contact under-bump metallized interconnect 109d. Solder interconnect 110e can be coupled to and contact under-bump metallized interconnect 109e.

[0069] In some specific implementations, some metallized interconnects from multiple metallized interconnects 103, multiple metallized interconnects 105, and / or multiple metallized interconnects 107 of integrated devices 100, 200, and / or 300 may be vertically positioned above a portion of the encapsulation layer 112, which is located on the side of the die interconnect 104 and on the side of the die substrate base 102. Therefore, some metallized interconnects from multiple metallized interconnects 103, multiple metallized interconnects 105, and / or multiple metallized interconnects 107 may not vertically overlap with the die substrate base 102 and the die interconnect 104.

[0070] Figure 4 An exemplary plan view of a cross-section of integrated device 400 is illustrated. Integrated device 400 may represent any integrated device, including integrated device 100, integrated device 200, integrated device 300, and / or integrated devices described in this disclosure. For example, integrated device 400 may be an example of a cross-section AA of integrated device 300.

[0071] The integrated device 400 includes a plurality of metallized interconnects 407 and a plurality of metallized interconnects 417. In some specific embodiments, the plurality of metallized interconnects 407 and / or the plurality of metallized interconnects 417 may represent a plurality of metallized interconnects 107 of the integrated device 300. The plurality of metallized interconnects 407 may include metallized interconnects 407a, 407b, 407c, 407d, 407e, 407f, and 407g.

[0072] Multiple metallized interconnects 407 may be configured to provide one or more electrical paths for one or more power supplies. Multiple metallized interconnects 417 may be configured to provide electrical paths for signals (e.g., input / output signals). Multiple metallized interconnects 417 may have a smaller minimum size than multiple metallized interconnects 407. For example, multiple metallized interconnects 417 may have a minimum pitch smaller than the minimum pitch of multiple metallized interconnects 407.

[0073] Figure 5 An exemplary plan view of a cross-section of integrated device 500 is illustrated. Integrated device 500 may represent any integrated device of integrated device 100, integrated device 200, integrated device 300 and / or integrated devices described in this disclosure. For example, integrated device 500 may be an example of a cross-section AA of integrated device 100.

[0074] The integrated device 500 includes a plurality of metallized interconnects 407, a plurality of metallized interconnects 417, and a plurality of metallized interconnects 503. In some specific embodiments, the plurality of metallized interconnects 407 and / or the plurality of metallized interconnects 417 may represent a plurality of metallized interconnects 107 of the integrated device 100. The plurality of metallized interconnects 407 may include metallized interconnects 407a, 407b, 407c, 407d, 407e, 407f, and 407g.

[0075] In some specific implementations, the plurality of metallized interconnects 503 may represent a plurality of metallized interconnects 103 and / or a plurality of metallized interconnects 105 of the integrated device 100. The plurality of metallized interconnects 503 may include metallized interconnects 503a, 503b, 503c, 503d, 503e, 503f, and 503g.

[0076] Some interconnects from multiple metallized interconnects 503 can be arranged in a spoke configuration. For example, metallized interconnects 503a, 503b, and 503c can be part of a first spoke configuration of metallized interconnects. Metallized interconnect 503b can be coupled to metallized interconnects 503a and 503c. Metallized interconnect 503a can be the axis of the first spoke configuration. Metallized interconnect 503c can be a spoke of the first spoke configuration. The width of metallized interconnect 503a can be greater than the width of metallized interconnect 503c. The first spoke configuration can include multiple spokes. The first spoke configuration can be configured to provide an electrical path for a first power supply.

[0077] Different axis-spoke configurations can have different arrangements. Metallized interconnects 503d, 503e, and 503f can be part of a metallized interconnect arranged in a second axis-spoke configuration. Metallized interconnect 503e can be coupled to metallized interconnects 503d and 503f. Metallized interconnect 503d can be the axis of the second axis-spoke configuration. Metallized interconnect 503f can be a spoke of the second axis-spoke configuration. The second axis-spoke configuration can include multiple spokes. The second axis-spoke configuration can be configured to provide an electrical path for a second power supply. The second power supply can be different from the first power supply. In some embodiments, the first power supply can have a first voltage, and the second power supply can have a second voltage different from the first voltage.

[0078] Different arrangements of multiple metallized interconnects 407 and / or multiple metallized interconnects 503 can help provide a more efficient power distribution network for the integrated device. For example, multiple metallized interconnects 407 and / or multiple metallized interconnects 503 can be arranged to efficiently provide appropriate power to the various components of the integrated device 500.

[0079] Figure 6 and Figure 7 Various examples of spoke configurations are shown. Figure 6 An axial-spoke configuration 600 is illustrated, including interconnects 601, 603, 605, 607, 609, 630, 650, 670, and 690. One or more of these interconnects may be metallized interconnects (e.g., 103, 105, 107). Interconnect 601 may be an axial interconnect. Interconnects 603, 605, 607, and 609 may each be a radial interconnect. Interconnects 601, 603, 605, 607, and 609 may each be a pad interconnect. Interconnect 630 may be coupled to interconnects 601 and 603. Interconnect 650 may be coupled to interconnects 601 and 605. Interconnect 670 may be coupled to interconnects 601 and 607. Interconnector 690 may be coupled to interconnectors 601 and 609. Spoke-axis configuration 600 may include a different number of spokes. Spoke-axis configuration 600 may be implemented in integrated device 100, integrated device 200 and / or integrated device 300.

[0080] Figure 7 An axial-spoke configuration 700 is illustrated, including interconnects 701, 703, 705, 707, 709, and 710. One or more of these interconnects may be metallized interconnects (e.g., 103, 105, 107). Interconnect 701 may be an axial interconnect. Interconnects 703, 705, 707, and 709 may each be a radial interconnect. Interconnects 701, 703, 705, 707, and 709 may each be a pad interconnect. Interconnect 710 may be coupled to interconnects 701, 703, 705, 707, and 709. The axial-spoke configuration 700 may include a different number of spokes. The axial-spoke configuration 700 may be implemented in integrated device 100, integrated device 200, and / or integrated device 300.

[0081] Figures 8 to 10 Various examples of the arrangement of pad interconnects for integrated devices are shown. Figures 8 to 10 The arrangement can be implemented in any of the integrated devices described in this disclosure.

[0082] Figure 8 A configuration 800 is illustrated, comprising a plurality of metallized interconnects 810 (e.g., large pad interconnects) and a plurality of metallized interconnects 820 (e.g., small pad interconnects). The plurality of metallized interconnects 820 have a smaller width than the plurality of metallized interconnects 810. Metallized interconnect 820a is located between metallized interconnects 810a and metallized interconnect 810b. Configuration 800 illustrates a small pad interconnect between two large pad interconnects. Configuration 800 illustrates a pitch of the plurality of metallized interconnects 820 that is smaller than the pitch of the plurality of metallized interconnects 810.

[0083] Figure 9 A configuration 900 is illustrated, comprising a plurality of metallized interconnects 810 (e.g., large pad interconnects) and a plurality of metallized interconnects 920 (e.g., small pad interconnects). The plurality of metallized interconnects 920 have a smaller width than the plurality of metallized interconnects 810. Metallized interconnects 920a and 920b are located between metallized interconnects 810a and 810b. Configuration 900 illustrates two small pad interconnects between two large pad interconnects. Configuration 900 illustrates that the pitch of the plurality of metallized interconnects 920 is smaller than the pitch of the plurality of metallized interconnects 810.

[0084] Figure 10 A configuration 1000 is illustrated, comprising a plurality of metallized interconnects 810 (e.g., large pad interconnects) and a plurality of metallized interconnects 1020 (e.g., small pad interconnects). The plurality of metallized interconnects 1020 have a smaller width than the plurality of metallized interconnects 810. Metallized interconnects 1020a and 1020b are located between metallized interconnects 810a and 810b. Configuration 1000 illustrates two small pad interconnects between two large pad interconnects. However, the spacing between the metallized interconnects from the plurality of metallized interconnects 1020 can vary. Configuration 1000 illustrates that the pitch of the plurality of metallized interconnects 1020 is smaller than the pitch of the plurality of metallized interconnects 810.

[0085] In some embodiments, multiple metallized interconnects 810 may be configured as landing points for probes during testing of integrated devices and / or wafers including integrated devices. In some embodiments, one or more of the metallized interconnects from the multiple metallized interconnects 810 may be dummy metallized interconnects and / or redundant metallized interconnects. Due to the size of the probes, it may be impossible to contact and / or properly align with the smaller multiple metallized interconnects 820, multiple metallized interconnects 920, and / or multiple metallized interconnects 1020, which may require larger pads. For example, the probes may contact metallized interconnects 810a to test signals or provide power to integrated devices. Metallized interconnects 810 may be coupled to metallized interconnects 820a (which can be used as landing pads for solder interconnects when an integrated device is coupled to another integrated device, substrate, or board). The combination of large and small pads allows for a compact form factor for integrated devices while providing metallized interconnects with small pitch, and simultaneously providing sufficiently large pads for probes to contact during testing of the wafer and / or integrated device. In some specific implementations, multiple metallized interconnects 820, multiple metallized interconnects 920, and / or multiple metallized interconnects 1020 may be configured to (i) provide electrical paths between integrated devices, (ii) between integrated devices and a substrate (e.g., an interposer), and / or (iii) between integrated devices and a board.

[0086] Figure 11 An example of integrated device 1100 is illustrated. Integrated device 1100 is similar to integrated device 300 and may include similar components arranged and / or configured in a similar manner to integrated device 300. However, integrated device 1100 may include additional components and / or components arranged and / or configured differently. For example, in Figure 11 In this configuration, the encapsulation layer 112 is located on the side of the integrated device 1100. However, in Figure 3 In this embodiment, the encapsulation layer 112 may be located on the side surface of the integrated device 300 and on the top surface of the integrated device 300. The integrated device 1100 includes a die substrate base 102 and die interconnects 104. The die substrate base 102 includes a die substrate 120, an active region 122, and a plurality of through-substrate vias 121. The active region 122 may include a plurality of logic cells, a plurality of transistors, and / or a plurality of filters. The die substrate 120 may include silicon (Si). The die substrate 120 may include bulk silicon. The bulk silicon may include a monolithic silicon. The plurality of through-substrate vias 121 may extend through the die substrate 120. Different specific embodiments may have different thicknesses of the die substrate 120.

[0087] The die interconnect 104 includes at least one dielectric layer 140 and a plurality of die interconnects 142. The die interconnect 104 is coupled to a die substrate base 102. The plurality of die interconnects 142 are coupled to an active region 122 of the die substrate base 102. The plurality of die interconnects 142 may be coupled to a plurality of through-substrate vias 121. The die interconnect 104 may also include a plurality of pad interconnects 101 and a passivation layer 106.

[0088] The integrated device 1100 includes multiple metallized interconnects 107, multiple metallized interconnects 1109, multiple solder interconnects 110, and an encapsulation layer 112. Multiple pad interconnects 101 include pad interconnects 101a, 101b, 101c, and 101d. Multiple metallized interconnects 107 include metallized interconnects 107a, 107b, and 107c. Multiple metallized interconnects 1109 include metallized interconnects 1109a, 1109b, 1109c, 1109d, and 1109e.

[0089] like Figure 11 As shown, metallized interconnect 107c is coupled to and contacts pad interconnect 101a. Metallized interconnect 107a is coupled to and contacts pad interconnect 101b and pad interconnect 101c. Metallized interconnect 107b is coupled to and contacts pad interconnect 101d. Metallized interconnect 1109a may be coupled to and contacts metallized interconnect 107c. Metallized interconnect 1109b may be coupled to and contacts metallized interconnect 107c. Metallized interconnect 1109c may be coupled to and contacts metallized interconnect 107a. Metallized interconnect 1109d may be coupled to and contacts metallized interconnect 107a. Metallized interconnect 1109e may be coupled to and contacts metallized interconnect 107b.

[0090] like Figure 11 As further shown, solder interconnect 110a can be coupled to and contact metallized interconnect 1109a. Solder interconnect 110b can be coupled to and contact metallized interconnect 1109b. Solder interconnect 110c can be coupled to and contact metallized interconnect 1109c. Solder interconnect 110d can be coupled to and contact metallized interconnect 1109d. Solder interconnect 110e can be coupled to and contact metallized interconnect 1109e.

[0091] Figure 12An example of integrated device 1200 is illustrated. Integrated device 1200 is similar to integrated device 300 and may include similar components arranged and / or configured in a similar manner to integrated device 300. However, integrated device 300 may include additional components and / or components arranged and / or configured differently. For example, thicker metallized interconnects 107 help provide interconnects with a higher aspect ratio, which can help provide more space between integrated device 1200 and another integrated device and / or another component. Integrated device 1200 includes a die substrate base 102 and die interconnects 104. Die substrate base 102 includes a die substrate 120, an active region 122, and a plurality of through-substrate vias 121. Active region 122 may include a plurality of logic cells, a plurality of transistors, and / or a plurality of filters. Die substrate 120 may include silicon (Si). Die substrate 120 may include bulk silicon. Bulk silicon may include a monolithic silicon. The plurality of through-substrate vias 121 may extend through die substrate 120. Different specific implementations may have different thicknesses of the die substrate 120.

[0092] The die interconnect 104 includes at least one dielectric layer 140 and a plurality of die interconnects 142. The die interconnect 104 is coupled to a die substrate base 102. The plurality of die interconnects 142 are coupled to an active region 122 of the die substrate base 102. The plurality of die interconnects 142 may be coupled to a plurality of through-substrate vias 121. The die interconnect 104 may also include a plurality of pad interconnects 101 and a passivation layer 106.

[0093] The integrated device 1200 includes a plurality of metallized interconnects 107, a plurality of solder interconnects 110, and an encapsulation layer 112. The plurality of pad interconnects 101 include pad interconnects 101a, 101b, 101c, 101d, and 101e. The plurality of metallized interconnects 107 include metallized interconnects 107a, 107b, 107c, 107d, and 107e.

[0094] like Figure 12 As shown, metallized interconnect 107a is coupled to and contacts pad interconnect 101e. Metallized interconnect 107b is coupled to and contacts pad interconnect 101a. Metallized interconnect 107c is coupled to and contacts pad interconnect 101a. Metallized interconnect 107d is coupled to and contacts pad interconnect 101b and pad interconnect 101c. Metallized interconnect 107e is coupled to and contacts pad interconnect 101d. The plurality of metallized interconnects 107 may be configured as pillar metallized interconnects having a thickness or height substantially greater than the thickness of the plurality of pad interconnects 101.

[0095] like Figure 12As further shown, solder interconnect 110a can be coupled to and contact metallized interconnect 107a. Solder interconnect 110b can be coupled to and contact metallized interconnect 107b. Solder interconnect 110c can be coupled to and contact metallized interconnect 107c. Solder interconnect 110d can be coupled to and contact metallized interconnect 107d. Solder interconnect 110e can be coupled to and contact metallized interconnect 107e.

[0096] The integrated device (e.g., 100) may include a die (e.g., a bare semiconductor die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory, power management processors, and / or combinations thereof. The integrated device may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include an input / output (I / O) hub. The integrated device may include transistors. The integrated device may be an example of an electronic component and / or electronic device.

[0097] In some embodiments, the integrated device may be a chiplet. Chipslets can be manufactured using processes that offer better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some embodiments, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned above, using several chiplets performing several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some embodiments, one or more chiplets and / or one or more integrated devices (e.g., 103) of the chiplets described in this disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device may be manufactured using a first technology node, and a chiplet may be manufactured using a second technology node that is less advanced than the first technology node. In such examples, the integrated device may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some embodiments, the first and second integrated devices of the package may be manufactured using the same or different technology nodes. In some embodiments, the chiplets and another chiplet of the package may be manufactured using the same or different technology nodes.

[0098] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or chiplets. A technology node can specify the minimum possible size that can be manufactured (e.g., minimum size) (e.g., transistor size, trace width, gap width between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes for components with finer manufacturing details are more expensive and may have higher yield losses compared to technology nodes for components with less fine manufacturing details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all functions of a package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not require manufacturing using that specific technology node. Therefore, the integrated device is locked to a single technology node. To optimize the cost of the package, some functions can be implemented in different integrated devices and / or chiplets, where different technology nodes can be used to manufacture different integrated devices and / or chiplets to reduce the overall cost. For example, functionality requiring state-of-the-art technology nodes can be implemented in an integrated device, while functionality achievable with less advanced technology nodes can be implemented in another integrated device and / or one or more chiplets. An example would be an integrated device manufactured using a first technology node (e.g., a more advanced technology node) and configured to provide computing applications, and at least one chiplet manufactured using a second technology node and configured to provide additional functionality, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures a component with a minimum size larger than the minimum size of a component manufactured using the first technology node. Examples of computing applications could include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packing as many transistors as possible into the integrated device. This is why the integrated device configured for computing applications can be manufactured using the most advanced available technology nodes, while other chiplets can be manufactured using less advanced technology nodes, as these chiplets may not require as many transistors to be manufactured in the chiplet. Therefore, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0099] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign each individual integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet unchanged. Therefore, the first chiplet can be reused along with improved and / or differently configured first integrated devices. This saves costs when manufacturing packages with improved integrated devices because the first chiplet does not need to be redesigned.

[0100] It should be noted that different embodiments may use solder interconnects with different materials, shapes, and / or sizes. For example, one or more solder interconnects from a plurality of solder interconnects 110 may have a dome shape. In some embodiments, one or more solder interconnects from a plurality of solder interconnects 110 may have one or more flat surfaces (e.g., a top flat surface, a bottom flat surface). Similarly, different embodiments may use pad interconnects with different materials, shapes, and / or sizes. For example, one or more pad interconnects may include aluminum (Al), copper (Cu), nickel (Ni), gold (Au), and / or platinum (Pt). Any of the multiple pad interconnects, multiple metallized interconnects, and / or multiple interconnects may include one or more layers of different materials. In some embodiments, multiple pad interconnects and multiple interconnects may form continuous interconnects and / or coherent interconnects.

[0101] It should be noted that the configuration of multiple metallized interconnects (e.g., 103), multiple metallized interconnects (e.g., 105), multiple metallized interconnects (e.g., 107), and multiple under-bump metallized interconnects (e.g., 109) is not limited to integrated devices. In some specific embodiments, the aforementioned metallized interconnects may be implemented as a passive device (e.g., a die-on passive device), an interposer (e.g., a passive silicon interposer), a metallized portion interposer, a reconstructed wafer (e.g., a rebuilt wafer), and / or a portion of the metallization on the reconstructed wafer.

[0102] Exemplary process for manufacturing integrated devices

[0103] In some specific implementations, manufacturing integrated devices involves several processes. Figures 13A to 13I Exemplary steps for providing or manufacturing integrated devices are illustrated. In some specific implementations, Figures 13A to 13I The process can be used to provide or manufacture integrated device 100. However, Figures 13A to 13I The process can be used to manufacture any integrated device described in this disclosure.

[0104] It should be noted that Figures 13A to 13IThe processes may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0105] like Figure 13A As shown, Stage 1 illustrates the state after the integrated device has been provided and / or manufactured. The integrated device 100 may include a die substrate base 102. The die substrate base 102 may include a die substrate 120, die interconnects 104 (e.g., die interconnect portions), a passivation layer 106, and a plurality of metallized interconnects 107. The integrated device 100 may include a bare die (e.g., a semiconductor bare die). Thus, in some embodiments, a bare die including a die substrate 120, die interconnects 104 (e.g., die interconnect portions, on-die interconnects), at least one passivation layer (e.g., 106), and a plurality of metallized interconnects 107 may be provided in Stage 1. In some embodiments, the integrated device 100 is provided and / or manufactured as part of a wafer. As will be further described below, the integrated device may include additional components and / or other components that may be manufactured on the integrated device provided at Stage 1.

[0106] Stage 2 illustrates the state after the formation of the seed layer 1310. The seed layer 1310 may include copper. The seed layer 1310 may be formed over the surface of the passivation layer 106. The seed layer 1310 may also be formed over a plurality of pad interconnects 101. The seed layer 1310 may be formed using a plating process.

[0107] like Figure 13B As shown, stage 3 illustrates the state after the photoresist layer 1320 has been formed above the seed layer 1310. The photoresist layer 1320 may include openings 1322. Deposition processes, lamination processes, exposure processes, and / or development processes can be used to form the photoresist layer 1320.

[0108] Stage 4 illustrates the state after the formation of multiple metallized interconnects 103. Multiple metallized interconnects 103 can be formed and coupled to the seed layer 1310. Multiple metallized interconnects 103 can be formed through openings 1322 in the photoresist layer 1320. Multiple metallized interconnects 103 can be formed using a plating process.

[0109] like Figure 13C As shown, stage 5 illustrates the state after the removal of photoresist layer 1320. A stripping process can be used to remove photoresist layer 1320.

[0110] Stage 6 illustrates the state after the photoresist layer 1330 has been formed over the seed layer 1310 and / or the plurality of metallized interconnects 103. The photoresist layer 1330 may include an opening 1332. The photoresist layer 1330 may be formed using deposition processes, lamination processes, exposure processes, and / or development processes.

[0111] like Figure 13D As shown, stage 7 illustrates the state after the formation of multiple metallized interconnects 105 and multiple metallized interconnects 107. Multiple metallized interconnects 105 may be formed and coupled to multiple metallized interconnects 103. Multiple metallized interconnects 107 may be formed and coupled to the seed layer 1310. Multiple metallized interconnects 105 and / or multiple metallized interconnects 107 may be formed through openings 1332 in the photoresist layer 1330. A plating process may be used to form multiple metallized interconnects 105 and / or multiple metallized interconnects 107.

[0112] Stage 8 illustrates the state after the removal of photoresist layer 1330. A stripping process can be used to remove photoresist layer 1330.

[0113] like Figure 13E As shown, stage 9 illustrates the state after the integrated device 100 is placed and coupled to the carrier 1300 by adhesive 1302.

[0114] Stage 10 illustrates the state after the encapsulation layer 112 has been formed and coupled to the integrated device 100. The encapsulation layer 112 may be coupled to the side surface and / or sidewall of the integrated device 100. The encapsulation layer 112 may contact the side surface of the passivation layer 106, the side surface of the dielectric layer 140, and / or the side surface of the die substrate 120. The encapsulation layer 112 may be formed over the passivation layer 106. The encapsulation layer 112 may include molding compound, resin, and / or epoxy resin. The encapsulation layer 112 may be formed using compression molding, transfer molding, or liquid molding processes.

[0115] like Figure 13F As shown, in stage 11, after a portion of the encapsulation layer 112 can be removed. For example, the top portion of the encapsulation layer 112 can be ground off.

[0116] Stage 12 illustrates the state after the solder mask 108 has been formed over the encapsulation layer 112. The solder mask 108 may include openings 1334. Deposition processes, lamination processes, exposure processes, and / or development processes can be used to form the solder mask 108.

[0117] like Figure 13G As shown, stage 13 illustrates the state after the photoresist layer 1340 has been formed over the solder mask layer 108. The photoresist layer 1340 may include an opening 1342. The photoresist layer 1340 may be formed using deposition processes, lamination processes, exposure processes, and / or development processes.

[0118] Stage 14 illustrates the state after the formation of multiple under-bump interconnects 109. Multiple under-bump interconnects 109 may be formed and coupled to multiple metallized interconnects 105 and / or multiple metallized interconnects 107. Multiple under-bump interconnects 109 may be formed through openings 1342 in the photoresist layer 1340. A plating process may be used to form the multiple under-bump interconnects 109.

[0119] like Figure 13H As shown, stage 15 illustrates the state after a plurality of solder interconnects 110 have been formed and coupled to a plurality of under-bump metallized interconnects 109. A bonding process can be used to form the plurality of solder interconnects 110 through openings 1342 in the photoresist layer 1340. A solder reflow process can be used to couple the plurality of solder interconnects 110 to the plurality of under-bump metallized interconnects 109.

[0120] Stage 16 illustrates the state after the removal of photoresist layer 1340. A stripping process can be used to remove photoresist layer 1340.

[0121] like Figure 13I As shown, stage 17 illustrates the state after the integrated device 100 is decoupled from the carrier 1300. The adhesive 1302 and the carrier 1300 can be separated from the integrated device 100.

[0122] Exemplary flowchart of a method for manufacturing integrated devices

[0123] In some specific implementations, manufacturing integrated devices involves several processes. Figure 14 An exemplary flowchart illustrating a method 1400 for providing or manufacturing an integrated device is shown. In some specific implementations, Figure 14 Method 1400 can be used to provide or manufacture the product described in this disclosure. Figure 1 The integrated device 100. However, method 1400 can be used to provide or manufacture any integrated device described in this disclosure.

[0124] It should be noted that Figure 14 Method 1400 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated devices. In some specific implementations, the order of the processes may be changed or modified.

[0125] The method (at 1405) provides an integrated device comprising a die substrate, die interconnects and multiple pad interconnects, and couples the integrated device to a carrier by an adhesive. Figure 13APhase 1 illustrates and describes an example of the state following the provision and / or fabrication of the integrated device. The integrated device 100 may include a die substrate base 102. The die substrate base 102 may include a die substrate 120, die interconnects 104 (e.g., interconnect portions), a passivation layer 106, and a plurality of metallized interconnects 107. The integrated device 100 may include a bare die (e.g., a semiconductor bare die). Thus, in some embodiments, a bare die including a die substrate 120, die interconnects 104 (e.g., die interconnect portions), at least one passivation layer (e.g., 106), and a plurality of metallized interconnects 107 may be provided in Phase 1. In some embodiments, the integrated device 100 is provided and / or fabricated as part of a wafer. As will be further described below, the integrated device may include additional components and / or other components that may be fabricated on the integrated device provided at Phase 1.

[0126] The method (in 1410) forms multiple metallized interconnects coupled to multiple pad interconnects. Some of the metallized interconnects can be arranged in a spoke configuration. Figure 13A Phase 2 to Figure 13D The eight stages illustrate and describe examples of forming multiple metallized interconnects.

[0127] Figure 13A Stage 2 illustrates and describes an example of the state after the formation of the seed layer 1310. The seed layer 1310 may include copper. The seed layer 1310 may be formed over the surface of the passivation layer 106. The seed layer 1310 may also be formed over a plurality of pad interconnects 101. The seed layer 1310 may be formed using a plating process.

[0128] Figure 13B Stage 3 illustrates and describes an example of the state after the photoresist layer 1320 is formed over the seed layer 1310. The photoresist layer 1320 may include an opening 1322. Deposition processes, lamination processes, exposure processes, and / or development processes can be used to form the photoresist layer 1320.

[0129] Figure 13B Stage 4 illustrates and describes an example of the state after the formation of multiple metallized interconnects 103. Multiple metallized interconnects 103 may be formed and coupled to a seed layer 1310. Multiple metallized interconnects 103 may be formed through openings 1322 in a photoresist layer 1320. Multiple metallized interconnects 103 may be formed using a plating process. The seed layer 1310 may be considered as part of the multiple metallized interconnects 103.

[0130] Figure 13C Stage 5 illustrates and describes an example of the state after the removal of photoresist layer 1320. A stripping process can be used to remove photoresist layer 1320.

[0131] Figure 13C Stage 6 illustrates and describes an example of the state after the photoresist layer 1330 has been formed over the seed layer 1310 and / or the plurality of metallized interconnects 103. The photoresist layer 1330 may include an opening 1332. Deposition processes, lamination processes, exposure processes, and / or development processes may be used to form the photoresist layer 1330.

[0132] Figure 13D Stage 7 illustrates and describes an example of the state after the formation of multiple metallized interconnects 105 and multiple metallized interconnects 107. Multiple metallized interconnects 105 may be formed and coupled to multiple metallized interconnects 103. Multiple metallized interconnects 107 may be formed and coupled to a seed layer 1310. Multiple metallized interconnects 105 and / or multiple metallized interconnects 107 may be formed through openings 1332 in a photoresist layer 1330. A plating process may be used to form multiple metallized interconnects 105 and / or multiple metallized interconnects 107.

[0133] Figure 13D Stage 8 illustrates and describes an example of the state after the removal of photoresist layer 1330. A stripping process can be used to remove photoresist layer 1330.

[0134] The method (in 1415) couples the integrated device to the carrier using an adhesive. Figure 13E Stage 9 illustrates and describes an example of the state after the integrated device 100 is placed and coupled to the carrier 1300 by an adhesive.

[0135] The method (at 1420) forms an encapsulation layer and couples it to the side surface of the integrated device. Figure 13E Stage 10 illustrates and describes an example of the state after the encapsulation layer 112 is formed and coupled to the integrated device 100. The encapsulation layer 112 may be coupled to the side surfaces and / or sidewalls of the integrated device 100. The encapsulation layer 112 may contact the side surfaces of the passivation layer 106, the side surfaces of the dielectric layer 140, and / or the side surfaces of the die substrate 120. The encapsulation layer 112 may be formed over the passivation layer 106. The encapsulation layer 112 may contact the top surface of the passivation layer 106. The encapsulation layer 112 may include molding materials, resins, and / or epoxy resins. The encapsulation layer 112 may be formed using compression molding, transfer molding, or liquid molding processes.

[0136] The method (in 1420) may also remove a portion of the encapsulation layer 112. Removing a portion of the encapsulation layer may include grinding away the top portion of the encapsulation layer 112. Figure 13F Phase 11 illustrates and describes the example of removing the encapsulation layer.

[0137] In some specific implementations, once the encapsulation layer is formed, the solder mask layer can be formed. Figure 13FStage 12 illustrates and describes an example of the state after the solder mask 108 has been formed over the encapsulation layer 112. The solder mask 108 may include openings 1334. Deposition processes, lamination processes, exposure processes, and / or development processes may be used to form the solder mask 108.

[0138] The method (in 1425) forms multiple under-bump metallized interconnects coupled to multiple metallized interconnects. Some of the under-bump metallized interconnects can be arranged in a spoke configuration. Figure 13G Stage 13 to Figure 13G Stage 14 illustrates an example of forming multiple bump-under-metallized interconnects. Figure 13G Stage 13 illustrates and describes an example of the state after the photoresist layer 1340 is formed over the solder mask layer 108. The photoresist layer 1340 may include an opening 1342. Deposition processes, lamination processes, exposure processes, and / or development processes can be used to form the photoresist layer 1340.

[0139] Figure 13G Stage 14 illustrates and describes an example of the state after the formation of multiple under-bump interconnects 109. Multiple under-bump interconnects 109 may be formed and coupled to multiple metallized interconnects 105 and / or multiple metallized interconnects 107. Multiple under-bump interconnects 109 may be formed through openings 1342 in the photoresist layer 1340. A plating process may be used to form the multiple under-bump interconnects 109.

[0140] The method (at 1430) forms multiple solder interconnects and couples them to multiple bump undermetallized interconnects. Figure 13H Stage 15 illustrates and describes an example of the state after multiple solder interconnects 110 have been formed and coupled to multiple under-bump metallized interconnects 109. A bonding process can be used to form the multiple solder interconnects 110 through openings 1342 in the photoresist layer 1340. A solder reflow process can be used to couple the multiple solder interconnects 110 to the multiple under-bump metallized interconnects 109.

[0141] Figure 13H Stage 16 illustrates and describes an example of the state after the removal of photoresist layer 1340. A stripping process can be used to remove photoresist layer 1340.

[0142] The method (in 1435) decouples the carrier and adhesive from the integrated device. Figure 13I Stage 17 illustrates and describes an example after the integrated device 100 is decoupled from the carrier 1300. The adhesive 1302 and the carrier 1300 can be separated from the integrated device 100.

[0143] In some implementations, the integrated device can be one or more integrated devices on a wafer. In such cases, the method (at 1440) can cleave a single wafer to form a separate integrated device.

[0144] Exemplary packages and integrated devices

[0145] Figure 15 A cross-sectional view of an integrated device 100 coupled to board 1502 is illustrated. Integrated device 100 may be coupled to board 1502 via a plurality of solder interconnects 110. Board 1502 may include a printed circuit board (PCB). Board 1502 may include a board dielectric layer 1520 and a plurality of board interconnects 1522. Any integrated device described in this disclosure may be coupled to the board. For example, integrated device 200 and / or integrated device 300 may be coupled to board 1502 via a plurality of solder interconnects.

[0146] Figure 16 A cross-sectional view of a package 1690 including two integrated devices is shown. Package 1690 includes integrated device 100 and integrated device 1600. Integrated device 1600 may be similar to integrated device 100.

[0147] The integrated device 1600 includes a die-substrate base 1602 and die interconnects 1604. The die-substrate base 1602 includes a die-substrate 1620, an active region 1622, and multiple through-substrate vias 1621. The active region 1622 may include multiple logic cells, multiple transistors, and / or multiple filters. Different implementations may use different types of transistors, such as field-effect transistors (FETs), planar FETs, finned FETs, and gate-all-around FETs. In some implementations, a front-end process (FEOL) may be used to fabricate the active region 1622 of the die-substrate 1620.

[0148] Die interconnect 1604 includes at least one dielectric layer 1640 and a plurality of die interconnects 1642. Die interconnect 1604 is coupled to a die substrate base 1602. The plurality of die interconnects 1642 are coupled to an active region 1622 of the die substrate base 1602. The plurality of die interconnects 1642 may be coupled to a plurality of through-substrate vias 1621. Die interconnect 1604 may also include a plurality of pad interconnects 1601 and a passivation layer 1606. In some embodiments, back-to-offline (BEOL) processes may be used to fabricate die interconnect 1604. Integrated device 1600 also includes an encapsulation layer 1612, a plurality of metallized interconnects 1607, and a plurality of solder interconnects 1610. Integrated device 1600 includes a plurality of back-side metallized interconnects 1624 coupled to the plurality of through-substrate vias 1621.

[0149] Integrated device 100 is coupled to integrated device 1600 via a plurality of solder interconnects 110. The front side of integrated device 100 is closest to the back side of integrated device 1600. The front side of integrated device 100 can be coupled to the back side of integrated device 1600 via a plurality of solder interconnects 110. The plurality of solder interconnects 110 can be coupled to metallized interconnects and / or under-bump metallized interconnects of integrated device 100. The plurality of solder interconnects 110 can be coupled to a plurality of back-side metallized interconnects 1624 and / or a plurality of through-substrate vias 1621 of integrated device 1600. Underfill 1680 can be located between integrated device 100 and integrated device 1600. In some embodiments, package 1690 can be coupled to board 1502 via a plurality of solder interconnects 1610.

[0150] It should be noted that the package may include any combination of the integrated devices (e.g., 100, 200, 300, 1610) described in this disclosure.

[0151] Exemplary process for manufacturing a package including integrated devices

[0152] In some specific implementations, manufacturing the package involves several processes. Figures 17A to 17C Exemplary steps for providing or manufacturing a package including integrated devices are illustrated. In some specific implementations, Figures 17A to 17C The process can be used to provide or manufacture Figure 16 The packaging component is 1690. However, Figures 17A to 17C The process can be used to manufacture any of the packages described in this disclosure.

[0153] It should be noted that Figures 17A to 17C The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0154] like Figure 17A As shown, stage 1 illustrates the state after several integrated devices (e.g., first integrated device 100) have been provided and coupled to carrier 1700. Adhesives may be used to couple the integrated devices to the carrier. The several integrated devices may be undrilled integrated devices that are part of a wafer.

[0155] Phase 2 illustrates the state after several integrated devices (e.g., a second integrated device, 1600) are coupled to a first integrated device (e.g., 100) via multiple solder interconnects (e.g., 110). A solder reflow process can be used to couple integrated device 1600 (e.g., the second integrated device) to integrated device 100 (e.g., the first integrated device). The multiple solder interconnects 110 can be coupled to (i) multiple back-side metallized interconnects 1624 of integrated device 1600 and (ii) multiple under-bump metallized interconnects 109 of integrated device 100.

[0156] like Figure 17B As shown, stage 3 illustrates the state after the bottom filler 1680 is provided between the integrated device 100 and the integrated device 1600.

[0157] Stage 4 illustrates the state after the encapsulation layer 1612 has been formed and coupled to the integrated device 1600. The encapsulation layer 1612 may include molding compound, resin, and / or epoxy resin. The encapsulation layer 1612 may be formed using compression molding, transfer molding, or liquid molding processes.

[0158] like Figure 17C As shown, stage 5 illustrates the process of cutting several integrated devices into packages. Cutting and / or slicing operations can be used to cut multiple integrated devices into packages that include a first integrated device (e.g., 100) and a second integrated device (e.g., 1600).

[0159] Phase 6 is illustrated in the state after the carrier 1700 is decoupled from the package. The carrier 1700 can be separated or ground off from the package 1690, which includes the integrated device 100 and the integrated device 1600.

[0160] An exemplary flowchart of a method for manufacturing a package including integrated devices.

[0161] In some specific implementations, manufacturing the package involves several processes. Figure 18 An exemplary flowchart illustrates a method 1800 for providing or manufacturing a package including integrated devices. In some specific implementations, Figure 18 Method 1800 can be used to provide or manufacture the product described in this disclosure. Figure 16 Package 1690. However, method 1800 can be used to provide or manufacture any package described in this disclosure.

[0162] It should be noted that Figure 18 The method may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture packages. In some implementations, the order of processes may be changed or modified.

[0163] The method (in 1805) provides multiple first integrated devices and couples them to a carrier. Figure 17A Phase 1 illustrates and describes an example of the state after several integrated devices (e.g., the first integrated device 100) have been provided and coupled to the carrier 1700. Adhesives may be used to couple the integrated devices to the carrier.

[0164] The method (in 1810) couples multiple second integrated devices to multiple first integrated devices via multiple solder interconnects. Figure 17A Phase 2 illustrates and describes an example of the state after several integrated devices (e.g., second integrated device, 1600) are coupled to a first integrated device (e.g., 100) via multiple solder interconnects (e.g., 110). A solder reflow process can be used to couple integrated device 1600 (e.g., second integrated device) to integrated device 100 (e.g., first integrated device).

[0165] The method (in 1815) provides an underfill material between a plurality of first integrated devices and a plurality of second integrated devices. Figure 17B Phase 3 illustrates and describes an example of the state after the bottom filler 1680 is provided between the integrated device 100 and the integrated device 1600.

[0166] The method (in 1820) forms an encapsulation layer that encapsulates a plurality of second integrated devices. The encapsulation layer may contact the side surfaces of the plurality of second integrated devices. Figure 17B Stage 4 illustrates and describes an example of the state after the encapsulation layer 1612 has been formed and coupled to the integrated device 1600. The encapsulation layer 1612 may include a molding compound, resin, and / or epoxy resin. The encapsulation layer 1612 may be formed using compression molding, transfer molding, or liquid molding processes.

[0167] The method (in 1825) cuts multiple first integrated devices and multiple second integrated devices into a package comprising multiple stacked integrated devices. Figure 17C Stage 5 illustrates and describes an example of the state after several integrated devices have been cut into packages. Cutting and / or slicing operations can be used to cut multiple integrated devices into packages that include a first integrated device (e.g., 100) and a second integrated device (e.g., 1600).

[0168] The method (in 1830) decouples the carrier from the package. Figure 17C Phase 6 illustrates and describes an example of the state after the package is decoupled by the carrier 1700. The carrier 1700 can be detached or ground off from the package 1690, which includes the integrated device 100 and the integrated device 1600.

[0169] Exemplary electronic devices

[0170] Figure 19Examples are illustrated of various electronic devices that can integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1902, laptop computer device 1904, fixed-location terminal device 1906, wearable device 1908, or motor vehicle 1910 may include device 1900 as described herein. For example, device 1900 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 19 The illustrated devices 1902, 1904, 1906, and 1908, as well as vehicle 1910, are merely exemplary. Other electronic devices may also feature device 1900, including but not limited to devices (e.g., electronic devices) comprising the following group: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (such as watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (such as autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0171] Figures 1 to 12 , Figures 13A to 13I , Figures 14 to 16 , Figures 17A to 17C and / or Figures 18 to 19 One or more of the illustrated components, processes, features, and / or functions may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1 to 12 , Figures 13A to 13I , Figures 14 to 16 , Figures 17A to 17C and / or Figures 18 to 19 The corresponding descriptions herein are not limited to dies and / or ICs. In some specific implementations, the following can be used: Figures 1 to 12 , Figures 13A to 13I , Figures 14 to 16 , Figures 17A to 17C and / or Figures 18 to 19The corresponding description is for manufacturing, establishing, providing, and / or producing equipment and / or integrated devices. In some specific implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0172] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts may be shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0173] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. An object coupled to another object may be coupled to at least a portion of another object. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "enclosing" means that an object can partially enclose or completely enclose another object. A first component "located" within a second component can mean that the first component is "partially located" within or "completely located" within the second component. A first component "embedded" within a second component can mean that the first component is "partially embedded" within or "completely embedded" within the second component. The terms "top" and "bottom" are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term "on top of" as used in this application in the context of one component being on top of another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, "first component on top of second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component "in" the second component can be partially or entirely located within the second component.As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "A plurality of" components may include all possible components or only some of all possible components. For example, if the device comprises ten components, the use of the term "a plurality of components" may refer to all ten components or only some of those ten components.

[0174] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0175] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0176] Further examples are described below to facilitate understanding of the invention.

[0177] Aspect 1: An integrated device comprising a die substrate; die interconnects coupled to the die substrate; an encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnects; a plurality of pad interconnects coupled to the die interconnects; and a plurality of metallized interconnects, wherein one or more metallized interconnects from the plurality of metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects.

[0178] Aspect 2: The integrated device according to aspect 1, wherein at least some of the metallized interconnects from the plurality of metallized interconnects are arranged in a radial configuration.

[0179] Aspect 3: The integrated device according to Aspect 2, wherein the plurality of metallized interconnects comprises: a first pad metallized interconnect configured as an axis of the spoke configuration; a first trace metallized interconnect coupled to the first pad metallized interconnect; a second pad metallized interconnect coupled to the first trace metallized interconnect; a second trace metallized interconnect coupled to the first pad metallized interconnect; and a third pad metallized interconnect coupled to the second trace metallized interconnect.

[0180] Aspect 4: The integrated device according to aspect 3, wherein the first trace metallized interconnect and the second trace metallized interconnect each have a corresponding thickness less than the thickness of the first pad metallized interconnect.

[0181] Aspect 5: The integrated device according to aspect 3, wherein the first pad metallized interconnect includes a first width, the first width being greater than the second width of the second pad metallized interconnect.

[0182] Aspect 6: The integrated device according to Aspect 2, wherein the plurality of metallized interconnects includes: a first pad metallized interconnect configured as an axis of the spoke configuration; a first metallized interconnect coupled to the first pad metallized interconnect; a second pad metallized interconnect coupled to the first metallized interconnect; and a third pad metallized interconnect coupled to the first metallized interconnect.

[0183] Aspect 7: The integrated device according to aspect 1, wherein the die interconnect is located between the die substrate and the plurality of metallized interconnects, and wherein the encapsulation layer laterally surrounds at least a portion of the plurality of metallized interconnects.

[0184] Aspect 8: The integrated device according to aspect 1 further includes a passivation layer coupled to the die interconnect, wherein the encapsulation layer is coupled to the passivation layer.

[0185] Aspect 9: The integrated device according to aspect 8 further includes a solder mask layer coupled to the encapsulation layer, wherein the encapsulation layer is located between the passivation layer and the solder mask layer.

[0186] Aspect 10: The integrated device according to aspect 1, wherein the integrated device is part of a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0187] Aspect 11: A package comprising a first integrated device, the first integrated device comprising: a die substrate; die interconnects coupled to the die substrate; an encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnects; a plurality of pad interconnects coupled to the die interconnects; and a plurality of metallized interconnects, wherein one or more metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects; and a second integrated device coupled to the first integrated device via a plurality of solder interconnects.

[0188] Aspect 12: The package according to aspect 11, wherein at least some of the metallized interconnects from the plurality of metallized interconnects are arranged in a spoke configuration.

[0189] Aspect 13: The package according to aspect 12, wherein the plurality of metallized interconnects includes: a first pad metallized interconnect configured as an axis of the spoke configuration; a first trace metallized interconnect coupled to the first pad metallized interconnect; a second pad metallized interconnect coupled to the first trace metallized interconnect; a second trace metallized interconnect coupled to the first pad metallized interconnect; and a third pad metallized interconnect coupled to the second trace metallized interconnect.

[0190] Aspect 14: The package according to aspect 13, wherein the first trace metallized interconnect and the second trace metallized interconnect each have a corresponding thickness less than the thickness of the first pad metallized interconnect.

[0191] Aspect 15: The package according to aspect 11, wherein the die interconnect is located between the die substrate and the plurality of metallized interconnects, and wherein the encapsulation layer laterally surrounds at least a portion of the plurality of metallized interconnects.

[0192] Aspect 16: The package according to aspect 11, wherein the first integrated device includes a first front side and a first back side, and wherein the second integrated device includes a second front side and a second back side.

[0193] Aspect 17: The package according to aspect 16, wherein the second back side of the second integrated device is coupled to the first front side of the first integrated device.

[0194] Aspect 18: The package according to aspect 16, wherein the first back side of the first integrated device is coupled to the second front side of the second integrated device.

[0195] Aspect 19: The package according to aspect 11 further includes a second encapsulation layer coupled to a side surface of the second integrated device.

[0196] Aspect 20: The package according to aspect 11, wherein at least some of the metallized interconnects from the plurality of metallized interconnects are arranged in a first axis-spoke configuration, wherein the second integrated device includes a second plurality of metallized interconnects, and wherein some of the metallized interconnects from the second plurality of metallized interconnects are arranged in a second axis-spoke configuration.

[0197] Aspect 21: A device comprising: a die substrate; die interconnects coupled to the die substrate; an encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnects; a plurality of pad interconnects coupled to the die interconnects; and a plurality of metallized interconnects, wherein one or more metallized interconnects from the plurality of metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects.

[0198] Aspect 22: The device according to aspect 21, wherein at least some of the metallized interconnects from the plurality of metallized interconnects are arranged in a radial configuration.

[0199] Aspect 23: The device according to aspect 22, wherein the plurality of metallized interconnects comprises: a first pad metallized interconnect configured as an axis of the spoke configuration; a first trace metallized interconnect coupled to the first pad metallized interconnect; a second pad metallized interconnect coupled to the first trace metallized interconnect; a second trace metallized interconnect coupled to the first pad metallized interconnect; and a third pad metallized interconnect coupled to the second trace metallized interconnect.

[0200] Aspect 24: The device according to aspect 23, wherein the first trace metallized interconnect and the second trace metallized interconnect each have a corresponding thickness less than the thickness of the first pad metallized interconnect.

[0201] Aspect 25: The device according to aspect 23, wherein the first pad metallized interconnect includes a first width, the first width being greater than the second width of the second pad metallized interconnect.

[0202] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An integrated device, the integrated device comprising: die substrate; A die interconnect coupled to the die substrate; An encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnect; Multiple pad interconnects coupled to the die interconnects; and A plurality of metallized interconnects, wherein one or more metallized interconnects from the plurality of metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects.

2. The integrated device of claim 1, wherein at least some of the metallized interconnects from the plurality of metallized interconnects are arranged in a radial configuration.

3. The integrated device of claim 2, wherein the plurality of metallized interconnects comprises: A first pad metallized interconnect is configured as the axis of the spoke configuration; A first trace metallized interconnect, the first trace metallized interconnect being coupled to the first pad metallized interconnect; A second pad metallized interconnect is coupled to the first trace metallized interconnect; A second trace metallized interconnect is coupled to the first pad metallized interconnect; and A third pad metallized interconnect is coupled to the second trace metallized interconnect.

4. The integrated device of claim 3, wherein the first trace metallized interconnect and the second trace metallized interconnect each have a corresponding thickness less than the thickness of the first pad metallized interconnect.

5. The integrated device of claim 3, wherein the first pad metallized interconnect includes a first width greater than the second width of the second pad metallized interconnect.

6. The integrated device of claim 2, wherein the plurality of metallized interconnects comprises: A first pad metallized interconnect is configured as the axis of the spoke configuration; A first metallized interconnect, the first metallized interconnect being coupled to the first pad metallized interconnect; A second pad metallized interconnect is coupled to the first metallized interconnect; and A third pad metallized interconnect is coupled to the first metallized interconnect.

7. The integrated device according to claim 1, The die interconnect is located between the die substrate and the plurality of metallized interconnects, and The encapsulation layer laterally surrounds at least a portion of the plurality of metallized interconnects.

8. The integrated device of claim 1, further comprising a passivation layer coupled to the die interconnect, wherein the encapsulation layer is coupled to the passivation layer.

9. The integrated device of claim 8, further comprising a solder mask layer coupled to the encapsulation layer, wherein the encapsulation layer is located between the passivation layer and the solder mask layer.

10. The integrated device of claim 1, wherein the integrated device is part of a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

11. A package, the package comprising: A first integrated device, the first integrated device comprising: die substrate; A die interconnect coupled to the die substrate; An encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnect; Multiple pad interconnects, the multiple pad interconnects being coupled to the die interconnects; and A plurality of metallized interconnects, wherein one or more metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects; and A second integrated device is coupled to the first integrated device via a plurality of solder interconnects.

12. The package of claim 11, wherein at least some of the metallized interconnects from the plurality of metallized interconnects are arranged in a spoke configuration.

13. The package of claim 12, wherein the plurality of metallized interconnects comprises: A first pad metallized interconnect is configured as the axis of the spoke configuration; A first trace metallized interconnect, the first trace metallized interconnect being coupled to the first pad metallized interconnect; A second pad metallized interconnect is coupled to the first trace metallized interconnect; A second trace metallized interconnect is coupled to the first pad metallized interconnect; and A third pad metallized interconnect is coupled to the second trace metallized interconnect.

14. The package of claim 13, wherein the first trace metallized interconnect and the second trace metallized interconnect each have a corresponding thickness less than the thickness of the first pad metallized interconnect.

15. The package according to claim 11, The die interconnect is located between the die substrate and the plurality of metallized interconnects, and The encapsulation layer laterally surrounds at least a portion of the plurality of metallized interconnects.

16. The package according to claim 11, The first integrated device includes a first front side and a first back side, and The second integrated device includes a second front side and a second back side.

17. The package of claim 16, wherein the second back side of the second integrated device is coupled to the first front side of the first integrated device.

18. The package of claim 16, wherein the first back side of the first integrated device is coupled to the second front side of the second integrated device.

19. The package of claim 11, further comprising a second encapsulation layer coupled to a side surface of the second integrated device.

20. The package according to claim 11, At least some of the metallized interconnects from the plurality of metallized interconnects are arranged in a first-axis-spoke configuration. The second integrated device includes a second plurality of metallized interconnects, and Some of the metallized interconnects from the second plurality of metallized interconnects are arranged in a second axial-spoke configuration.

21. A device, the device comprising: die substrate; A die interconnect coupled to the die substrate; An encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnect; Multiple pad interconnects coupled to the die interconnects; and A plurality of metallized interconnects, wherein one or more metallized interconnects from the plurality of metallized interconnects are coupled to one or more pad interconnects from the plurality of pad interconnects.

22. The device of claim 21, wherein at least some of the metallized interconnects from the plurality of metallized interconnects are arranged in a radial-axial configuration.

23. The device of claim 22, wherein the plurality of metallized interconnects comprises: A first pad metallized interconnect is configured as the axis of the spoke configuration; A first trace metallized interconnect, the first trace metallized interconnect being coupled to the first pad metallized interconnect; A second pad metallized interconnect is coupled to the first trace metallized interconnect; A second trace metallized interconnect is coupled to the first pad metallized interconnect; and A third pad metallized interconnect is coupled to the second trace metallized interconnect.

24. The device of claim 23, wherein the first trace metallized interconnect and the second trace metallized interconnect each have a corresponding thickness less than the thickness of the first pad metallized interconnect.

25. The device of claim 23, wherein the first pad metallized interconnect includes a first width, the first width being greater than the second width of the second pad metallized interconnect.

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