High pressure resistant electrofluidic chip and method of forming same

Abstract

The application discloses a high-pressure-resistant electrofluidic chip and a forming method thereof. The electrofluidic chip comprises a jet plate, bosses, an electrode structure and a passivation layer. The surface of the jet plate is provided with a plurality of through jet holes. The bottom surface of the jet plate is provided with a plurality of jet grooves. The plurality of jet grooves correspond to the plurality of jet holes one by one. The jet grooves are in communication with the corresponding jet holes. The plurality of bosses are arranged in the plurality of jet grooves respectively, and the bosses are arranged at the groove bottoms of the jet grooves. The bottom surface of each boss is provided with a through hole in communication with the jet hole. The electrode structure is arranged at the bottom surface of the jet plate. The electrode structure is suitable for arranging an independent electric field at each jet hole. The passivation layer covers the electrode structure, and the passivation layer comprises a PI layer. The PI passivation layer is arranged to cover the electrode structure, so that the insulation stability of the electrode structure is improved.

Description

Technical Field

[0001] This invention relates to the field of inkjet printing technology, and in particular to a high-voltage resistant current-carrying chip and its molding method. Background Technology

[0002] Inkjet printing, as a direct-write additive manufacturing technology, boasts advantages such as no need for masks, flexible production, and high material utilization, showing promising application prospects in fields such as printed displays, printed circuits, and printed solar cells. Electrohydraulic inkjet printing, in particular, uses an electric field as the primary driving force, significantly enhancing the ink's driving power and enabling the printing of high-viscosity inks. Furthermore, because the ink is ejected locally from the meniscus, the resulting droplet size can be much smaller than the nozzle diameter, thus significantly improving printing resolution. Electrohydraulic inkjet printing technology overcomes two major drawbacks of traditional inkjet printing technologies and has broad application prospects.

[0003] By machining jet holes on a substrate and then placing electrodes at the jet holes on the bottom surface of the substrate, an electric field is applied at the jet holes to eject the functional liquid. In electrohydraulic printing, relatively high voltages (several kilovolts) are required to eject the functional liquid. However, directly controlling the high-voltage electrodes on the bottom surface of the substrate is not only costly but also difficult to implement. Therefore, a base electrode is first applied to the functional liquid to reduce the voltage required to apply to the electrodes on the bottom surface of the substrate, thereby achieving control of the electrodes.

[0004] Generally, a passivation layer of silicon dioxide needs to be deposited on the electrode surface to prevent functional liquid from overflowing to the electrode and causing a short circuit, thus ensuring the normal operation of the chip.

[0005] However, the silicon dioxide passivation layer is formed by deposition, and its thickness is relatively thin, making it susceptible to breakdown. Furthermore, after the silicon dioxide passivation layer is formed, it has high internal stress, and changes in operating temperature can easily cause the passivation layer to crack, thus losing its insulating effect. Summary of the Invention

[0006] One objective of this invention is to provide a high-voltage resistant current-carrying chip that can be flexibly adjusted to adapt to high-frequency signals.

[0007] Another objective of this invention is to provide a method for molding a high-voltage resistant current-carrying chip that can be flexibly adjusted to adapt to high-frequency signals.

[0008] To achieve the above objectives, the present invention provides a high-voltage resistant current-carrying chip and its forming method, comprising a spray plate, an electrode structure, a passivation layer, and multiple bosses. The spray plate has multiple through-holes on its surface and multiple spray grooves on its bottom surface, each spray groove corresponding to one of the spray holes and communicating with its corresponding spray hole. Multiple bosses are respectively arranged within the multiple spray grooves, with each boss located at the bottom of the groove. A through-hole is formed on the bottom surface of each boss, communicating with the spray hole. The electrode structure is arranged on the bottom surface of the spray plate and is adapted to generate an independent electric field at each spray hole. The passivation layer covers the electrode structure and includes a PI layer.

[0009] Preferably, a spin coating process is used to spin-coat the PI material onto the electrode structure to form the passivation layer.

[0010] Preferably, the thickness of the passivation layer is 5-15 micrometers.

[0011] Preferably, the spray plate includes a first substrate and a second substrate. The bottom surface of the first substrate is integrally formed with a plurality of protrusions. The spray holes are formed on the first substrate. The plurality of spray holes correspond one-to-one with the plurality of protrusions in the vertical direction, and the spray holes penetrate to the bottom surface of the protrusions. The spray grooves are formed through the second substrate. The second substrate is connected to the bottom surface of the first substrate. The plurality of protrusions are located in the plurality of spray grooves.

[0012] Preferably, the first substrate comprises a silicon substrate, and the second substrate comprises a glass substrate.

[0013] Preferably, the electrode structure includes a plurality of electrode rings and leads, wherein the plurality of electrode rings are arranged around the plurality of spray grooves respectively; the plurality of leads are respectively connected to the plurality of electrode rings, and the plurality of leads extend to the edge of the spray plate.

[0014] Preferably, the bottom surface of the boss is higher than the bottom surface of the spray plate.

[0015] Preferably, the high-voltage resistant current-carrying chip further includes a hydrophobic layer, which covers the passivation layer, the bottom surface of the boss, and the bottom surface of the spray plate.

[0016] Compared with existing technologies, this invention provides a high-voltage resistant current-current chip. By employing a PI (polyimide) layer as a passivation layer covering the electrode structure, and utilizing the excellent dielectric strength and insulation resistance of PI material, its voltage withstand strength is far higher than that of a silicon dioxide layer of the same thickness, providing reliable insulation protection in high-voltage electric field environments of several kilovolts. Compared to the shortcomings of traditional silicon dioxide passivation layers, which are limited by thickness and cannot withstand high voltages, the PI passivation layer can be formed using a spin-coating process to increase its thickness and achieve a higher breakdown voltage. This effectively prevents high-voltage breakdown between the electrode and the functional liquid or between the electrode and the external environment, ensuring the electrical safety of the current-current chip under high-voltage operating conditions and providing a key guarantee for the stable implementation of high-voltage driving schemes in current-current inkjet printing technology.

[0017] PI material possesses excellent flexibility and a low elastic modulus. Its internal stress after film deposition is significantly lower than that of deposited silicon dioxide films. Furthermore, PI's coefficient of thermal expansion is more compatible with the spray plate or metal electrodes. When the chip's operating temperature changes or the ambient temperature fluctuates, the PI passivation layer can flexibly adapt to the deformation of the spray plate, avoiding microcracks and peeling caused by accumulated thermal stress. Simultaneously, the PI layer exhibits excellent coverage and adhesion to the electrode structure, tightly covering it and forming a continuous and complete insulating barrier. Even under harsh operating conditions of long-term high voltage and temperature cycling, it maintains stable insulation performance, significantly extending the lifespan of current-current chips.

[0018] The PI passivation layer can be uniformly formed on the bottom surface of the spray plate using mature coating processes such as spin coating, spraying, and screen printing. Compared to the stringent requirements for equipment vacuum and temperature uniformity in silicon dioxide deposition, the PI coating process is simpler and more flexible, and has greater adaptability to substrate morphology. It can completely cover the edges and steps of the electrode structure, avoiding the defect of easy breakage of deposited films at steps. At the same time, the PI curing process is compatible with standard semiconductor back-end processes, eliminating the need for high-temperature annealing, reducing the risk of thermal damage to the previously formed electrode structure, and significantly improving the manufacturing yield and process reliability of current-current chips.

[0019] To achieve the above objectives, the present invention provides a method for molding a high-voltage resistant current-current chip, comprising the following steps: S100, obtaining a silicon substrate as a first substrate, and processing an array of jet holes on the surface of the first substrate, the jet holes being arranged through the first substrate; S200, etching the bottom surface of the first substrate to partially thin the first substrate and form a plurality of protrusions; S300, obtaining a glass substrate as a second substrate, and processing a plurality of through jet grooves on the surface of the second substrate; S400, fixing the second substrate to the bottom surface of the first substrate to form a jet plate, wherein the plurality of protrusions are respectively located within the plurality of jet grooves; S500, patterning an electrode structure on the bottom surface of the second substrate; S600, forming a passivation layer on the surface of the electrode structure; S700, forming a hydrophobic layer on the surface of the passivation layer, the bottom surface of the protrusions, and the bottom surface of the second substrate.

[0020] Preferably, the passivation layer is formed on the surface of the electrode structure using a spin coating process, in which PI material is spin-coated onto the electrode structure to form the passivation layer.

[0021] Another embodiment of the present invention provides a method for molding a high-voltage resistant current-current chip. Since this method for molding a high-voltage resistant current-current chip is used to mold the aforementioned high-voltage resistant current-current chip, the beneficial effects of this method are the same as those of the aforementioned high-voltage resistant current-current chip, and will not be repeated here. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of a high-voltage resistant current-carrying chip provided in an embodiment of the present invention; Figure 2 for Figure 1 Enlarged view of point A in the middle; Figure 3 A schematic diagram of the bottom surface of the spray plate provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a high-voltage resistant current-carrying chip molding method provided in another embodiment of the present invention.

[0024] In the figure: 1. Spray plate; 11. First substrate; 11a. Spray hole; 11b. Boss; 12. Second substrate; 12a. Spray groove; 2. Electrode structure; 21. Electrode ring; 22. Lead wire; 3. Passivation layer; 4. Hydrophobic layer. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] This invention provides a high-voltage resistant current-carrying chip and its molding method. By arranging a PI passivation layer to cover the electrode structure, the insulation stability of the electrode structure is improved. This invention solves the technical problems in related technologies where the passivation layer is thin due to process limitations, posing a risk of voltage breakdown, and where internal stress easily leads to cracking of the passivation layer, causing it to lose its insulating function.

[0027] Reference Figure 1 and Figure 2 A high-voltage resistant current-carrying chip includes a spray plate 1, multiple protrusions 11b, an electrode structure 2, and a passivation layer 3.

[0028] Reference Figure 3 The spray plate 1 has multiple through-holes 11a on its surface, and the spray holes 11a are arranged in an array. In this embodiment, the spray holes 11a are arranged in multiple rows, and each row of spray holes 11a is staggered.

[0029] This configuration, with its multiple rows of staggered jet holes 11a, increases the spacing between adjacent jet holes 11a in each row, thereby reducing electric field crosstalk between jet holes 11a. Furthermore, the interpolation of each row of jet holes 11a ensures a high density of jet holes 11a, meeting the high-efficiency printing requirements of large-size panels.

[0030] Reference Figure 1 and Figure 2 The bottom surface of the spray plate 1 has multiple spray grooves 12a, each corresponding to a spray hole 11a, and the spray grooves 12a are connected to their corresponding spray holes 11a. That is, the lower opening of the spray hole 11a is located inside the spray groove 12a.

[0031] Multiple protrusions 11b are respectively arranged in multiple spray grooves 12a, and the protrusions 11b are arranged at the bottom of the spray grooves 12a. A through hole is opened on the bottom surface of the protrusion 11b, and the through hole is connected to the spray hole 11a.

[0032] Due to the arrangement of the spray groove 12a, the boss 11b is separated, ensuring that the functional liquid forms a stable Taylor cone on the bottom surface of the boss 11b. Furthermore, the distance between the boss 11b and the groove wall of the spray groove 12a can accommodate the functional liquid overflowing from the boss 11b, preventing the functional liquid from spreading to the bottom of the second substrate 12.

[0033] Preferably, the center line of the spray groove 12a is aligned with the center line of its corresponding boss 11b, so as to ensure that the distance between each part of the boss 11b and the wall of the spray groove 12a is consistent, and to avoid the functional liquid from spreading due to the boss 11b being too close to the wall of the spray groove 12a.

[0034] In this embodiment, preferably, the diameter of the spray groove 12a is 1.5-3 times the diameter of the boss 11b.

[0035] The bottom surface of the boss 11b is higher than the bottom surface of the spray plate 1, that is, the bottom surface of the boss 11b is located inside the spray groove 12a.

[0036] This configuration provides an installation position for the electrode structure 2 on the bottom surface of the spray plate 1, and also increases the distance between the boss 11b and the electrode structure 2, ensuring a height difference between the boss 11b and the electrode structure 2. This ensures the potential difference between the boss 11b and the electrode structure 2, guarantees the stability of the electric field force applied to the functional liquid, and ensures printing quality.

[0037] Since the boss 11b is arranged in the spray tank 12a and is located in the middle of the spray tank 12a, the spray tank 12a provides storage space for the functional liquid. Some of the functional liquid overflowing from the bottom surface of the boss 11b will be collected in the area between the tank wall of the spray tank 12a and the boss 11b, thus preventing the functional liquid from overflowing to the bottom surface of the second substrate 12, protecting the electrode structure 2 on the bottom surface of the second substrate 12, and preventing contamination of the outer surface of the chip.

[0038] Reference Figure 1 and Figure 2 In this embodiment, the center lines of a corresponding set of injection holes 11a, injection grooves 12a and bosses 11b are arranged collinearly.

[0039] In this embodiment, the center lines of the injection hole 11a and its corresponding boss 11b are collinear to ensure that the functional liquid flows out from the middle of the bottom surface of the boss 11b, and to ensure that the functional liquid forms a stable Taylor cone on the bottom surface of the boss 11b, thereby improving printing stability and accuracy.

[0040] In this embodiment, the diameter of the bottom surface of the boss 11b is 1.5-3 times the diameter of the injection hole 11a.

[0041] Specifically, the spray plate 1 includes a first substrate 11 and a second substrate 12, with the second substrate 12 fixed to the bottom surface of the first substrate 11, thereby forming the spray plate 1.

[0042] Reference Figure 1 and Figure 2 Specifically, the bottom surface of the first substrate 11 is integrally formed with multiple protrusions 11b, and the top surface of the first substrate 11 is provided with multiple through-holes 11a. The multiple through-holes 11a correspond one-to-one with the multiple protrusions 11b in the vertical direction, and the through-holes 11a extend to the bottom surface of the protrusions 11b. The functional liquid enters the through-holes 11a from the top of the first substrate 11 and is then ejected from the openings of the through-holes 11a on the bottom surface of the protrusions 11b.

[0043] Specifically, positions for multiple protrusions 11b are reserved on the bottom surface of the first substrate 11, and the remaining portion of the bottom surface of the first substrate 11 is thinned by etching to form multiple protrusions 11b. It can be understood that the protrusions 11b are integrally formed by thinning the first substrate 11 through etching.

[0044] With this configuration, the protrusion 11b and the first substrate 11 have good integrity. Since the protrusion 11b is part of the first substrate 11, it is easier to ensure the positional accuracy of the protrusion 11b and the injection hole 11a, thereby ensuring printing accuracy.

[0045] The bottom surface of the boss 11b is the original bottom surface of the first substrate 11. There is no need to etch the bottom surface of the boss 11b. Since the bottom surface of the boss 11b has not been further processed, its flatness is guaranteed. Therefore, the functional liquid can be formed more stably on the bottom surface of the boss 11b, thus ensuring the printing quality.

[0046] Since the jet holes 11a are arranged through the first substrate 11, the processing depth of the jet holes 11a is easier to ensure, thereby ensuring the processing consistency of all jet holes 11a and ensuring printing consistency.

[0047] Reference Figure 1 and Figure 2 The second substrate 12 has multiple through-hole spray grooves 12a on its surface. The second substrate 12 is connected to the bottom surface of the first substrate 11, and multiple bosses 11b are located in the multiple spray grooves 12a respectively.

[0048] Since the spray groove 12a is arranged through the second substrate 12, the processing depth of the spray groove 12a is easier to ensure.

[0049] This configuration, by forming the injection holes 11a and bosses 11b on the first substrate 11 and the injection grooves 12a on the second substrate 12, and then assembling them to form a chip, ensures the processing accuracy and efficiency of the bosses 11b, injection holes 11a, and injection grooves 12a, which is more in line with the needs of mass production. It reduces the processing difficulty of the injection holes 11a and injection grooves 12a and makes it easier to ensure the forming accuracy of the injection holes 11a and injection grooves 12a.

[0050] In this embodiment, the first substrate 11 and the second substrate 12 are fixed by anodic bonding.

[0051] Reference Figure 1 and Figure 2 The electrode structure 2 is arranged on the spray plate 1, and the electrode structure 2 is adapted to arrange an independent electric field at each spray hole 11a.

[0052] In this embodiment, the electrode structure 2 is arranged on the surface of the second substrate 12.

[0053] The first substrate 11 is a silicon substrate or a glass substrate, and the second substrate 12 is a glass substrate.

[0054] With this configuration, since the electrode structure 2 is arranged on the glass substrate, the insulation performance of the glass substrate prevents the spray plate 1 from being broken down, thereby improving the applicable voltage range of the current-current chip.

[0055] Specifically, the electrode structure 2 includes multiple electrode rings 21 and multiple leads 22, with the multiple electrode rings 21 arranged around multiple spray grooves 12a. The multiple leads 22 are connected to the multiple electrode rings 21, and all the multiple leads 22 extend to the edge of the spray plate 1.

[0056] In this embodiment, electrode ring 21 and lead wire 22 are formed by deposition process.

[0057] The electrode ring 21 and the lead wire 22 are made of one or more of the following materials: gold, silver, copper, aluminum, and chromium.

[0058] The passivation layer 3 covers the electrode structure 2, and the passivation layer 3 includes a PI layer.

[0059] Reference Figure 1 and Figure 2 Specifically, the passivation layer 3 covers the electrode ring 21 and the lead 22. The end of the lead 22 away from the electrode ring 21 is not covered by the passivation layer 3, so as to reserve the connection position with the flexible circuit board.

[0060] This configuration, using a PI (polyimide) layer as the passivation layer 3 covering the electrode structure 2, leverages the excellent dielectric strength and insulation resistance of PI material. Its voltage withstand strength is far higher than that of a silicon dioxide layer of the same thickness, providing reliable insulation protection in high-voltage electric field environments of several kilovolts. Compared to the shortcomings of traditional silicon dioxide passivation layers 3, which are limited by thickness and cannot withstand high voltages, the PI passivation layer can be formed using a spin-coating process to increase its thickness and achieve a higher breakdown voltage. This effectively prevents high-voltage breakdown between the electrode and the functional liquid or between the electrode and the external environment, ensuring the electrical safety of the current-current chip under high-voltage operating conditions and providing a key guarantee for the stable implementation of high-voltage driving schemes in current-current inkjet printing technology.

[0061] PI material possesses excellent flexibility and a low elastic modulus. Its internal stress after film formation is significantly lower than that of deposited silicon dioxide films. Furthermore, PI's coefficient of thermal expansion is more compatible with the spray plate 1 or the metal electrode. When the chip operating temperature changes or the ambient temperature fluctuates, the PI passivation layer can flexibly adapt to the deformation of the spray plate 1, avoiding microcracks and peeling caused by accumulated thermal stress. Simultaneously, the PI layer exhibits excellent coverage and adhesion to the electrode structure 2, tightly covering it and forming a continuous and complete insulating barrier. Even under harsh operating conditions of long-term high voltage and temperature cycling, it can maintain stable insulation performance, significantly extending the lifespan of the current-current chip.

[0062] In this embodiment, a spin coating process is used to spin-coat PI material onto the electrode structure 2 to form the passivation layer 3.

[0063] The PI passivation layer can be uniformly formed on the bottom surface of the spray plate 1 using mature coating processes such as spin coating, spraying, and screen printing. Compared with the stringent requirements of silicon dioxide deposition process for equipment vacuum and temperature uniformity, the PI coating process is simpler and more flexible, and has a stronger adaptability to substrate morphology. It can completely cover the edges and steps of the electrode structure 2, avoiding the defect of easy breakage of deposited films at steps. At the same time, the PI curing process is compatible with standard semiconductor back-end processes, eliminating the need for high-temperature annealing, reducing the risk of thermal damage to the previously formed electrode structure 2, and significantly improving the manufacturing yield and process reliability of current-current chips.

[0064] In this embodiment, the thickness of the passivation layer 3 is 5-15 micrometers.

[0065] The high-voltage resistant current-carrying chip also includes a hydrophobic layer 4, which covers the passivation layer 3, the bottom surface of the boss 11b, and the bottom surface of the spray plate 1.

[0066] Specifically, the hydrophobic layer 4 is made of materials including phenelzine or Teflon, and is applied to the bottom of the sputtering plate 1 via a sputtering process to cover the structure of the bottom surface of the sputtering plate 1, namely, the surface of the passivation layer 3, the bottom surface of the sputtering plate 1, and the bottom surface of the boss 11b. In this embodiment, the end of the lead 22 away from the electrode ring 21 is blocked by a mask, and the hydrophobic layer 4 is formed during sputtering. The end of the lead 22 is not covered by the hydrophobic layer 4 to leave a connection position with the flexible circuit board.

[0067] This arrangement of the hydrophobic layer 4 allows the functional liquid to form a more stable meniscus on the bottom surface of the boss 11b, preventing the functional liquid from overflowing.

[0068] This invention provides a high-voltage resistant current-current chip. By employing a PI (polyimide) layer as the passivation layer 3 covering the electrode structure 2, and utilizing the excellent dielectric strength and insulation resistance of PI material, its voltage withstand strength is far higher than that of a silicon dioxide layer of the same thickness, providing reliable insulation protection in high-voltage electric field environments of several kilovolts. Compared to the shortcomings of traditional silicon dioxide passivation layers 3, which are limited by thickness and cannot withstand high voltages, the PI passivation layer can be formed using a spin-coating process to increase its thickness and achieve a higher breakdown voltage. This effectively prevents high-voltage breakdown between the electrode and the functional liquid or between the electrode and the external environment, ensuring the electrical safety of the current-current chip under high-voltage operating conditions and providing a key guarantee for the stable implementation of high-voltage driving schemes in current-current inkjet printing technology.

[0069] PI material possesses excellent flexibility and a low elastic modulus. Its internal stress after film formation is significantly lower than that of deposited silicon dioxide films. Furthermore, PI's coefficient of thermal expansion is more compatible with the spray plate 1 or the metal electrode. When the chip operating temperature changes or the ambient temperature fluctuates, the PI passivation layer can flexibly adapt to the deformation of the spray plate 1, avoiding microcracks and peeling caused by accumulated thermal stress. Simultaneously, the PI layer exhibits excellent coverage and adhesion to the electrode structure 2, tightly covering it and forming a continuous and complete insulating barrier. Even under harsh operating conditions of long-term high voltage and temperature cycling, it can maintain stable insulation performance, significantly extending the lifespan of the current-current chip.

[0070] The PI passivation layer can be uniformly formed on the bottom surface of the spray plate 1 using mature coating processes such as spin coating, spraying, and screen printing. Compared with the stringent requirements of silicon dioxide deposition process for equipment vacuum and temperature uniformity, the PI coating process is simpler and more flexible, and has a stronger adaptability to substrate morphology. It can completely cover the edges and steps of the electrode structure 2, avoiding the defect of easy breakage of deposited films at steps. At the same time, the PI curing process is compatible with standard semiconductor back-end processes, eliminating the need for high-temperature annealing, reducing the risk of thermal damage to the previously formed electrode structure 2, and significantly improving the manufacturing yield and process reliability of current-current chips.

[0071] Reference Figure 4 Another embodiment of the present invention provides a method for forming a high voltage resistant current fluid chip, which is used to form the high voltage resistant current fluid chip as described above, including steps S100-S700.

[0072] S100. Obtain a silicon substrate as a first substrate 11, and process an array of jet holes 11a on the surface of the first substrate 11. The jet holes 11a are arranged through the first substrate 11.

[0073] S200: Etching process is performed on the bottom surface of the first substrate 11 to partially thin the first substrate 11 and form a plurality of protrusions 11b.

[0074] S300: Obtain a glass substrate as a second substrate 12, and process a plurality of through-hole spray grooves 12a on the surface of the second substrate 12.

[0075] S400, the second substrate 12 is fixed to the bottom surface of the first substrate 11 to form a spray plate 1, and a plurality of protrusions 11b are respectively located in a plurality of spray grooves 12a.

[0076] S500, Electrode structure 2 is patterned on the bottom surface of the second substrate 12.

[0077] S600, A passivation layer 3 is formed on the surface of electrode structure 2.

[0078] S700, a hydrophobic layer 4 is formed on the surface of the passivation layer 3, the bottom surface of the boss 11b, and the bottom surface of the second substrate 12.

[0079] In step S600, a spin coating process is used to spin-coat PI material onto the electrode structure 2 to form the passivation layer 3.

[0080] Specifically, the thickness of passivation layer 3 is 5-15 micrometers.

[0081] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0082] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0083] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A high-voltage resistant current-carrying chip, characterized in that, It includes: A spray plate, wherein a plurality of through spray holes are formed on the surface of the spray plate and a plurality of spray grooves are formed on the bottom surface of the spray plate, wherein each of the plurality of spray grooves corresponds one-to-one with a plurality of spray holes and the spray grooves are connected to their corresponding spray holes; Multiple protrusions are arranged in multiple spray grooves, and the protrusions are arranged at the bottom of the spray grooves. A through hole is opened on the bottom surface of the protrusion, and the through hole communicates with the spray hole. An electrode structure is arranged on the bottom surface of the spray plate, and the electrode structure is adapted to arrange an independent electric field at each of the spray holes; A passivation layer covering the electrode structure, the passivation layer comprising a PI layer.

2. The high-voltage resistant current-carrying chip according to claim 1, characterized in that, The passivation layer is formed by spin-coating PI material onto the electrode structure.

3. The high-voltage resistant current-carrying chip according to claim 1 or 2, characterized in that, The passivation layer has a thickness of 5-15 micrometers.

4. The high-voltage resistant current-carrying chip according to claim 1, characterized in that, The spray plate includes: A first substrate has a plurality of protrusions integrally formed on its bottom surface. The injection holes are formed on the first substrate, and the plurality of injection holes correspond one-to-one with the plurality of protrusions in the vertical direction. The injection holes penetrate to the bottom surface of the protrusions. The second substrate has the spray groove extending through it, and the second substrate is connected to the bottom surface of the first substrate. The plurality of protrusions are respectively located within the plurality of spray grooves.

5. The high-voltage resistant current-carrying chip according to claim 4, characterized in that, The first substrate includes a silicon substrate, and the second substrate includes a glass substrate.

6. The high-voltage resistant current-carrying chip according to claim 1, characterized in that, The electrode structure includes: Multiple electrode rings are arranged to surround multiple injection slots respectively; Multiple leads are connected to multiple electrode rings, and all of the multiple leads extend to the edge of the spray plate.

7. The high-voltage resistant current-carrying chip according to claim 1, characterized in that, The bottom surface of the boss is higher than the bottom surface of the spray plate.

8. The high-voltage resistant current-carrying chip according to claim 1, characterized in that, It also includes a hydrophobic layer that covers the passivation layer, the bottom surface of the boss, and the bottom surface of the spray plate.

9. A method for molding a high-voltage resistant current-carrying chip, characterized in that, The method for molding a high-voltage resistant current-carrying chip as described in any one of claims 1 to 8 includes the following steps: A silicon substrate is obtained as the first substrate, and an array of jet holes is processed on the surface of the first substrate, with the jet holes arranged through the first substrate. The bottom surface of the first substrate is etched to partially thin the first substrate, forming a plurality of the protrusions; A glass substrate is obtained as a second substrate, and a plurality of through-holes are processed on the surface of the second substrate; The second substrate is fixed to the bottom surface of the first substrate to form the spray plate, and the plurality of protrusions are respectively located in the plurality of spray grooves; An electrode structure is patterned on the bottom surface of the second substrate; A passivation layer is formed on the surface of the electrode structure; A hydrophobic layer is formed on the surface of the passivation layer, the bottom surface of the boss, and the bottom surface of the second substrate.

10. The method for forming a high-voltage resistant current-carrying chip according to claim 9, characterized in that, The process of forming a passivation layer on the surface of the electrode structure includes: The passivation layer is formed by spin-coating PI material onto the electrode structure.

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