Microelectromechanical package

Abstract

A microelectromechanical package includes a first substrate, an interconnect layer, a microelectromechanical component layer, and a second substrate. The interconnect layer is disposed on the first substrate, the interconnect layer including a first metal layer, a second metal layer, a first dielectric layer, a second dielectric layer, and an opening. The second metal layer is beneath the first metal layer and is thicker than the first metal layer. The first dielectric layer is on the first metal layer and the second dielectric layer is between the first metal layer and the second metal layer. The opening passes through the first dielectric layer and the second dielectric layer and exposes a portion of the second metal layer. The microelectromechanical component layer is bonded to the interconnect layer, the second substrate includes a cavity, and is bonded to the microelectromechanical component layer.

Description

[Technical Field]

[0001] This disclosure relates to microelectromechanical system (MEMS) packaging, and more particularly to a MEMS package having thick bonding pads in the interconnect layer for wire bonding and a method for manufacturing the same. [Background Technology]

[0002] Microelectromechanical systems (MEMS) components are miniature devices that integrate mechanical and electrical components to sense physical quantities and / or interact with their surroundings. In recent years, MEMS components have been commonly used as miniature sensors, such as motion sensors, pressure sensors, and accelerometers, and are widely used in modern electronic products, such as tablet computers, automobiles, and smartphones. As the application of MEMS components in consumer electronics becomes increasingly widespread, there is a growing desire to reduce their cost. However, current MEMS packaging methods still cannot fully meet the requirements of both cost reduction and maintaining MEMS component performance. [Summary of the Invention]

[0003] In view of this, the present disclosure provides a microelectromechanical system (MEMS) package and a method for manufacturing the same, which can reduce the cost of MEMS packaging while maintaining the performance of MEMS components. According to embodiments of the present disclosure, copper wires are used instead of gold wires for wire bonding, thereby reducing the cost of MEMS packaging. Furthermore, embodiments of the present disclosure also use thicker bonding pads for wire bonding in the interconnect layer of the MEMS package, thereby maintaining the performance of the MEMS component.

[0004] According to one embodiment of this disclosure, a microelectromechanical package (MEMS) is provided, including a first substrate, an interconnect layer, a MEMS component layer, and a second substrate. The interconnect layer is disposed on the first substrate and includes a first metal layer, a second metal layer, a first dielectric layer, a second dielectric layer, and an opening. The second metal layer is disposed below the first metal layer and is thicker than the first metal layer. The first dielectric layer is disposed on the first metal layer, and the second dielectric layer is disposed between the first and second metal layers. The opening extends through the first and second dielectric layers and exposes a portion of the second metal layer. The MEMS component layer is bonded to the interconnect layer, and the second substrate includes a cavity and is bonded to the MEMS component layer.

[0005] To make the features of this disclosure clear and easy to understand, embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. [Attached Image Description]

[0006] To facilitate understanding, reference should be made to the accompanying drawings and detailed textual descriptions while reading this disclosure. Specific embodiments described herein, along with corresponding drawings, are used to explain the detailed implementation principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced. Figure 1 This is a schematic cross-sectional view of a microelectromechanical (MEMS) package according to an embodiment of the present disclosure. Figure 2 This is a cross-sectional schematic diagram of a microelectromechanical package according to another embodiment of the present disclosure. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 This is a cross-sectional schematic diagram illustrating some stages of a method for manufacturing a microelectromechanical package according to an embodiment of the present disclosure. Figure 9 and Figure 10 This is a cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a microelectromechanical package according to another embodiment of the present disclosure.

Detailed Implementation Methods

[0007] This disclosure provides several different embodiments that can be used to implement different features of this disclosure. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature being formed on or above a second feature" may mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments in this disclosure may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any correlation between different embodiments and / or configurations.

[0008] Furthermore, for the spatially related descriptive terms mentioned in this disclosure, such as "below," "low," "under," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their use is to describe the relative relationship between one component or feature and another (or more) components or features in the diagram. In addition to the orientation shown in the diagram, these spatially related terms are also used to describe the possible orientation of the MEMS package during use and operation. As the orientation of the MEMS package varies (rotation 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0009] Although this disclosure uses terms such as first, second, third, etc., to describe various components, parts, regions, layers, and / or blocks, it should be understood that such components, parts, regions, layers, and / or blocks should not be limited by these terms. These terms are used only to distinguish one component, part, region, layer, and / or block from another, and do not in themselves imply or represent any prior ordinal number of the component, nor do they represent the order of arrangement of one component with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of this disclosure, the first component, part, region, layer, or block discussed below may also be referred to as a second component, part, region, layer, or block.

[0010] The terms "about" or "substantially" as used in this disclosure generally mean within 20%, more preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, meaning that the meaning of "about" or "substantially" may be implied even without specific specification.

[0011] The terms “coupled,” “coupled,” and “electrically connected” as used in this disclosure include any means of direct or indirect electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means of connection.

[0012] Although the invention of this disclosure is described below with reference to specific embodiments, the inventive principles of this disclosure can also be applied to other embodiments. Furthermore, in order to avoid obscuring the inventive spirit of this disclosure, certain details have been omitted, and these omitted details fall within the scope of knowledge of those skilled in the art.

[0013] This disclosure relates to a microelectromechanical system (MEMS) package and a method for manufacturing the same. The interconnect layer of the MEMS package has thick bond pads for copper wire bonding. The interconnect layer includes at least a first metal layer (also called a top metal layer) and a second metal layer (also called a penultimate metal layer) disposed below it, wherein the second metal layer is thicker than the first metal layer and provides the thick bond pads. In the MEMS package of this disclosure, copper wires are used instead of gold wires, thereby reducing the cost of the MEMS package. Furthermore, without increasing the thickness of the first metal layer, the thick bond pads in the interconnect layer can provide good wire bonding quality for the copper wires. Therefore, according to embodiments of this disclosure, the complexity of fabricating the interconnect layer on a complementary metal-oxide-semiconductor (CMOS) wafer is not increased, while maintaining the overall performance of the MEMS package, such as maintaining the eutectic bonding quality, electrode gap control, and sensitivity of the MEMS component.

[0014] Figure 1 This is a cross-sectional schematic diagram of a microelectromechanical system (MEMS) package 100 according to an embodiment of the present disclosure. The MEMS package 100 includes a first substrate 101, an interconnect layer 110, a MEMS component layer 120, and a second substrate 103. The first substrate 101 is, for example, a silicon wafer, and may contain multiple CMOS transistors or other components formed therein. The interconnect layer 110 is disposed on the first substrate 101 and includes multiple metal layers, multiple inter-metal dielectric (IMD) layers, and multiple vias in these IMD layers for connecting any two metal layers. The metal layers include at least a first metal layer 111 and a second metal layer 112, the IMD layers include at least a first dielectric layer 117, a second dielectric layer 116, a third dielectric layer 115, and a fourth dielectric layer 114, and the vias include at least via V1 and via V2. In addition, the interconnect layer 110 also includes a protective layer 119 disposed on the first dielectric layer 117.

[0015] The first metal layer 111 is the topmost metal layer, and the second metal layer 112 is the penultimate metal layer located below the first metal layer 111. The thickness of the second metal layer 112 is greater than the thickness of the first metal layer 111, for example, the thickness of the second metal layer 112 may be about 2 to 7 times the thickness of the first metal layer 111. In some embodiments, the thickness of the second metal layer 112 is, for example, greater than 0.9 micrometers (μm) and less than about 5 μm, and the thickness of the first metal layer 111 is, for example, less than 1 μm and greater than 0.5 μm. In other embodiments, the thickness of the first metal layer 111 is, for example, less than 0.9 μm and greater than 0.3 μm. Furthermore, according to embodiments of this disclosure, a portion 112B of the second metal layer 112 may provide a thicker bonding pad for copper wire bonding, the thickness of the portion 112B of the second metal layer 112 is greater than the thickness of the first metal layer 111, and the first metal layer 111 is not disposed directly above the portion 112B of the second metal layer 112. In one embodiment, the second metal layer 112 may have a uniform thickness in different regions of the interconnect layer 110, for example, the thickness of the second metal layer 112 may be the thickness of a portion 112B. In another embodiment, a portion 112B of the second metal layer 112 may have the largest thickness to provide a thicker bonding pad, while the thickness of other portions 112A of the second metal layer 112 may be less than the thickness of a portion 112B, such that the second metal layer 112 has different thicknesses in different regions of the interconnect layer 110, and the thickness of other portions 112A of the second metal layer 112 may be greater than or equal to the thickness of the first metal layer 111. Furthermore, other portions 112A of the second metal layer 112 may be electrically connected to the first metal layer 111 via via V1 and electrically connected to CMOS transistors or other components in the first substrate 101 via via V2, such that the interconnect layer 110 is electrically coupled to the CMOS transistors or other components in the first substrate 101. In some embodiments, the first metal layer 111 and the second metal layer 112 may be composed of an aluminum-copper (AlCu) alloy or aluminum (Al), and the first metal layer 111 and the second metal layer 112 may have the same composition. The vias V1 and V2 may be composed of tungsten (W), but are not limited thereto.

[0016] A first dielectric layer 117 is disposed on and covers the first metal layer 111. A protective layer 119 is disposed on the first dielectric layer 117. A second dielectric layer 116 is disposed between the first metal layer 111 and the second metal layer 112. A via V1 is formed in the second dielectric layer 116. Additionally, an opening 132 is formed in the interconnect layer 110, extending through the first dielectric layer 117, the second dielectric layer 116, and the protective layer 119, thereby exposing a portion 112B of the second metal layer 112 to provide a thicker bonding pad for wire bonding. In this embodiment, the protective layer 119 may extend laterally to a portion 132B of the sidewall 132S and bottom surface of the opening 132, and the exposed surface of the portion 112B of the second metal layer 112 may be lower than a portion 132B of the bottom surface of the opening 132. In some embodiments, the protective layer 119 is composed of, for example, silicon oxide or silicon nitride, and the multiple IMD layers of the interconnect layer 110 may have the same composition, for example, silicon oxide.

[0017] like Figure 1 As shown, the MEMS component layer 120 is bonded to the interconnect layer 110. The MEMS component layer 120 includes a sealing ring 122 and can be bonded to the first metal layer 111 of the interconnect layer 110 via a eutectic bonding material 124. The sealing ring 122 is a standoff structure protruding toward the interconnect layer 110. The sealing ring 122 is integrated with the MEMS component layer 120 and has the same composition as the MEMS component layer 120. In some embodiments, the first metal layer 111 is, for example, an aluminum (Al) layer or an aluminum-copper (AlCu) alloy layer, and a bonding layer, for example, germanium (Ge), can be deposited on the sealing ring 122 for eutectic bonding. Therefore, the eutectic bonding material 124 can contain germanium (Ge) and aluminum (Al), for example, an aluminum-germanium (AlGe) alloy.

[0018] Furthermore, the MEMS component layer 120 includes features such as trenches, cantilever beams, membranes, and proofmasses to construct the microelectromechanical component 126. In some embodiments, the microelectromechanical component 126 is, for example, an inertial measurement unit (IMU), an inertial sensor, a pressure sensor, a microfluidic component, other micro-components, or a combination thereof, wherein the inertial measurement unit (IMU) includes an accelerometer, a gyroscope, other IMU components, or a combination thereof.

[0019] like Figure 1As shown, an opening may be formed in the interconnect layer 110, which penetrates the protective layer 119 and the first dielectric layer 117, thereby exposing a portion 111A of the first metal layer 111, and the portion 111A of the first metal layer 111 corresponds to the microelectromechanical component 126. Additionally, other openings are formed in the interconnect layer 110, which penetrate the protective layer 119 and the first dielectric layer 117, thereby exposing other portions of the first metal layer 111, which are bonded to the sealing ring 122 by a eutectic bonding material 124.

[0020] Additionally, the second substrate 103 is bonded to the MEMS component layer 120 via a bonding layer 127 (e.g., a silicon oxide layer). The second substrate 103 is, for example, a silicon wafer, having opposing back sides 103B and front sides 103F, and includes a cavity 105 formed therein, adjacent to the front side 103F of the second substrate 103 and directly above the MEMS component 126. Furthermore, in some embodiments, a barrier 104 may be disposed within the cavity 105, corresponding to the mass block of the MEMS component 126, to prevent breakage or damage to the MEMS component 126. The barrier 104 is integrated with the second substrate 103 and has the same composition as the second substrate 103. Additionally, a metal layer 107, such as an aluminum layer, may be formed on the back side 103B of the second substrate 103. The metal layer 107 can be used for shielding electromagnetic waves, such as radio frequency (RF) shielding, and / or for electrical grounding.

[0021] The MEMS package 100 further includes a wire 130 disposed on the back surface 103B of the second substrate 103, and the wire 130 is bonded to a portion 112B of the second metal layer 112. The wire 130 can directly contact the metal layer 107 (e.g., an aluminum layer) located on the back surface 103B of the second substrate 103, and the thickness of the metal layer 107 can be greater than 0.9 μm. According to some embodiments of this disclosure, the wire 130 in the MEMS package 100 is, for example, a copper (Cu) wire, which can replace a gold (Au) wire, thereby reducing the cost of the MEMS package 100. Furthermore, in the MEMS package 100 of this disclosure, a portion 112B of the second metal layer 112 includes a bonding pad with a thickness greater than 0.9 μm. The thickness of this bonding pad is sufficient for wire bonding using copper (Cu) wire, so it is not necessary to increase the thickness of the first metal layer 111.

[0022] Increasing the thickness of the first metal layer 111 affects the eutectic bonding effect between the eutectic bonding material 124 and the first metal layer 111. Therefore, it is necessary to simultaneously increase the thickness of the eutectic bonding material 124, and consequently, the thickness of the protective layer 119 and the height of the sealing ring 122. However, increasing the thickness of the eutectic bonding material 124 can cause alignment problems during eutectic bonding and easily lead to squishing problems of the eutectic bonding material 124, all of which are detrimental to electrode gap control in MEMS packaging. In addition, increasing the thickness of the protective layer 119 and the height of the sealing ring 122 will further lead to poor electrode gap control in MEMS packaging. Furthermore, increasing the height of the sealing ring 122 is also detrimental to the manufacturing of MEMS package 100. The MEMS package 100 of the embodiments of this disclosure can overcome the above problems, simplify the MEMS packaging manufacturing process, and reduce the cost of MEMS packaging.

[0023] Figure 2 This is a cross-sectional schematic diagram of a MEMS package 100 according to another embodiment of this disclosure. Figure 2 In the MEMS package 100, an opening 132 is formed in the interconnect layer 110, extending through the protective layer 119, the first dielectric layer 117, and the second dielectric layer 116, thereby exposing a portion 112B of the second metal layer 112. This portion 112B of the second metal layer 112 includes thick bonding pads for wire bonding with the conductor 130 using copper (Cu) wires. In this embodiment, the protective layer 119 does not extend to the sidewalls and bottom surface of the opening 132, and the exposed surface of the portion 112B of the second metal layer 112 and the bottom surface of the opening 132 may be on the same plane.

[0024] In some embodiments, such as Figure 2 As shown, the interconnect layer 110 further includes a third metal layer 113, a fifth dielectric layer 118, and a via V3. The third metal layer 113 is disposed below the second metal layer 112 and is thinner than the second metal layer 112. The thickness of the third metal layer 113 can be the same as the thickness of the first metal layer 111. The third metal layer 113 is, for example, an aluminum (Al) layer or an aluminum-copper (AlCu) alloy layer. The fifth dielectric layer 118 is located below the fourth dielectric layer 114. The third metal layer 113 is formed on the fifth dielectric layer 118. The via V2 is formed in the fourth dielectric layer 114, and the via V3 is formed in the fifth dielectric layer 118. The via V3 is electrically connected to the third metal layer 113, and the third metal layer 113 can be electrically coupled to the CMOS transistor in the first substrate 101 through the via V3. Additionally, Figure 2 For details on other features of the MEMS package 100, please refer to the foregoing. Figure 1The relevant descriptions of the MEMS package 100 will not be repeated here.

[0025] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 This is a cross-sectional schematic diagram of some stages of a manufacturing method for a MEMS package 100 according to an embodiment of this disclosure, see reference. Figure 3 In step S101, a second substrate 103, such as a silicon wafer, is first provided. Alignment marks are formed on the back side 103B of the second substrate 103. Then, an etching process is used to form a cavity 105 and a barrier 104 on the front side 103F of the second substrate 103. Next, a bonding layer 106 is formed oriented in the same direction on the front side 103F, sidewalls, and back side 103B of the second substrate 103, as well as within the cavity 105 and on the barrier layer 104, to encapsulate the second substrate 103. The bonding layer 106 is composed of, for example, silicon oxide and can be formed by thermal oxidation or deposition.

[0026] Next, refer to Figure 3 In step S103, a component wafer (e.g., a silicon wafer) is provided and bonded to the second substrate 103 via a bonding layer 106 using fusion bonding. The component wafer covers the cavity 105 and the barrier 104. Then, the component wafer is thinned using back-side grinding and chemical-mechanical planarization (CMP) processes, and the edges of the thinned component wafer are trimmed to form a MEMS component layer 120. The MEMS component layer 120 is bonded to the second substrate 103 via the bonding layer 106, and the MEMS component layer 120 covers the cavity 105 and the barrier 104.

[0027] See Figure 4 In step S105, the MEMS component layer 120 is etched to form a sealing ring 122. Then, a bonding material 123, such as germanium (Ge), is formed on the sealing ring 122 using a deposition and patterning process. See still... Figure 4 In step S107, the MEMS component layer 120 is patterned using an etching process to form a microelectromechanical component 126. A sealing ring 122 surrounds the microelectromechanical component 126, and multiple trenches of the microelectromechanical component 126 are connected to the cavity 105.

[0028] See Figure 5In step S201, a first substrate 101, such as a CMOS wafer, is provided. Then, a fourth dielectric layer 114, such as a silicon oxide layer, is formed on the first substrate 101. Next, holes are etched in the fourth dielectric layer 114, and tungsten (W) is filled into the holes to form vias V2. Subsequently, a second metal layer 112, such as an aluminum copper (AlCu) layer, is deposited on the fourth dielectric layer 114. In embodiments of this disclosure, the thickness of the second metal layer 112 is greater than 0.9 μm, for example, about 4.5 μm.

[0029] Next, refer to Figure 5 In step S203, the second metal layer 112 is patterned using an etching process to form a portion 112B and some other portions 112A. Then, a third dielectric layer 115 and a second dielectric layer 116, both for example silicon oxide layers, are sequentially formed using a deposition process. The third dielectric layer 115 fills the space between the portion 112B and the other portions 112A of the second metal layer 112, and the second dielectric layer 116 covers the second metal layer 112. Next, holes are etched into the second dielectric layer 116 and filled with tungsten (W) to form a plurality of vias V1. These vias V1 are electrically connected to some portions 112A of the second metal layer 112, but not to the portion 112B of the second metal layer 112. After forming the vias V1, a chemical mechanical planarization (CMP) process is performed on the second dielectric layer 116.

[0030] See also Figure 5 In step S205, a first metal layer 111, such as an aluminum copper (AlCu) layer, is formed on the flat surface of the second dielectric layer 116 using a deposition and patterning process. In some embodiments, the thickness of the first metal layer 111 is less than 1 μm, for example, about 0.4 μm. The first metal layer 111 is electrically connected to the via V1 and is disposed above some portions 112A of the second metal layer 112. Furthermore, the first metal layer 111 is not disposed directly above a portion 112B of the second metal layer 112.

[0031] Next, refer to Figure 6 In step S207, a first dielectric layer 117, such as a silicon oxide layer, is deposited on the second dielectric layer 116, and the first dielectric layer 117 covers the first metal layer 111. Then, a chemical mechanical planarization (CMP) process is performed on the first dielectric layer 117.

[0032] See also Figure 6 In step S209, the first dielectric layer 117 is etched to form a pre-cut line 133 and a recess 131 located directly above a portion 112B of the second metal layer 112. The recess 131 may have sloping sidewalls and does not expose a portion 112B of the second metal layer 112. Then, still referring to... Figure 6 In step S211, a protective layer 119, such as a silicon nitride layer, is formed in the first dielectric layer 117 and within the recess 131 and the pre-cut line 133 via a deposition process.

[0033] Next, refer to Figure 7 In step S213, a portion of the protective layer 119 in the recess 131 and a portion of the second dielectric layer 116 directly below the recess 131 are etched to form an opening 132, thereby exposing a portion 112B of the second metal layer 112, which contains a thick bonding pad that will be used for wire bonding later. Additionally, the protective layer 119 in the pre-cut line 133 and the second dielectric layer 116 directly below the pre-cut line 133 are also simultaneously etched away. Then, the protective layer 119 and the first dielectric layer 117 are etched to form an opening 134 and a plurality of openings 136, respectively exposing a portion 111A and other portions 111B of the first metal layer 111.

[0034] See also Figure 7 In step S215, a vapor hydrogen fluoride (VHF) etching process is used to remove the precipitate. Figure 4 In step S107, the bonding layer 106 located within the cavity 105 and on the blocking member 104 is removed, leaving a bonding layer 127 between the second substrate 103 and the MEMS component layer 120. Then, a portion 111B of the sealing ring 122 is bonded to the first metal layer 111 using a eutectic bonding material 124, thereby bonding the MEMS component layer 120 to the interconnect layer 110. The eutectic bonding material 124 comprises germanium (Ge) of the bonding material 123 and aluminum (Al) of the first metal layer 111. After the MEMS component layer 120 is bonded to the interconnect layer 110, a portion 111A of the first metal layer 111 is located directly below and corresponds to the MEMS component 126.

[0035] Next, refer to Figure 8 In step S217, a metal layer 107, such as an aluminum (Al) layer, is deposited on the back side 103B of the second substrate 103. Then, still referring to... Figure 8 In step S219, a portion of the second substrate 103 and a portion of the MEMS component layer 120 located at the cutting path SL are removed using a saw. Afterwards, the interconnect layer 110 and the first substrate 101 are cut along the pre-cut line 133. Then, wires 130, such as copper wires, are formed on the metal layer 107, and the wires 130 are bonded to a portion 112B of the second metal layer 112, which provides thick bonding pads, using wire bonding to complete the process. Figure 1 MEMS package 100.

[0036] Figure 9 and Figure 10 This is a cross-sectional schematic diagram of an intermediate stage in a method for manufacturing a MEMS package 100 according to another embodiment of this disclosure, see reference. Figure 9 In step S208, upon completion Figure 6 Following step S207, a protective layer 119 is deposited on the flat surface of the first dielectric layer 117. Then, still referring to... Figure 9 In step S210, the protective layer 119, the first dielectric layer 117, and the second dielectric layer 116 are etched to form an opening 132, thereby exposing a portion 112B of the second metal layer 112, which contains a thick bonding pad that will be subsequently used for wire bonding. Then, the protective layer 119 and the first dielectric layer 117 are etched to form an opening 134 and a plurality of openings 136, respectively exposing a portion 111A and other portions 111B of the first metal layer 111.

[0037] Next, refer to Figure 10 In step S212, a metal layer 107, such as an aluminum (Al) layer, is deposited on the back side 103B of the second substrate 103. Then, still referring to... Figure 10 In step S214, a portion of the second substrate 103 and a portion of the MEMS component layer 120 located at the cutting path SL are removed using a saw. Afterwards, the interconnect layer 110 and the first substrate 101 are cut. Then, wires 130, such as copper wires, are formed on the metal layer 107, and the wires 130 are bonded to a portion 112B of the second metal layer 112, which provides thick bonding pads, by wire bonding to complete the process. Figure 2 MEMS package 100.

[0038] According to embodiments of this disclosure, the interconnect layer of the MEMS package includes thick bonding pads for wire bonding of copper wires, thereby reducing the cost of the MEMS package. Since the bonding pads, thicker than 0.9 μm, are provided by a second metal layer in the interconnect layer, which is disposed below and thicker than the first metal layer, the interconnect layer can provide thick bonding pads to achieve good wire bonding of copper wires without increasing the thickness of the first metal layer. Furthermore, since the first metal layer in the interconnect layer is not thickened, the eutectic bonding material, protective layer, and sealing ring of the MEMS package do not need to be thickened. This allows the overall performance of the MEMS package, such as the quality of the eutectic bonding, alignment control of the eutectic bonding, overflow control of the eutectic bonding material, control of electrode gap, and sensitivity of the microelectromechanical components, to be maintained or improved. Additionally, overflow control of the eutectic bonding material can reduce the likelihood of short circuits in the microelectromechanical components. Moreover, the manufacturing process of the interconnect layer with thick bonding pads is compatible with the manufacturing process of CMOS wafers, which helps simplify the manufacturing of MEMS packages. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention. [Symbol Explanation]

[0039] 100: Microelectromechanical Package 101: First substrate 103: Second substrate 103B: Back 103F: Front 104: Blocking component 105: Cavity 106: Bonding layer 107: Metal layer 110: Interconnection Layer 111: First metal layer 111A: Part 111B: Some parts 112: Second metal layer 112A: Other parts 112B: Part 113: Third metal layer 114: Fourth dielectric layer 115: Third dielectric layer 116: Second dielectric layer 117: First dielectric layer 118: Fifth dielectric layer 119: Protective layer V1, V2, V3: Through holes 120: Microelectromechanical Components Layer 122: Sealing ring 123: Bonding materials 124: Eutectic Bonding Materials 126: Microelectromechanical components 127: Bonding layer 130: Wire 131: Depression 132: Opening 132B: Part of the bottom surface 132S: Sidewall 133: Pre-cut line 134, 136: Opening SL: Cutting Track S101, S103, S105, S107, S201, S203, S205, S207, S208, S209, S210, S211, S212, S213, S214, S215, S217, S219: Steps

Claims

1. A microelectromechanical package, comprising: First substrate; An interconnect layer is disposed on the first substrate, wherein the interconnect layer includes: A first metal layer; A second metal layer is disposed below the first metal layer and is thicker than the first metal layer; A first dielectric layer is disposed on the first metal layer; A second dielectric layer is disposed between the first metal layer and the second metal layer; and An opening is made that passes through the first dielectric layer and the second dielectric layer to expose a portion of the second metal layer; A microelectromechanical component layer, bonded to the interconnect layer; and A second substrate includes a cavity and is bonded to the microelectromechanical component layer.

2. The microelectromechanical package of claim 1 further includes a wire disposed on the second substrate and the wire being bonded to the portion of the second metal layer, wherein the portion of the second metal layer includes a bonding pad.

3. The microelectromechanical package of claim 2, wherein the conductor comprises a copper wire, and the second metal layer comprises an aluminum-copper alloy layer or an aluminum layer.

4. The microelectromechanical package of claim 2 further includes a metal layer disposed on a surface of the second substrate, wherein the conductive wire directly contacts the metal layer.

5. The microelectromechanical package of claim 4, wherein the metal layer comprises an aluminum layer.

6. The microelectromechanical package of claim 1, wherein the first metal layer is not disposed directly above that portion of the second metal layer.

7. The microelectromechanical package of claim 1, wherein the thickness of the second metal layer is 2 to 7 times the thickness of the first metal layer.

8. The microelectromechanical package of claim 1, wherein the thickness of the second metal layer is greater than 0.9 micrometers (μm) and less than 5 μm.

9. The microelectromechanical package of claim 1, wherein the thickness of the first metal layer is less than 1 micrometer (μm) and greater than 0.5 μm.

10. The microelectromechanical package of claim 1, wherein the interconnect layer further includes a protective layer disposed on the first dielectric layer, and the opening passes through the protective layer.

11. The microelectromechanical package of claim 10, wherein an exposed surface of the portion of the second metal layer and a bottom surface of the opening are on the same plane.

12. The microelectromechanical package of claim 1, wherein the interconnect layer further comprises a protective layer disposed on the first dielectric layer, and the protective layer extends laterally to a portion of the sidewall of the opening and a bottom surface.

13. The microelectromechanical package of claim 12, wherein an exposed surface of the portion of the second metal layer is lower than the portion of the bottom surface of the opening.

14. The microelectromechanical package of claim 1, wherein the microelectromechanical component layer includes a sealing ring and is bonded to the first metal layer by a eutectic bonding material.

15. The microelectromechanical package of claim 14, wherein the eutectic bonding material comprises germanium and aluminum.

16. The microelectromechanical package of claim 14, wherein the sealing ring and the microelectromechanical component layer have the same composition and are integrated together.

17. The microelectromechanical package of claim 1, wherein the second metal layer has a uniform thickness in the interconnect layer.

18. The microelectromechanical package of claim 1, wherein the first substrate comprises a plurality of complementary metal-oxide-semiconductor transistors therein. Furthermore, the interconnect layer is electrically coupled to the plurality of complementary metal-oxide-semiconductor transistors.

19. The microelectromechanical package of claim 1, wherein the microelectromechanical component layer includes an inertial measurement unit, and the inertial measurement unit includes an accelerometer, a gyroscope, or a combination thereof.

20. The microelectromechanical package of claim 1, wherein a portion of the first metal layer corresponds to and is exposed in a region of the inertial measurement unit.

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