Deposition mask and method for manufacturing a deposition mask

Abstract

The present disclosure relates to a deposition mask and a method for manufacturing a deposition mask. The deposition mask includes a base layer, a protection layer, and a pattern layer. The base layer has an opening defined in the base layer corresponding to a transmission region. The protection layer is disposed on the base layer and has an opening defined in the protection layer overlapping the transmission region. The pattern layer is disposed on the protection layer and includes a pattern grid overlapping the transmission region. An area of a lower surface of the pattern grid adjacent to the protection layer is less than an area of an upper surface of the pattern grid opposite the lower surface. The pattern layer includes at least one selected from a single-crystal silicon and a polycrystal silicon.

Description

[0001] This application claims priority and all benefits arising therefrom to Korean Patent Application No. 10-2025-0052543, filed on April 22, 2025, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to deposition masks and methods for manufacturing deposition masks. Specifically, this disclosure relates to deposition masks with improved deposition accuracy and methods for manufacturing such deposition masks. Background Technology

[0003] To achieve ultra-compact and high-resolution display devices, organic light-emitting diodes (OLEDs) on silicon (OLEDoS) technology has been developed, in which organic light-emitting diodes are disposed on a silicon (Si) substrate. In the fabrication of OLED pixels, a deposition process is performed by evaporating and depositing light-emitting materials onto the substrate. For this purpose, fine-patterned masks are used to ensure that the light-emitting material is accurately deposited at the target locations. As a type of fine-patterned mask, fine metal masks (FMMs) made of metallic materials such as nickel (Ni) alloys or Invar are primarily used.

[0004] However, in high-resolution display devices, as the size of the pixels to be implemented decreases and the precision requirements increase, fine silicon masks (FSMs) based on silicon are employed. FSMs allow for precise patterning based on silicon and have a low coefficient of thermal expansion (CTE), thereby minimizing deformation during the deposition process. Summary of the Invention

[0005] This disclosure provides a deposition mask and a method for manufacturing such a deposition mask, which has minimal shading effect caused by the mask during deposition.

[0006] Furthermore, this disclosure provides a deposition mask and a method for manufacturing such a deposition mask, wherein the deposition mask has improved deposition accuracy by forming a mask pattern grid comprising silicon (Si) in an inverted conical shape.

[0007] According to embodiments of the present disclosure, a deposition mask includes a base layer, a protective layer, and a patterned layer. In this embodiment, the base layer has an opening defined therein corresponding to a transmission region. In this embodiment, the protective layer is disposed on the base layer and has an opening defined therein overlapping the transmission region. In this embodiment, the patterned layer is disposed on the protective layer and includes a patterned mesh overlapping the transmission region. In this embodiment, the area of ​​the lower surface of the patterned mesh adjacent to the protective layer is smaller than the area of ​​the upper surface of the patterned mesh opposite to the lower surface. In this embodiment, the patterned layer includes at least one selected from monocrystalline silicon and polycrystalline silicon.

[0008] In this implementation, the width of the patterned grid can increase as it moves away from the protective layer.

[0009] In some implementations, the base layer may include silicon.

[0010] In one implementation, the area of ​​the upper surface of the base layer adjacent to the protective layer can be greater than the area of ​​the lower surface of the base layer, wherein the lower surface of the base layer is opposite to the protective layer, and the upper surface of the base layer is between the lower surface of the base layer and the protective layer.

[0011] In some embodiments, the protective layer may include silicon oxide (SiO2). x ).

[0012] In one implementation, the area of ​​the upper surface of the protective layer adjacent to the pattern layer can be larger than the area of ​​the lower surface of the protective layer adjacent to the base layer.

[0013] In an embodiment, the deposition mask may further include a lower layer disposed below the base layer and having an opening defined therein that overlaps with the transmission region.

[0014] In some embodiments, the lower layer may include silicon oxide (SiO2). x ).

[0015] A method for manufacturing a deposition mask according to embodiments of the present disclosure includes: preparing a base substrate comprising silicon; forming a mask body by depositing a first protective layer, an intermediate layer, and a second protective layer, wherein the first protective layer surrounds the base substrate, the intermediate layer surrounds the first protective layer and comprises at least one selected from monocrystalline silicon and polycrystalline silicon, and the second protective layer surrounds the intermediate layer; forming a patterned mesh by etching the second protective layer and the intermediate layer formed on a first side of the mask body; performing a first etching process to remove the second protective layer and the intermediate layer formed on a second side of the mask body, wherein the second side is opposite to the first side and the base substrate is between the second side and the first side; forming a mask opening overlapping the patterned mesh by etching the first protective layer and the base substrate from the second side; and performing a second etching process to remove the second protective layer remaining on the first side.

[0016] In one implementation, forming the patterned grid may include dry etching the second protective layer and the intermediate layer using a Bosch etching process.

[0017] In one embodiment, the patterned mesh can be formed in such a way that the area of ​​the upper surface of the patterned mesh adjacent to the first side of the mask body is greater than the area of ​​the lower surface of the patterned mesh adjacent to the base substrate.

[0018] In one embodiment, between forming the mask body and forming the patterned mesh, the method may further include applying photoresist to a first side of the mask body and performing exposure and development processes.

[0019] In one implementation, forming the mask opening may include using a wet etching process.

[0020] In an implementation, the mask opening can be formed in such a way that the area of ​​the upper surface of the base substrate adjacent to the pattern grid is greater than the area of ​​the lower surface of the base substrate adjacent to the second side of the mask body.

[0021] In an embodiment, the second protective layer may include silicon nitride (SiN). x ).

[0022] In one implementation, the second protective layer can be deposited thinner than the intermediate layer during the formation of the mask body.

[0023] In one implementation, in forming the mask body, a second protective layer may be deposited with a thickness greater than or equal to about 400 angstroms (Å) and less than or equal to 500 Å.

[0024] In one embodiment, performing the first etching process may include removing a first protective layer formed on a second side of the mask body, and forming a mask opening may include etching the first protective layer formed on a first side.

[0025] In one implementation, performing the second etching process may include removing the second protective layer using a wet etching process.

[0026] In an embodiment, the first protective layer may include silicon oxide (SiO2). x ).

[0027] According to embodiments of this disclosure, since the mask pattern layer comprises silicon (Si), the pattern mesh can be etched more easily in an inverted conical shape.

[0028] Furthermore, according to embodiments of this disclosure, deposition accuracy can be improved and the shadowing effect caused by the deposition mask can be reduced. Attached Figure Description

[0029] These and / or other features of the embodiments will become apparent and more readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic top plan view of a deposition mask according to an embodiment of the present disclosure; Figure 2 This is a schematic cross-sectional view of a deposition mask according to an embodiment of the present disclosure; Figure 3 yes Figure 2 An enlarged view of region AA shown in the image; Figure 4 It is an image of a patterned grid created according to embodiments of the present disclosure; Figure 5 This is a schematic cross-sectional view of a display panel manufactured according to an embodiment of the present disclosure; Figure 6 This is a flowchart illustrating a method for manufacturing a deposition mask according to an embodiment of the present disclosure; and Figures 7A to 7I This is a cross-sectional view schematically illustrating the various steps of a method for manufacturing a deposition mask according to an embodiment of the present disclosure. Detailed Implementation

[0030] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0031] When a component (or area, layer, section, etc.) is described as being "set on," "placed on," "arranged on," "connected to," or "linked to" another component, it should be interpreted as being directly set on, placed on, arranged on, directly connected to, or directly linked to another component, but there may also be another component between them. When a component is described as being "directly set on," "placed on," "arranged on," "directly connected to," or "linked to" another component, it should be interpreted as no other component is present between them.

[0032] Similar or identical reference numerals indicate similar or identical elements. Furthermore, in the drawings, the thickness, scale, and dimensions of elements may not be drawn precisely and may be exaggerated to facilitate the effective interpretation of the technical features associated with these elements. Therefore, this disclosure should not be limited to the thickness, scale, dimensions, characteristics, etc., shown in the drawings.

[0033] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0034] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used in this specification to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to encompass different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Thus, based on the specific orientation of the drawing, the term “down” can encompass both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the term “below” or “under” can encompass both “up” and “down” orientations.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a”, “an”, “the”, and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, a reference to “the” element following a reference to “a” element in a claim includes one element and multiple elements. For example, “a single element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprises” and / or “comprising” or “includes” and / or “including” specify the presence of the stated feature, region, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0036] As used herein, the term "substantially" means approximately or actually. The term "substantially equal" means approximately equal or actually equal. The term "substantially identical" means approximately identical or actually identical. The term "substantially perpendicular" means approximately perpendicular or actually perpendicular. The term "substantially parallel" means approximately parallel or actually parallel.

[0037] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include the value and mean within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the value.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0039] Embodiments are described herein with reference to schematic cross-sectional views as idealized embodiments. Thus, variations in the shape of the figures should be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0040] In this specification, the specified order of the processes may be performed differently than the order described, where any implementation may be carried out differently. For example, in an implementation, two processes described as being performed sequentially may be performed simultaneously or in reverse order.

[0041] In this disclosure, for the purpose of describing the deposition mask in the embodiments, a first direction DR1, a second direction DR2, and a third direction DR3 may be defined. The deposition mask is disposed on the plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 is defined as the thickness direction of the deposition mask, and the first direction DR1, the second direction DR2, and the third direction DR3 may be orthogonal to each other.

[0042] Figure 1 This is a schematic top plan view illustrating a deposition mask according to an embodiment of the present disclosure. Reference Figure 1 The deposition mask DPM can include a non-transparent region NPA and a transparent region PA. The non-transparent region NPA can have a shape surrounding the transparent region PA. The non-transparent region NPA can include a mask frame MF and a mask mesh MGD.

[0043] In an implementation, the deposition mask (DPM) can be configured to allow deposition material to be deposited at designated locations on a substrate (not shown) during the deposition process. Reference will be made later. Figure 5 Describe the detailed configuration of the substrate, in which the deposition material is deposited onto the substrate through a deposition mask (DPM).

[0044] The mask frame (MF) can form the outer portion of the deposition mask (DPM). In an implementation, such as... Figure 1 As shown, the mask frame MF can have a circular shape, but is not limited to this.

[0045] The transmission region PA or an opening corresponding to the transmission region PA can be defined by a mask mesh MGD. During the deposition process, the deposited material can be blocked by the mask mesh MGD.

[0046] A patterned grid (PGD) can be formed within the transmission region (PA). Within the transmission region (PA), a patterned opening (POP) can be defined by the patterned grid (PGD). The shapes of the patterned grid (PGD) and the patterned opening (POP) are not limited to... Figure 1 The shape shown. The deposited material can pass through the patterned opening POP.

[0047] The openings corresponding to the transmission region PA and the patterned openings POPs defined by the patterned grid PGD can be defined by different layers of the deposition mask DPM, or formed in different layers of the deposition mask DPM. The openings corresponding to the transmission region PA and the patterned openings POPs will be described in detail later.

[0048] Figure 2 This is a schematic cross-sectional view illustrating a deposition mask according to an embodiment of the present disclosure. Reference Figure 2 Deposition mask DPM (see Figure 1 The deposition mask (DPM) may include a base layer (BL), a protective layer (PRL), a patterning layer (PL), and a lower layer (LL). The materials forming the deposition mask (DPM) and the stacking structure of the deposition mask (DPM) are not limited to these.

[0049] The base layer BL may have a first opening OP1 defined in the base layer BL corresponding to the transmission region PA. Deposited material emitted from the deposition source DPS on the third direction DR3 can reach the substrate (not shown) through the first opening OP1. The substrate may be disposed adjacent to the patterning layer PL. The area of ​​the upper surface of the base layer BL adjacent to the protective layer PRL may be larger than the area of ​​the lower surface of the base layer BL, wherein the lower surface of the base layer BL may be opposite the protective layer PRL, and the upper surface of the base layer BL may be between the lower surface of the base layer BL and the protective layer PRL. Therefore, in a cross-sectional view or in a plane defined by the first direction DR1 and the third direction DR3, the base layer BL may have an inverted conical shape in which the upper surface is larger than the lower surface. In a cross-sectional view or in the same plane defined by the first direction DR1 and the third direction DR3, the first opening OP1 may have a conical shape such that the size of the first opening OP1 at the lower surface of the base layer BL is larger than that at the upper surface of the base layer BL.

[0050] In embodiments of this disclosure, the base layer BL may include silicon. Therefore, the deposition mask DPM may be a fine silicon mask (FSM) in which mask patterns (or mask septa) are formed on a silicon wafer substrate. By including silicon in the base layer BL, the precision of mask pattern fabrication can be improved. The deposition mask DPM according to embodiments of this disclosure can be used to fabricate organic light-emitting diode (OLED) (OLEDoS) panels with high-resolution pixels.

[0051] A protective layer PRL can be disposed on the base layer BL. A second opening OP2 overlapping the transmission region PA can be defined in the protective layer PRL. The second opening OP2 can extend from or connect to the first opening OP1. That is, deposited material emitted from the deposition source DPS on the third direction DR3 can reach the substrate through the first opening OP1 and the second opening OP2. The area of ​​the upper surface of the protective layer PRL adjacent to the pattern layer PL can be larger than the area of ​​the lower surface of the protective layer PRL adjacent to the base layer BL. Therefore, in a cross-sectional view or in a plane defined by the first direction DR1 and the third direction DR3, the protective layer PRL can have an inverted conical shape in which the upper surface is larger than the lower surface. In the same plane defined by the first direction DR1 and the third direction DR3, the second opening OP2 can have a conical shape such that the size of the second opening OP2 is larger at the lower surface of the protective layer PRL than at the upper surface of the protective layer PRL.

[0052] In an implementation, the protective layer PRL may include silicon oxide (SiO2). x The protective layer PRL serves to protect the base layer BL from over-etching during the fabrication of the deposition mask DPM. In this implementation, the protective layer PRL improves the uniformity of the pattern layer PL deposited on the protective layer PRL and minimizes surface defects. The protective layer PRL also enhances the adhesion of the pattern layer PL and the interfacial stability with the base layer BL.

[0053] A patterned layer PL can be disposed on a protective layer PRL. The patterned layer PL may include a patterned grid PGD overlapping the transmission region PA. Within the transmission region PA, a patterned opening POP can be defined by the patterned grid PGD. The patterned layer PL can serve as a diaphragm for the deposition mask DPM. The patterned grid PGD can be configured to allow deposited material emitted from the deposition source DPS on a third-direction DR3 to pass through the patterned opening POP and deposit only at designated locations on the substrate. That is, the patterned grid PGD can block the deposited material.

[0054] A deposition process can be performed simultaneously with the substrate positioned facing the deposition source DPS and the deposition mask DPM positioned between the deposition source DPS and the substrate. When the deposition material passes through the patterned opening POP on the third-direction DR3 and is deposited on the substrate, the shape of the patterned grid PGD can affect deposition accuracy. If the shape of the patterned grid PGD causes a shading effect, the deposition material may fail to deposit in the target deposition area.

[0055] In embodiments where the patterned grid PGD is formed in an inverted conical shape (i.e., the surface of the patterned grid PGD adjacent to the substrate is larger than the surface of the patterned grid PGD adjacent to the deposition source DPS), the shading effect can be minimized. Here, the patterned opening POP can be formed in a conical shape, such that the size of the patterned opening POP increases towards the deposition source DPS. Therefore, the deposition area relative to the deposition source DPS can be widened, thereby reducing the shading area.

[0056] In traditional deposition masks, the patterned layer typically comprises silicon nitride (SiN) deposited via low-pressure chemical vapor deposition (LPCVD). x Therefore, the patterned layer can be formed as a low-stress nitride (LSN) film. Due to its high density and strong binding energy, LSN exhibits high etch resistance, and thus may require a high bias voltage during the etching process. Therefore, since isotropic etching will be difficult for LSN, it may be difficult to achieve a patterned mesh in an inverted conical shape.

[0057] In an embodiment, the patterned layer PL may include at least one selected from monocrystalline silicon (Si) and polycrystalline silicon (Poly-Si). The patterned layer PL may include, or be formed from, the same material as the base layer BL. Monocrystalline silicon or polycrystalline silicon exhibits high chemical reactivity with SF6 plasma. Furthermore, when monocrystalline silicon or polycrystalline silicon is etched using a Bosch etching process, hole patterns with high aspect ratios can be formed. Therefore, during dry etching, the patterned layer PL, comprising, or formed from monocrystalline silicon or polycrystalline silicon, can be more easily etched in an inverted conical shape. Reference will be made later. Figure 6 Describes a method for creating patterned grid PGD.

[0058] Therefore, in embodiments where the patterned layer PL is formed to include at least one selected from monocrystalline silicon (Si) and polycrystalline silicon (Poly-Si), the patterned mesh PGD can be fabricated in an inverted conical shape. Consequently, the area of ​​the lower surface of the patterned mesh PGD adjacent to the protective layer PRL can be smaller than the area of ​​the upper surface of the patterned mesh PGD opposite to that lower surface. The width of the patterned mesh PGD can increase with distance from the protective layer PRL (or with distance from the protective layer).

[0059] The lower layer LL can be located below the base layer BL. The third opening OP3, which overlaps with the transmission region PA, can be confined within the lower layer LL. The third opening OP3 can extend from the first opening OP1. That is, the deposited material emitted from the deposition source DPS on the third-direction DR3 can reach the substrate through the first opening OP1 to the third opening OP3.

[0060] In this embodiment, the lower LL layer may include silicon oxide (SiO2). x The lower layer LL serves to protect the base layer BL from over-etching during the fabrication of the deposition mask DPM. The lower layer LL can include, or be formed of, the same material as the protective layer PRL.

[0061] Figure 3 It is shown schematically. Figure 2 A magnified view of region AA shown. Figure 3 The diagram schematically illustrates a cross-sectional view of a patterned mesh PGD. The shaded area can be determined based on the cone angle A1 of the patterned mesh PGD, in which no material is deposited on the substrate. Here, the cone angle A1 can be defined as an acute angle formed between a plane parallel to the lower surface of the patterned mesh PGD and a side surface of the patterned mesh PGD. In other words, the cone angle A1 can be an angle formed between a side surface of the patterned mesh PGD inclined relative to a third direction DR3 and a plane of the patterned opening POP defined by a first direction DR1 and a second direction DR2. In embodiments, for example, the cone angle A1 of the patterned mesh PGD used to minimize the shading effect can be greater than or equal to about 80° and less than or equal to about 85°.

[0062] In embodiments of this disclosure, a patterned grid PGD comprising at least one selected from monocrystalline silicon (Si) and polycrystalline silicon (Poly-Si) can be etched in an inverted conical shape. In embodiments, for example, the cone angle A1 of the patterned grid PGD can be greater than or equal to about 80° and less than about 90°. Due to the relationship between the patterned grid PGD and the deposition source DPS (see...) Figure 2 The adjacent surface area is smaller than the surface area of ​​the pattern grid PGD adjacent to the substrate, thus reducing the shadow area on the substrate.

[0063] Figure 4 This is an image of a patterned grid created according to embodiments of this disclosure. (Reference) Figure 4 Patterned mesh PGD can be etched in an inverted conical shape, and the patterned openings (POPs) formed by etching can also have a conical shape. The cone angle A1 of the patterned mesh PGD can be greater than or equal to about 80° and less than about 90°. From the deposition source DPS (see...) Figure 2 The deposited material emitted can reach the substrate along the third direction DR3 through the patterned opening POP. Because the patterned grid PGD has an inverted conical shape, shading effects can be minimized and deposition accuracy can be improved.

[0064] Figure 5 This is a schematic cross-sectional view illustrating a display panel manufactured according to an embodiment of the present disclosure. Reference Figure 5The display panel DP may include a base component SBL, a circuit layer CL, a light-emitting element layer ELL, and a packaging layer TFE. The base component SBL and the circuit layer CL may include multiple transistors T1 and T2. The structure of the first transistor T1 and the second transistor T2 is not limited to this. Figure 5 Some of the components of the display panel DP shown can be formed by a deposition process using a reference. Figure 1 The described deposition mask DPM.

[0065] The base component SBL may include a semiconductor wafer. In embodiments, the base component SBL may include, for example, a silicon wafer, a compound semiconductor wafer, a silicon carbide wafer, a sapphire wafer, a diamond wafer, etc. The base component SBL may include portions of multiple transistors T1, T2.

[0066] The circuit layer CL may include a buffer layer BFL, a first gate insulating layer GI1 and a second gate insulating layer GI2, an interlayer insulating layer ILD, a circuit insulating layer VIA, and other portions of the plurality of transistors T1 and T2. In an embodiment, for example, the circuit layer CL may include a control electrode GE, a first electrode ED1, and a second electrode ED2 constituting each of the plurality of transistors T1 and T2.

[0067] The buffer layer BFL can be configured to prevent impurities present in the base layer BL from penetrating into the pixel during the manufacturing process. In particular, it can effectively prevent impurities from diffusing into the active regions ACL of the multiple transistors T1, T2 that constitute the pixel. Furthermore, the buffer layer BFL can be used to block moisture from entering the pixel from the outside.

[0068] The active region ACL may include a channel region and a first ion-doped region and a second ion-doped region, wherein the channel region serves as a channel through which electrons or holes move, and the first ion-doped region and the second ion-doped region are disposed on opposite sides of the channel region.

[0069] The first gate insulating layer GI1 covering the active region ACL can be disposed on the buffer layer BFL. The first gate insulating layer GI1 can include at least one of an organic film and an inorganic film.

[0070] The control electrode GE of each of the plurality of transistors T1 and T2 can be disposed on the first gate insulating layer GI1. The control electrode GE of the first transistor T1 can correspond to one of the two electrodes forming a capacitor.

[0071] A second gate insulating layer GI2 covering the control electrode GE may be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2 may include at least one selected from organic films and inorganic films.

[0072] The other of the two electrodes forming the capacitor can be disposed on the second gate insulating layer GI2. However, the structure in which the electrode forming the capacitor is disposed is not limited to this.

[0073] An interlayer insulating layer (ILD) may be disposed on the second gate insulating layer GI2. The ILD may cover the first gate insulating layer GI1, the second gate insulating layer GI2, and multiple control electrodes GE. The ILD may include at least one selected from organic and inorganic films.

[0074] Multiple first electrodes ED1 and multiple second electrodes ED2 constituting each of multiple transistors T1 and T2 may be disposed on an interlayer insulating layer ILD. The first electrodes ED1 and the second electrodes ED2 may be electrically connected to the respective active regions ACL through contact holes, wherein the contact holes penetrate (or are limited to) the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD.

[0075] The circuit insulating layer VIA covering the first electrode ED1 and the second electrode ED2 can be disposed on the interlayer insulating layer ILD. The circuit insulating layer VIA can include at least one selected from organic films and inorganic films, and can provide a flat surface.

[0076] The pixel limiting layer (PDL) can be disposed on a portion of the circuit insulating layer (VIA). The light-emitting aperture (LOP) can be defined by the pixel limiting layer (PDL). The light-emitting diode (LD) can be disposed or formed at the light-emitting aperture (LOP).

[0077] A light-emitting diode (LD) may include an anode (AE), a hole functional layer (HFL), an emitter layer (EML), an electron functional layer (EFL), and a cathode (CE). An LD can emit light.

[0078] The anode AE ​​can be disposed on a portion of the circuit insulating layer VIA. In an embodiment, the anode AE ​​can be disposed at the light-emitting opening LOP and can be electrically connected to the second electrode ED2. Although Figure 5 An embodiment is shown in which the second electrode ED2 of the first transistor T1 is in direct contact with the anode AE, but this disclosure is not limited thereto.

[0079] The hole functional layer (HFL) can be placed on the anode (AE). The hole functional layer (HFL) can assist in the movement of holes generated at the anode (AE).

[0080] The emitter layer (EML) can be disposed on the hole functional layer (HFL) and configured to emit light. In one embodiment, the emitter layer (EML) may include an organic light-emitting material. In this embodiment, the light-emitting diode (LD) may be an OLED.

[0081] The electronic functional layer (EFL) can be placed on the emitter layer (EML) and can assist the movement of electrons generated at the cathode (CE).

[0082] The cathode (CE) can be disposed on the electronic functional layer (EFL). The cathode (CE) can have low resistance to facilitate current flow.

[0083] The encapsulation layer TFE can seal the light-emitting diode (LD) to protect it from external oxygen and / or moisture. The encapsulation layer TFE may include a layer in which organic and inorganic films are mixed.

[0084] The deposition mask DPM disclosed herein (see [link]) Figure 1 The method can be used to form at least one selected from a first gate insulating layer GI1 and a second gate insulating layer GI2 comprising organic materials, an interlayer insulating layer ILD, a circuit insulating layer VIA, an emitter layer EML, and a packaging layer TFE. However, the configuration of the display panel DP formed using the deposition mask DPM of this disclosure is not limited thereto.

[0085] Figure 6 This is a flowchart illustrating a method for manufacturing a deposition mask according to an embodiment of the present disclosure. Figures 7A to 7I The various steps (processes or operations) of a method for manufacturing a deposition mask according to this disclosure are illustrated schematically. Figures 7A to 7I This can be understood as a deposition mask DPM (see Figure 1 A sectional view of ( ). Refer to Figures 7A to 7I describe Figure 6 The method.

[0086] refer to Figure 6 An implementation of a method for manufacturing a deposition mask (DPM) may include a preparation step S100, a deposition step S200, a patterning step S300, a first etching step S400, a mask opening forming step S500, and a second etching step S600.

[0087] refer to Figure 6 and Figure 7A In preparation step S100, a base substrate BS comprising silicon can be prepared. The base substrate BS can be a silicon wafer.

[0088] refer to Figure 6 and Figure 7B In deposition step S200, a first protective layer PRL1 may be deposited around the base substrate BS. The first protective layer PRL1 may include silicon oxide (SiO2). x The first protective layer, PRL1, serves to protect the base substrate, BS, from excessive etching during the fabrication of the deposition mask, DPM.

[0089] In deposition step S200, prior to depositing the intermediate layer IL surrounding the first protective layer PRL1, additional processes can be performed to ensure uniform deposition and precise alignment of the intermediate layer IL. Specifically, photolithography and etching processes can be performed to generate alignment marks. To provide a precise alignment reference, photoresist can be coated onto the base substrate BS, and exposure and development processes can be performed to form a pattern for generating the alignment marks. Furthermore, at least a portion of the base substrate BS can be etched using the formed pattern. The base substrate BS can be etched using a reactive ion etching (RIE) process. Thus, alignment marks can be generated, and an optimal surface can be prepared for depositing the intermediate layer IL.

[0090] refer to Figure 6 and Figure 7C In deposition step S200, an intermediate layer IL may be deposited around the first protective layer PRL1. The intermediate layer IL may include at least one selected from monocrystalline silicon (Si) and polycrystalline silicon (Poly-Si). The intermediate layer IL may include the same material as the base substrate BS, or may be formed of the same material as the base substrate BS.

[0091] refer to Figure 6 and Figure 7D In deposition step S200, a second protective layer PRL2 may be deposited around the intermediate layer IL. The second protective layer PRL2 may include silicon nitride (SiN). x Silicon nitrides can be deposited using low-pressure chemical vapor deposition (LP CVD). Therefore, the intermediate layer (IL) can be formed as a low-stress nitride film. This low-stress nitride film can be used as a hard mask to protect the intermediate layer (IL).

[0092] In deposition step S200, the second protective layer PRL2 can be deposited to be thinner than the intermediate layer IL. In an embodiment, for example, the second protective layer PRL2 can be deposited to a thickness greater than or equal to about 400 angstroms (Å) and less than or equal to about 500 Å.

[0093] Therefore, in the deposition step S200, a mask body can be formed by depositing a first protective layer PRL1 around the base substrate BS, an intermediate layer IL around the first protective layer PRL1, and a second protective layer PRL2 around the intermediate layer IL.

[0094] In the deposition step S200, for example, but not limited to sputtering, physical vapor deposition, chemical vapor deposition, or atomic layer deposition, the first protective layer PRL1, the intermediate layer IL, and the second protective layer PRL2 can be deposited as thin films.

[0095] The mask body may include a first side SF1 and a second side SF2 that are opposite to each other along the thickness direction of the mask body. The base substrate BS may be located between the first side SF1 and the second side SF2. When the deposition step S200 is completed, a second protective layer PRL2 may be formed on both the first side SF1 and the second side SF2 of the mask body.

[0096] An embodiment of the method for manufacturing a deposition mask (DPM) may further include a photolithography step between a deposition step S200 and a patterning step S300. In the photolithography step, photoresist can be applied to a first side SF1 of the mask body, and exposure and development processes can be performed. Therefore, a patterned grid (PGD) can be formed on the first side SF1 of the mask body (see [link to relevant documentation]). Figure 1 (Prepared pattern)

[0097] refer to Figure 6 and Figure 7E In the patterning step S300, a second protective layer PRL2 and an intermediate layer IL formed on the first side SF1 of the mask body can be etched to form a pattern grid PGD. The second protective layer PRL2 and the intermediate layer IL can be etched using a dry etching process.

[0098] In dry etching processes, CF4, such as C4F8 or CF4, can be formed on the surface and sidewalls. x The polymer is used as the base material, and the Bosch etching process is performed using SF6 plasma etching. Furthermore, the deposition and etching can be repeatedly performed using the Bosch etching process. Therefore, high aspect ratio patterns can be formed, and the etched sidewalls can be protected against undercutting.

[0099] The Bosch etching process is more suitable for etching intermediate layers IL, including at least one selected from monocrystalline silicon (Si) and polycrystalline silicon (Poly-Si), than etching intermediate layers IL, which include low-stress nitride (LSN). Therefore, in the patterning step S300, a patterned mesh PGD with an inverted conical shape can be formed by the Bosch etching process. The area of ​​the upper surface of the patterned mesh PGD adjacent to the first side SF1 of the mask body can be larger than the area of ​​the lower surface of the patterned mesh PGD adjacent to the base substrate BS.

[0100] The method for forming the pattern grid PGD in the pattern forming step S300 is not limited to the description above. In another embodiment, dry etching techniques other than the Bosch etching process can also be used to form the inverted conical pattern grid PGD.

[0101] refer to Figure 6 and Figure 7FIn the first etching step S400, the second protective layer PRL2 and the intermediate layer IL formed on the second side SF2 of the mask body can be removed. The first etching step S400 can be understood as a pretreatment step for forming mask openings in the base substrate BS.

[0102] In the first etching step S400, the first protective layer PRL1 formed on the second side SF2 of the mask body can also be removed. The first protective layer PRL1 can be removed using a dry etching process or a wet etching process.

[0103] refer to Figure 6 and Figure 7G In the mask opening formation step S500, the first protective layer PRL1 and the base substrate BS can be etched (for example, the first protective layer PRL1 and the base substrate BS can be etched starting from the second side SF2) to form a mask opening overlapping the patterned grid PGD. In the mask opening formation step S500, a wet etching process can be used to form the mask opening. The mask opening can be formed such that the area of ​​the upper surface of the base substrate BS adjacent to the patterned grid PGD is larger than the area of ​​the lower surface of the base substrate BS adjacent to the second side SF2 of the mask body. Therefore, the mask opening can have a tapered shape in cross-section. The first protective layer PRL1 can be etched starting from both the upper and lower portions of the base substrate BS.

[0104] After removing the first protective layer PRL1 on the second side SF2 in the first etching step S400, the first protective layer PRL1 remaining on the first side SF1 of the mask body can be etched in the mask opening forming step S500. Therefore, as Figure 7I As shown, the deposition mask DPM may not include the first protective layer PRL1 on the second side SF2 of the mask body.

[0105] refer to Figure 6 and Figure 7H In the second etching step S600, the second protective layer PRL2 remaining on the first side SF1 of the mask body can be removed. The second protective layer PRL2 that was not removed in the first etching step S400 can also be removed in the second etching step S600. The second protective layer PRL2 can be removed using a wet etching process.

[0106] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0107] While the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to the invention without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A deposition mask, comprising: A base layer having an opening defined in the base layer corresponding to the transmission region; A protective layer is disposed on the base layer and has an opening defined in the protective layer that overlaps with the transmissive region; as well as A patterned layer is disposed on the protective layer and includes a patterned grid that overlaps with the transmissive region. Wherein, the area of ​​the lower surface of the patterned mesh adjacent to the protective layer is smaller than the area of ​​the upper surface of the patterned mesh opposite to the lower surface, and The patterned layer includes at least one selected from monocrystalline silicon and polycrystalline silicon.

2. The deposition mask according to claim 1, wherein, The width of the patterned grid increases with distance from the protective layer.

3. The deposition mask according to claim 2, wherein, The base layer comprises silicon.

4. The deposition mask according to claim 3, wherein, The area of ​​the upper surface of the base layer adjacent to the protective layer is greater than the area of ​​the lower surface of the base layer, the lower surface of the base layer is opposite to the protective layer, and the upper surface of the base layer is between the lower surface of the base layer and the protective layer.

5. The deposition mask according to claim 1, wherein, The protective layer comprises silicon oxide.

6. The deposition mask according to claim 5, wherein, The area of ​​the upper surface of the protective layer adjacent to the pattern layer is greater than the area of ​​the lower surface of the protective layer adjacent to the base layer.

7. The deposition mask of claim 1 further includes a lower layer disposed below the base layer and having an opening defined in the lower layer that overlaps with the transmission region.

8. The deposition mask according to claim 7, wherein, The lower layer comprises silicon oxide.

9. A method for manufacturing a deposition mask, the method comprising: Prepare a base substrate including silicon; A mask body is formed by depositing a first protective layer, an intermediate layer, and a second protective layer, wherein the first protective layer surrounds the base substrate, the intermediate layer surrounds the first protective layer and comprises at least one selected from monocrystalline silicon and polycrystalline silicon, and the second protective layer surrounds the intermediate layer. A patterned grid is formed by etching the second protective layer and the intermediate layer formed on the first side of the mask body; A first etching process is performed to remove the second protective layer and the intermediate layer formed on the second side of the mask body, wherein the second side is opposite to the first side and the base substrate is between the second side and the first side; A mask opening overlapping the patterned grid is formed by etching the first protective layer and the base substrate from the second side; and A second etching process is performed to remove the second protective layer remaining on the first side.

10. The method for manufacturing a deposition mask according to claim 9, wherein, In forming the patterned mesh, the patterned mesh is formed in such a way that the area of ​​the upper surface of the patterned mesh adjacent to the first side of the mask body is greater than the area of ​​the lower surface of the patterned mesh adjacent to the base substrate.

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